IR MOSFET
StrongIRFET™
IRL40SC228
HEXFET® Power MOSFET
Application
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
VDSS
40V
RDS(on) typ.
0.50m
max
0.65m
D
G
ID (Silicon Limited)
557A
ID (Package Limited)
360A
S
D
Benefits
Optimized for Logic Level Drive
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free*
RoHS Compliant, Halogen-Free
S
SS
SS
S
G
Package Type
IRL40SC228
D2PAK-7Pin
D
Drain
Standard Pack
Form
Quantity
Tape and Reel Left
800
5
S
Source
Orderable Part Number
IRL40SC228
600
ID = 100A
LIMITED BY PACKAGE
500
4
3
2
TJ = 125°C
1
400
300
200
100
TJ = 25°C
0
0
4
8
0
12
16
20
V GS, Gate-to-Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
1
G
Gate
ID, Drain Current (A)
RDS(on), Drain-to -Source On Resistance ( m )
Base Part Number
D2PAK-7Pin
IRL40SC228
25
50
75
100
125
150
175
TC, Case Temperature (°C)
Fig 2. Maximum Drain Current vs. Case Temperature
2017-05-12
IRL40SC228
Absolute Maximum Rating
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
TJ
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Operating Junction and
Max.
557
393
360
1440
416
2.8
± 20
-55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Avalanche Characteristics
EAS (Thermally limited)
1275
Single Pulse Avalanche Energy
2150
EAS (Thermally limited)
Single Pulse Avalanche Energy
IAR
Avalanche Current
See Fig 15, 16, 23a, 23b
Repetitive Avalanche Energy
EAR
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Junction-to-Case
RJC
–––
0.36
Case-to-Sink, Flat Greased Surface
RCS
0.50
–––
RJA
Junction-to-Ambient
–––
62
TSTG
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
Min. Typ. Max.
40
––– –––
––– 0.031 –––
––– 0.50 0.65
––– 0.60 0.90
1.0 –––
2.4
––– –––
1.0
––– ––– 150
––– ––– 100
––– ––– -100
–––
2.2
–––
Units
A
W
W/°C
V
°C
mJ
A
mJ
Units
°C/W
Units
Conditions
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 5mA
VGS = 10V, ID = 100A
m
VGS = 4.5V, ID = 50A
V
VDS = VGS, ID = 250µA
VDS = 40 V, VGS = 0V
µA
VDS = 40V,VGS = 0V,TJ =125°C
VGS = 20V
nA
VGS = -20V
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 360A. Note that
Current imitations arising from heating of the device leads may occur with some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.146mH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1008A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 65A, VGS =10V.
Pulse drain current is limited to 1440A by source bonding technology.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.infineon.com/technical-info/appnotes/an-994.pdf
2
2017-05-12
IRL40SC228
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg– Qgd)
Turn-On Delay Time
Rise Time
Min.
264
–––
–––
–––
–––
–––
–––
Typ.
–––
205
57
104
101
67
210
Max. Units
Conditions
–––
S VDS = 10V, ID = 100A
307
ID = 100A
VDS = 20V
–––
nC
VGS = 4.5V
–––
–––
–––
VDD = 20V
–––
ID = 30A
ns
–––
RG= 2.7
VGS = 4.5V
–––
td(off)
Turn-Off Delay Time
–––
222
tf
Ciss
Coss
Fall Time
Input Capacitance
Output Capacitance
–––
–––
–––
176
19680
2305
Crss
Reverse Transfer Capacitance
–––
1575
–––
Coss eff.(ER) Effective Output Capacitance (Energy Related)
–––
2690
–––
VGS = 0V, VDS = 0V to 32V
Coss eff.(TR) Output Capacitance (Time Related)
–––
3390
–––
VGS = 0V, VDS = 0V to 32V
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min.
Typ.
Max. Units
–––
–––
557
–––
–––
1440
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
VSD
Diode Forward Voltage
–––
–––
1.2
dv/dt
Peak Diode Recovery dv/dt
–––
2.0
–––
trr
Reverse Recovery Time
–––
42
–––
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
–––
–––
–––
–––
43
43
45
1.7
–––
–––
–––
–––
–––
–––
VGS = 0V
VDS = 25V
pF ƒ = 1.0MHz, See Fig.7
Diode Characteristics
Symbol
IS
ISM
3
A
V
D
G
S
TJ = 25°C,IS =100A,VGS = 0V
V/ns TJ = 175°C,IS = 100A,VDS = 40V
ns
TJ = 25°C
VDD = 34V
TJ = 125°C
IF = 100A,
TJ = 25°C di/dt = 100A/µs
nC
TJ = 125°C
A TJ = 25°C
2017-05-12
IRL40SC228
1000
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
3.25V
100
TOP
60µs PULSE WIDTH
Tj = 25°C
BOTTOM
VGS
15V
10V
6.0V
5.0V
4.5V
4.0V
3.5V
3.25V
3.25V
100
60µs PULSE WIDTH
Tj = 175°C
BOTTOM
10
10
0.1
1
10
0.1
100
1000
100
2.2
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
100
TJ = 175°C
TJ = 25°C
10
1
V DS = 10V
60µs PULSE WIDTH
0.1
ID = 100A
V GS = 10V
1.8
1.4
1.0
0.6
0
1
2
3
4
5
-60
V GS, Gate-to-Source Voltage (V)
C oss = C ds + C gd
Ciss
10000
60
100
140
180
14
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
100000
20
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
1000000
-20
TJ , Junction Temperature (°C)
V GS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Coss
Crss
1000
12
ID= 100A
V DS= 32V
10
V DS= 20V
V DS= 8V
8
6
4
2
0
100
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
4
VGS
15V
10V
6.0V
5.0V
4.5V
4.0V
3.5V
3.25V
TOP
0
50 100 150 200 250 300 350 400 450 500
QG, Total Gate Charge (nC)
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
2017-05-12
IRL40SC228
OPERATION IN THIS AREA
LIMITED BY RDS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
TJ = 175°C
TJ = 25°C
10
1
1000
100µsec
100
1msec
10
LIMITED BY PACKAGE
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V GS = 0V
0.1
0.1
0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
1.0
10.0
V DS , Drain-toSource Voltage (V)
V SD, Source-to-Drain Voltage (V)
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
52
2.0
Id = 5.0mA
50
1.6
48
1.2
Energy (µJ)
V (BR)DSS, Drain-to-Source Breakdown Voltage (V)
DC
46
0.8
44
0.4
42
0.0
-60
-20
20
60
100
140
0
180
10
TJ , Temperature ( °C )
Fig 11. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( m )
20
30
40
V DS, Drain-to-Source Voltage (V)
Fig 12. Typical Coss Stored Energy
1.0
V GS = 3.5V
0.8
V GS = 4.5V
V GS = 6.0V
V GS = 8.0V
V GS = 10V
0.6
0.4
0
40
80
120
160
200
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
2017-05-12
IRL40SC228
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Avalanche Current vs. Pulse Width
1400
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 100A
EAR , Avalanche Energy (mJ)
1200
1000
800
600
400
200
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy vs. Temperature
6
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 14)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
2017-05-12
IRL40SC228
28
24
IF = 60A
V R = 34V
20
TJ = 25°C
TJ = 125°C
2.0
1.5
IRRM (A)
V GS(th) , Gate threshold Voltage (V)
2.5
ID = 250µA
ID = 1.0mA
ID = 1.0A
1.0
16
12
8
0.5
4
0.0
0
-75
-25
25
75
125
175
0
200
TJ , Temperature ( °C )
600
800
1000
diF /dt (A/µs)
Fig 18. Typical Recovery Current vs. dif/dt
Fig 17. Threshold Voltage vs. Temperature
2400
28
24
IF = 60A
V R = 34V
20
TJ = 25°C
TJ = 125°C
16
QRR (nC)
IRRM (A)
400
12
2000
IF = 60A
V R = 34V
1600
TJ = 25°C
TJ = 125°C
1200
800
8
400
4
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/µs)
diF /dt (A/µs)
Fig 19. Typical Recovery Current vs. dif/dt
Fig 20. Typical Stored Charge vs. dif/dt
QRR (nC)
2400
2000
IF = 100A
V R = 34V
TJ = 25°C
1600
TJ = 125°C
1200
800
400
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig 21. Typical Stored Charge vs. dif/dt
7
2017-05-12
IRL40SC228
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
L
VDS
D.U.T
RG
IAS
20V
tp
DRIVER
+
V
- DD
A
I AS
0.01
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Qgs1 Qgs2
Fig 25a. Gate Charge Test Circuit
8
Qgd
Qgodr
Fig 25b. Gate Charge Waveform
2017-05-12
IRL40SC228
D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches))
D2Pak - 7 Pin Part Marking Information
PART NUMBER
INTERNATIONAL
RECTIFIER LOGO
F1324S-7P
YWWP
17
ASSEMBLY
LOT CODE
9
89
DATE CODE
Y = YEAR
W = WEEK
P = LEADFREE
2017-05-12
IRL40SC228
Qualification Information
Qualification Level
Moisture Sensitivity Level
D2PAK-7Pin
Industrial
(per JEDEC JESD47F) †
MSL1
(per JEDEC J-STD-020D†)
Yes
RoHS Compliant
†
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
05/12/2017
Comments
Corrected package picture added “s” on pin number 4 - page 1.
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
10
2017-05-12
