IRLI2505

PD - 9.1327A IRLI2505 HEXFET® Power MOSFET Logic-Level Gate Drive Advanced Process Technology l Ultra Low On-Resistance l Isolated Package l High Voltage Isolation = 2.5KVRMS … l Sink to Lead Creepage Dist. = 4.8mm l Fully Avalanche Rated Description l D l VDSS = 55V RDS(on) = 0.008Ω G ID = 58A S Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. TO-220 FULLPAK Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current † Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ‚† Avalanche Current† Repetitive Avalanche Current Peak Diode Recovery dv/dt ƒ† Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw. Units 58 41 360 63 0.42 ±16 500 54 6.3 5.0 -55 to + 175 A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case) 10 lbf•in (1.1N•m) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient Min. Typ. Max. Units –––– –––– –––– –––– 2.4 65 °C/W 8/25/97 IRLI2505 Electrical Characteristics @ TJ = 25°C (unless otherwise specified) ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LD Internal Drain Inductance LS Internal Source Inductance Ciss Coss Crss C Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance IGSS Min. 55 ––– ––– ––– ––– 1.0 59 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 0.035 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 12 160 43 84 Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA† 0.008 VGS = 10V, ID = 31A „ 0.010 Ω VGS = 5.0V, ID = 31A „ 0.013 VGS = 4.0V, ID = 26A „ 2.0 V VDS = VGS , ID = 250µA ––– S VDS = 25V, I D = 54A† 25 VDS = 55V, VGS = 0V µA 250 VDS = 44V, VGS = 0V, TJ = 150°C 100 VGS = 16V nA -100 VGS = -16V 130 ID = 54A 25 nC VDS = 44V 67 VGS = 5.0V, See Fig. 6 and 13 „† ––– VDD = 28V ––– ID = 54A ns ––– RG = 1.3Ω, VGS = 5.0V ––– RD = 0.50Ω, See Fig. 10 „† Between lead, ––– 4.5 ––– 6mm (0.25in.) nH from package ––– 7.5 ––– and center of die contact ––– 5000 ––– VGS = 0V ––– 1100 ––– pF VDS = 25V ––– 390 ––– ƒ = 1.0MHz, See Fig. 5† ––– 12 ––– ƒ = 1.0MHz D G S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)  Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Notes:  Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ‚ VDD = 25V, starting TJ = 25°C, L = 240µH RG = 25Ω, IAS = 54A. (See Figure 12) Min. Typ. Max. Units Conditions MOSFET symbol ––– ––– 58 showing the A G integral reverse ––– ––– 360 p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 31A, VGS = 0V „ ––– 140 210 ns TJ = 25°C, IF = 54A ––– 650 970 nC di/dt = 100A/µs „ Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) ƒ ISD ≤ 54A, di/dt ≤ 230A/µs, VDD ≤ V(BR)DSS, D S … t=60s, ƒ=60Hz TJ ≤ 175°C „ Pulse width ≤ 300µs; duty cycle ≤ 2%. † Use IRL2505 data and test conditions IRLI2505 1000 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V 100 10 2 .5V 20 µ s PU LSE W ID TH T J = 2 5°C 1 0.1 1 10 100 2.5V 10 0.1 3.0 R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d ) I D , D r ain- to-S ourc e C urre nt (A ) T J = 2 5 °C T J = 1 7 5 °C 10 V DS = 2 5V 2 0 µ s P U L S E W ID T H 3.5 4.5 5.5 6.5 V G S , Ga te-to-S o urce V oltage (V ) Fig 3. Typical Transfer Characteristics 10 A 100 Fig 2. Typical Output Characteristics 1000 1 1 V D S , Drain-to-S ource Voltage (V ) Fig 1. Typical Output Characteristics 100 2 0µ s PU L SE W ID TH T J = 1 75 °C 1 A 100 V D S , Drain-to-Source V oltage (V ) 2.5 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP ID , D ra in -to -S o u rce C u rre n t (A ) ID , D ra in -to -S o u rc e C u rre n t (A ) TOP 7.5 A I D = 90 A 2.5 2.0 1.5 1.0 0.5 V G S = 10 V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 180 T J , Junction T emperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature IRLI2505 15 V GS C is s C rss C oss C , C a p a c ita n c e (p F ) 8000 = 0 V, f = 1M H z = C gs + C gd , Cds SH OR TE D = C gd = C d s + C gd V G S , G a te -to -S o u rce V o lta g e (V ) 10000 C i ss 6000 C o ss 4000 2000 C rs s 0 10 V DS = 44 V V DS = 28 V 12 9 6 3 FO R TEST CIR CU IT SEE FIG UR E 13 0 A 1 I D = 54A 0 100 80 120 160 A 200 Q G , T otal Gate C harge (nC ) V D S , D rain-to-S ource Voltage (V ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 OPE R ATIO N IN TH IS A RE A LIMITE D BY R DS (on) 1 0µs I D , D ra in C u rre n t (A ) I S D , R e v e rse D ra in C u rre n t (A ) 40 100 TJ = 175 °C T J = 25 °C 100 100 µs 1m s 10 10m s VG S = 0 V 10 0.4 0.8 1.2 1.6 2.0 2.4 V S D , S ource-to-Drain Voltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage A 2.8 T C = 25 °C T J = 17 5°C S ing le Pulse 1 1 A 10 100 V D S , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area IRLI2505 60 RD VDS VGS D.U.T. RG + -VDD 40 5.0V 30 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 20 Fig 10a. Switching Time Test Circuit VDS 10 90% 0 25 50 75 100 125 T C , Case Temperature 150 175 ( ° C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms (Z thJC) 10 Thermal Response ID , Drain Current (A) 50 D = 0.50 1 0.20 0.10 PDM 0.05 0.1 t1 0.02 t2 0.01 Notes: 1. Duty factor D = t1 / t 2 2. Peak T J = P DM x Z thJC + T C SINGLE PULSE (THERMAL RESPONSE) 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 10 IRLI2505 D.U.T. RG + V - DD IAS 5.0 V tp 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS E A S , S in g le P u ls e A va la n c h e E n e rg y (m J) 1200 L VDS TO P 1000 BO TTOM 800 600 400 200 0 V D D = 2 5V 25 tp ID 2 2A 38A 54 A 50 A 75 100 125 150 Starting TJ , Junction T emperature (°C) VDD Fig 12c. Maximum Avalanche Energy Vs. Drain Current VDS IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 175 IRLI2505 Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ƒ + ‚ - - „ +  • • • • RG Driver Gate Drive P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Period D= - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS ISD * IRLI2505 Package Outline TO-220 FullPak Outline Dimensions are shown in millimeters (inches) 10.60 (.41 7) 10.40 (.40 9) ø 3.40 (.133 ) 3.10 (.123 ) 4.8 0 (.189) 4.6 0 (.181) -A 3.70 (.145) 3.20 (.126) 16 .0 0 (.630) 15 .8 0 (.622) 2 .80 (.110) 2 .60 (.102) LE AD A S SIGN M E N T S 1 - GA TE 2 - D R AIN 3 - SO U R C E 7 .10 (.280) 6 .70 (.263) 1.15 (.04 5) M IN . N O T ES : 1 D IM EN SION IN G & T O LER A N C IN G PE R AN S I Y14.5 M , 1982 1 2 3 2 C O N TR OLLIN G D IM EN S ION : IN C H . 3.30 (.130 ) 3.10 (.122 ) -B- 13 .7 0 (.540) 13 .5 0 (.530) C A 1.40 (.05 5) 3X 1.05 (.04 2) 0.9 0 (.035) 3X 0.7 0 (.028) 0.25 (.010 ) 3X M A M 0.48 (.019) 0.44 (.017) 2.85 (.112 ) 2.65 (.104 ) B 2 .54 (.100) 2X D B M IN IM U M C R E EP AG E D IST A NC E B ET W E EN A-B -C -D = 4.80 (.189 ) Part Marking Information TO-220 FullPak E XAM PLE : T HIS IS A N IRF I840G W ITH AS SE MBLY LOT CODE E401 A INT ER NAT IONA L RE CTIF IER PA RT NU MBE R IRF I840G LOGO E 401 9 24 5 AS SE MBLY LOT COD E D ATE CODE (YYW W ) YY = YE AR W W = W E EK WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 8/97 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/