IRLIB9343PBF

IRLIB9343PbF   HEXFET® Power MOSFET Key Parameters Features  Advanced Process Technology  Key Parameters Optimized for Class-D Audio Amplifier Applications  Low RDSON for Improved Efficiency  Low QG and Qsw for Better THD and Improved Efficiency  Low Qrr for Better THD and Lower EMI  175°C Operating Junction Temperature for Ruggedness  Repetitive Avalanche Capability for Robustness and Reliability  Lead-Free VDS -55 V RDS(ON) typ. @ VGS =-10V 93 m RDS(ON) typ. @ VGS = -4.5V 150 m Qg typ. 31 nC TJ max 175 °C D S G TO-220 Full-Pak G Gate D Drain S Source Description This Digital Audio HEXFET® is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD and EMI. Additional features of this MosFET are 175°C operating junction temperature and repetitive avalanche capability. These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier applications. Base Part Number Package Type IRLIB9343PbF TO-220 Full-Pak Standard Pack Form Quantity Tube 50 Absolute Maximum Ratings Symbol Parameter VDS Drain-to-Source Voltage Gate-to-Source Voltage VGS ID @ TC = 25°C Continuous Drain Current, VGS @ -10V ID @ TC = 100°C Continuous Drain Current, VGS @ -10V IDM Pulsed Drain Current  PD @TC = 25°C Maximum Power Dissipation PD @TC = 100°C Maximum Power Dissipation Linear Derating Factor TJ Operating Junction and TSTG Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Thermal Resistance   Symbol Parameter Junction-to-Case  RJC Junction-to-Ambient (PCB Mount)  RJA 1 Orderable Part Number IRLIB9343PbF Max. -55 ± 20 -14 -10 -60 33 20 0.26 -40 to + 175 Units   300 10lbin (1.1Nm)     V  A  W W/°C °C  Typ. ––– ––– Max. 3.84 65 Units °C/W 2017-04-27 IRLIB9343PbF   Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage V(BR)DSS V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient gfs Qg Qgs Qgd Qgodr Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Trans conductance Total Gate Charge Pre-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive -1.0 ––– ––– ––– ––– ––– 5.3 ––– ––– ––– ––– Typ. ––– -52 93 150 ––– -3.7 ––– ––– ––– ––– ––– 31 7.1 8.5 15 Max. Units Conditions ––– V VGS = 0V, ID = -250µA ––– mV/°C Reference to 25°C, ID = -1mA 105 VGS = -10V, ID = -3.4A m 170 VGS = -4.5V, ID = -2.7A ––– V VDS = VGS, ID = -250µA ––– mV/°C -2.0 VDS = -55V, VGS = 0V µA   -25 VDS = -55V,VGS = 0V,TJ =125°C -100 VGS = -20V nA   100 VGS = 20V ––– S VDS = -25V, ID = -14A 47 VDS = -44V ––– ID = -14A, nC   ––– VGS = -10V See Fig. 6 and 19. ––– td(on) tr td(off) tf Ciss Coss Crss Coss eff. Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance ––– ––– ––– ––– ––– ––– ––– ––– 9.5 24 21 9.5 660 160 72 280 ––– ––– ––– ––– ––– ––– ––– ––– LD Internal Drain Inductance ––– 4.5 ––– LS Internal Source Inductance ––– 7.5 ––– RDS(on) Static Drain-to-Source On-Resistance VGS(th) VGS(th)/TJ Gate Threshold Voltage Gate Threshold Voltage Temp. Coefficient IDSS Drain-to-Source Leakage Current IGSS   Min. -55 ––– ––– Avalanche Characteristics  Parameter EAS Single Pulse Avalanche Energy  IAR Avalanche Current  EAR Repetitive Avalanche Energy  Diode Characteristics Parameter Continuous Source Current IS @ TC = 25°C (Body Diode) Pulsed Source Current ISM (Body Diode) VSD Diode Forward Voltage VDD = -28V, VGS = -10V  ID = -14A RG= 2.5 ns VGS = 0V VDS = -50V pF   ƒ = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 0V to –44V Between lead, 6mm (0.25in.) nH   from package and center of die contact Typ. ––– Max. 190 See Fig. 14, 15, 17a, 17b Max. Units Units mJ   A  mJ   Min. Typ. ––– ––– -14 ––– ––– -60 ––– ––– -1.2 V Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C,IS = -14A,VGS = 0V  A trr Reverse Recovery Time ––– 57 86 ns TJ = 25°C ,IF = -14A Qrr Reverse Recovery Charge ––– 120 180 nC di/dt = 100A/µs  Notes:      2 Repetitive rating; pulse width limited by max. junction temperature. starting TJ = 25°C, L = 3.89mH, RG = 25, IAS = -10A. Pulse width 400µs; duty cycle  2%. Rθ is measured at TJ of approximately 90°C. Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information 2017-04-27 IRLIB9343PbF   100 100 10 BOTTOM 1 -2.5V  60µs PULSE WIDTH Tj = 25°C 0.1 0.1 1 10 TOP -I D, Drain-to-Source Current (A) -I D, Drain-to-Source Current (A) TOP VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V 10 BOTTOM 1 -2.5V  60µs PULSE WIDTH Tj = 175°C 0.1 0.1 100 Fig. 1 Typical Output Characteristics 100 2.0 T J = 25°C R DS(on) , Drain-to-Source On Resistance (Normalized) -I D, Drain-to-Source Current ) 10 Fig. 2 Typical Output Characteristics 100.0 T J = 175°C 10.0 1.0 VDS = -25V  60µs PULSE WIDTH ID = -14A VGS = -10V 1.5 1.0 0.5 0.1 0.0 5.0 10.0 -60 -40 -20 15.0 20 -V GS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd Coss = Cds + Cgd 1000 Ciss Coss Crss 100 20 40 60 80 100 120 140 160 180 Fig. 4 Normalized On-Resistance vs. Temperature Fig. 3 Typical Transfer Characteristics 10000 0 T J , Junction Temperature (°C) -VGS, Gate-to-Source Voltage (V) C, Capacitance (pF) 1 -VDS, Drain-to-Source Voltage (V) -VDS, Drain-to-Source Voltage (V) ID= -14A 16 VDS= -44V VDS= -28V VDS= -11V 12 8 4 FOR TEST CIRCUIT SEE FIGURE 19 0 10 1 3 VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V 10 100 0 10 20 30 40 50 -VDS , Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 2017-04-27 IRLIB9343PbF   1000 T J = 175°C 10.0 T J = 25°C 1.0 OPERATION IN THIS AREA LIMITED BY R DS(on) -I D, Drain-to-Source Current (A) -ISD, Reverse Drain Current (A) 100.0 100 100µsec 10 VGS = 0V 0.1 10msec 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 -VSD , Source-to-Drain Voltage (V) 100 1000 -VDS , Drain-toSource Voltage (V) Fig. 7 Typical Source-to-Drain Diode Fig 8. Maximum Safe Operating Area 16 2.5 -V GS(th) Gate threshold Voltage (V) -I D , Drain Current (A) 1msec Tc = 25°C Tj = 175°C Single Pulse 12 8 4 2.0 ID = -250µA 1.5 1.0 0 25 50 75 100 125 150 -75 -50 -25 175 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) T J , Junction Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 D = 0.50 1 0.20 0.10 0.05 0.1 J 0.02 0.01 R1 R1 J 1 R2 R2 R3 R3 C 2 1 2 3 3 Ci= iRi Ci= iRi 0.01 SINGLE PULSE ( THERMAL RESPONSE ) C Ri (°C/W) i (sec) 0.8737 0.000799 0.877 0.068578 2.089 2.593 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 4  2017-04-27 IRLIB9343PbF 1000 600 EAS, Single Pulse Avalanche Energy (mJ) RDS(on), Drain-to -Source On Resistance ( m)   ID = -14A 500 400 300 T J = 125°C 200 100 T J = 25°C 0 4.0 6.0 8.0 ID -5.0A -5.6A BOTTOM -10A TOP 800 600 400 200 0 10.0 25 -VGS, Gate-to-Source Voltage (V) 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12. On-Resistance Vs. Gate Voltage Fig 13. Maximum Avalanche Energy Vs. Drain Current -Avalanche Current (A) 1000 100 Allowed avalanche Current vs avalanche pulsewidth, tav assuming  Tj = 25°C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax Duty Cycle = Single Pulse 0.01 10 0.05 0.10 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs. Pulse width EAR , Avalanche Energy (mJ) 200 TOP Single Pulse BOTTOM 1% Duty Cycle ID = -10A 160 120 80 40 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 15. Maximum Avalanche Energy vs. Temperature 5  Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 17a, 17b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC Iav = 2T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav 2017-04-27 IRLIB9343PbF   Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET® Power MOSFETs Fig 17a. Unclamped Inductive Test Circuit Fig 18a. Switching Time Test Circuit Fig 19a. Gate Charge Test Circuit 6  Fig 17b. Unclamped Inductive Waveforms Fig 18b. Switching Time Waveforms Fig 19b. Gate Charge Waveform 2017-04-27 IRLIB9343PbF   TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches)) TO-220 Full-Pak Part Marking Information TO-220AB Full-Pak packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 7  2017-04-27 IRLIB9343PbF   Qualification information Industrial Qualification level (per JEDEC JESD47F †guidelines ) Moisture Sensitivity Level N/A TO-220 Full-Pak (per JEDEC J-STD-020D† ) RoHS compliant † Yes Applicable version of JEDEC standard at the time of product release. Revision History Date 04/27/2017 Comments    Changed datasheet with Infineon logo - all pages. Corrected Package Outline on page 7. Added disclaimer on last page. Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2016-04-19 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? 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