PD - 95851
DIGITAL AUDIO MOSFET
IRLR4343
IRLU4343
IRLU4343-701
Features
Advanced Process Technology
Key Parameters Optimized for Class-D Audio
Amplifier Applications
l Low RDSON for Improved Efficiency
l Low Qg and Qsw for Better THD and Improved
Efficiency
l Low Qrr for Better THD and Lower EMI
l 175°C Operating Junction Temperature for
Ruggedness
l Repetitive Avalanche Capability for Robustness and
Reliability
l Multiple Package Options
l
Key Parameters
l
VDS
RDS(ON) typ. @ VGS = 10V
RDS(ON) typ. @ VGS = 4.5V
Qg typ.
TJ max
55
42
57
28
175
V
m:
m:
nC
°C
D
D-Pak
IRLR4343
I-Pak
IRLU4343
I-Pak Leadform 701
IRLU4343-701
Refer to page 10 for package outline
G
S
Description
This Digital Audio HEXFET® is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest
processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery
and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD
and EMI. Additional features of this MosFET are 175°C operating junction temperature and repetitive avalanche capability.
These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier
applications.
Absolute Maximum Ratings
Parameter
Max.
Units
V
VDS
Drain-to-Source Voltage
55
VGS
±20
ID @ TC = 25°C
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
19
IDM
Pulsed Drain Current c
80
PD @TC = 25°C
Power Dissipation
79
PD @TC = 100°C
Power Dissipation
39
Linear Derating Factor
0.53
W/°C
TJ
Operating Junction and
-40 to + 175
°C
TSTG
Storage Temperature Range
Clamping Pressure h
–––
N
26
A
W
Thermal Resistance
Parameter
Typ.
Max.
RθJC
Junction-to-Case g
–––
1.9
RθJA
Junction-to-Ambient (PCB Mounted) gj
Junction-to-Ambient (free air) g
–––
50
–––
110
RθJA
Units
°C/W
Notes through are on page 10
www.irf.com
1
3/26/04
IRLR/U4343 & IRLU4343-701
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min.
Conditions
Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
55
–––
–––
∆ΒVDSS/∆TJ
RDS(on)
Breakdown Voltage Temp. Coefficient
–––
15
–––
Static Drain-to-Source On-Resistance
–––
42
50
–––
57
65
V
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 4.7A e
VGS = 4.5V, ID = 3.8A e
VDS = VGS, ID = 250µA
VGS(th)
Gate Threshold Voltage
1.0
–––
–––
V
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
–––
-4.4
–––
mV/°C
Drain-to-Source Leakage Current
–––
–––
2.0
µA
VDS = 55V, VGS = 0V
–––
–––
25
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
VDS = 55V, VGS = 0V, TJ = 125°C
VGS = -20V
VDS = 25V, ID = 19A
gfs
Forward Transconductance
8.8
–––
–––
Qg
Total Gate Charge
–––
28
42
VDS = 44V
S
Qgs
Pre-Vth Gate-to-Source Charge
–––
3.5
–––
VGS = 10V
Qgd
Gate-to-Drain Charge
–––
9.5
–––
ID = 19A
Qgodr
Gate Charge Overdrive
–––
15
–––
td(on)
Turn-On Delay Time
–––
5.7
–––
See Fig. 6 and 19
VDD = 28V, VGS = 10Ve
tr
Rise Time
–––
19
–––
ID = 19A
td(off)
Turn-Off Delay Time
–––
23
–––
tf
Fall Time
–––
5.3
–––
Ciss
Input Capacitance
–––
740
–––
Coss
Output Capacitance
–––
150
–––
Crss
Reverse Transfer Capacitance
–––
59
–––
Coss
Effective Output Capacitance
–––
250
–––
ƒ = 1.0MHz,
See Fig.5
VGS = 0V, VDS = 0V to -44V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
ns
VGS = 0V
pF
nH
LS
Internal Source Inductance
–––
7.5
RG = 2.5Ω
–––
VDS = 50V
6mm (0.25in.)
D
G
from package
and center of die contact f
S
Avalanche Characteristics
Parameter
Typ.
Max.
Units
160
mJ
EAS
Single Pulse Avalanche Energyd
–––
IAR
Avalanche Currenti
See Fig. 14, 15, 17a, 17b
EAR
Repetitive Avalanche Energy i
A
mJ
Diode Characteristics
Parameter
IS @ TC = 25°C Continuous Source Current
Min.
Typ. Max. Units
–––
–––
(Body Diode)
ISM
Pulsed Source Current
A
–––
–––
Conditions
MOSFET symbol
26
showing the
80
integral reverse
VSD
Diode Forward Voltage
–––
–––
1.2
V
p-n junction diode.
TJ = 25°C, IS = 19A, VGS = 0V e
trr
Reverse Recovery Time
–––
52
78
ns
TJ = 25°C, IF = 19A
Qrr
Reverse Recovery Charge
–––
100
150
nC
di/dt = 100A/µs e
(Body Diode)c
2
www.irf.com
IRLR/U4343 & IRLU4343-701
1000
1000
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.3V
100
BOTTOM
10
2.3V
1
≤ 60µs PULSE WIDTH
Tj = 25°C
100
BOTTOM
10
2.3V
1
≤ 60µs PULSE WIDTH
Tj = 175°C
0.1
0.1
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000.0
ID, Drain-to-Source Current (Α)
1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
T J = 25°C
100.0
T J = 175°C
10.0
1.0
VDS = 30V
≤ 60µs PULSE WIDTH
0.1
0
2
4
6
8
10
ID = 19A
VGS = 10V
2.0
1.5
1.0
0.5
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
10000
20
VGS, Gate-to-Source Voltage (V)
C oss = C ds + C gd
Ciss
Coss
Crss
100
20 40 60 80 100 120 140 160 180
Fig 4. Normalized On-Resistance vs. Temperature
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
1000
0
T J , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.3V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
ID= 19A
VDS= 44V
VDS= 28V
VDS= 11V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 19
0
10
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
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0
10
20
30
40
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
3
IRLR/U4343 & IRLU4343-701
1000
1000.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100.0
T J = 175°C
10.0
1.0
T J = 25°C
100
100µsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
10msec
1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
1.8
1
10
100
1000
VSD, Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
2.0
VGS(th) Gate threshold Voltage (V)
30
ID , Drain Current (A)
25
20
15
10
5
1.5
ID = 250µA
1.0
0
0.5
25
50
75
100
125
150
175
-75
-50
T J , Junction Temperature (°C)
-25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 10. Threshold Voltage vs. Temperature
Fig 9. Maximum Drain Current vs. Case Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
τJ
0.02
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τC
τ
τ2
Ri (°C/W)
1.359
0.5409
τi (sec)
0.00135
0.003643
Ci= τi/Ri
Ci i/Ri
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
www.irf.com
700
200
EAS, Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance ( mΩ)
IRLR/U4343 & IRLU4343-701
ID = 19A
150
100
T J = 125°C
50
T J = 25°C
0
2.0
4.0
6.0
8.0
ID
2.4A
3.3A
BOTTOM 19A
TOP
600
500
400
300
200
100
0
10.0
25
VGS, Gate-to-Source Voltage (V)
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13. Maximum Avalanche Energy Vs. Drain Current
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
10
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 14. Typical Avalanche Current Vs.Pulsewidth
180
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 19A
EAR , Avalanche Energy (mJ)
160
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
5
IRLR/U4343 & IRLU4343-701
Driver Gate Drive
D.U.T
+
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
InductorInductor
Curent
Current
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
15V
LD
VDS
DRIVER
L
VDS
+
VDD -
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
D.U.T
A
VGS
0.01Ω
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 17a. Unclamped Inductive Test Circuit
V(BR)DSS
Fig 18a. Switching Time Test Circuit
VDS
tp
90%
10%
VGS
td(on)
I AS
Fig 17b. Unclamped Inductive Waveforms
tr
td(off)
tf
Fig 18b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
1K
Qgs1 Qgs2
Fig 19a. Gate Charge Test Circuit
6
Qgd
Qgodr
Fig 19b Gate Charge Waveform
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IRLR/U4343 & IRLU4343-701
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
1
2
LEAD ASSIGNMENTS
1 - GATE
3
0.51 (.020)
MIN.
-B1.52 (.060)
1.15 (.045)
3X
2X
1.14 (.045)
0.76 (.030)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - DRAIN
3 - SOURCE
4 - DRAIN
0.58 (.023)
0.46 (.018)
M A M B
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4.57 (.180)
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS SEMBLY
LOT CODE 9U1P
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
9U
016
1P
DAT E CODE
YEAR = 0
WEEK = 16
AS S EMBLY
LOT CODE
Notes : This part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS SEMBLY
LOT CODE 1234
ASS EMBLED ON WW 16, 1999
IN T HE AS SEMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
12
ASS EMBLY
LOT CODE
www.irf.com
PART NUMBER
916A
34
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
7
IRLR/U4343 & IRLU4343-701
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A-
0.58 (.023)
0.46 (.018)
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
LEAD ASSIGNMENTS
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
3
-B-
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045)
0.76 (.030)
2.28 (.090)
3X
1.14 (.045)
0.89 (.035)
0.89 (.035)
0.64 (.025)
0.25 (.010)
M A M B
2X
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 9U1P
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
016
9U
1P
DAT E CODE
YEAR = 0
WEEK = 16
AS S EMBLY
LOT CODE
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 5678
AS SEMBLED ON WW 19, 1999
IN T HE AS S EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
8
PART NUMBER
IRFU120
919A
56
78
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
www.irf.com
IRLR/U4343 & IRLU4343-701
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
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9
IRLR/U4343 & IRLU4343-701
I-Pak Leadform Option 701 Package Outline
Dimensions are shown in millimeters (inches)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.93mH,
RG = 25Ω, IAS = 19A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This only applies for I-Pak, LS of D-Pak is
measured between lead and center of die contact
Rθ is measured at TJ of approximately 90°C.
Contact factory for mounting information
Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information
When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Refer to D-Pak package for Part Marking, Tape and Reel information.
Data and specifications subject to change without notice.
This product has been designed for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.3/04
10
www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/