PD - 97360
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
IRLR8259PbF
IRLU8259PbF
HEXFET® Power MOSFET
VDSS
RDS(on) max
Qg
25V
8.7mΩ
6.8nC
D
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l Lead-Free
l RoHS compliant
S
S
D
G
G
D-Pak
I-Pak
IRLR8259PbF IRLU8259PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Parameter
Max.
Units
25
V
VDS
Drain-to-Source Voltage
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
57
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
230
ID @ TC = 25°C
ID @ TC = 100°C
IDM
c
PD @TC = 100°C
g
Maximum Power Dissipation g
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
PD @TC = 25°C
f
40f
Maximum Power Dissipation
A
48
W
24
W/°C
°C
0.32
-55 to + 175
Soldering Temperature, for 10 seconds
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
g
Typ.
Max.
–––
3.15
–––
50
–––
110
Units
°C/W
ORDERING INFORMATION:
See detailed ordering and shipping information on the last page of this data sheet.
Notes through
are on page 11
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1
12/16/08
IRLR/U8259PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
25
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
–––
–––
–––
18
–––
–––
6.3
8.7
–––
10.6
12.9
V
mV/°C Reference to 25°C, ID = 1mA
mΩ
Gate Threshold Voltage
1.35
1.90
2.35
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-7.1
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
–––
–––
150
IGSS
gfs
Qg
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
55
–––
–––
Conditions
VGS = 0V, ID = 250µA
µA
nA
S
VGS = 10V, ID = 21A
VGS = 4.5V, ID = 17A
e
e
VDS = VGS, ID = 25µA
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VDS = 13V, ID = 17A
Total Gate Charge
–––
6.8
10
Qgs1
Pre-Vth Gate-to-Source Charge
–––
1.5
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.1
–––
Qgd
Gate-to-Drain Charge
–––
2.4
–––
ID = 17A
Qgodr
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
1.8
–––
See Fig. 16
Qsw
–––
3.5
–––
Qoss
Output Charge
–––
5.9
–––
nC
RG
td(on)
Gate Resistance
2.2
8.4
3.6
–––
Ω
Turn-On Delay Time
–––
–––
tr
Rise Time
–––
38
–––
td(off)
Turn-Off Delay Time
–––
9.1
–––
tf
Fall Time
–––
8.9
–––
Ciss
Input Capacitance
–––
900
–––
Coss
Output Capacitance
–––
300
–––
Crss
Reverse Transfer Capacitance
–––
110
–––
VDS = 13V
nC
VGS = 4.5V
VDS = 16V, VGS = 0V
VDD = 13V, VGS = 4.5V
ns
ID = 17A
e
RG = 1.8Ω
See Fig. 14
VGS = 0V
pF
VDS = 13V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
EAS
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
Typ.
–––
d
c
Max.
67
Units
mJ
–––
17
A
–––
4.8
mJ
Diode Characteristics
Parameter
IS
Continuous Source Current
Min. Typ. Max. Units
–––
–––
–––
–––
(Body Diode)
ISM
Pulsed Source Current
c
(Body Diode)
f
56
A
230
VSD
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
17
26
ns
Qrr
Reverse Recovery Charge
–––
15
23
nC
ton
2
Forward Turn-On Time
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 17A, VGS = 0V
TJ = 25°C, IF = 17A, VDD = 13V
di/dt = 200A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRLR/U8259PbF
1000
1000
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
2.5V
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
10
2.5V
1
≤60µs PULSE WIDTH
BOTTOM
10
2.5V
≤60µs PULSE WIDTH
Tj = 25°C
0.1
1
10
0.1
100
1
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
Tj = 175°C
1
0.1
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
2.5V
100
T J = 175°C
10
T J = 25°C
1
VDS = 15V
≤60µs PULSE WIDTH
0.1
ID = 21A
VGS = 10V
1.5
1.0
0.5
1
2
3
4
5
6
7
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRLR/U8259PbF
10000
5.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 17A
C, Capacitance (pF)
Coss = Cds + Cgd
Ciss
1000
Coss
VDS= 20V
VDS= 13V
4.0
3.0
2.0
1.0
Crss
100
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
3
4
5
6
7
8
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
1000
ISD, Reverse Drain Current (A)
2
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
100
T J = 175°C
10
T J = 25°C
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
100
1msec
10msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1
0.1
0.0
0.5
1.0
1.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1
2.0
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U8259PbF
2.5
60
VGS(th) , Gate threshold Voltage (V)
Limited By Package
ID, Drain Current (A)
50
40
30
20
10
2.0
1.5
ID = 25µA
1.0
0.5
0
25
50
75
100
125
150
-75 -50 -25
175
0
25 50 75 100 125 150 175
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
τJ
R1
R1
τJ
τ1
τ1
R2
R2
τ2
R3
R3
τ2
1E-005
τ3
τ4
τ4
τi (sec)
0.08148
0.000017
0.88089
0.000107
1.48814
0.001018
0.69949
0.006290
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
Ri (°C/W)
τC
τ
τ3
Ci= τi/Ri
Ci i/Ri
0.01
R4
R4
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U8259PbF
300
D.U.T
RG
VGS
20V
DRIVER
L
VDS
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
15V
ID
4.2A
6.4A
BOTTOM 17A
TOP
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
V DS
VGS
RG
Current Regulator
Same Type as D.U.T.
D.U.T.
+
-V DD
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ
12V
RD
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
10%
VGS
td(on)
Fig 13. Gate Charge Test Circuit
6
tr
t d(off)
tf
Fig 14b. Switching Time Waveforms
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IRLR/U8259PbF
D.U.T
Driver Gate Drive
P.W.
+
+
-
-
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
Fig 16. Gate Charge Waveform
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7
IRLR/U8259PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
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