IRLR8503PBF

PD- 95095A IRLR8503PbF IRLR8503PbF • • • • N-Channel Application-Specific MOSFET Ideal for CPU Core DC-DC Converters Low Conduction Losses Minimizes Parallel MOSFETs for high current applications • Lead-Free HEXFET® MOSFET for DC-DC Converters D Description This new device employs advanced HEXFET Power MOSFET technology to achieve very low on-resistance. The reduced conduction losses makes it ideal for high efficiency DC-DC converters that power the latest generation of microprocessors. The IRLR8503 has been optimized and is 100% tested for all parameters that are critical in synchronous buck converters including RDS(on), gate charge and Cdv/dtinduced turn-on immunity. The IRLR8503 offers an extremely low combination of Qsw & RDS(on) for reduced losses in control FET applications. The package is designed for vapor phase, infra-red, convection, or wave soldering techniques. Power dissipation of greater than 2W is possible in a typical PCB mount application. G S D-Pak DEVICE RATINGS (MAX. Values) IRLR8503PbF VDS RDS(on) 30V 18 mΩ QG 20 nC Qsw 8 nC Qoss 29.5 nC Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain or Source Current (VGS ≥ 10V)… TC = 25°C IRLR8503 Units VDS 30 V VGS ±20 ID 44 TC = 90°C Pulsed Drain Current Power Dissipation… Symbol TC = 25°C A 32 IDM 196 PD 62 TC = 90°C W 30 TJ, TSTG –55 to 150 °C Continuous Source Current (Body Diode) IS 15 A Pulsed source Current  ISM 196 Symbol Max. Units Maximum Junction-to-Ambientƒ R θJA 50 °C/W Maximum Junction-to-Lead R θJL 2.0 °C/W Junction & Storage Temperature Range Thermal Resistance Parameter www.irf.com 1 12/06/04 IRLR8503PbF Electrical Characteristics Parameter Symbol Min Typ Max Units Drain-to-Source Breakdown Voltage* Static Drain-Source V(BR)DSS 30 – – V VGS = 0V, ID = 250µA RDS (on) – 11 16 mΩ VGS = 10V, ID =15A‚ – 13 18 Gate Threshold Voltage* VGS(th) 1.0 Drain-Source Leakage Current IDSS on Resistance* – – 30* – – 150 Conditions VGS = 4.5V, ID =15A V VDS = VGS, ID = 250µA µA VDS = 24V, VGS = 0 VDS = 24V, VGS = 0, Tj = 100°C Gate-Source Leakage Current* IGSS – – ±100 nA VGS = ±12V Total Gate Charge Control FET* Qg – 15 20 VGS= 5V, ID= 15A, VDS =16V, Total Gate Charge Sync FET* Qg – 13 17 VGS = 5V, VDS < 100mV Pre-Vth Gate-Source Charge Qgs1 – 3.7 – VDS = 16V, ID = 15A Post-Vth Gate-Source Charge Qgs2 – 1.3 – Gate to Drain Charge Qgd – 4.1 – Switch Charge* (Qgs2 + Qgd) Q SW – 5.4 8 Output Charge* Qoss – 23 29.5 Gate Resistance Rg – 1.7 – Turn-on Delay Time td (on) – 10 – Drain Voltage Rise Time trv – 18 – Turn-off Delay Time td (off) – 11 – Clamped Inductive Load Drain Voltage Fall Time tfv – 3 – See test diagram Fig 14. Input Capacitance Ciss – 1650 – Output Capacitance Coss – 650 – Reverse Transfer Capacitance Crss – 58 – Min Typ Max Units 1.0 V nC VDS = 16V, VGS = 0 Ω VDD = 16V, ID = 15A ns pF VGS = 5V VDS = 25V, VGS = 0 Source-Drain Rating & Characteristics Parameter Symbol Diode Forward Voltage* VSD – Reverse Recovery Charge„ Q rr – 76 nC Conditions IS = 15A‚, VGS = 0V di/dt = 700A/µs VDS = 16V, VGS = 0V, IS = 15A Reverse Recovery Charge (with Parallel Schottky)„ Qrr(s) – 67 di/dt = 700A/µs (with 10BQ040) VDS = 16V, VGS = 0V, IS = 15A Notes:  ‚ ƒ * 2 „ Typ = measured - Qoss Repetitive rating; pulse width limited by max. junction temperature. … Calculated continuous current based on maximum allowable Pulse width ≤ 300 µs; duty cycle ≤ 2%. Junction temperature; switching and other losses will When mounted on 1 inch square copper board, t < 10 sec. decrease RMS current capability; package limitation current = 20A. Devices are 100% tested to these parameters. www.irf.com IRLR8503PbF Power MOSFET Optimization for DC-DC Converters While the IRLR8103V and IRLR8503 can and are being used in a variety of applications, they were designed and optimized for low voltage DC-DC conversion in a synchronous buck converter topology, specifically, microprocessor power applications. The IRLR8503 (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. IRLR8503 (Cont FET) Table 2 – New Charge Parameters New Charge Parameter Description QGS1 Pre-Threshold Gate Charge Waveform QGS2 Post-Threshold Gate Charge QGCONT Control FET Total QG Figure 3 QSWITCH Charge during control FET switching Combines QGS2 and QGD Q OSS Output charge Charge supplied to COSS during the QGD period of control FET switching Figure 5 Figure 6 QGSYNC Synchronous FET Total QG (VDS ≤ 0) Figure 4 Drain Voltage CGD Drain Voltage CGS IRLR8103V (Sync FET) QSwitch QGD Figure 2 – Inter-electrode Capacitance Because of the inter-electrode capacitance (Figure 2) of the Power MOSFET, specifying the RDSON of the device is not enough to ensure good performance. An optimization between RDSON and charge must be performed to insure the best performing MOSFET for a given application. Both die size and device architecture must be varied to achieve the minimum possible in-circuit losses. This is independently true for both control FET and synchronous FET. Unfortunately, the capacitances of a FET are non-linear and voltage dependent. Therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. This was well understood years ago and resulted in changing the emphasis from capacitance to gate charge on Power MOSFET data sheets. Table 1 – Traditional Charge Parameters Device Capacitance Corresponding Charge Parameter C GS QGS CGS + CGD QG C GD QGD International Rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to DC-DC converter design (Table 2). In order to understand these parameters, it is best to start with the in-circuit waveforms in Figure 3 & Figure 4. 0V Gate Voltage QGS1 QGS2 VGTH Figure 1 – Application Topology www.irf.com QG (Control FET) CDS Dead Time Gate Voltage VGTH QG (Sync FET) 0A Drain Current Figure 3 – Control FET Waveform Body Diode Current Drain Current Figure 4 – Sync FET Waveform The waveforms are broken into segments corresponding to charge parameters. These, in turn, correspond to discrete time segments of the switching waveform. VIN g1 N1 Cont FET Coss1 2n SN g2 N2 Sync FET Coss2 2n Figure 5 – QOSS Equivalent Circuit Switch node voltage (VSN) N1 Gate Voltage N1 Current N1 Coss Discharge + N2 Coss Charge Figure 6 – QOSS Waveforms Losses may be broken into four categories: conduction loss, gate drive loss, switching loss, and output loss. The following simplified power loss equation is true for both MOSFETs in a synchronous buck converter: PLOSS = PCONDUCTION + PGATE DRIVE + PSWITCH + POUTPUT For the synchronous FET, the PSWITCH term becomes virtually zero and is ignored. 3 IRLR8503PbF Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that period. Table 3 – Control FET Losses Description Segment Losses 2 Conduction Losses associated with MOSFET on time. IRMS is a function of load P COND = I RMS × R DS ( on) current and duty cycle. Loss Gate Drive Losses associated with charging and discharging the gate of the PIN = VG × QG × ƒ MOSFET every cycle. Use the control FET QG. Loss Switching Loss Output Loss Losses during the drain voltage and drain current transitions for every full cycle. Losses occur during the QGS2 and QGD time period and can be simplified by using Qswitch. Output Loss Q GS 2 ׃ IG PQGD ≈ VIN × IL × Q GD ׃ IG PSWITCH ≈ VIN × IL Q SW ׃ IG Losses associated with the QOSS of the device every cycle when the control Q FET turns on. Losses are caused by both FETs, but are dissipated by the control POUTPUT = OSS × VIN × F 2 FET. Table 4 – Synchronous FET Losses Description Conduction Losses associated with MOSFET on time. IRMS is a function of load current and Loss duty cycle. Gate Drive Losses associated with charging and discharging the gate of the MOSFET every Loss cycle. Use the Sync FET QG. Switching Loss PQGS 2 ≈ VIN × IL × Generally small enough to ignore except at light loads when the current reverses in the output inductor. Under these conditions various light load power saving techniques are employed by the control IC to maintain switching losses to a negligible level. Segment Losses 2 PCOND = IRMS × RDSon PIN = VG × QG × ƒ PSWITCH ≈ 0 Losses associated with the QOSS of the device every cycle when the control FET Q turns on. They are caused by the synchronous FET, but are dissipated in the control POUTPUT = OSS × VIN × ƒ 2 FET. Typical PC Application The IRLR8103V and the IRLR8503 are suitable for Synchronous Buck DC-DC Converters, and are optimized for use in next generation CPU applications. The IRLR8103V is primarily optimized for use as the low side synchronous FET (Q2) with low RDS(on) and high CdV/dt immunity.The IRLR8503 is primarily optimized for use as the high side control FET (Q2) with low cobmined Qsw and RDS(on) , but can also be used as a synchronous FET. The IRLR8503 is also tested for Cdv/dt immunity, critical for the low side socket. The typical configuration in which these devices may be used in shown in Figure 7. IRLR8503 Control FET (Q1) 1 x IRLR8103Vor or 2 x IRLR8503 Synchronous FET (Q2) Figure 7. 2 & 3-FET solution for Synchronous Buck Topology. 4 www.irf.com IRLR8503PbF Typical Characteristics IRLR8503 6.0 VGS, Gate-to-Source Voltage (V) ID = 15A VGS = 4.5V 2.0 (Normalized) R DS(on) , Drain-to-Source On Resistance 2.5 1.5 1.0 ID = 15A VDS = 20V 4.0 2.0 0.0 0.5 -60 -40 -20 0 20 40 60 0 80 100 120 140 160 4 2500 0.014 VGS Ciss Crss Coss 2000 C, Capacitance (pF) R DS(on) , Drain-to -Source On Resistance ( Ω) 0.015 0.013 0.012 ID = 15A 1000 0.010 0 6.0 7.0 8.0 9.0 = = = = 0V, f = 1MHz Cgs + Cgd , Cds SHORTED Cgd Cds + Cgd Ciss 500 5.0 16 1500 0.011 4.0 12 Figure 9. Gate-to-Source Voltage vs. Typical Gate Charge Figure 8. Normalized On-Resistance vs. Temperature 3.0 8 QG, Total Gate Charge (nC) T J , Junction Temperature ( °C ) 10.0 11.0 12.0 Coss Crss 1 10 100 V DS , Drain-to-Source Voltage (V) VGS, Gate -to -Source Voltage (V) Figure 11. Typical Capacitance vs. Drain-to-Source Voltage Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage 1000.0 ID, Drain-to-Source Current (Α ) 100 100.0 T J = 150°C 10.0 T J = 25°C VDS = 15V 20µs PULSE WIDTH 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VGS, Gate-to-Source Voltage (V) Figure 12. Typical Transfer Characteristics www.irf.com 5 IRLR8503PbF Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 PDM 0.05 0.1 0.02 0.01 0.01 0.00001 t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x ZthJC + TC 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Inductive Load Circuit Figure 15. Switching waveform Figure 14. Clamped Inductive Load test diagram 6 www.irf.com IRLR8503PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WITH AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN THE AS S EMBLY LINE "A" PART NUMBER INTERNATIONAL RECTIFIER LOGO Note: "P" in as sembly line pos ition indicates "Lead-Free" IRFU120 12 916A 34 AS S EMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRFU120 12 AS S EMBLY LOT CODE www.irf.com 34 DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S ITE CODE 7 IRLR8503PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed and qualified for the commercial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 8 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/