PD -97371
IRLS4030-7PPbF
Applications
l DC Motor Drive
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
HEXFET® Power MOSFET
D
G
S
VDSS
RDS(on) typ.
max.
ID
Benefits
l Optimized for Logic Level Drive
l Very Low RDS(ON) at 4.5V VGS
l Superior R*Q at 4.5V VGS
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
100V
3.2mΩ
3.9mΩ
190A
D
S
G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current c
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery e
Operating Junction and
Storage Temperature Range
Max.
Units
190
130
750
A
W
370
2.5
± 16
W/°C
V
13
-55 to + 175
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
10lbxin (1.1Nxm)
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy d
Avalanche Current c
Repetitive Avalanche Energy f
320
See Fig. 14, 15, 22a, 22b
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθJA
www.irf.com
Typ.
Max.
Units
Junction-to-Case jk
Parameter
–––
°C/W
Junction-to-Ambient (PCB Mount) ij
–––
0.40
40
1
02/12/09
IRLS4030-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
Min. Typ. Max. Units
VGS(th)
IDSS
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
100
–––
–––
–––
1.0
–––
–––
–––
–––
RG(int)
Internal Gate Resistance
–––
–––
0.10
3.2
3.3
–––
–––
–––
–––
–––
–––
–––
3.9
4.1
2.5
20
250
100
-100
2.0
–––
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 5mAc
mΩ VGS = 10V, ID = 110A f
VGS = 4.5V, ID = 94A f
V VDS = VGS, ID = 250µA
µA VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
nA VGS = 16V
VGS = -16V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
250 ––– –––
–––
93
140
–––
27
–––
–––
43
–––
–––
50
–––
–––
53
–––
––– 160 –––
––– 110 –––
–––
87
–––
––– 11490 –––
––– 680 –––
––– 300 –––
Effective Output Capacitance (Energy Related)h ––– 760 –––
––– 1170 –––
Effective Output Capacitance (Time Related)g
S
nC
ns
pF
Conditions
VDS = 25V, ID = 110A
ID = 110A
VDS = 50V
VGS = 4.5V f
ID = 110A, VDS =0V, VGS = 4.5V
VDD = 65V
ID = 110A
RG = 2.7Ω
VGS = 4.5V f
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V h
VGS = 0V, VDS = 0V to 80V g
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)c
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.05mH
RG = 25Ω, IAS = 110A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 110A, di/dt ≤ 1520A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
–––
–––
190
–––
–––
750
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
S
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 110A, VGS = 0V f
VR = 85V,
–––
53
–––
ns TJ = 25°C
TJ = 125°C
IF = 110A
–––
63
–––
di/dt = 100A/µs f
–––
99
–––
nC TJ = 25°C
TJ = 125°C
––– 155 –––
–––
3.3
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
www.irf.com
IRLS4030-7PPbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
BOTTOM
100
10
2.5V
2.5V
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
10
1
0.1
1
10
100
0.1
1000
Fig 1. Typical Output Characteristics
10
100
1000
Fig 2. Typical Output Characteristics
1000
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
T J = 175°C
100
10
T J = 25°C
1
VDS = 25V
≤60µs PULSE WIDTH
0.1
ID = 110A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
5.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 110A
C oss = C ds + C gd
C, Capacitance (pF)
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
Ciss
10000
Coss
1000
Crss
4.0
VDS= 80V
VDS= 50V
3.0
2.0
1.0
0.0
100
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
www.irf.com
0
20
40
60
80
100
120
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRLS4030-7PPbF
10000
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
T J = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
1msec
10msec
10
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
1
2.0
180
ID, Drain Current (A)
160
140
120
100
80
60
40
20
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
200
50
Id = 5mA
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
4.0
EAS , Single Pulse Avalanche Energy (mJ)
1400
3.5
ID
12A
16A
BOTTOM 110A
1200
3.0
TOP
1000
2.5
Energy (µJ)
1000
125
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
2.0
1.5
1.0
0.5
0.0
800
600
400
200
0
-20
0
20
40
60
80
100
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
10
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
120
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
www.irf.com
IRLS4030-7PPbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
τJ
R1
R1
τJ
τ1
R2
R2
τC
τ2
τ1
τC
Ri (°C/W) τi (sec)
0.176
0.000343
0.227
τ2
0.006073
C i= τi /R i
Ci= τ i/ Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
400
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 110A
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRLS4030-7PPbF
30
2.5
25
IF = 75A
V R = 85V
2.0
20
TJ = 25°C
TJ = 125°C
1.5
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
3.0
ID = 250µA
ID = 1.0mA
10
ID = 1.0A
1.0
15
5
0.5
0
0.0
-75 -50 -25
0
0
25 50 75 100 125 150 175
200
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
30
1400
25
IF = 110A
V R = 85V
20
TJ = 25°C
TJ = 125°C
IF = 75A
V R = 85V
1200
TJ = 25°C
TJ = 125°C
1000
QRR (A)
IRRM (A)
400
diF /dt (A/µs)
T J , Temperature ( °C )
15
10
800
600
400
5
200
0
0
0
200
400
600
800
1000
0
diF /dt (A/µs)
200
400
600
800
1000
diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
1600
IF = 110A
V R = 85V
1400
TJ = 25°C
TJ = 125°C
1200
QRR (A)
1000
800
600
400
200
0
0
200
400
600
800
1000
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
www.irf.com
IRLS4030-7PPbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
www.irf.com
Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRLS4030-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
8
www.irf.com
IRLS4030-7PPbF
D2Pak - 7 Pin Part Marking Information
14
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/09
9
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
