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IRS2011PBF

IRS2011PBF

  • 厂商:

    EUPEC(英飞凌)

  • 封装:

    DIP8

  • 描述:

    IC GATE DRVR HALF-BRIDGE 8DIP

  • 数据手册
  • 价格&库存
IRS2011PBF 数据手册
IRS2011(S)PBF High and Low Side Driver Features           Product Summary Floating channel designed for bootstrap operation Fully operational to 200V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 to 20V Independent low and high side channels Input logic HIN/LIN active high Undervoltage lockout for both channels 3.3V and 5V logic compatible CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels Description VOFFSET (max) 200V IO+/- (typ) 1.0A / 1.0A VOUT 10 – 20V ton/off (typ) 60ns Delay Matching (max) 20ns Package Options The IRS2011 is a high power, high speed power MOSFET driver with independent high and low side referenced output channels. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET in the high side configuration which operates up to 200 volts. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. 8-Lead PDIP 8-Lead SOIC Applications   Converters DC motor drive Ordering Information Standard Pack Base Part Number Package Type IRS2011PBF IRS2011SPBF IRS2011SPBF 1 www.irf.com PDIP8 SO8N Form Tube Tube Quantity 50 95 SO8N Tape and Reel 2500 © 2015 International Rectifier Orderable Part Number IRS2011PBF IRS2011SPBF IRS2011STRPBF October 28, 2015 IRS2011(S)PBF Typical Connection Diagram (Refer to Lead Assignments for correct configuration.) This diagram shows electrical connections only. Please refer to our Application Notes and Design Tips for proper circuit board layout. 2 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VIN dVs/dt PD RthJA TJ TS TL † Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic input voltage (HIN, LIN) Allowable offset supply voltage transient 8-Lead PDIP Package power dissipation @ TA ≤ +25°C 8-Lead SOIC 8-Lead PDIP Thermal resistance, junction to ambient 8-Lead SOIC Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. -0.3 VB - 20 VS - 0.3 -0.3 -0.3 -0.3 — — — — — — -55 — Max. † 220 VB + 0.3 VB + 0.3 † 20 VCC + 0.3 VCC + 0.3 50 1.0 0.625 125 200 150 150 300 Units V V/ns W °C/W °C All supplies are fully tested at 25V and an internal 20V clamp exists for each supply Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings are tested with all supplies biased at 15V differential. Symbol VB VS VHO VCC VLO VIN TA †† Definition High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic input voltage (HIN, LIN) Ambient temperature Min. Max. VS + 10 VS + 20 200 VB 20 VCC VCC 125 †† VS 10 0 COM -40 Units V °C Logic operational for VS of -5 to +200V. Logic state held for VS of -5V to -VBS. 3 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, CL = 1000pF and TA = 25°C unless otherwise specified. Figure 1 shows the timing definitions. Symbol ton toff tr tf DM1 DM2 Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Turn-on delay matching | ton (H) - ton (L) | Turn-off delay matching | toff (H) - toff (L) | Min. — — — — Typ. 60 60 25 15 Max. 80 80 40 35 — — 20 — — 20 Units Test Conditions VS = 0V VS = 200V ns Static Electrical Characteristics VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH VIL VOH VOL ILK IQBS IQCC IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO- 4 Definition Logic “1” input voltage Logic “0” input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic “1” input bias current Logic “0” input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current www.irf.com Min. 2.5 — — — — — — — — Typ. — — — — — 120 200 3 — Max. — 0.7 1.4 0.1 50 210 300 10 5 8.3 9.0 9.7 7.5 8.2 8.9 8.3 9.0 9.7 7.5 8.2 8.9 — 1.0 — — 1.0 — © 2015 International Rectifier Units Test Conditions VCC = 10V – 20V V μA IO = 0A IO = 20mA VB = VS = 200V VIN = 0V or 3.3V VIN = 3.3V VIN = 0V V A VO = 0V, PW ≤ 10 μs VO = 15V PW ≤ 10 μs October 28, 2015 IRS2011(S)PBF Functional Block Diagram 5 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Lead Definitions Symbol Description HIN LIN VB HO VS VCC LO COM Logic input for high side gate driver outputs (HO), in phase Logic input for low side gate driver outputs (LO), in phase High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 8-Lead PDIP 6 www.irf.com © 2015 International Rectifier 8-Lead SOIC October 28, 2015 IRS2011(S)PBF Application Information and Additional Details ’ Figure 1. Timing Diagram 7 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 2A. Turn-on Propagation Delay vs. Temperature Figure 2B. Turn-on Propagation Delay vs. Supply Voltage Figure 3A. Turn-off Propagation Delay vs. Temperature Figure 3B. Turn-off Propagation Delay vs. Supply Voltage 8 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 4A. Turn-on Rise Time vs. Temperature Figure 4B. Turn-on Rise Time vs. Supply Voltage Figure 5A. Turn-off Fall Time vs. Temperature Figure 5B. Turn-off Fall Time vs. Supply Voltage 9 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 6A. Turn-on Delay Matching Time vs. Temperature Figure 6B. Turn-on Delay Matching Time vs. Supply Voltage Figure 7A Turn-off Delay Matching Time vs. Temperature Figure 7B. Turn-off Delay Matching Time vs. Supply Voltage 10 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 8A. Logic “1” Input Voltage vs. Temperature Figure 8B. Logic “1” Input Voltage vs. Supply Voltage Figure 9A. Logic “0” Input Voltage vs. Temperature Figure 9B. Logic “0” Input Voltage vs. Supply Voltage 11 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 10A. High Level Output Voltage vs. Temperature (IO = 0mA) Figure 10B. High Level Output Voltage vs. Supply Voltage (IO = 0mA) Figure 11A. Low Level Output Voltage vs. Temperature Figure 11B. Low Level Output vs. Supply Voltage 12 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 12A. Offset Supply Leakage Current vs. Temperature Figure 12B. Offset Supply Leakage Current vs. Supply Voltage Figure 13A. VBS Supply Current vs. Temperature Figure 13B. VBS Supply Current vs. Supply Voltage 13 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 14A. VCC Supply Current vs. Temperature Figure 14B. VCC Supply Current vs. Supply Voltage Figure 15A. Logic “1” Input Current vs. Temperature Figure 15 B. Logic “1” Input Current vs. Supply Voltage 14 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 16A. Logic “0” Input Bias Current vs. Temperature Figure 16B. Logic “0” Input Bias Current vs. Voltage Figure 17. VCC and VBS Undervoltage Threshold (+) vs. Temperature Figure 18. VCC and VBS Undervoltage Threshold (-) vs. Temperature 15 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 19A. Output Source Current vs. Temperature Figure 19B. Output Source Current vs. Supply Voltage Figure 20A. Output Sink Current vs. Temperature Figure 20B. Output Sink Currnt vs. Supply Voltage 16 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Figure 21. Maximum VS Negative Offset vs. VBS Floating Supply Voltage Figure 22. IRS2011S vs. Frequency (IRFBC20) Rgate = 33Ω, VCC = 12v 17 www.irf.com © 2015 International Rectifier Figure 23. IRS2011S vs. Frequency (IRFB30) Rgate = 22Ω, VCC = 12V October 28, 2015 IRS2011(S)PBF Figure 24. IRS2011S vs. Frequency (IRFBC40) Rgate = 15Ω, VCC = 12V Figure 25. IRS2011S vs. Frequency (IRFB23N15D) Rgate = 10Ω, VCC = 12V Figure 26. IRS2011S vs. Frequency (IRFB4212) Rgate = 10Ω, VCC = 12V 18 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Package Details 19 www.irf.com © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Tape and Reel Details LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN Metric Imperial Code Min Max Min Max A 7.90 8.10 0.311 0.318 B 3.90 4.10 0.153 0.161 C 11.70 12.30 0.46 0.484 D 5.45 5.55 0.214 0.218 E 6.30 6.50 0.248 0.255 F 5.10 5.30 0.200 0.208 G 1.50 n/a 0.059 n/a H 1.50 1.60 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 20 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 © 2015 International Rectifier October 28, 2015 IRS2011(S)PBF Part Marking Information IRxxxxx Part number YWW ? Date code Pin 1 Identifier ? XXXX ? MARKING CODE P Lead Free Released Non-Lead Free Released 21 www.irf.com IR logo © 2015 International Rectifier Lot Code (Prod mode – 4 digit SPN code) Assembly site code Per SCOP 200-002 October 28, 2015 IRS2011(S)PBF Qualification Information † †† Qualification Level Moisture Sensitivity Level 8-Lead SOIC RoHS Compliant Industrial (per JEDEC JESD 47) Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. ††† MSL2 (per IPC/JEDEC J-STD-020) Yes † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 22 www.irf.com © 2015 International Rectifier October 28, 2015
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