August 9, 2011
IRS21844MPBF
HALF-BRIDGE DRIVER
Features
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to + 600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V and 5 V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5 V offset
Lower di/dt gate driver for better noise immunity
Output source/sink current capability 1.4 A/1.8 A
Lead free, RoHS compliant
Product Summary
Topology
VOFFSET
VOUT
Half-Bridge
600 V
10 V – 20 V
Io+ & I o- (typical)
1.9 A & 2.3 A
ton & toff (typical)
680 ns & 270 ns
Deadtime (typical)
400 ns (RDT = 0 Ω)
5 µs (RDT = 200 kΩ)
Package Options
MLPQ4x4 16- Leads
(Without 2 leads)
Typical Connection
* Qualification standards can be found at www.irf.com
© 2008 International Rectifier
IRS21844MPBF
Description
The IRS21844MPBF is a high voltage, high speed power MOSFET and IGBT drivers with dependent high
and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the
high-side configuration which operates up to 600 V.
Feature Comparison: IRS2181(4)/IRS2183(4)/IRS2184(4)
Part
2181
21814
2183
21834
2184
21844
Input
Logic
CrossConduction
Prevention
logic
HIN/LIN
no
HIN/LIN
yes
IN/SD
yes
Qualification Information
Dead-Time
none
Internal 500ns
Programmable 0.4 – 5 us
Internal 500ns
Programmable 0.4 – 5 us
Ground
Pins
Ton/Toff
COM
VSS/COM
COM
VSS/COM
COM
VSS/COM
180/220 ns
180/220 ns
680/270 ns
†
††
Qualification Level
Moisture Sensitivity Level
Machine Model
ESD
Human Body Model
Charged Device Model
IC Latch-Up Test
RoHS Compliant
Industrial
(per JEDEC JESD 47)
Comments: This IC has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
†††
MSL2
MLPQ4x4 14L
(per IPC/JEDEC J-STD-020)
Class A (+/-100V)
(per JEDEC standard JESD22-A115)
Class 1C (+/-1500V)
(per EIA/JEDEC standard EIA/JESD22-A114)
Class III (+/-1000V)
(per JEDEC standard JESD22-C101)
Class II, Level A
(per JESD78A)
Yes
†
††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please
contact your International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
www.irf.com
© 2008 International Rectifier
2
IRS21844MPBF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation
ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min
Max
Units
VB
High-side floating absolute voltage
-0.3
620
VS
High-side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High-side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low-side and logic fixed supply voltage
-0.3
VLO
Low-side output voltage
-0.3
20
VCC + 0.3
DT
Programmable deadtime pin voltage
VSS -0.3
VCC + 0.3
VIN
Logic input voltage (IN & SD )
Logic ground
VSS -0.3
VCC + 0.3
VCC - 20
VCC + 0.3
VSS
†
†
V
dVS/dt
Allowable offset supply voltage transient
—
50
PD
Package power dissipation @ TA ≤ 25°C
—
2.08
V/ns
W
RthJA
Thermal resistance, junction to ambient
—
36
°C/W
TJ
Junction temperature
—
150
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
—
300
°C
All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Figure 1. For proper operation the device should be used
within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V
differential.
Symbol
Definition
Min
Max
VS + 10
VS + 20
(††)
600
VB
High-side floating supply absolute voltage
VS
High-side floating supply offset voltage
VHO
High-side floating output voltage
VS
VB
VCC
Low-side and logic fixed supply voltage
10
20
VLO
Low-side output voltage
0
VCC
VIN
VSS
VCC
DT
Logic input voltage (IN & SD )
Programmable deadtime pin voltage
VSS
VCC
VSS
Logic ground
-5
5
(†††)
Units
V
TA
Ambient temperature
-40
125
°C
†† Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to –VBS. (Please refer to Design
Tip DT97-3 for more details).
††† HIN and LIN are internally clamped with a 5.2 V zener diode.
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© 2008 International Rectifier
3
IRS21844MPBF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified.
Symbol
Definition
Min Typ Max Units Test Conditions
ton
Turn-on propagation delay
—
680 900
VS = 0 V
toff
Turn-off propagation delay
—
270 400
VS = 0 V or 600 V
tsd
Shut-down propagation delay
—
180 270
MTon
Delay matching, HS & LS turn-on
—
0
90
MToff
Delay matching , HS & LS turn-off
—
0
40
tr
Turn-on rise time
—
40
60
tf
Turn-off fall time
—
20
35
DT
MDT
Deadtime: LO turn-off to HO turn-on (DTLO-HO) &
HO turn-off to LO turn-on (DTHO-LO)
Deadtime matching DTLO-HO - DTHO-LO
ns
VS = 0 V
280 400 520
4
5
6
—
0
50
—
0
600
RDT = 0 Ω
µs
ns
RDT = 200 kΩ
RDT = 0 Ω
RDT = 200 kΩ
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, VSS = COM, DT = VSS and TA = 25°C unless otherwise specified. The VIL, VIH and IIN
parameters are referenced to VSS/COM and are applicable to the respective input leads: IN and SD . The VO,
IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
Min Typ Max Units Test Conditions
Definition
VIH
Logic “1” input voltage for HO & logic “0” for LO
2.5
—
—
VIL
Logic “0” input voltage for HO & logic “1” for LO
—
—
0.8
2.5
—
—
—
—
0.8
VOH
SD input positive going threshold
SD input negative going threshold
High level output voltage, VBIAS - VO
—
—
1.4
IO = 0 A
VOL
Low level output voltage, VO
—
—
0.2
IO = 20 mA
VSD,TH+
VSD,TH-
ILK
Offset supply leakage current
—
—
50
IQBS
Quiescent VBS supply current
20
60
150
IQCC
Quiescent VCC supply current
0.4
1.0
1.6
IIN+
Logic “1” input bias current
—
25
60
Logic “0” input bias current
VCC and VBS supply undervoltage positive going
threshold
VCC and VBS supply undervoltage negative going
threshold
—
—
5.0
8.0
8.9
9.8
7.4
8.2
9.0
Hysteresis
0.3
0.7
—
Output high short circuit pulsed current
1.4
1.9
—
IINVCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
IO+
VCC = 10 V to 20 V
V
µA
mA
µA
Output low short circuit pulsed current
www.irf.com
1.8
2.3
—
VIN = 0 V or 5 V
IN = 5 V, SD = 0 V
IN = 0 V, SD = 5 V
V
A
IO-
VB = VS = 600 V
VO = 0 V,
PW ≤ 10 µs
VO = 15 V,
PW ≤ 10 µs
© 2008 International Rectifier
4
IRS21844MPBF
Functional Block Diagram: IRS21844
www.irf.com
© 2008 International Rectifier
5
IRS21844MPBF
Input/Output Pin Equivalent Circuit Diagrams: IRS21844
www.irf.com
© 2008 International Rectifier
6
IRS21844MPBF
Lead Definitions
PIN
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SD
VSS
DT
COM
LO
NC
VCC
NC
NC
NC
VS
HO
VB
NC
NC
IN
Description
Logic input for shutdown (referenced to VSS)
Logic ground
Programmable deadtime lead, referenced to VSS
Low-side return
Low-side gate drive output
No Connection
Low-side and logic fixed supply
No Connection
No Connection
No Connection (removed lead)
High-side floating supply return
High-side gate drive output
High-side floating supply
No Connection
No Connection (removed lead)
Logic input for high-side gate driver output (HO), in phase
Lead Assignments: IRS21844
16
SD
15
14
13
1
12
HO
11
VS
10
NC
9
NC
IRS21844MPBF
Vss
2
DT
3
COM
4
16L- MLPQ4x 4
with 2 leads
removed
5
6
7
8
= Removed lead
IRS21844MPBF
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© 2008 International Rectifier
7
IRS21844MPBF
Application Information and Additional Details
SD
Figure 1: Input/Output Timing Diagram
Figure 2: Switching Time Waveform Definitions
SD
Figure 3: Shutdown Waveform Definitions
Figure 4: Deadtime Waveform Definitions
IN (LO)
50%
50%
IN (HO)
LO
HO
10%
MT
MT
90%
LO
HO
Figure 5: Delay Matching Waveform Definitions
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© 2008 International Rectifier
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IRS21844MPBF
Package Details: MLPQ 4x4 -16L
www.irf.com
© 2008 International Rectifier
24
IRS21844MPBF
Tape and Reel Details: MLPQ 4x4
www.irf.com
© 2008 International Rectifier
25
IRS21844MPBF
Part Marking Information
Ordering Information
Base Part Number
IRS21844
Package Type
Standard Pack
Complete Part Number
Form
Quantity
Tube/Bulk
92
IRS21844MPBF
Tape and Reel
3,000
IRS21844MTRPBF
MLPQ 4x4-16L
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any
infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by
implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are
subject to change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
© 2008 International Rectifier
26
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