IRS2330STRPBF

Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF June 1 2011 IRS233(0,2)(D)(S & J)PbF 3-PHASE-BRIDGE DRIVER Features • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage – dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent half-bridge drivers Matched propagation delay for all channels 3.3 V logic compatible Outputs out of phase with inputs Cross-conduction prevention logic Integrated Operational Amplifier Integrated Bootstrap Diode function (IRS233(0,2)D) RoHS Compliant Description The IRS233(0,2)(D)(S & J) is a high voltage, high speed power MOSFET and IGBT driver with three independent high and low side referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V logic. A ground-referenced operational amplifier provides analog feedback of bridge current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The floating channel can be used to drive N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Product Summary VOFFSET 600V max. IO+/- 200 mA / 420 mA VOUT 10 V – 20 V (233(0,2)(D)) ton/off (typ.) 500 ns Deadtime (typ.) 2.0 us (IRS2330(D)) 0.7 us (IRS2332(D)) Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Packages 28-Lead SOIC 44-Lead PLCC w/o 12 Leads Typical Connection Absolute Maximum Ratings www.irf.com 1 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF † Qualification Information †† Industrial Qualification Level Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. ††† SOIC28W MSL3 , 260°C (per IPC/JEDEC J-STD-020) PLCC44 MSL3 , 245°C (per IPC/JEDEC J-STD-020) Moisture Sensitivity Level ††† Human Body Model ESD Machine Model IC Latch-Up Test RoHS Compliant † †† ††† Class 2 (per JEDEC standard JESD22-A114) Class B (per EIA/JEDEC standard EIA/JESD22-A115) Class I, Level A (per JESD78) Yes Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com 2 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. VB1,2,3 High-side floating supply voltage -0.3 620 VS1,2,3 High-side floating offset voltage VB1,2,3 - 20 VB1,2,3 + 0.3 High-side floating output Voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3 -0.3 20 VCC - 20 VCC + 0.3 -0.3 VCC + 0.3 VHO1,2,3 VCC Low-side and logic fixed supply voltage VSS Logic ground VLO1,2,3 Low-side output voltage Units V _______ ______ Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) VSS -0.3 VFLT VCAO FAULT output voltage Operational amplifier output voltage VSS -0.3 VSS -0.3 (VSS + 15) or (VCC + 0.3) Whichever is lower VCC +0.3 VCC +0.3 VCA- Operational amplifier inverting input voltage VSS -0.3 VCC +0.3 — 50 V/ns — — 1.6 2.0 W 78 63 150 VIN dVS/dt PD Allowable offset supply voltage transient Package power dissipation @ TA ≤ +25 °C (28 lead SOIC) (44 lead PLCC) (28 lead SOIC) (44 lead PLCC) TJ Junction temperature — — — TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 RthJA Thermal resistance, junction to ambient www.irf.com °C/W °C 3 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested with all supplies biased at 15 V differential. Symbol Definition Min. Max. VS1,2,3 +10 VS1,2,3 +20 VSO-8 (Note1) 600 -50 (Note2) VS1,2,3 600 VB1,2,3 VB1,2,3 High-side floating supply voltage VS1,2,3 Static high-side floating offset voltage VSt1,2,3 VHO1,2,3 Transient high-side floating offset voltage VCC Low-side and Logic fixed supply voltage 10 20 VSS Logic ground -5 5 0 VSS VSS VCC VSS + 5 VCC VLO1,2,3 VIN VFLT High-side floating output voltage Low-side output voltage Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP) FAULT output voltage VCAO Operational amplifier output voltage VSS VSS + 5 VCA- Operational amplifier inverting input voltage VSS VSS + 5 Ambient temperature -40 125 TA Units V °C Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO – VBS). Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. Note 3: CAO input pin is internally clamped with a 5.2 V zener diode. Dynamic Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions ton Turn-on propagation delay 400 500 700 toff Turn-off propagation delay 400 500 700 tr Turn-on rise time — 80 125 tf Turn-off fall time — 35 55 titrip ITRIP to output shutdown propagation delay 400 660 920 tbl tflt ITRIP blanking time ITRIP to FAULT indication delay Input filter time (all six inputs) LIN1,2,3 to FAULT clear time (2330/2) — 350 — 400 550 325 — 870 — tflt, in tfltclr DT MDT Deadtime: (IRS2330(D)) (IRS2332(D)) Deadtime matching: : (IRS2330(D)) (IRS2332(D)) 5300 8500 13700 1300 2000 3100 500 700 1100 — — 400 — — 140 MT Delay matching time (t ON , t OFF) — — 50 PM Pulse width distortion — — 75 VS1,2,3 = 0 V to 600 V VS1,2,3 = 0 V ns VIN = 0 V & 5 V without external deadtime VIN = 0 V & 5 V without external deadtime larger than DT PM input 10 µs NOTE: For high side PWM, HIN pulse width must be > 1.5 usec www.irf.com 4 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Dynamic Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified. Symbol SR+ SR- www.irf.com Definition Operational amplifier slew rate (+) Operational amplifier slew rate (-) Min Typ Max Units Test Conditions 5 2.4 10 3.2 — — V/µs 1 V input step 5 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Static Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition Min Typ Max Units Test Conditions VIH Logic “0” input voltage (OUT = LO) — — 2.2 VIL VIT,TH+ Logic “1” input voltage (OUT = HI) ITRIP input positive going threshold 0.8 400 — 490 — 580 VOH High level output voltage, VBIAS - VO — — 1000 VOL Low level output voltage, VO — — 400 ILK Offset supply leakage current — — 50 IQBS Quiescent VBS supply current — 30 50 IQCC Quiescent VCC supply current — 4.0 6.2 IIN+ IIN- Logic “1” input bias current (OUT =HI) Logic “0” input bias current (OUT = LO) “High” ITRIP bias current “LOW” ITRIP bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold IITRIP+ IITRIPVBSUV+ VBSUVVCCUV+ VCCUV- -400 -300 -100 -300 -220 -100 — 5 10 — — 30 7.5 8.35 9.2 7.1 7.95 8.8 8.3 9 9.7 8 8.7 9.4 VCCUVH Hysteresis — 0.3 — VBSUVH Hysteresis FAULT low on-resistance — 0.4 — — 55 75 IO+ Output high short circuit pulsed current — IO- Output low short circuit pulsed current 420 500 — — — — 200 — — — 20 100 — 80 — Ron, FLT V mV VIN = 5 V, IO = 20 mA µA mA µA nA CMRR PSRR VOH,AMP VOL,AMP Integrated bootstrap diode resistance Operational amplifier input offset voltage CA- input bias current Operational amplifier common mode rejection ratio Operational amplifier power supply rejection ratio Operational amplifier high level output voltage Operational amplifier low level output voltage VB = VS = 600 V VIN = 0 V or 4 V VIN = 4 V VIN = 0 V VIN = 4 V ITRIP = 4 V ITRIP = 0 V V Ω -250 -180 mA RBS VOS ICA- VIN = 0 V, IO = 20 mA Ω mV nA VO = 0 V, VIN = 0 V PW ≤ 10 us VO = 15 V, VIN = 5 V PW ≤ 10 us VSO = 0.2 V VCA- = 1 V VSO = 0.1 V & 5 V dB VSO = 0.2 V VCC = 9.7 V & 20 V — 75 — 4.8 5.2 5.6 V VCA- = 0 V, VSO =1 V — — 40 mV VCA- = 1 V, VSO =0 V Note: The integrated bootstrap diode does not work well with the trapezoidal control. www.irf.com 6 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Static Electrical Characteristics- Continued VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition Min Typ Max Units Test Conditions ISRC,AMP Operational amplifier output source current — -7 -4 ISNK,AMP Operational amplifier output sink current 1 2.1 — -30 -10 — — 4 — IO+,AMP IO-,AMP Operational amplifier output high short circuit current Operational amplifier output low short circuit current mA VCA- = 0 V, VSO =1 V VCAO = 4 V VCA- = 1 V, VSO =0 V VCAO = 2 V VCA- = 0 V, VSO =5 V VCAO = 0 V VCA- = 5 V, VSO =0 V VCAO = 5 V Functional Block Diagram Note: IRS2330 & IRS2332 are without integrated bootstrap diode. www.irf.com 7 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Lead Definitions Symbol HIN1,2,3 LIN1,2,3 FAULT VCC Description Logic input for high-side gate driver outputs (HO1,2,3), out of phase Logic input for low-side gate driver output (LO1,2,3), out of phase Indicates over-current or undervoltage lockout (low-side) has occurred, negative logic Low-side and logic fixed supply ITRIP Input for over-current shutdown CAO Output of current amplifier CA- Negative input of current amplifier VSS VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 VSO Logic Ground High-side floating supply High-side gate drive output High-side floating supply return Low-side gate drive output Low-side return and positive input of current amplifier Lead Assignments www.irf.com 8 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Application Information and Additional Details Information regarding the following topics are included as subsections within this section of the datasheet. • • • • • • • • • • • • • • • • • • • • • IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Fault Reporting Over-Current Protection Over-Temperature Shutdown Protection Truth Table: Undervoltage lockout, ITRIP Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Bootstrap Power Supply Design Separate Logic and Power Grounds Negative VS Transient SOA DC- bus Current Sensing PCB Layout Tips Integrated Bootstrap FET limitation Additional Documentation IGBT/MOSFET Gate Drive The IRS233(2,0)(D) HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the highside power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) + HO (or LO) IO- VHO (or VLO) VS (or COM) - Figure 1: HVIC sourcing current www.irf.com VS (or COM) Figure 2: HVIC sinking current 9 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Switching and Timing Relationships The relationship between the input and output signals of the IRS233(0,2)(D) are illustrated below in Figures 3. From these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this device. LINx (or HINx) 50% 50% PWIN tON LOx (or HOx) tOFF tR tF PWOUT 90% 10% 90% 10% Figure 3: Switching time waveforms The following two figures illustrate the timing relationships of some of the functionality of the IRS233(0,2)(D); this functionality is described in further detail later in this document. During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output are held in the off state. Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault condition is latched until the all LINx become high. www.irf.com 10 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF HIN1,2,3 A B LIN1, 2, 3 ITRIP FAULT HO1, 2, 3 LO1, 2, 3 Figure 4: Input/output timing diagram Deadtime This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. Figure 5: Illustration of deadtime www.irf.com 11 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Matched Propagation Delays The IRS233(0,2)(D) family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the lowside channels and the high-side channels. Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other. The propagation turn-on delay (tON) of the IRS233(0,2)(D) is matched to the propagation turn-on delay (tOFF). Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS233(0,2)(D) family has been designed to be compatible with 3.3 V and 5 V logic-level signals. The IRS233(0,2)(D) features an integrated 5.2 V Zener clamp on the HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the IRS233(0,2)(D), its input threshold values, and the logic state of the IC as a result of the input signal. Figure 6: HIN & LIN input thresholds Undervoltage Lockout Protection This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. www.irf.com 12 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Figure 7: UVLO protection Shoot-Through Protection The IRS233(0,2)(D) family of high-voltage ICs is equipped with shoot-through protection circuitry (also known as crossconduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that the IRS233(0,2)(D) has inverting inputs (the output is out-of-phase with its respective input). Figure 8: Illustration of shoot-through protection circuitry IRS233(0,2)(D) HIN LIN HO LO 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 Table 1: Input/output truth table www.irf.com 13 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Fault Reporting The IRS233(0,2)(D) family provides an integrated fault reporting output. There are two situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault condition is latched. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. Over-Current Protection The IRS233(0,2)(D) HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is reported through the FAULT pin. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2) connected to ITRIP as shown in Figure 9, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VIT,TH+) at that current level. VIT,TH+ = R0IDC-(R1/(R1+R2)) I RS233(0,2)(D) Figure 9: Programming the over-current protection For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. Over-Temperature Shutdown Protection The ITRIP input of the IRS233(0,2)(D) can also be used to detect over-temperature events in the system and initiate a shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the resistor network as shown in Figure 10 and select the maximum allowable temperature. This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V. When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g., DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D1 and D2. www.irf.com 14 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Figure 10: Programming over-temperature protection Figure 11: Using over-current protection and over-temperature protection Truth Table: Undervoltage lockout and ITRIP Table 2 provides the truth table for the IRS233(0,2)(D). The first line shows that the UVLO for VCC has been tripped; the FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. UVLO VCC UVLO VBS Normal operation ITRIP fault VCC 0 In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current conduction path is created between VCC & VB pins, as illustrated in Fig.38 below, resulting in power loss and possible damage to the HVIC. Figure 38: Current conduction path between VCC and VB pin Relevant Application Situations: The above mentioned bias condition may be encountered under the following situations: • In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In this condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes resulting unwanted current flow to VCC. • Potential situations in other applications where VS/VB node voltage potential increases before the VCC voltage is available (for example due to sequencing delays in SMPS supplying VCC bias) Application Workaround: Insertion of a standard p-n junction diode between VCC pin of IC and positive terminal of VCC capacitors (as illustrated in Fig.39) prevents current conduction “out-of” VCC pin of gate driver IC. It is important not to connect the VCC capacitor directly to pin of IC. Diode selection is based on 25V rating or above & current capability aligned to ICC consumption of IC - 100mA should cover most application situations. As an example, Part number # LL4154 from Diodes Inc (25V/150mA standard diode) can be used. www.irf.com 25 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF VCC VCC Capacitor VB VSS (or COM) Figure 39: Diode insertion between VCC pin and VCC capacitor Note that the forward voltage drop on the diode (VF) must be taken into account when biasing the VCC pin of the IC to meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – VF of Diode. Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs www.irf.com 26 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Parameter Temperature Trends Figures 40-78 provide information on the experimental performance of the IRS233(0,2)(D)(S&J) HVIC. The line plotted in each figure is generated from actual lab data. A small number of individual samples were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 800 800 700 700 600 600 Exp. Exp. 500 tON (ns) tON (ns) 500 400 400 300 300 200 200 100 100 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 Fig. 40. Turn-on Propagation Delay vs. Temperature 800 700 700 75 100 125 Exp. 600 Exp. 500 tOFF (ns) tOFF (ns) 50 Fig. 41. Turn-on Propagation Delay vs. Temperature 800 600 25 Temperature (o C) Temperature (o C) 400 500 400 300 300 200 200 100 100 0 -50 -25 0 25 50 75 100 Temperature (o C) Fig. 42. Turn-off Propagation Delay vs. Temperature www.irf.com 125 0 -50 -25 0 25 50 75 100 Temperature (o C) Fig. 43. Turn-off Propagation Delay vs. Temperature 27 125 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF 200 60 180 50 160 40 120 tF (ns) tR (ns) 140 100 30 80 Exp. Exp. 20 60 40 10 20 0 -50 -25 0 25 50 75 100 0 -50 125 -25 0 25 Temperature (oC) Fig. 44. Turn-on Rise Time vs. Temperature 1000 900 900 800 700 600 tFLT (ns) tITRIP (ns) 100 125 800 Exp. 500 400 500 400 300 200 200 100 100 -25 0 25 50 75 100 Exp. 600 300 0 -50 0 -50 125 -25 0 Temperature (o C) 50 75 100 125 Fig. 47. ITRIP to FAULT Indication Delay vs. Temperature 16000 1200 14000 1000 Exp. Exp. DLTon1 (ns) 12000 25 Temperature (oC) Fig. 46. ITRIP to Output Shutdown Propagation Delay vs. Temperature TFLTCLR (ns) 75 Fig.45. Turn-off Fall Time vs. Temperature 1000 700 50 Temperature (oC) 10000 8000 6000 800 600 400 4000 200 2000 0 -50 -25 0 25 50 75 100 Temperature (o C) Fig.48. FAULT Clear Time vs. Temperature www.irf.com 125 0 -50 -25 0 25 50 75 100 Temperature (oC) Fig. 49. Dead Time vs. Temperature 28 125 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF 60 6 50 5 SR-_Amp (V/uS) SR+_Amp (V/uS) Exp. 40 30 20 4 3 2 Exp. 10 1 0 -50 -25 0 25 50 75 100 0 -50 125 -25 0 25 Temperature (oC) Fig. 50. Operational Amplifier Slew Rate (+) vs. Temperature 2.0 LIN1_VTH- (V) LIN1_VTH+ (V) Exp. 1.0 0.5 Exp. 1.5 1.0 -25 0 25 50 75 100 0.0 -50 125 -25 0 Temperature (oC) 25 50 75 100 125 Temperature (oC) Fig. 52. Input Positive Going Threshold vs. Temperature Fig. 53. Input Negative Going Threshold vs. Temperature 800 800 700 700 600 600 VIT,TH- (mV) VIT,TH+ (mV) 125 0.5 0.0 -50 EXP. p. 400 300 500 400 Exp. 300 200 200 100 100 0 -50 100 2.5 1.5 500 75 Fig. 51. Operational Amplifier Slew Rate (-) vs. Temperature 2.5 2.0 50 Temperature (oC) 0 -25 0 25 50 75 100 Temperature (oC) Fig. 54. ITRIP Input Positive Going Threshold vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 55. ITRIP Input Negative Going Threshold vs. Temperature 29 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF 450 60 400 50 ileak1_VCCMAX (µA) VOL_LO1 (mV) 350 300 250 200 150 Exp. 100 40 30 20 10 Exp. 50 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 25 50 75 100 125 Temperature (oC) Fig. 56. Low Level Output Voltage vs. Temperature Fig. 57. Offset Supply Leakage Current vs. Temperature 12 7 6 10 Exp. 5 Exp. I QCC0 (mA) I QCC1 (mA) 8 6 4 3 4 2 2 1 0 -50 -25 0 25 50 75 100 0 -50 125 -25 0 Temperature (oC) 80 80 70 70 60 60 50 50 Exp. 30 10 25 50 75 100 Temperature (oC) Fig. 60. Quiescent VBS Supply Current vs. Temperature www.irf.com 125 30 10 0 100 Exp. 20 -25 75 40 20 0 -50 50 Fig. 59. Quiescent VCC Supply Current vs. Temperature IQBS11 (µA) IQBS10 (µA) Fig. 58. Quiescent VCC Supply Current vs. Temperature 40 25 Temperature (oC) 125 0 -50 -25 0 25 50 75 100 Temperature (oC) Fig. 61. Quiescent VBS Supply Current vs. Temperature 30 125 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF 9.6 9.8 9.4 9.6 9.2 9.4 VCCUV+ (V) VCCUV- (V) 9.0 8.8 8.6 Exp. 8.4 9.2 9.0 Exp. 8.8 8.6 8.2 8.4 8.0 7.8 -50 -25 0 25 50 75 100 8.2 -50 125 -25 0 25 Temperature (oC) 50 75 100 125 Temperature (oC) Fig. 62. VCC Supply Undervoltage Negative Going Threshold vs. Temperature Fig. 63. VCC Supply Undervoltage Positive Going Threshold vs. Temperature 9.5 9.0 9.0 8.5 8.5 Exp. Exp. V BSUV+ (V) VBSUV- (V) 8.0 7.5 8.0 7.5 7.0 7.0 6.5 6.5 6.0 -50 -25 0 25 50 75 100 6.0 -50 125 -25 0 25 Temperature (o C) Fig. 64. VBS Supply Undervoltage Negative Going Threshold vs. Temperature 75 100 0 -50 -50 80 70 -25 0 25 50 75 100 -100 60 IO+ (mA) -150 50 Exp. 40 -200 -250 30 -300 Exp. p. 20 -350 10 0 -50 -400 -25 0 25 50 75 100 Temperature (oC) Fig. 66. FAULT Low On-Resistance vs. Temperature www.irf.com 125 Fig. 65. VBS Supply Undervoltage Positive Going Threshold vs. Temperature 90 RON,FLT (Ω) 50 Temperature (oC) 125 -450 Temperature (oC) Fig. 67. Output High Short Circuit Pulsed Current vs. Temperature 31 125 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF 706 20 Exp. 606 15 10 VOS_AMP (mV) I O- (mA) 506 406 306 206 5 0 -50 -5 Exp. p. -25 0 25 50 75 100 125 -10 106 -15 6 -50 -25 0 25 50 75 100 125 -20 Temperature (oC) Temperature (oC) Fig. 69. Offset Opamp vs. Temperature 200 200 180 180 160 160 140 140 CMRR_AMP (dB) PSRR_AMP (dB) Fig. 68. Output Low Short Circuit Pulsed Current vs. Temperature 120 100 Exp. 80 60 120 100 Exp. 80 60 40 40 20 20 0 -50 -25 0 25 50 75 100 0 -50 125 -25 0 Temperature (o C) Fig. 70. Operational Amplifier Power Supply Rejection Ratio vs. Temperature 35 5.5 30 VOH_AMP (mV) VOH_AMP (V) 5.4 5.3 5.2 Exp. 5.0 75 100 125 25 20 Exp. 15 10 5 4.9 4.8 -50 50 Fig. 71. Operational Amplifier Common Mode Rejection Ratio vs. Temperature 5.6 5.1 25 Temperature (oC) -25 0 25 50 75 100 125 Temperature (oC) Fig. 72. Operational Amplifier High Level Output Voltage vs. Temperature www.irf.com 0 -50 -25 0 25 50 75 100 Temperature (oC) Fig. 73. Operational Amplifier Low Level Output Voltage vs. Temperature 32 125 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF 6 16 14 5 Exp. 4 Io-_AMP (mA) Isnk_AMP (mA) 12 Exp. 3 2 10 8 6 4 1 2 0 -50 -25 0 25 50 75 100 0 -50 125 -25 0 Temperature (oC) Fig. 74. Operational Amplifier Output Sink Current vs. Temperature 0 -50 -2 -25 0 25 50 75 100 0 -50 125 75 100 -25 0 25 50 75 100 -5 -10 Io+_AMP (mA) Isrc_AMP (mA) 50 -6 -8 Exp. -15 Exp. -20 -25 -12 -30 -14 -16 -35 Temperature (oC) Temperature (oC) Fig. 76. Operational Amplifier Output Source Current vs. Temperature Fig. 77. Operational Amplifier Output High Short Circuit Current vs. Temperature 0 -50 -25 0 25 50 75 100 125 Vs1_RST_domin (V) -2 -4 -6 -8 -10 Exp. -12 -14 Temperature (o C) Fig. 78. Max –Vs vs. Temperature www.irf.com 125 Fig. 75. Operational Amplifier Output Low Short Circuit Current vs. Temperature -4 -10 25 Temperature (oC) 33 125 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Case Outlines www.irf.com 34 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Case Outlines www.irf.com 35 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Tape and Reel Details: SOIC28W LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 11.90 12.10 B 3.90 4.10 C 23.70 24.30 D 11.40 11.60 E 10.80 11.00 F 18.20 18.40 G 1.50 n/a H 1.50 1.60 28SOICW Imperial Min Max 0.468 0.476 0.153 0.161 0.933 0.956 0.448 0.456 0.425 0.433 0.716 0.724 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 28SOICW Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 30.40 n/a 1.196 G 26.50 29.10 1.04 1.145 H 24.40 26.40 0.96 1.039 www.irf.com 36 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Tape and Reel Details: PLCC44 LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR 44PLCC Metric Imperial Code Min Max Min Max A 23.90 24.10 0.94 0.948 B 3.90 4.10 0.153 0.161 C 31.70 32.30 1.248 1.271 D 14.10 14.30 0.555 0.562 E 17.90 18.10 0.704 0.712 F 17.90 18.10 0.704 0.712 G 2.00 n/a 0.078 n/a H 1.50 1.60 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 44PLCC Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 38.4 G 34.7 35.8 H 32.6 33.1 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 1.511 1.366 1.409 1.283 1.303 37 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Ordering Information Base Part Number Package Type SOIC28W IRS233(0,2)(D) PLCC44 Standard Pack Complete Part Number Form Quantity Tube/Bulk 25 Tape and Reel 1000 Tube/Bulk 27 IRS233(0,2)(D)JPbF Tape and Reel 500 IRS233(0,2)(D)JTRPbF IRS233(0,2)(D)SPbF IRS233(0,2)(D)STRPbF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com 38 Not recommended for new designs. For new designs, we recommend 6EDL04I06NT IRS233(0,2)(D)(S&J)PbF Change History Revision Date 0.0 10/17/07 0.1 03/05/08 0.2 03/18/08 0.3 03/18/08 0.4 03/26/08 0.5 03/27/08 0.6 03/27/08 0.7 03/28/08 0.8 04/02/08 0.9 1.0 1.1 1.2 04/11/08 04/15/08 04/16/08 04/28/08 May 8, 08 July 8, 08 June 1, 11 www.irf.com Change comments Initial data sheet converted from IRS2130xD data sheet Initial Review Included tri-temp plots Updated test conditions Updated limits using DR3 Limits table Included application notes Updated minor errors and completed review for DR3 Corrected reflow temperature for PLCC44 to 245°C Added Integrated Operational Amplifier feature on front page and RoHS compliant. Corrected logic level compatible on Page1 from 2.5V to 3.3V Added MDT parameter Updated MDT spec. and changed latch-up level to A Removed typical MDT spec.; MDT expected to be zero and cannot be more than maximum spec. Changed file format from “rev1.2” to May 8, 2008. Corrected part number in Fig. 15 changed Iqcc test condition to Vin=4V from 0V. Add bootstrap fet limitation 39