IRS2334SPBF

27 January 2011 IRS2334SPbF/IRS2334MPbF 3 PHASE GATE DRIVER HVIC Product Summary Features               Floating channel designed for bootstrap operation Fully operational to 600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Integrated dead time protection Shoot-through (cross-conduction) prevention logic Under-Voltage lockout for both channels Independent 3 half-bridge drivers 3.3 V input logic compatible Advanced input filter Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity Outputs in phase with inputs RoHS compliant Topology 3 phase VOFFSET ≤ 600 V VOUT Io+ & I o- (typical) 200 mA & 350 mA tON & tOFF (typical) 530 ns Package Options Typical Applications     10 V – 20 V 20 leads wide body SOIC Motor Control Low Power Fans General Purpose Inverters Micro/Mini Inverter Drivers 28 leads MLPQ 5x5 (32 leads without 4) Typical Connection Diagram Up to 600V Vcc Vcc HIN1,2,3 HIN1,2,3 LIN1,2,3 LIN1,2,3 VB1,2,3 HO1,2,3 VS 1,2,3 TO LOAD LO1,2,3 COM IRS2334 GND www.irf.com 02-Apr-10 1 © 2010 International Rectifier IRS2334SPbF/MPbF Table of Contents Page Description 3 Simplified Block Diagram 3 Typical Application Diagram 4 Qualification Information 5 Absolute Maximum Ratings 6 Recommended Operating Conditions 6 Static Electrical Characteristics 7 Dynamic Electrical Characteristics 7 Functional Block Diagram 8 Input/Output Pin Equivalent Circuit Diagram 9 Lead Definitions 10 Lead Assignments 11 Application Information and Additional Details 12 Parameter Temperature Trends 21 Package Details 25 Tape and Reel Details 27 Part Marking Information 29 Ordering Information 30 www.irf.com © 2010 International Rectifier 2 IRS2334SPbF/MPbF Description The IRS2334 is a high voltage, high speed power MOSFET and IGBT driver with three independent high side and low side referenced output channels for 3-phase applications. Proprietary HVIC and latch immune CMOS technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration up to 600 V. Simplified Block Diagram HV floating well Schmitt trigger, minimum dead time and shoot-through protection to high side power switches (x3) HV Level Shifters Delay www.irf.com to low side power switches (x3) © 2010 International Rectifier 3 IRS2334SPbF/MPbF Typical Application Diagram www.irf.com © 2010 International Rectifier 4 IRS2334SPbF/MPbF Qualification Information† Industrial†† Comments: This IC has passed JEDEC industrial qualification. IR consumer qualification level is granted by extension of the higher Industrial level. Qualification Level MSL2 , 260C (per IPC/JEDEC J-STD-020) Moisture Sensitivity Level Class 1C (per JEDEC standard JESD22-A114) Class B (per EIA/JEDEC standard EIA/JESD22-A115) Class I, Level A (per JESD78) Human Body Model ESD Machine Model IC Latch-Up Test Yes RoHS Compliant † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. www.irf.com © 2010 International Rectifier 5 IRS2334SPbF/MPbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS Definition VHO1,2,3 VCC VLO1,2,3 VIN PWHIN dVS/dt High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic and analog input voltages High-side input pulse width Allowable offset supply voltage slew rate PD Package power dissipation @ TA ≤ 25°C RthJA TJ TS TL † Thermal resistance, junction to ambient 20 lead SOIC 28 lead MLPQ 20 lead SOIC 28 lead MLPQ Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. Max. -0.3 † VB1,2,3 - 25 VS1,2,3 - 0.3 -0.3 -0.3 -0.3 500 — — — — — — -55 — 625 VB1,2,3 + 0.3 VB1,2,3 + 0.3 † 25 VCC + 0.3 VCC + 0.3 — 50 1.14 3.363 65.8 22.3 150 150 300 Units V ns V/ns W °C/W °C All supplies are fully tested at 25 V. An internal 25 V clamp exists for each supply. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM unless otherwise specified. The VS1,2,3 offset ratings are tested with all supplies biased at 15 V. Symbol VB1,2,3 VS1,2,3 VS1,2,3(t) VHO1,2,3 VCC VLO1,2,3 VIN TA † †† Definition Min. High side floating supply voltage † Static high side floating supply offset voltage Transient high side floating supply offset voltage†† High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Ambient temperature VS1,2,3 +10 -8 -50 VS1,2,3 10 0 0 -40 Max. VS1,2,3 + 20 600 600 VB1,2,3 20 VCC VCC 125 Units V °C Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Operational for transient negative VS of -50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com © 2010 International Rectifier 6 IRS2334SPbF/MPbF Static Electrical Characteristics (VCC-COM) = (VB1,2,3-VS1,2,3) = 15 V and TA = 25 oC unless otherwise specified. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the output leads LO1,2,3 and HO1,2,3 respectively. The VCCUV and VBSUV parameters are referenced to COM and VS respectively. Symbol VIH VIL VIN,TH+ VIN,THVOH VOL VCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH ILK IQBS IQCC IIN+ IINIo+ Io- Definition Min. Typ. Max. Units 2.5 — — — — — — — 1.9 1 0.9 0.4 — 0.8 — — 1.4 0.6 V 10.4 11.1 11.6 10.2 10.9 11.4 VCC and VBS supply under-voltage hysteresis 0.1 0.2 — Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic “1” input bias current Logic “0” input bias current Output high short circuit pulsed current Output low short circuit pulsed current — — — — — 120 250 1 40 300 150 50 120 700 250 1 — — Logic “1” input voltage Logic “0” input voltage Input positive going threshold Input negative going threshold High level output voltage Low level output voltage VCC and VBS supply under-voltage positive going threshold VCC and VBS supply under-voltage negative going threshold 200 350 µA µA Test Conditions IO = 20 mA VB =VS = 600 V VIN = 0 V µA VIN = 5 V VIN = 0 V mA VO = 0 V or 15 V PW ≤ 10 µs Dynamic Electrical Characteristics VCC = VB1,2,3 = 15 V, VS1,2,3 = COM, TA = 25 oC and CL = 1000 pF unless otherwise specified. Symbol ton toff tr tf tFILIN DT MDT MT PM † Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Input filter time Dead time Dead time matching ton, toff propagation delay matching time † PW pulse width distortion Min. Typ. Max. 400 400 — — 200 190 — — — 530 530 125 50 350 290 — — — 750 750 190 75 510 420 60 50 75 Units Test Conditions VIN = 0V and 5V ns VIN = 0V & 5V External dead time 0s PW input =10µs PM is defined as PWIN - PWOUT. www.irf.com © 2010 International Rectifier 7 IRS2334SPbF/MPbF Functional Block Diagram HIN1 Input Noise Filter LIN1 Input Noise Filter HIN2 Input Noise Filter LIN2 Input Noise Filter HIN3 Input Noise Filter LIN3 Input Noise Filter VB1 SD SD SD HV Level Shifter Deadtime & Shoot-Through Prevention Deadtime & Shoot-Through Prevention HV Level Shifter Deadtime & Shoot-Through Prevention HV Level Shifter SET Latch RESET UV Detect Driver HO1 VS1 VB2 SET Latch RESET UV Detect SET Latch RESET UV Detect Driver HO2 VS2 VB3 Driver HO3 VS3 VCC UV Detect Delay Driver LO1 Delay Driver LO2 Delay Driver LO3 COM www.irf.com © 2010 International Rectifier 8 IRS2334SPbF/MPbF Input/Output Pin Equivalent Circuit Diagrams www.irf.com © 2010 International Rectifier 9 IRS2334SPbF/MPbF Lead Definitions Symbol VCC VB1 VB2 VB3 VS1 VS2 VS3 HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 HO1 HO2 HO3 LO1 LO2 LO3 COM Description Low side and logic power supply High side floating power supply (phase 1) High side floating power supply (phase 2) High side floating power supply (phase 3) High side floating supply return (phase 1) High side floating supply return (phase 2) High side floating supply return (phase 3) Logic input for high side gate driver output HO1, input is in-phase with output Logic input for high side gate driver output HO2, input is in-phase with output Logic input for high side gate driver output HO3, input is in-phase with output Logic input for low side gate driver output LO1, input is in-phase with output Logic input for low side gate driver output LO2, input is in-phase with output Logic input for low side gate driver output LO3, input is in-phase with output High side gate driver output (phase 1) High side gate driver output (phase 2) High side gate driver output (phase 3) Low side gate driver output (phase 1) Low side gate driver output (phase 2) Low side gate driver output (phase 3) Low side supply return www.irf.com © 2010 International Rectifier 10 IRS2334SPbF/MPbF Lead Assignments VB2 HO2 VS2 VB3 HO3 HS3 31 30 27 26 25 32 leads MLPQ 5x5 without 4 leads 32 20 leads wide body SOIC VS1 1 24 HO1 2 23 VB1 3 22 21 20 VCC LO3 www.irf.com COM 16 17 15 8 14 HIN3 13 LO2 12 18 11 7 LIN3 HIN2 10 LO1 LIN2 19 9 6 LIN1 HIN1 © 2010 International Rectifier 11 IRS2334SPbF/MPbF Application Information and Additional Details              IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Shoot-Through Protection Under-Voltage Lockout Protection Truth Table: Under-Voltage lockout Advanced Input Filter Short-Pulse and Noise Rejection Tolerant to Negative VS Transients PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS2334 HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and 2 show the definition of some of the relevant parameters associated with the gate driver output functionality. The output current that drives the gate of the external power switches is defined as IO. The output voltage that drives the gate of the external power switches is defined as VHO for the high side and VLO for the low side; this parameter is sometimes generically called VOUT and in this case the high side and low side output voltages are not differentiated. VB (or VCC) VB (or VCC) IO+ H (or LO) H (or LO) + VH (or VL ) (or VS ) (or Figure 1: HVIC sourcing current VS IO - ) Figure 2: HVIC sinking current www.irf.com © 2010 International Rectifier 12 IRS2334SPbF/MPbF Switching and Timing Relationships The relationship between the input and output signals of the IRS2334 HVIC is shown in Figure 3. The definitions of some of the relevant parameters associated with the gate driver input to output transmission are given. LIN or HIN 50% 50% PWIN t ON LO or HO tR PWOUT 90% 10% tOFF tF 90% 10% Figure 3: Switching time waveforms During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at the same time; correspondingly, the shoot-through protection prevents the high and low side signals HO and LO turn on by keeping them low. Figure 4: Input/output timing diagram Deadtime The IRS2334 HVIC provides an integrated deadtime protection circuitry. The deadtime interval for this HVIC is fixed; while other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time interval in which both the gate driver outputs LO and HO are held off; to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime commanded by the host microcontroller is shorter than DT, while external deadtimes larger than DT are not modified by the gate driver. Figure 7 illustrates the deadtime interval definition and the relationship between the output gate signals. www.irf.com © 2010 International Rectifier 13 IRS2334SPbF/MPbF The deadtime interval introduced is matched with respect to the commutation from HIN turning off to LIN turning on, and viceversa. Figure 5 defines the two deadtime parameters DT1 and DT2. The deadtime matching parameter MDT is defined as the maximum difference between DT1 and DT2. LIN HIN 50% LO HO 50% DT1 DT2 50% 50% Figure 5: Deadtime definition Matched Propagation Delays The IRS2334 HVIC is designed for propagation delay matching. With this feature, the input to output propagation delays tON, tOFF are the same for the low side and the high side channels; the maximum difference being specified by the delay matching parameter MT as defined in Figure 6. Figure 6: Delay Matching Waveform Definition Input Logic Compatibility The IRS2334 HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5 V logic level signals. Figure 7 shows how an input signal is logically interpreted. www.irf.com © 2010 International Rectifier 14 IRS2334SPbF/MPbF Figure 7: HIN & LIN input thresholds Shoot-Through Protection The IRS2334 is equipped with a shoot-through protection circuitry which prevents cross-conduction of the power switches. Table 1 shows the input to output relationship in the form of a truth table. Note that the HVIC has noninverting inputs (the output is in-phase with the respective input). HIN LIN HO LO 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 Table 1: Input/output truth table Under-Voltage Lockout Protection The IRS2334 HVIC provides under-voltage lockout protection on both the VCC low side and logic fixed power supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the VCC (or VBS) plotted over time: as the waveform crosses the UVLO threshold, the under-voltage protection is entered or exited. Upon power up, should the VCC voltage fail to reach the VCCUV+ threshold, the gate driver outputs LO and HO will remain disabled. Additionally, if the VCC voltage decreases below the VCCUV- threshold during normal operation, the under-voltage lockout circuitry will shutdown the gate driver outputs LO and HO. Upon power up, should the VBS voltage fail to reach the VBSUV threshold, the gate driver output HO will remain disabled. Additionally, if the VBS voltage decreases below the VBSUV threshold during normal operation, the undervoltage lockout circuitry will shutdown the high side gate driver output HO. The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven www.irf.com © 2010 International Rectifier 15 IRS2334SPbF/MPbF with a low voltage, which would result in power switches conducting current while with a high channel impedance, which would produce very high conduction losses possibly leading to power device failure. VCC (or B ) V CCU + (or BSU + ) VCCU (or BSU - ) Time UVLO Protection (Gate Driver Outputs Disabled ) Norma Operation Norma Operation Figure 8: UVLO protection Truth Table: Under-Voltage lockout Table 2 provides the truth table for the IRS2334 HVIC. The 1st line shows that for VCC below the UVLO threshold both the gate driver outputs LO and HO are disabled. After VCC returns above VCCUV, the gate driver outputs return functional. The 2nd line shows that for VBS below the UVLO threshold, the gate driver output HO is disabled. After VBS returns above VBSUV, HO remains low until a new rising transition of HIN is received. The last line shows the normal operation of the HVIC. UVLO VCC UVLO VBS Normal operation VCC VBS