IRS23365DM
Product Summary
Features
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Drives up to six IGBT/MOSFET power devices
Gate drive supplies up to 20 V per channel
Integrated bootstrap functionality
Over-current protection
Over-temperature shutdown input
Advanced input filter
Integrated deadtime protection
Shoot-through (cross-conduction) protection
Undervoltage lockout for VCC & VBS
Enable/disable input and fault reporting
Adjustable fault clear timing
Separate logic and power grounds
3.3 V input logic compatible
Tolerant to negative transient voltage
Designed for use with bootstrap power supplies
Matched propagation delays for all channels
-40°C to 125°C operating range
RoHS compliant
Lead-Free
Topology
3 Phase
VOFFSET
≤ 600 V
VOUT
10 V – 20 V
Io+ & I o- (typical)
180 mA & 380 mA
tON & tOFF (typical)
530 ns & 530 ns
Deadtime (typical)
275 ns
Package Options
48-Lead MLPQ7X7
(without 14 leads)
Typical Applications
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Appliance motor drives
Servo drives
Micro inverter drives
General purpose three phase inverters
Typical Connection Diagram
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© 2012 International Rectifier
3 December, 2012
IRS23365DM
Description
The IRS23365DM is a high voltage, high speed, power MOSFET and IGBT gate drivers with three high-side and three lowside referenced output channels for 3-phase applications. This IC is designed to be used with low-cost bootstrap power
supplies; the bootstrap diode functionality has been integrated into this device to reduce the component count and the PCB
size. Proprietary HVIC and latch immune CMOS technologies have been implemented in a rugged monolithic structure. The
floating logic input is compatible with standard CMOS or LSTTL outputs (down to 3.3 V logic). A current trip function which
terminates all six outputs can be derived from an external current sense resistor. Enable functionality is available to terminate
all six outputs simultaneously. An open-drain FAULT signal is provided to indicate that a fault (e.g., over-current, overtemperature, or undervoltage shutdown event) has occurred. Fault conditions are cleared automatically after a delay
programmed externally via an RC network connected to the RCIN input. The output drivers feature a high-pulse current
buffer stage designed for minimum driver cross-conduction. Shoot-through protection circuitry and a minimum deadtime
circuitry have been integrated into this IC. Propagation delays are matched to simplify the HVIC’s use in high frequency
applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high-side configuration,
which operate up to 600 V.
Simplified Block Diagram
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© 2012 International Rectifier
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IRS23365DM
Typical Application Diagram
DC Bus ≤ 600 V
+
To
Load
Input
Voltage
-
IRS2336xD
VCC
Control Inputs,
EN, & FAULT
Qualification Information†
Industrial
Qualification Level
††
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
†††
Moisture Sensitivity Level
MLPQ7X7
Human Body Model
ESD
Machine Model
Charged Device Model
††††
IC Latch-Up Test
RoHS Compliant
†
††
MSL3 , 260°C
(per IPC/JEDEC J-STD-020)
Class 1B
(per JEDEC standard JESD22-A114)
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Class IV
(per JEDEC standard JESD22-C101)
Class I, Level A
(per JESD78)
Yes
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your International
Rectifier sales representative for further information.
Charged Device Model classification is based on SOIC28W package.
†††
††††
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© 2012 International Rectifier
3 December, 2012
IRS23365DM
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to VSS unless otherwise stated in the table. The thermal resistance and power dissipation
ratings are measured under board mounted and still air conditions. Voltage clamps are included between VCC & COM (25 V),
VCC & VSS (25 V), and VB & VS (25 V).
Definition
Symbol
VCC
Low side supply voltage
VIN
Logic input voltage (HIN, LIN, ITRIP, EN)
VRCIN
VB
VS
VHO
VLO
VFLT
COM
dVS/dt
PW HIN
PD
Package power dissipation @ TA ≤+25ºC
RthJA
TJ
TS
TL
†
RCIN input voltage
High-side floating well supply voltage
High-side floating well supply return voltage
Floating gate drive output voltage
Low-side output voltage
Fault output voltage
Power ground
Allowable VS offset supply transient relative to VSS
High-side input pulse width
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min
Max
Units
†
-0.3
25
VSS-0.3
VSS+5.2
VSS-0.3
-0.3
†
VB-25
VS-0.3
COM-0.3
VSS-0.3
VCC-25
—
500
—
VCC+0.3
†
625
VB+0.3
VB+0.3
VCC+0.3
VCC+0.3
VCC+0.3
50
—
V/ns
ns
2.0
W
63
ºC/W
150
150
300
ºC
—
—
-55
—
V
All supplies are tested at 25 V. An internal 25 V clamp exists for each supply.
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© 2012 International Rectifier
3 December, 2012
IRS23365DM
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to VSS unless otherwise stated in the table. The offset rating is tested with supplies of (VCC-COM) = (VBVS) = 15 V.
Definition
Min
Max
10
VSS
20
VSS+5
VS+10
COM-8
-50
Vs
COM
-5
VSS
VSS
VSS
-40
VS+20
600
600
VB
VCC
5
VCC
VCC
VSS+5
125
Units
Symbol
VCC
VIN
Low-side supply voltage
HIN, LIN, & EN input voltage
VB
VS
VS(t)
VHO
VLO
COM
VFLT
VRCIN
VITRIP
TA
High-side floating well supply voltage
†
High-side floating well supply offset voltage
††
Transient high-side floating supply voltage
Floating gate drive output voltage
Low-side output voltage
Power ground
FAULT output voltage
RCIN input voltage
ITRIP input voltage
Ambient temperature
V
ºC
†
Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Please refer to Design Tip DT97-3 for
more details.
†† Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the
Application Information section of this datasheet for more details.
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IRS23365DM
Static Electrical Characteristics
o
(VCC-COM) = (VB-VS) = 15 V. TA = 25 C unless otherwise specified. The VIN and IIN parameters are referenced to VSS and are
applicable to all six channels. The VO and IO parameters are referenced to respective VS and COM and are applicable to the
respective output leads HO or LO. The VCCUV parameters are referenced to VSS. The VBSUV parameters are referenced to VS.
Symbol
VCCUV+
Definition
VCC supply undervoltage positive going threshold
VCC supply undervoltage negative going
threshold
VCC supply undervoltage hysteresis
VBS supply undervoltage positive going threshold
VBS supply undervoltage negative going
threshold
VBS supply undervoltage hysteresis
High-side floating well offset supply leakage
Quiescent VBS supply current
Quiescent VCC supply current
High level output voltage drop, VBIAS-VO
Low level output voltage drop, VO
Min
8
Typ
8.9
7.4
8.2
9
0.3
0.7
—
8
8.9
9.8
7.4
8.2
9
0.3
—
—
—
—
—
—
0.7
—
70
2
0.90
0.40
50
120
4
1.4
0.6
Io+
Output high short circuit pulsed current
120
180
—
Io-
Output low short circuit pulsed current
250
380
—
VIH
Logic “1” input voltage
2.5
—
—
VIL
Logic “0” input voltage
Input voltage clamp
(HIN, LIN, ITRIP and EN)
Input bias current (HO = High)
—
—
0.8
4.8
5.2
5.65
IIN = 100 µA
—
165
220
VIN = 0 V
Input bias current (HO = Low)
Input bias current (LO = High)
Input bias current (LO = Low)
RCIN positive going threshold
RCIN hysteresis
RCIN input bias current
RCIN low on resistance
ITRIP positive going threshold
ITRIP negative going threshold
ITRIP hysteresis
“High” ITRIP input bias current
“Low” ITRIP input bias current
Enable positive going threshold
Enable negative going threshold
“High” enable input bias current
“Low” enable input bias current
FAULT low on resistance
Internal BS diode Ron
—
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—
—
—
—
—
0.37
—
—
—
—
—
0.8
—
—
—
—
120
165
120
8
3
—
50
0.46
0.4
0.07
5
—
—
—
5
—
50
200
165
220
165
—
—
1
100
0.55
—
—
20
1
2.5
—
20
1
100
—
VCCUVVCCUVHY
VBSUV+
VBSUVVBSUVHY
ILK
IQBS
IQCC
VOH
VOL
Max
9.8
Units
Test Conditions
V
NA
µA
mA
V
V
mA
VIN,CLAMP
IHIN+
IHINILIN+
ILINVRCIN,TH
VRCIN,HY
IRCIN
RON,RCIN
VIT,TH+
VIT,THVIT,HYS
IITRIP+
IITRIPVEN,TH+
VEN,THIEN+
IENRON,FLT
RBS
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© 2012 International Rectifier
VB = VS = 600 V
All inputs are in the off
state
IO= 20 mA
VO=0 V,VIN=0 V,
PW ≤ 10 µs
VO=15 V,VIN=5 V,
PW ≤ 10 µs
NA
V
µA
VIN = 4 V
VIN = 0 V
VIN = 4 V
V
NA
µA
Ω
V
VRCIN = 0 V or 15 V
I = 1.5 mA
NA
µA
VIN = 4 V
VIN = 0 V
NA
V
µA
Ω
VIN = 4 V
VIN = 0 V
I = 1.5 mA
NA
3 December, 2012
IRS23365DM
Dynamic Electrical Characteristics
o
VCC= VB = 15 V, VS = VSS = COM, TA = 25 C, and CL = 1000 pF unless otherwise specified.
Symbol
tON
tOFF
tR
tF
tFIL,IN
tEN
tFILTER,EN
tFLTCLR
tITRIP
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
†
Input filter time
(HIN, LIN, ITRIP)
Min
400
400
—
—
Typ
530
530
125
50
Max
750
750
190
75
200
350
510
Enable low to output shutdown
propagation delay
350
460
650
Enable input filter time
100
200
—
VIN = 0 V & 5 V
ns
VIN, VEN = 0 V or 5 V
NA
FAULT clear time
RCIN: R = 2 MΩ, C = 1 nF
1.3
ITRIP to output shutdown
propagation delay
500
750
1200
VITRIP = 5 V
—
400
—
VIN = 0 V or 5 V
VITRIP = 5 V
1.65
2
tFLT
ITRIP to FAULT propagation delay
400
600
950
Deadtime
190
—
275
—
420
DT matching
ms
VITRIP = 0 V
ITRIP blanking time
MDT
Test Conditions
VIN = 0 V or 5 V
tBL
DT
Units
††
VIN = 0 V & 5 V without
60
ns
external deadtime
MT
Delay matching time (tON, tOFF)
PM
Pulse width distortion
†
†††
††
—
—
—
—
50
75
VIN = 0 V & 5 V with
external deadtime larger
than DT
PW input=10 µs
The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the input
filter is exceeded.
This parameter applies to all of the channels. Please see the application section for more details.
PM is defined as PW IN - PW OUT.
††
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IRS23365DM
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© 2012 International Rectifier
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IRS23365DM
Functional Block Diagram: IRS23365D
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IRS23365DM
Input/Output Pin Equivalent Circuit Diagrams: IRS23365D
VB
ESD
Diode
20 V
Clamp
HO
ESD
Diode
V CC
ESD
Diode
VS
RPU
20 V
Clamp
HIN
or LIN
ESD
Diode
600V
VC C
V IN
Clamp
ESD
Diode
VSS
25 V
Clamp
LO
ESD
Diode
COM
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IRS23365DM
Lead Definitions: IRS23365DM
Symbol
Description
VCC
Low-side supply voltage
VSS
Logic ground
VB1
High-side gate drive floating supply (phase 1)
VB2
High-side gate drive floating supply (phase 2)
VB3
High-side gate drive floating supply (phase 3)
VS1
High voltage floating supply return (phase 1)
VS2
High voltage floating supply return (phase 2)
VS3
High voltage floating supply return (phase 3)
HIN1/N
Logic inputs for high-side gate driver outputs (phase 1); input is out-of-phase with output
HIN2/N
Logic inputs for high-side gate driver outputs (phase 2); input is out-of-phase with output
HIN3/N
Logic inputs for high-side gate driver outputs (phase 3); input is out-of-pha
LIN1/N
Logic inputs for low-side gate driver outputs (phase 1); input is out-of-phase with output
LIN2/N
Logic inputs for low-side gate driver outputs (phase 2); input is out-of-phase with output
LIN3/N
Logic inputs for low-side gate driver outputs (phase 3); input is out-of-phase with output
se with output
HO1
High-side driver outputs (phase 1)
HO2
High-side driver outputs (phase 2)
HO3
High-side driver outputs (phase 3)
LO1
Low-side driver outputs (phase 1)
LO2
Low-side driver outputs (phase 2)
LO3
Low-side driver outputs (phase 3)
COM
Low-side gate drive return
Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred. This pin
has negative logic and an open-drain output. The use of over-current and over-temperature protection
requires the use of external components.
Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No effect on
FAULT and not latched.
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates FAULT and
RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time tFLTCLR, then
automatically becomes inactive (open-drain high impedance).
An external RC network input used to define the FAULT CLEAR delay (tFLTCLR) approximately equal to R*C.
When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance state.
FAULT/N
EN
ITRIP
RCIN
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IRS23365DM
Lead Assignments
The central exposed pad (35) has to be connected to COM for better electrical performance.
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IRS23365DM
Application Information and Additional Details
Information regarding the following topics are included as subsections within this section of the datasheet.
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IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Undervoltage Lockout Protection
Shoot-Through Protection
Enable Input
Fault Reporting and Programmable Fault Clear Timer
Over-Current Protection
Over-Temperature Shutdown Protection
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Advanced Input Filter
Short-Pulse / Noise Rejection
Integrated Bootstrap Functionality
Bootstrap Power Supply Design
Separate Logic and Power Grounds
Tolerant to Negative VS Transients
PCB Layout Tips
Integrated Bootstrap FET limitation
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS23365D HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several
parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the
power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side
power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not
differentiate between the high-side or low-side output voltage.
VB
(or VCC)
VB
(or VCC)
IO+
HO
(or LO)
HO
(or LO)
+
IO-
VHO (or VLO)
VS
(or COM)
-
VS
(or COM)
Figure 1: HVIC sourcing current
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© 2012 International Rectifier
Figure 2: HVIC sinking current
3 December, 2012
IRS23365DM
Switching and Timing Relationships
The relationship between the input and output signals of the IRS23365D are illustrated below in Figures 3 . From these
figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this
device.
LINx
(or HINx)
50%
50%
PWIN
tON
LOx
(or HOx)
tOFF
tR
tF
PWOUT
90%
10%
90%
10%
Figure 3: Switching time waveforms
The following two figures illustrate the timing relationships of some of the functionality of the IRS23365D; this functionality is
described in further detail later in this document.
During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same
time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output
are held in the off state.
Interval B of Figures 4 and 5 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of
the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low), the voltage
on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT output transitioning to the low state. Once the
ITRIP input has returned to the low state, the output will remain disabled and the fault condition reported until the voltage on
the RCIN pin charges up to VRCIN,TH (see interval C in Figure 6); the charging characteristics are dictated by the RC network
attached to the RCIN pin.
During intervals D and E of Figure 4, we can see that the enable (EN) pin has been pulled low (as is the case when the driver IC
has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx) being held in the low state
until the enable pin is pulled high.
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IRS23365DM
Figure 4: Input/output timing diagram
Interval B
Interval C
VIT,TH-
VIT,TH+
ITRIP
FAULT
tFLT
50%
50%
RCIN
VRCIN,TH
90%
HOx
tFLTCLR
tITRIP
Figure 5: Detailed view of B & C intervals
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a
minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power
switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is
automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified
by the gate driver. Figure 6 illustrates the deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS23365D is matched with respect to the high- and low-side outputs of a given channel;
additionally, the deadtimes of each of the three channels are matched. Figure 6 defines the two deadtime parameters (i.e.,
DT1 and DT2) of a specific channel; the deadtime matching parameter (MDT) associated with the IRS23365D specifies the
maximum difference between DT1 and DT2. The MDT parameter also applies when comparing the DT of one channel of the
IRS23365D to that of another.
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3 December, 2012
IRS23365DM
Figure 6: Illustration of deadtime
Matched Propagation Delays
The IRS23365D is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a
signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the highside channels; the maximum difference is specified by the delay matching parameter (MT). Additionally, the propagation delay
for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the highside channels are matched with each other; the MT specification applies as well. The propagation turn-on delay (tON) of the
IRS23365D is matched to the propagation turn-on delay (tOFF).
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS23365D has been designed to be
compatible with 3.3 V and 5 V logic-level signals. Figure 7 illustrates an input signal to the IRS23365D, its input threshold
values, and the logic state of the IC as a result of the input signal.
Figure 7: HIN & LIN input thresholds
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IRS23365DM
Undervoltage Lockout Protection
This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the
VBS (high-side circuitry) power supply. Figure 8 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the
waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC
voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault
condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform
the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage
decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and
shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to
fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low
voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high
conduction losses within the power device and could lead to power device failure.
Figure 8: UVLO protection
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IRS23365DM
Shoot-Through Protection
The IRS23365D is equipped with shoot-through protection circuitry (also known as cross-conduction prevention circuitry).
Figure 9 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time.
Table 1 illustrates the input/output relationship of the devices in the form of a truth table.
Figure 9: Illustration of shoot-through protection circuitry
IRS23365D
HIN
LIN
HO
LO
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
Table 1: Input/output truth table for IRS23365D
Enable Input
The IRS23365D is equipped with an enable input pin that is used to shutdown or enable the HVIC. When the EN pin is in the
high state the HVIC is able to operate normally (assuming no other fault conditions). When a condition occurs that should
shutdown the HVIC, the EN pin should see a low logic state. The enable circuitry of the IRS23365D features an input filter; the
minimum input duration is specified by tFILTER,EN. Please refer to the EN pin parameters VEN,TH+, VEN,TH-, and IEN for the details
of its use. Table 2 gives a summary of this pin’s functionality and Figure 10 illustrates the outputs’ response to a shutdown
command.
EN
VEN,TH-
Enable Input
tEN
*
Enable input high
Outputs enabled
Enable input low
Outputs disabled
Table 2: Enable functionality truth table
HOx
(or LOx)
90%
Figure 10: Output enable timing waveform
(*assumes no other fault condition)
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IRS23365DM
Fault Reporting and Programmable Fault Clear Timer
The IRS23365D provides an integrated fault reporting output and an adjustable fault clear timer. There are two situations that
would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the
ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault clear timer
is activated. The fault output stays in the low state until the fault condition has been removed and the fault clear timer expires;
once the fault clear timer expires, the voltage on the FAULT pin will return to VCC.
The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the capacitor where
the time constant is set by RRCIN and CRCIN. In Figure 11 where we see that a fault condition has occurred (UVLO or ITRIP),
RCIN and FAULT are pulled to VSS, and once the fault has been removed, the fault clear timer begins. Figure 12 shows that
RRCIN is connected between the VCC and the RCIN pin, while CRCIN is placed between the RCIN and VSS pins.
Figure 11: RCIN and FAULT pin waveforms
Figure 12: Programming the fault clear timer
The design guidelines for this network are shown in Table 3.
≤1 nF
CRCIN
Ceramic
0.5 MΩ to 2 MΩ
RRCIN
>> RON,RCIN
Table 3: Design guidelines
The length of the fault clear time period can be determined by using the formula below.
vC(t) = Vf(1-e
-t/RC
)
tFLTCLR = -(RRCINCRCIN)ln(1-VRCIN,TH/VCC)
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IRS23365DM
Over-Current Protection
The IRS23365D HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in
the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is
reported through the FAULT pin, and RCIN is pulled to VSS.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2)
connected to ITRIP as shown in Figure 13, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the
maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the
over-current threshold (VIT,TH+) at that current level.
VIT,TH+ = R0IDC-(R1/(R1+R2))
Figure 13: Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5
V; if necessary, an external voltage clamp may be used.
Over-Temperature Shutdown Protection
The ITRIP input of the IRS23365D can also be used to detect over-temperature events in the system and initiate a shutdown
of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the
resistor network as shown in Figure 14 and select the maximum allowable temperature.
This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the
thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the
voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable
temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.
When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g.,
DL4148) can be used. This network is shown in Figure 15; the OR-ing diodes have been labeled D1 and D2.
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IRS23365DM
Figure 14: Programming over-temperature
protection
Figure 15: Using over-current protection and overtemperature protection
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Table 4 provides the truth table for the IRS23365D. The first line shows that the UVLO for VCC has been tripped; the FAULT
output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater
than VCCUV, the FAULT output returns to the high impedance state.
The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled.
After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising transition of HIN. The third
case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and
that the gate drive outputs have been disabled and a fault has been reported through the fault pin. In the last case, the HVIC
has received a command through the EN input to shutdown; as a result, the gate drive outputs have been disabled.
UVLO VCC
UVLO VBS
Normal operation
ITRIP fault
EN command
VCC
