IRS2509STRPBF

Not recommended for new designs. For new designs, we recommend IRS2109SPBF November 15, 2010 IRS2509SPbF HALF-BRIDGE DRIVER Features             600V half-bridge driver Tolerant to negative transient voltages Gate drive supply range from 10 V to 20 V Under-voltage lock-out for both channels 3.3 V, 5 V and 15 V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High side output in phase with IN input Internal 530 ns dead-time Lower di/dt gate driver for better noise immunity Shut down input turns off both channels RoHS compliant Description The IRS2509 is a high-voltage, high-speed power MOSFET and IGBT half-bridge driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable a ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600V. Typical Connection Packages 8-Lead SOIC Product Summary VOFFSET IO+/VOUT ton/off (typ.) Dead Time Applications: *HID Electronic Ballasts 600 V max. 120 mA / 250 mA 10 V – 20 V 750 ns & 200 ns 530 ns Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF † Qualification Information Qualification Level Moisture Sensitivity Level Machine Model ESD IC Latch-Up Test RoHS Compliant Human Body Model Industrial†† (per JEDEC JESD 47) Comments: This IC has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. ††† MSL2 SOIC-8N (per IPC/JEDEC J-STD-020) Class B (+/-200V) (per JEDEC standard JESD22-A115) Class 1C (+/-1000V) (per EIA/JEDEC standard EIA/JESD22-A114) Class I, Level A (per JESD78A) Yes † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com 2 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units VB High side floating absolute voltage -0.3 620 VS High side floating supply offset voltage VB - 20 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side and logic fixed supply voltage -0.3 20 VLO VIN Low side output voltage -0.3 COM -0.3 VCC + 0.3 VCC + 0.3 Logic input voltage (IN & SD) V COM Logic ground VCC - 20 VCC + 0.3 dVS/dt Allowable offset supply voltage transient — 50 V/ns Package power dissipation @ TA ≤ +25 °C — 0.625 W Thermal resistance, junction to ambient — 200 °C/W PD RthJA TJ Junction temperature — 150 TS Storage temperature -50 150 TL Lead temperature (soldering, 10 seconds) — 300 °C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. The VS and COM offset rating are tested with all supplies biased at 15 V differential. Symbol Definition VB High side floating supply absolute voltage VS Static High side floating supply offset voltage VSt Transient High side floating supply offset voltage High side floating output voltage VHO Min. Max. VS +10 COM- 8(Note 1) VS +20 600 -50 (Note2) 600 VS VB VCC Low side and logic fixed supply voltage 10 20 VLO Low side output voltage 0 VCC VIN Logic input voltage (IN & SD) Units V VSS VCC TA Ambient temperature -40 125 °C Note 1: Logic operational for VS of -8 V to +600 V. Logic state held for VS of -8 V to – VBS. Note 2: Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com 3 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15 V, COM = VCC, CL = 1000 pF, TA = 25 °C, DT = VSS unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions ton Turn-on propagation delay — 750 1100 toff Turn-off propagation delay — 250 400 tsd Shut-down propagation delay — 250 400 MT Delay matching, HS & LS turn-on/off — — 60 tr Turn-on rise time — 150 220 t Turn-off fall time — 50 80 VS = 0 V 350 530 800 — — — — 60 60 VIN = 0 V & 5 V Without external deadtime f DT MT MDT Deadtime: LO turn-off to HO turn-on(DTLO-HO) HO turn-off to LO turn-on (DTHO-LO) Delay matching time (t ON , t OFF) Deadtime matching = DTLO-HO - DTHO-LO & VS = 0 V or 600 V VS = 0 V or 600 V ns VS = 0 V Static Electrical Characteristics VBIAS (VCC, VBS) = 15 V, VCC = COM, DT = VCC and TA = 25 °C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to VCC/COM and are applicable to the respective input leads: IN and SD. The VO, IO parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Min Typ Max Units Test Conditions VIH logic “1” input voltage for HO & logic “0” for LO 2.2 VIL logic “0” input voltage for HO & logic “1” for LO VOH High level output voltage, VBIAS - VO VOL Low level output voltage, VO ILK Offset supply leakage current IQBS Quiescent VBS supply current IQCC Quiescent VCC supply current IIN+ IIN- Logic “1” input bias current Logic “0” input bias current SD input positive going threshold SD input negative going threshold VCC and VBS supply undervoltage positive going Threshold VCC and VBS supply undervoltage negative going Threshold ISD, TH+ ISD, THVCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH Hysteresis — — — — 0.8 — 0.8 1.4 — 0.3 0.6 — — 50 VB = VS = 600 V — 45 70 VIN = 0 V or 4 V 1000 2000 3000 — — — — 5 — 15 10 20 2 30 20 8.0 8.9 9.8 7.4 8.2 9.0 — 0.7 — IO+ Output high short circuit pulsed current 120 200 — IO- Output low short circuit pulsed current 250 350 — www.irf.com V IO = 20 mA IO = 20 mA µA VIN = 0 V or 4 V VIN = 4 V VIN = 0 V V mA VO = 0 V, PW ≤ 10 us VO = 15 V, PW ≤ 10 us 4 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Functional Block Diagrams Lead Definitions Symbol Description VB Logic input for high and low side gate driver outputs (HO and LO), in phase Logic input for shutdown High side floating supply HO VS VCC High side gate drive output High side floating supply return Low side and logic fixed supply IN SD LO COM Low side gate drive output Low side return Lead Assignments www.irf.com 5 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Application Information and Additional Details Informations regarding the following topics are included as subsections within this section of the datasheet.            IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Shut down Input Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Negative VS Transient SOA PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS2509 HVIC is designed to drive MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the lowside power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. Figure 1: HVIC sourcing current www.irf.com Figure 2: HVIC sinking current 6 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Switching and Timing Relationships The relationships between the input and output signals of the IRS2509 are illustrated below in Figures 3, 4. From these figures, we can see the definitions of several timing parameters (i.e. tON, tOFF, tR, and tF) associated with this device. Figure 3: Switching time waveforms Figure 4: Input/output timing diagram Deadtime This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserter whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of the IRS2509 is matched with respect to the high- and low-side outputs. Figure 6 defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT) associated with the IRS2509 specifies the maximum difference between DTLO-HO and DTHO-LO. Matched Propagation Delays The IRS2509 is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON) of the IRS2509 is matched to the propagation turn-on delay (tOFF). www.irf.com 7 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Shut down Input The IRS2509 is equipped with a shut down (/SD) input pin that is used to shutdown or enable the HVIC. When the /SD pin is in the high state the HVIC is able to operate normally. When the /SD pin is in low state the HVIC is tristated. 50% 50% IN 90% HO LO DTLO-HO 10% 90% DTHO-LO 10% MDT = DTLO-HO Figure 5: Shut down - DTHO-LO Figure 6: Dead time Definition Figure 7: Delay Matching waveform Definition Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2509 has been designed to be compatible with 3.3 V and 5 V logic-level signals. The IRS2509 features an integrated 5.2 V Zener clamp on the /SD. Figure 8 illustrates an input signal to the IRS2509, its input threshold values, and the logic state of the IC as a result of the input signal. www.irf.com 8 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Input Logic Level Input Signal (IRS23364D) V IH VIL High Low Low Figure 8: HIN & LIN input thresholds Undervoltage Lockout Protection This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 9 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. Figure 9: UVLO protection Shoot-Through Protection The IRS2509 high-voltage IC is equipped with shoot-through protection circuitry (also known as cross-conduction prevention circuitry). www.irf.com 9 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Negative VS Transient SOA A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 11; here we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 12 and 13) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. Figure 11: Three phase inverter DC+ BUS DC+ BUS Q1 ON Q1 OFF D1 IU VS1 Q2 OFF VS1 D2 DC- BUS Figure 12: Q1 conducting Q2 OFF IU D2 DC- BUS Figure 13: D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 14 and 15), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. www.irf.com 10 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF DC+ BUS Q3 OFF D3 VS2 IV Q4 ON DC- BUS Figure 14: D3 conducting Figure 15: Q4 conducting However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”. The circuit shown in Figure 16 depicts one leg of the three phase inverter; Figures 17 and 18 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). Figure 16: Parasitic Elements Figure 17: VS positive Figure 18: VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An indication of the IRS2509’s robustness can be seen in Figure 19, where there is represented the IRS2509 Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA. At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design the high-side outputs in the off state for 4.5 μs. www.irf.com 11 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Figure 19: Negative VS transient SOA for IRS2509 @ VBS=15V Even though the IRS2509 has been shown able to handle these large negative VS transient conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use. PCB Layout Tips Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case Outline information in this datasheet for the details. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 20). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. www.irf.com 12 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Figure 20: Antenna Loops Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic 1 μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce parasitic elements. Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 21), and in some cases using a clamping diode between COM and VS (see Figure 22). See DT04-4 at www.irf.com for more detailed information. Figure 21: VS resistor Figure 22: VS clamping diode Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs www.irf.com 13 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF 1500 Turn-Off Propagation Delay (ns) Turn-On Propagation Delay (ns) Figures 23-45 provide information on the experimental performance of the IRS2509 HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 1200 900 Exp. 600 300 0 -50 -25 0 25 50 75 100 500 400 300 Exp. 200 100 0 125 -50 -25 0 o 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 23. Turn-on Propagation Delay vs. Temperature Fig. 24. Turn-off Propagation Delay vs. Temperature 250 Turn-Off fall Time (ns) Turn-On Rise Time (ns) 25 200 150 100 125 100 75 50 Exp. Exp. 50 ` 25 0 0 -50 -25 0 25 50 75 100 Temperature (oC) Fig. 25. Turn-on Rise Time vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 26. Turn-off Rise Time vs. Temperature 14 Not recommended for new designs. For new designs, we recommend IRS2109SPBF 4 4 3 3 VBSUV hysteresis (V) VCCUV hysteresis (V) IRS2509SPbF 2 1 Exp. 2 1 Exp. 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 100 125 Temperature ( C) Fig. 27. VCC Supply UV Hysteresis vs. Temperature Fig. 28. VBS Supply UV Hysteresis vs. Temperature 100 VBS Quiescent Current (µA) 10 VCC Quiescent Current (mA) 75 o Temperature (oC) 8 6 4 2 Exp. 0 -50 -25 0 25 50 75 100 80 60 Exp. 40 ` 20 0 -50 125 -25 0 25 50 75 100 125 o Temperature ( C) Temperature (oC) Fig. 30. VBS Quiescent Supply Current vs. Temperature Fig. 29. VCC Quiescent Supply Current vs. Temperature 12 12 Exp. 9 VCCUV- Threshold (V) VCCUV+ Threshold (V) 50 6 3 0 9 Exp. 6 3 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 31. VCCUV+ Threshold vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 32. VCCUV- Threshold vs. Temperature 15 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF 12 Exp. 9 9 V BSUV- Threshold (V) VBSUV+ Threshold (V) 12 6 3 Exp. 6 3 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 50 75 100 125 o Temperature ( C) Fig. 33. VBSUV+ Threshold vs. Temperature Fig. 34. VBSUV- Threshold vs. Temperature 400 300 200 EXP. 100 0 -50 -25 0 25 50 75 100 125 High Level Output Voltage (mV) 400 Low Level Output Voltage (mV) 25 300 200 Exp. 100 0 -50 -25 0 Temperature (oC) 25 50 75 100 125 o Temperature ( C) Fig. 36. High Level Output Voltage vs. Temperature Fig. 35. Low Level Output Voltage vs. Temperature 8 IN VTH+ (V) 6 4 Exp. 2 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 37. IN VTH+ vs. Temperature www.irf.com 16 Not recommended for new designs. For new designs, we recommend IRS2109SPBF 8 8 6 6 HIN VTH+ (V) IN VTH- (V) IRS2509SPbF 4 2 Exp. 0 4 Exp. 2 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 o 100 125 Temperature ( C) Fig. 39. HIN VTH+ vs. Temperature Fig. 38. LIN VTH- vs. Temperature 8 50 6 40 Tbson_VccTYP(ns) HIN VTH- (V) 75 o Temperature ( C) 4 2 Exp. 0 30 20 Exp. 10 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 Temperature (oC) 75 100 125 Temperature ( C) Fig. 41. Tbson_VCCTYP vs. Temperature 1000 400 800 Deadtime (ns) 500 300 50 o Fig. 40. HIN VTH- vs. Temperature Shut-down propagation delay (ns) 50 Exp. 200 100 0 Exp. 600 400 200 0 -50 -25 0 25 50 75 100 Temperature (oC) Fig. 42. Shut-down Propagation Delay vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 43. Deadtime vs. Temperature 17 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF 30 50 25 40 20 20 MDT (ns) MT (ns) 30 Exp. 10 15 Exp. 10 5 0 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 44. Delay Matching vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 45. Deadtime Matching vs. Temperature 18 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Case Outlines www.irf.com 19 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF Tape and Reel Details: 8L-SOIC LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 20 Not recommended for new designs. For new designs, we recommend IRS2109SPBF IRS2509SPbF S2509 ORDER INFORMATION 8-Lead SOIC IRS2509SPbF 8-Lead SOIC Tape & Reel IRS2509STRPbF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com 21