IRS26302DJPBF

Data Sheet No. PD 60321A IRS26302DJPBF FULLY PROTECTED 3-PHASE BRIDGE PLUS ONE GATE DRIVER Product Summary Features • • • • • • • • • • • • • • • • Floating channel designed for bootstrap operation, fully operational to +600 V Tolerant to negative transient voltage – dV/dt immune Full three phase gate driver plus one low side driver Undervoltage lockout for all channels Cross-conduction prevention logic Power-on reset Integrated bootstrap diode for floating channel supply Over current protection on: DC-(Itrip), DC+(Ground fault), PFCtrip/BRtrip (PFC/Brake protection). Single pin fault diagnostic function Diagnostic protocol to address fault register Self biasing for ground fault detection high voltage circuit 3.3 V logic compatible Lower di/dt gate drive for better noise immunity Externally programmable delay for automatic fault clear RoHS compliant Typical Applications • • • • Topology 3 Phase VOFFSET ≤ 600 V VOUT 10 V – 20 V Io+ & I o- (typical) 200 mA & 350 mA Deadtime (typical) 290 ns Package 44-Lead PLCC Air conditioners inverters Micro/Mini inverter drives General purpose inverter Motor control Typical Connection Diagram www.irf.com 3-Jul-09 © 2009 International Rectifier IRS26302DJ Table of Contents Page Description 3 Simplified Block Diagram 3 Typical Application Diagram 4 Qualification Information 5 Absolute Maximum Ratings 6 Recommended Operating Conditions 7 Static Electrical Characteristics 8 Dynamic Electrical Characteristics 10 Functional Block Diagram 12 Input/Output Pin Equivalent Circuit Diagram 13 Lead Definitions 14 Lead Assignments 15 Application Information and Additional Details 16 Parameter Temperature Trends 36 Package Details 49 Tape and Reel Details 50 Part Marking Information 51 Ordering Information 52 www.irf.com © 2009 International Rectifier 2 IRS26302DJ Description The IRS26302DJPBF are high voltage, high speed power MOSFET and IGBT drivers with three independent high and low side referenced output channels for 3-phase applications. An additional low side driver is included for PFC or Brake IGBT driving operation. Proprietary HVIC technology enables rugged monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. Three current trip functions that terminate all seven outputs can be derived from three external shunt resistors. Each overcurrent trip functions consists of detecting excess current across a shunt resistor on DC+ bus, on DC- bus and on Brake or PFC circuitry. An enable function is available to terminate all outputs simultaneously and is provided through a bidirectional pin combined with an open-drain FAULT pin. Fault signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault conditions are cleared automatically after an externally programmed delay via an RC network connected to the RCIN input. A diagnostic feature can give back to the controller the fault cause (UVcc, DC- or DC- overcurrent) and address a fault register. The output drivers feature a high pulse current buffer stage. Propagation delays are matched to simplify use in high frequency applications designed for minimum driver cross conduction. The floating channel can be used to drive N-channel power MOSFET’s or IGBT’s in the high side configuration which operates up to 600 V. Simplified Block Diagram www.irf.com © 2009 International Rectifier 3 IRS26302DJ Typical Application Diagram DC+ BUS V cc VDC GF VSDC HIN (x3) LIN (x3) AC main VB ( x3 ) FLT/EN PCFtrip/BRtrip IRS26302D PCFin/BRin PCFout/BRout RCIN HO ( x 3) VS (x 3) VS1 VS2 VS 3 To Load LO (x 3) ITRIP COM VSS DC - BUS www.irf.com © 2009 International Rectifier 4 IRS26302DJ † Qualification Information †† Industrial (per JEDEC JESD 47E) Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. Qualification Level ††† PLCC44 Moisture Sensitivity Level Class B (per JEDEC standard JESD22-A114D) Class 2 (per EIA/JEDEC standard EIA/JESD22-A115-A) Class IV (per JEDEC standard JESD22-C101C) Class I, Level A (per JESD78A) Yes Machine Model ESD MSL3 (per IPC/JEDEC J-STD-020C) Human Body Model Charged Device Model IC Latch-Up Test RoHS Compliant † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com © 2009 International Rectifier 5 IRS26302DJ Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Voltage clamps are included between VCC & COM (25 V), VCC & VSS (20 V), and VB & VS (20 V). Symbol Min. Max. VB1,2,3 High side floating supply voltage -0.3 620 VHO1,2,3 High side floating output voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3 VS1,2,3 High side offset voltage VB1,2,3 - 20 VB 1,2,3 + 0.3 VDC DCbus Supply Voltage -0.3 620 GF VSDC VCC COM VLO1,2,3 VIN VPFCtrip/VBRtrip dV/dt PD RTHJA † Definition Input voltage for Ground Fault detection VDC-20 VDC+0.3 High voltage return for Ground Fault circuit VDC-20 VDC+0.3 -0.3 VCC - 25 20† VCC + 0.3 -0.3 VCC + 0.3 -0.3 VCC + 0.3 -2 — — — VCC + 0.3 50 4.6 27 150 Low side and logic fixed supply voltage Power ground Low side output voltage LO1,2,3, PFCout Input voltage LIN1,2,3, HIN1,2,3, ITRIP, PFCtrip, FLTEN, RCIN Input voltage VPFCtrip/VBRtrip Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient TJ Junction temperature — TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 Units V V/ns W °C/W °C All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply. www.irf.com © 2009 International Rectifier 6 IRS26302DJ Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated in the table. The offset rating is tested with supplies of (VCC-COM) = (VB-VS) = 15 V. For proper operation the device should be used within the recommended conditions. Symbol Definition Min. Max. VB1,2,3 High side floating supply voltage VS1,2,3 + 10 VHO 1,2,3 High side output voltage HO1,2,3 VS1,2,3 VS 1,2,3 High side floating supply voltage † Vss – 8 600 VSt 1,2,3 Transient high side floating supply voltage †† -50 600 VDC GF VSDC VCC VLO1,2,3 COM VSCOM VFLT VRCIN VS1,2,3 + 20 VB1,2,3 DCbus Supply Voltage (TBD) 600 Input voltage for Ground Fault detection VDC-5 VDC High voltage return for Ground Fault circuit VDC-12 VDC-11 Low side supply voltage 10 20 Low side output voltage LO1,2,3, PFCout 0 VCC Power ground -5 5 V 1) Negative transient Vs voltage 0 -20 FAULT output voltage 0 VCC 0 VCC VHO 1,2,3 High side output voltage VS1,2,3 VB1,2,3 VLO1,2,3 Low side output voltage VITRIP PFCITRIP /BRITRIP VIN TA † †† RCIN input voltage COM VCC ITRIP input voltage 0 5 PFCITRIP/BRITRIP input voltage -2 0 VSS -40 VSS +5 125 Logic input voltage LIN, HIN, PFCin, BRin, EN Ambient temperature Units ºC Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Please refer to Design Tip DT97-3 for more details. Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com © 2009 International Rectifier 7 IRS26302DJ Static Electrical Characteristics (VCC-COM) = (VB-VS) = 15 V. TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective output leads HO or LO. The VCCUV parameters are referenced to VSS. The VBSUV parameters are referenced to VS. The PFCIo/BRIo and VPFC/ VBR are referenced to VSS and are applicable to PFCout/BRout lead. Symbol Definition Min Typ Max VIH Logic “1” input voltage 2.5 — — VIL Logic “0” input voltage — — 0.8 VIN,TH+ Input positive going threshold — 1.9 2.5 VIN,TH- Input negative going threshold 0.8 1 — VIT,TH+ Input positive going threshold 0.160 0.200 0.240 VIT,TH- Input negative going threshold 0.144 0.180 0.216 — 20 — PFC/BR positive going threshold -0.144 -0.180 -0.216 PFC/BR negative going threshold -0.160 -0.200 -0.240 — 20 — GF positive going threshold 0.140 0.180 0.220 VGFT,TH- GF negative going threshold 0.150 0.200 0.240 VIT,HYS VPFCT,TH+ VBRT,TH+ VPFCT,THVBRT,THVPFCT,HYS VBRT,HYS VGFT,TH+ ITRIP hysteresis PFC/BR hysteresis VGFT,HYS GF hysteresis — 20 — RCIN positive going threshold — 8 — VRCIN,HYS RCIN hysteresis VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage hysteresis VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VBS supply undervoltage hysteresis — 3 — 10.2 11.1 12.0 10.0 10.9 11.8 — 0.2 — 10.2 11.1 12.0 10.0 10.9 11.8 — 0.2 — VCC,UVTHVCC,UVHYS VBS,UVTH+ VBS, UVTHVBS,UVHS Test Conditions V mV V VRCIN,TH+ VCC,UVTH+ Units mV V VGFT = VDC - VGF mV V Offset supply leakage current — — 50 Iqbs Quiescent VBS supply current — 45 120 — 2.5 4 100 200 — 190 350 — mA Vout = 15 V, PW > RON,RCIN Table 3: Design guidelines www.irf.com © 2009 International Rectifier 22 IRS26302DJ The length of the fault clear time period can be determined by using the formula below. -t/RC vC(t) = Vf(1-e ) tFLTCLR = -(RRCINCRCIN)ln(1-VRCIN,TH/VCC) Over-Current Protections The IRS26302DJ HVICs are equipped with an ITRIP, GF and PFCtrip input pin. These functionality can be used to detect over-current events in the DC- bus, in the DC+ bus, in the PFC section and Ground related. Once the HVIC detects an over-current event, the outputs are shutdown, a fault is reported through the FAULT pin, and RCIN is pulled to VSS. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2) connected to ITRIP as shown in Figure 14, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VIT,TH+) at that current level. VIT,TH+ = R0IDC-(R1/(R1+R2)) Figure 14: Programming the over-current protection For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. The shunt resistor or resistor network for GF or PCFtrip can be determined according to GF, PCFtrip threshold and level of protection current. The GF pin should not be outside this range (VDC+0.3V, VDC-5V) and PCFtrip should not be outside (Vcc+0.3V, Vss-5V); if necessary, an external voltage clamp may be used. Over-Temperature Shutdown Protection The ITRIP input of the IRS26302DJ can also be used to detect over-temperature events in the system and initiate a shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the resistor network as shown in Figure 15 and select the maximum allowable temperature. This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should www.irf.com © 2009 International Rectifier 23 IRS26302DJ be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V. When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g., DL4148) can be used. This network is shown in Figure 16; the OR-ing diodes have been labeled D1 and D2. Figure 15: Programming over-temperature protection Figure 16: Using over-current protection and overtemperature protection Truth Table: Undervoltage lockout, ITRIP, GF, PCFtrip and ENABLE Table 4 provides the truth table for the IRS26302DJ. The first line shows that the UVLO for VCC has been tripped; the FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. Same behavior if GF or PCFtrip threshold has been reached. In the last case, the HVIC has received a command through the EN input to shutdown; as a result, the gate drive outputs have been disabled. GF PFC trip EN RCIN FAULT LO HO PCFout --- --- --- --- High 0 0 0 0 VITRIP 0V 0V 5V Low 0 0 0 0 GF 15 V 15 V 0V < GFth 0V 5V Low 0 0 0 0 PCFtrip 15 V 15 V 0V 0V HZ (0) 0 0 HZ 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X 0 0 HZ 0 0 0 0 0 0 0 0 0 X X X V > Vth (**) V > Vth (**) 0 X X X 0 0 HZ 0 0 0 0 0 0 0 0 0 X X X X X X VCC < UVCC VCC < UVCC VCC > UVCC 0 0 HZ 0 0 0 0 0 0 0 0 0 RCIN Itrip 0 (*) (*) HZ HZ 0 0 0 V > Vth (**) V > Vth (**) 0 PFCinx/BRinx PFCinx/BRinx PFCinx/BRinx (*) (*) 0 0 0 X X X V > Vth (**) V > Vth (**) 0 Hinx ALL H ALL H PFCinx/BRinx PFCinx/BRinx PFCinx/BRinx (*) (*) 0 0 0 X X X Hinx ALL H ALL H PFCinx/BRinx PFCinx/BRinx PFCinx/BRinx (*) (*) HZ 0 0 X X X (0) PFCtrip GF 0 Fault register = 1 (**) X X X X X X (0) HAND SHAKE SYNC (*) Operation available only in DIAL MODE. (**) Internal Register fault DIAG MODE available when FLT=0 Set DIAG MODE: Hinx=Linx=H During DIAG MODE operation Lox=Hox=0 PFCout/BRout=0 RCIN=0 Reset DIAG MODE: hold Linx=H Hinx=L Figure 17: State Diagram www.irf.com © 2009 International Rectifier 25 IRS26302DJ HANDSHAKE mode Fault query start Set LIN1=L, LIN2,3=H;HINx=H Wait tDIAGIN FLT/EN = 0 YES ITRIP FAULT NO Set LIN2=L, LIN1,3=H;HINx=H Wait tDIAGIN FLT/EN = 0 YES PFCtrip FAULT NO Set LIN3=L, LIN1,2=H;HINx=H Wait tDIAGIN FLT/EN = 0 YES GF FAULT NO Set LIN3=L, LIN1,2=H;HINx=H Wait tDIAGIN FLT/EN = 0 YES Uvcc FAULT NO Exit fault query Figure 18: Fault Query Procedure www.irf.com © 2009 International Rectifier 26 IRS26302DJ Advanced Input Filter The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise spikes and short pulses. This input filter has been applied to the HIN, LIN, PFCin and EN inputs. The working principle of the new filter is shown in Figures 19 and 20. Figure 19 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN. Figure 20 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the same duration as the input signal. Figure 19: Typical input filter Figure 20: Advanced input filter Short-Pulse / Noise Rejection Example 2 Example 1 This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 21 shows the input and output in the low state with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2 of Figure 21 shows the input and output in the high state with negative noise spikes of durations less than tFIL,IN; the output does not change states. Figure 21: Noise rejecting input filters www.irf.com © 2009 International Rectifier 27 IRS26302DJ Figures 22 and 23 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses. The input filter characteristic is shown in Figure 22; the left side illustrates the narrow pulse ON (short positive pulse) characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 22 shows the duration of PW IN, while the y-axis shows the resulting PW OUT duration. It can be seen that for a PW IN duration less than tFIL,IN, that the resulting PW OUT duration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PW IN duration exceed tFIL,IN, that the PW OUT durations mimic the PW IN durations very well over this interval with the symmetry improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the high-side inputs be ≥ 500 ns. Time (ns) The difference between the PW OUT and PW IN signals of both the narrow ON and narrow OFF cases is shown in Figure 23; the careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PW IN, while the y-axis shows the resulting PW OUT–PW IN duration. This data illustrates the performance and near symmetry of this input filter. Figure 22: IRS2336xD input filter characteristic Figure 23: Difference between the input pulse and the output pulse www.irf.com © 2009 International Rectifier 28 IRS26302DJ Integrated Bootstrap Functionality The IRS26302DJ features integrated high-voltage bootstrap MOSFETs that eliminate the need of the external bootstrap diodes and resistors in many applications. There is one bootstrap MOSFET for each high-side output channel and it is connected between the VCC supply and its respective floating supply (i.e., VB1, VB2, VB3); see Figure 24 for an illustration of this internal connection. The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source current due to RBS. The VBS voltage will be charged each cycle depending on the on-time of LO and the value of the CBS capacitor, the drain-source (collector-emitter) drop of the external IGBT (or MOSFET), and the low-side freewheeling diode drop. The bootstrap MOSFET of each channel follows the state of the respective low-side output stage (i.e., the bootstrap MOSFET is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 110% of VCC. In that case, the bootstrap MOSFET is designed to remain off until VB returns below that threshold; this concept is illustrated in Figure 25. VB1 VCC VB2 VB3 Figure 24: Internal bootstrap MOSFET connection Figure 25: Bootstrap MOSFET state diagram A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with the external bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations. An example of this limitation may arise when this functionality is used in non-complementary PWM schemes (typically 6-step modulations) and at very high PWM duty cycle. In these cases, superior performances can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network. Bootstrap Power Supply Design For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality of the IRS26302DJ, please refer to Application Note 1123 (AN-1123) entitled “Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality.” This application note is available at www.irf.com. For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode) please refer to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is available at www.irf.com. www.irf.com © 2009 International Rectifier 29 IRS26302DJ Separate Logic and Power Grounds The IRS26302DJ has separate logic and power ground pin (VSS and COM respectively) to eliminate some of the noise problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for motor current measurements. In these situations, it is often beneficial to separate the logic and power grounds. Figure 26 shows a HVIC with separate VSS and COM pins and how these two grounds are used in the system. The VSS is used as the reference point for the logic and over-current circuitry; VX in the figure is the voltage between the ITRIP pin and the VSS pin. Alternatively, the COM pin is the reference point for the low-side gate drive circuitry. The output voltage used to drive the low-side gate is VLO-COM; the gate-emitter voltage (VGE) of the low-side switch is the output voltage of the driver minus the drop across RG,LO. DC+ BUS DBS VB (x3) VCC CBS HO (x3) HVIC ITRIP VSS RG,HO VS (x3) LO (x3) VS1 VS2 VS3 RG,LO + + + VGE1 VGE2 VGE3 COM - - - R2 R0 + VX R1 - DC- BUS Figure 26: Separate VSS and COM pins Tolerant to Negative VS Transients A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 27; here we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 28 and 29) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the lowside switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. www.irf.com © 2009 International Rectifier 30 IRS26302DJ Figure 27: Three phase inverter DC+ BUS Q1 ON IU VS1 Q2 OFF D2 DC- BUS Figure 28: Q1 conducting Figure 29: D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 30 and 31), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. Figure 30: D3 conducting Figure 31: Q4 conducting However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”. The circuit shown in Figure 32 depicts one leg of the three phase inverter; Figures 33 and 34 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, www.irf.com © 2009 International Rectifier 31 IRS26302DJ VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). Figure 32: Parasitic Elements Figure 33: VS positive Figure 34: VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. The IRS26302DJ has been seen to withstand large negative VS transient conditions on the order of -50 V for a period of 50 ns. An illustration of the IRS26302DJ’s performance can be seen in Figure 35. This experiment was conducted using various loads to create this condition; the curve shown in this figure illustrates the successful operation of the IRS26302DJ under these stressful conditions. In case of -VS transients greater then -20 V for a period of time greater than 100 ns; the HVIC is designed to hold the high-side outputs in the off state for 4.5 µs in order to ensure that the high- and low-side power switches are not on at the same time. Figure 35: Negative VS transient results for an International Rectifier HVIC Even though the IRS26302DJ has been shown able to handle these large negative VS transient conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use. www.irf.com © 2009 International Rectifier 32 IRS26302DJ PCB Layout Tips Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. The IRS26302DJ in the PLCC44 package has had some unused pins removed in order to maximize the distance between the high voltage and low voltage pins. Please see the Case Outline PLCC44 information in this datasheet for the details. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 36). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. Figure 36: Antenna Loops Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins. connection is shown in Figure 37. A ceramic 1 µF ceramic capacitor is suitable for most applications. component should be placed as close as possible to the pins in order to reduce parasitic elements. This This Figure 37: Supply capacitor www.irf.com © 2009 International Rectifier 33 IRS26302DJ Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 36), and in some cases using a clamping diode between VSS and VS (see Figure 39). See DT04-4 at www.irf.com for more detailed information. Figure 38: VS resistor Figure 39: VS clamping diode Integrated Bootstrap FET limitation The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to the HVIC: • • VCC pin voltage = 0V AND VS or VB pin voltage > 0 In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current conduction path is created between VCC & VB pins, as illustrated in Fig.40 below, resulting in power loss and possible damage to the HVIC. Figure 40: Current conduction path between VCC and VB pin www.irf.com © 2009 International Rectifier 34 IRS26302DJ Relevant Application Situations: The above mentioned bias condition may be encountered under the following situations: • In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In this condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes resulting unwanted current flow to VCC. • Potential situations in other applications where VS/VB node voltage potential increases before the VCC voltage is available (for example due to sequencing delays in SMPS supplying VCC bias) Application Workaround: Insertion of a standard p-n junction diode between VCC pin of IC and positive terminal of VCC capacitors (as illustrated in Fig.41) prevents current conduction “out-of” VCC pin of gate driver IC. It is important not to connect the VCC capacitor directly to pin of IC. Diode selection is based on 25V rating or above & current capability aligned to ICC consumption of IC - 100mA should cover most application situations. As an example, Part number # LL4154 from Diodes Inc (25V/150mA standard diode) can be used. VCC VCC Capacitor VB VSS (or COM) Figure 41: Diode insertion between VCC pin and VCC capacitor Note that the forward voltage drop on the diode (VF) must be taken into account when biasing the VCC pin of the IC to meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – VF of Diode. Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs www.irf.com © 2009 International Rectifier 35 IRS26302DJ Parameter Temperature Trends Figures 42-117 provide information on the experimental performance of the IRS26302DJ HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 0.35 0.30 8.4 0.25 Lin- (uA) llk (uA) 10.5 6.3 4.2 Exp. 0.20 0.15 0.10 2.1 Exp. 0.05 0.0 -50 -25 0 25 50 75 100 0.00 125 -50 o -25 0 Temperature ( C) 1500.00 0.05 1200.00 0.04 900.00 Exp . 600.00 100 125 Fig. 43. Input Bias Current vs. Temperature IRCIN (uA) Lin+ (uA) Fig. 42. Offset Supply Leakage Current vs. Temperature 25 50 75 o Temperature ( C) 0.03 0.02 Exp. 0.01 300.00 0.00 0.00 -50 -25 0 25 50 75 100 -0.01 -50 125 Temperature (oC) -25 0 25 50 75 100 125 o Temperature ( C) Fig. 44. Input Bias Current vs. Temperature Fig. 45. RCIN Input Bias Current vs. Temperature www.irf.com © 2009 International Rectifier 36 IRS26302DJ 0.70 30.60 0.60 Ipfctrip- (uA) Ipfctrip+ (uA) 25.50 20.40 Exp. 15.30 0.50 0.40 0.30 10.20 0.20 5.10 0.10 0.00 -50 Exp. 0.00 -25 0 25 50 75 100 -50 125 -25 0 50 75 100 125 o Temperature ( C) o Temperature ( C) Fig. 46. PFCTRIP Input Bias Current vs. Temperature Fig. 47. PFCTRIP Input Bias Current vs. Temperature 0.06 2.00 0.05 1.60 Iitrip+ (uA) 0.04 Exp. Iitrip- (uA) 25 0.03 0.02 1.20 Exp. 0.80 0.40 0.01 0.00 0.00 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 o Temperature ( C) o Temperature ( C) Fig. 48. ITRIP Input Bias Current vs. Temperature Fig. 49. ITRIP Input Bias Current vs. Temperature 100 5.00 80 IQBS (uA) IQCC (mA) 3.75 Exp. 2.50 1.25 60 Exp. 40 20 0 0.00 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 o o Temperature ( C) Temperature ( C) Fig. 50. Quiescent VCC Supply Current vs. Temperature Fig. 51. Quiescent VBS Supply Current vs. Temperature www.irf.com © 2009 International Rectifier 37 IRS26302DJ 1000 1000 800 LOtoff (ns) LOton (ns) 800 Exp. 600 400 Exp. 600 400 200 200 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 o Temperature ( C) o Temperature ( C) Fig. 53. Turn-Off Propagation Delay vs. Temperature Fig. 52. Turn-On Propagation Delay vs. Temperature 70 200 60 50 Exp. 100 Lotoff (ns) LOtr (ns) 150 50 40 Exp. 30 20 10 0 0 -50 -25 0 25 50 75 100 -50 125 -25 25 50 75 100 125 100 125 Temperature ( C) Temperature ( C) Fig. 54. Turn-On Rise Time vs. Temperature Fig. 55. Turn-Off Fall Time vs. Temperature 1000 1000 800 800 HOtoff (ns) Exp. HOton (ns) 0 o o 600 400 200 Exp. 600 400 200 0 -50 -25 0 25 50 75 100 0 125 -50 o Temperature ( C) -25 0 25 50 75 o Temperature ( C) Fig. 56. Turn-On Propagation Delay vs. Temperature Fig. 57. Turn-Off Propagation Delay vs. Temperature www.irf.com © 2009 International Rectifier 38 IRS26302DJ 200 60 50 HOtff (ns) 160 Hotr (ns) 120 Exp. 80 40 Exp. 30 20 40 10 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 1000 1000 800 800 600 Exp. 400 600 200 0 0 25 50 75 100 Exp. -50 125 -25 0 25 50 75 100 125 o Temperature ( C) o Temperature ( C) Fig. 61. Turn-Off Propagation Delay vs. Temperature Fig. 60. Turn-On Propagation Delay vs. Temperature 100 300 80 PFCtf (ns) 250 200 PFCtr (ns) 125 400 200 0 100 Fig. 59. Turn-Off Fall Time vs. Temperature PFCtoff (ns) PFCton (ns) Fig. 58. Turn-On Rise Time vs. Temperature -25 75 Temperature ( C) Temperature ( C) -50 50 o o Exp. 150 60 Exp. 40 100 20 50 0 -50 0 -50 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 o Temperature ( C) o Temperature ( C) Fig. 63. Turn-Off Fall Time vs. Temperature Fig. 62. Turn-On Rise Time vs. Temperature www.irf.com © 2009 International Rectifier 39 IRS26302DJ 600 50 40 MT (ns) DT (ns) 450 Exp. 300 30 Exp. 20 150 10 0 -50 -25 0 25 50 75 100 0 125 -50 o -25 0 Temperature ( C) 50 50 40 40 30 Exp. 125 30 Exp. 20 20 10 10 0 0 -50 -25 0 25 50 75 100 -50 125 -25 25 50 75 100 125 Temperature ( C) o Fig. 66. Deadtime Matching vs. Temperature Fig. 67. Pulse Width Distortion vs. Temperature 2000 500 1600 TitripFlt (ns) 600 400 0 o Temperature ( C) Tfilin (ns) 100 Fig. 65. Ton, Off Matching Time vs. Temperature PM (ns) MDT(ns) Fig. 64. Deadtime Rise Time vs. Temperature 25 50 75 o Temperature ( C) Exp. 300 Exp. 1200 800 200 400 100 0 -50 0 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 o Temperature ( C) o Temperature ( C) Fig. 68. Input Filter Time vs. Temperature Fig. 69. ITRIP to Fault Time vs. Temperature www.irf.com © 2009 International Rectifier 40 1500 1500 1250 1250 1000 1000 750 TitripPfc (ns) TitripOut (ns) IRS26302DJ Exp. 500 250 750 Exp. 500 250 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 o 75 100 125 Fig. 71. ITRIP to PFCOUT Shutdown Propagation Delay vs. Temperature 100 1000 800 80 Titripblk (ns) Exp. Tfltclr (us) 50 Temperature ( C) Fig. 70. ITRIP to Output Shutdown Propagation Delay vs. Temperature 60 40 600 Exp. 400 200 20 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 50 75 100 125 Temperature ( C) o Fig. 72. FAULT Clear Time RCIN vs. Temperature Fig. 73. ITRIP Blanking Time vs. Temperature 1000 1600 800 TpfctripOut (ns) 2000 1200 25 o Temperature ( C) TpfctripFlt (ns) 25 o Temperature ( C) Exp. 800 400 600 Exp. 400 200 0 0 -50 -25 0 25 50 75 100 125 -50 o -25 0 25 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 74. PFCTRIP to Fault Time vs. Temperature Fig. 75. PFCTRIP to Output Shutdown Propagation Delay vs. Temperature www.irf.com © 2009 International Rectifier 41 IRS26302DJ 100 80 800 Tfltclr (us) TpfctripPfc (ns) 1000 600 Exp. Exp. 60 40 400 20 200 0 -50 0 -50 -25 0 25 50 75 100 -25 0 25 50 75 100 125 o 125 Temperature ( C) o Temperature ( C) Fig. 77. FAULT Clear Time RCIN vs. Temperature 750 2500 600 2000 TgftripFlt (ns) Tpfctripblk (ns) Fig. 76. PFCTRIP to PFC Output Shutdown Propagation Delay vs. Temperature 450 300 Exp. 150 Exp. 1500 1000 500 0 -50 0 -25 0 25 50 75 100 125 -50 -25 0 o 50 75 100 125 100 125 o Temperature ( C) Temperature ( C) Fig. 78. PFCTRIP Blanking Time vs. Temperature Fig. 79. GFTRIP to Fault Time vs. Temperature 2500 2500 2000 2000 TgftripPfc (ns) TgftripOut (ns) 25 1500 Exp. 1000 500 1500 Exp. 1000 500 0 -50 -25 0 25 50 75 100 0 -50 125 o Temperature ( C) -25 0 25 50 75 o Temperature ( C) Fig. 80. GFTRIP to Output Shutdown Propagation Delay vs. Temperature Fig. 81. GFTRIP to PFC Output Shutdown Propagation Delay vs. www.irf.com © 2009 International Rectifier 42 IRS26302DJ 1000 1000 800 TenOut (ns) TgftripBlk (ns) 800 Exp. 600 400 600 Exp. 400 200 200 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 o Fig. 82. GFTRIP Blanking Time vs. Temperature 75 100 125 Fig. 83. EN On to Output Propagation Delay vs. Temperature 1000 500 800 400 TfilterEn (ns) TsdOut (ns) 50 o Temperature ( C) 600 Exp. 400 300 Exp. 200 100 200 0 -50 0 -50 -25 0 25 50 75 100 125 -25 0 o 25 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 84. EN Off to Output Shutdown Propagation Delay vs. Temperature Fig. 85. Enable Input Filter Time vs. Temperature 500 750 400 600 TsdPfc (ns) Exp. TenPfc (ns) 25 Temperature ( C) 300 200 100 0 -50 450 Exp. 300 150 -25 0 25 50 75 100 0 -50 125 o Temperature ( C) -25 0 25 50 75 100 125 o Temperature ( C) Fig. 86. EN On to PFC Output Propagation Delay vs. Temperature Fig. 87. EN off to Output Shutdown PFC Propagation Delay vs. Temperature www.irf.com © 2009 International Rectifier 43 1000 1000 800 800 600 TdiagIN (ns) Tnandshake (ns) IRS26302DJ Exp. 400 600 Exp. 400 200 200 0 -50 -25 0 25 50 75 100 125 0 -50 o Temperature ( C) -25 0 25 50 75 100 125 o Temperature ( C) Fig. 89. Input to DIAG Mode in Delay vs. Temperature 1000 1000 800 800 600 PfcIo+ (mA) TdiagOUT (ns) Fig. 88. Input to Hand Shake Mode Delay vs. Temperature Exp. 400 600 400 Exp. 200 200 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 o 25 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 91. Output High Short Circuit Pulsed Current PFCOUT vs. Temperature Fig. 90. Input to DIAG Mode Out Delay vs. Temperature 500 500 400 400 Io- (mA) Io+ (mA) Exp. 300 Exp. 200 100 0 -50 300 200 100 -25 0 25 50 75 100 0 -50 125 o Temperature ( C) -25 0 25 50 75 100 125 o Temperature ( C) Fig. 92. Output High Short Circuit Pulsed Current, HO1,2,3 vs. Temperature Fig. 93. Output Low Short Circuit Pulsed Current, HO1,2,3 vs. Temperature www.irf.com © 2009 International Rectifier 44 1000 100 800 80 600 Ron_RCIN (ohm) PfcIo- (mA) IRS26302DJ Exp. 400 60 Exp. 40 20 200 0 -50 0 -50 -25 0 25 50 75 100 125 -25 0 Temperature ( C) 50 75 100 125 Fig. 95. RCIN Low On Resistance vs. Temperature 100 2.50 80 2.00 Vin,th- (V) Ron_Flt (ohm) Fig. 94. Output Low Short Circuit Pulsed Current, PFCOUT vs. Temperature 60 Exp. 40 25 Temperature (oC) o 20 1.50 Exp. 1.00 0.50 0 0.00 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 25 50 75 100 125 Temperature (oC) Fig. 96. FLT Low On Resistance vs. Temperature Fig. 97. Input Negative Going Threshold vs. Temperature 0.50 3.00 2.50 0.40 Vitrip,th- (V) Vin,th+ (V) Exp. 2.00 1.50 0.30 0.20 Exp. 1.00 0.10 0.50 0.00 0.00 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 Temperature (oC) Temperature (oC) Fig. 99. Input Negative Going Threshold vs. Temperature Fig. 98. Input Positive Going Threshold vs. Temperature www.irf.com © 2009 International Rectifier 45 0.50 0.50 0.40 0.40 Vpfctrip,th- (V) Vitrip,th+ (V) IRS26302DJ 0.30 Exp. 0.20 0.10 0.30 Exp. 0.20 0.10 0.00 0.00 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 0.50 0.50 0.40 0.40 Vgf,th- (V) Vpfctrip,th+ (V) 75 100 125 Fig. 101. PFC Negative Going Threshold vs. Temperature 0.30 Exp. 0.30 Exp. 0.20 0.10 0.10 0.00 0.00 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 Temperature (oC) Temperature (oC) Fig. 103. GF Negative Going Threshold vs. Temperature Fig. 102. PFC Positive Going Threshold vs. Temperature 0.50 15.00 0.40 12.00 VRCin,th+ (V) Vgf,th+ (V) 50 Temperature (oC) Fig. 100. Input Positive Going Threshold vs. Temperature 0.20 25 0.30 0.20 Exp. Exp. 9.00 6.00 3.00 0.10 0.00 0.00 -50 -50 -25 0 25 50 75 Temperature (oC) 100 125 -25 0 25 50 75 100 125 Temperature (oC) Fig. 104. GF Positive Going Threshold vs. Temperature Fig. 105. RCIN Positive Going Threshold vs. Temperature www.irf.com © 2009 International Rectifier 46 20.00 20.00 16.00 16.00 12.00 Vcc,UVth+ (V) Vcc,UVth- (V) IRS26302DJ Exp. 8.00 12.00 Exp. 8.00 4.00 4.00 0.00 -50 -25 0 25 50 75 100 0.00 125 -50 Temperature (oC) -25 0 25 50 75 100 125 Temperature (oC) Fig. 106. VCC Supply Undervoltage Negative Going Threshold vs. Temperature Fig. 107. VCC Supply Undervoltage Positive Going Threshold vs. Temperature 0.50 0.40 Vbs,Uvhys (V) Vcc,Uvhys (V) 0.40 0.30 Exp. 0.20 0.30 Exp. 0.20 0.10 0.10 0.00 0.00 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 50 75 100 125 Temperature (oC) Fig. 109. VBS Supply Undervoltage Hysteresis vs. Temperature Fig. 108. VCC Supply Undervoltage Hysteresis vs. Temperature 25.00 25.00 20.00 20.00 Vbs,Uvth+ (V) Vbs,UVth- (V) 25 15.00 Exp. 10.00 5.00 15.00 Exp. 10.00 5.00 0.00 -50 -25 0 25 50 75 100 0.00 125 -50 Temperature (oC) -25 0 25 50 75 100 125 Temperature (oC) Fig. 111. VBS Supply Undervoltage Positive Going Threshold vs. Temperature Fig. 110. VBS Supply Undervoltage Negative Going Threshold vs. Temperature www.irf.com © 2009 International Rectifier 47 250.00 1000.00 200.00 800.00 VpfcH (mV) VpfcL (mV) IRS26302DJ 150.00 Exp. 100.00 600.00 400.00 Exp. 50.00 200.00 0.00 -50 -25 0 25 50 75 100 0.00 125 -50 Temperature (oC) 500.00 1750.00 400.00 1400.00 VOH (mV) VOL (mV) 0 25 50 75 Temperature (oC) 100 125 Fig. 113. High Level Output Voltage, VBIAS VO, PFCOUT vs. Temperature Fig. 112. Low Level Output Voltage, VBIAS VO, PFCOUT vs. Temperature 300.00 Exp. 200.00 -25 1050.00 700.00 Exp. 350.00 100.00 0.00 0.00 -50 -50 -25 0 25 50 75 100 -25 0 125 25 50 75 100 125 Temperature (oC) Temperature (oC) Fig. 115. High Level Output Voltage, VBIAS VO, HO1,2,3 vs. Temperature Fig. 114. Low Level Output Voltage, VO, HO1,2,3 vs. Temperature 0.05 700.00 0.04 IENin (uA) RBS (ohm) 525.00 350.00 0.03 0.02 Exp. 175.00 Exp. 0.01 0.00 -50 -25 0 25 50 75 100 0.00 -50 125 Temperature (oC) -25 0 25 50 75 100 125 o Temperature ( C) Fig. 116. Ron Internal Bootstrap Diode vs. Temperature Fig. 117. En Input Bias Current vs. Temperature www.irf.com © 2009 International Rectifier 48 IRS26302DJ Package Details: PLCC44 www.irf.com © 2009 International Rectifier 49 IRS26302DJ Tape and Reel Details: PLCC44 LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR 44PLCC Metric Imperial Code Min Max Min Max A 23.90 24.10 0.94 0.948 B 3.90 4.10 0.153 0.161 C 31.70 32.30 1.248 1.271 D 14.10 14.30 0.555 0.562 E 17.90 18.10 0.704 0.712 F 17.90 18.10 0.704 0.712 G 2.00 n/a 0.078 n/a H 1.50 1.60 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 44PLCC Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 38.4 G 34.7 35.8 H 32.6 33.1 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 1.511 1.366 1.409 1.283 1.303 © 2009 International Rectifier 50 IRS26302DJ Part Marking Information www.irf.com © 2009 International Rectifier 51 IRS26302DJ Ordering Information Standard Pack Base Part Number IRS26302DJ Package Type PLCC44 Complete Part Number Form Quantity Tube/Bulk 27 IRS26302DJPBF Tape and Reel 500 IRS26302DJTRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com © 2009 International Rectifier 52 IRS26302DJ Revision History Date MM/DD/YY Rev3.1 Rev3.3 Comment Original document Started from rev3.0 of repository: header and footer updated, standard package PLCC44 specified, duplicate definition in dynamic electrical characteristic deleted Add application part related to bootstrap fet limitation www.irf.com © 2009 International Rectifier 53