IRS2890DSPBF

IRS2890DS Half-Bridge Driver with Overcurrent Protection Features                 Product Summary Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V, 5 V, and 15 V input logic compatible Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity Outputs in phase with inputs Integrated bootstrap functionality Suitable for both trapezoidal and sinusoidal motor control Overcurrent protection and fault reporting Advanced input filter Integrated deadtime protection Shoot-through (cross-conduction) protection Adjustable fault clear timing Description VOFFSET ≤ 600 V VOUT 10 V – 20 V IO+ & IO- (typ.) 220 mA & 480 mA tON & tOFF (typ.) 500 ns & 500 ns Deadtime (typ.) 300 ns Package Options The IRS2890D is a high voltage, high speed power MOSFET and IGBT half bridge gate driver. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or TTL outputs, down to 3.3 V logic. The output drivers feature a high-pulse current buffer stage designed for minimum driver crossconduction.The floating channel can be used to drive Nchannel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V. Propagation delays are matched to simplify the HVIC’s use in high frequency applications. 14-Lead SOIC Typical Applications     Base Part Number Package Type IRS2890DSPBF 14-Lead SOIC N 1 Rev 1.0 Motor Control Air Conditioners/Washing Machines Micro/Mini inverter drives General Purpose Inverters Standard Pack Form Tube/Bulk Quantity 55 Tape and Reel 2500 www.infineon.com/gdhalfbridge Orderable Part Number IRS2890DSPBF IRS2890DSTRPBF 2017-03-02 IRS2890DS Typical Connection Diagram DC BUS + Vcc VB Hin HO Lin IRS2890 RFE COM VS LO ITRIP DC BUS (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to Application Notes & Design Tips for proper circuit board layout. 2 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VCC VIN VB VS VHO VLO COM dVS/dt PD RthJA TJ TS TL Definition Low side supply voltage Logic input voltage (LIN, HIN, RFE, ITRIP) High-side floating well supply voltage High-side floating well supply return voltage Floating gate drive output voltage Low-side output voltage Power ground Allowable VS offset supply transient relative to COM Package power dissipation @ T A +25ºC Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. -0.3 COM - 0.3 -0.3 VB - 25 VS - 0.3 COM - 0.3 VCC - 25 — — — — -55 — Max. † 25 VCC + 0.3 625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 50 1 120 150 150 300 Units V V/ns W ºC/W ºC † All supplies are tested at 25V . Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with supplies of (VCC - COM) = (VB - VS) = 15 V. Symbol VCC VIN VB VS VSt VHO VLO TA Definition Low-side supply voltage Logic input voltage High-side floating well supply voltage † High-side floating well supply offset voltage Transient High-side floating well supply offset voltage Floating gate drive output voltage Low-side output voltage Ambient temperature Min 10 0 VS + 10 † COM - 8 †† Max 20 VCC VS + 20 600 - 50 600 VS COM -40 VB VCC 125 Units V ºC † Logic operation for VS of –8 V to 200 V. Logic state held for VS of –8 V to –VBS. Please refer to Design Tip DT97-3 for more details. †† Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. 3 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS Static Electrical Characteristics (VCC - COM) = (VB - VS) = 15 V. TA = 25 °C unless otherwise specified. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to VS. Symbol VBSUV+ VBSUVVBSUVHY VCCUV+ VCCUVVCCUVHY VOH VOL VIH VIL VRFE+ VRFEVITRIP+ VITRIPVITRIP HYS ILK IQBS IQCC Definition VBS supply under voltage positive threshold VBS supply under voltage negative threshold VBS supply under voltage hysteresis VCC supply under voltage positive threshold VCC supply under voltage negative threshold VCC supply under voltage hysteresis High level output voltage drop, VBIAS-VO Low level output voltage drop, VO Logic “1” input voltage Logic “0” input voltage RFE positive going threshold RFE negative going threshold ITRIP positive going threshold ITRIP negative going threshold ITRIP hysteresis High-side floating well offset supply leakage Quiescent VBS supply current Quiescent VCC supply current Min. 8.0 6.9 — 8.0 6.9 — — — 2.2 — — 0.8 0.475 — — — — — Typ. 8.9 7.7 1.2 8.9 7.7 1.2 0.65 0.13 — — 1.9 1.1 0.500 0.43 0.07 — 45 — Max. Units 9.8 8.5 — 9.8 8.5 — — V — — 0.8 2.2 — 0.525 — — 50 70 µA 3000 Test Conditions IO = 20 mA VB = VS = 600 V VIN = 0 V or 4 V VO = 0 V PW ≤ 10 µs VO = 15 V PW ≤ 10 µs IO+ Output high short circuit pulsed current — 220 — IO- Output low short circuit pulsed current — 480 — IRFE+ Logic “1” Input bias current (RFE) — 0 1 IRFE- Logic “0” Input bias current (RFE) 1 0 — IIN+ Logic “1” Input bias current (LIN, HIN) — 5 10 IIN- Logic “0” Input bias current (LIN, HIN) — — 1 IITRIP+ Logic “1” Input bias current (ITRIP) — 5 10 VIN = 4 V IITRIP- Logic “0” Input bias current (ITRIP) — — 1 VIN = 0 V RBS Bootstrap resistance — 200 — Ω RON, RFE RFE mos resistance — 40 100 Ω mA µA VIN = 4 V VIN = 0 V Io = 1.5mA Please refer to Application Section for integrated bootstrap description. 4 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS Dynamic Electrical Characteristics o VCC = VB = 15 V, VS = COM, TA = 25 C, and CL = 1000 pF unless otherwise specified. Symbol tON tOFF tR tF DT MT tEN TFIL,EN TFLTCLR TITRIP TBL TFLT 5 Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Dead time, LO turn-off to HO turn-on & HO turn-off to LO turn-on Delay matching time (tON, tOFF) Enable low to output shutdown propagation delay Enable input filter time FAULT clear time (R = 2 MΩ, C = 1 nF) ITRIP to output shutdown propagation delay ITRIP blanking time ITRIP to FAULT propagation delay Rev 1.0 www.infineon.com/gdhalfbridge Min. 350 350 — — Typ. 500 500 85 30 Max. 650 650 — — Units Test Conditions 200 300 430 ns VS = 0 V — — 50 270 400 530 100 200 300 1.35 1.75 2.1 ms VDD = 3.3 V 500 300 450 720 500 680 950 700 900 ns VS =0 V or 600 V 2017-03-02 IRS2890DS Functional Block Diagram VB S Input Noise filter HIN Input Noise filter LIN Deadtime & Shoot-Through Prevention VSS/COM Level Shifter Latch & UV Detect HV Level Shifter Driver R VS Integrated BootFet COM UV Detect ITRIP HO ITRIP Noise filter VCC VSS/COM Level Shifter Delay Driver LO COM Noise filter RFE 6 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS Lead Definitions Pin Symbol 1 2 3 VCC HIN LIN 4 ITRIP 5 6 NC COM 7 RFE 8 9 10 11 12 13 14 NC LO NC NC VS HO VB Description Low side and logic fixed supply Logic input for high side gate driver output (HO), in phase Logic input for low side gate driver output (LO), in phase Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates RFE low. When ITRIP becomes inactive, RFE stays active low for an externally set time tFLTCLR, then automatically becomes inactive (open-drain high impedance). No connection Low side return Integrated fault reporting function like over-current (ITRIP), or low-side undervoltage lockout and the fault clear timer. This pin has negative logic and an open-drain output. The use of over-current protection requires the use of external components. No connection Low side gate drive output No connection No connection High side floating supply return High side gate drive output High side floating supply Lead Assignments VCC 1 14 VB HIN 2 13 HO LIN 3 12 VS ITRIP 4 11 NC NC 5 10 NC COM 6 9 LO RFE 7 8 NC 14-Lead SOIC N 7 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS Application Information and Additional Details Information regarding the following topics are included as subsections within this section of the datasheet.                   IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Enable Input Fault Reporting and Programmable Fault Clear Timer Over-Current Protection Truth Table: Undervoltage lockout, ITRIP, and ENABLE Daisy Chain Multiple Devices Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Negative VS Transient SOA PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS2890D HVICs are designed to drive MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) HO (or LO) + IO- VHO (or VLO) VS (or COM) - VS (or COM) Figure 1: HVIC sourcing current Figure 2: HVIC sinking current Switching and Timing Relationships The relationships between the input and output signals of the IRS2890D are illustrated below in Figures 3. From these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this device. 8 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS PWIN 50% 50% LIN, HIN ton toff tr 90% LO, HO tf PWOUT 10% 90% 10% Figure 3: Switching time waveforms The following two figures illustrate the timing relationships of some of the functionality of the IRS2890D; this functionality is described in further detail later in this document. During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output are held in the off state. Interval B of Figures 4 and 5 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state; LO is also held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has returned to the low state, the output will remain disabled and the fault condition reported until the voltage on the RFE pin charges up to VRFE+ threshold (see interval C in Figure 4); the charging characteristics are dictated by the RC network attached to the RFE pin. During interval E of Figure 4 and 6, we can see that the RFE pin has been pulled low (as is the case when the driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and LO) being held in the low state until the RFE pin is pulled high. A B C D E HIN LIN ITRIP RFE HO LO Figure 4: Input/output timing diagram 9 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS VIT,TH+ VIT,TH- ITRIP RFE VRFE+ 50% tFLT tFLTCLR tTRIP HO, LO 90% Figure 5: Detailed view of B interval RFE VRFEtEN 90% LO, HO Figure 6: Detailed view of E interval Deadtime This HVIC features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Matched Propagation Delays The IRS2890D HVIC is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., t ON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON) of the IRS2890D is matched to the propagation turn-on delay (tOFF). 10 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS 50 % HIN LIN LO 50% HO 10% MT MT 90% LO HO Figure 7: Delay Matching Waveform Definition Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2890D has been designed to be compatible with 3.3 V and 5 V logic-level signals. Figure 8 illustrates an input signal to the IRS2890D, its input threshold values, and the logic state of the IC as a result of the input signal. Figure 8: HIN & LIN input thresholds Undervoltage Lockout Protection This HVIC provides undervoltage lockout protection on both the V CC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 9 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this 11 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS could result in very high conduction losses within the power device and could lead to power device failure. VCC (or VBS) VCCUV+ (or VBSUV+) VCCUV(or VBSUV-) Time UVLO Protection (Gate Drive Outputs Disabled) Normal Operation Normal Operation Figure 9: UVLO protection Shoot-Through Protection The IRS2890D is equipped with shoot-through protection circuitry (also known as cross-conduction prevention circuitry). Figure 10 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Shoot-through protection enabled HIN LIN HO LO Figure 10: Illustration of shoot-through protection circuitry IRS2890D HIN LIN HO LO 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 Table 1: Input/output truth table for IRS2890D 12 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS Enable Input The IRS2890D provides an enable functionality that allows it to shutdown or enable the HVIC. When the RFE pin is in the high state the HVIC is able to operate normally (assuming no other under voltage fault conditions on Vcc). When the RFE pin is in a low state, the gate drive outputs are pulled low until the enable condition is restored. The enable circuitry of the IRS2890D features an input filter; the minimum input duration is specified by t FIL,EN. Please refer to the RFE pin parameters VRFE+, VRFE-, and IRFE for the details of its use. Table 2 gives a summary of this pin’s functionality. Enable Input * Enable input high Outputs enabled Enable input low Outputs disabled Table 2: Enable functionality truth table (*assumes no undervoltage fault on Vcc) Fault Reporting and Programmable Fault Clear Timer The IRS2890D provides an integrated fault reporting output and an adjustable fault clear timer. There are two situations that would cause the HVIC to report a fault via the RFE pin. The first is an undervoltage condition of V CC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the RFE pin is internally pulled to COM and the fault clear timer is activated. The RFE output stays in the low state until the fault condition has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the RFE pin will return to its external pull-up voltage. The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the capacitor where the time constant is set by RRFE and CRFE. Figure 11 shows that RRFE is connected between the external supply (VDD) and the RFE pin, while CRFE is placed between the RFE and COM pins. uC VCC HIN LIN HIN U LIN U HIN V LIN V HIN W LIN W VDD HO GK RRFE VS RFE LO CRFE COM ITRIP DC - BUS R Figure 11 Programming the fault clear timer The design guidelines for this network are shown in Table 3. 13 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS ≤1 nF CRFE Ceramic 0.5 MΩ to 2 MΩ RRFE >> RON,RCIN Table 3: Design guidelines The length of the fault clear time period can be determined by using the formula below. -t/RC vC(t) = Vf*(1-e ) tFLTCLR = -(RRFE*CRFE)*ln(1-VRFE+/VDD ) + 100ns The voltage on the RFE pin should not exceed the VDD of the uC power supply. Over-Current Protection The IRS2890D HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, and RFE is pulled to COM. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R 0, R1, and R2) connected to ITRIP as shown in Figure 12, and the ITRIP threshold (V ITRIP+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VITRIP+) at that current level. VITRIP+ = R0*IDC-(R1/(R1+R2)) DC BUS + Vcc Hin Lin RFE ITRIP VB HO VS To load LO COM R2 R1 DC BUS - Vx R0 IDC- Figure 12 Programming the over-current protection For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. Truth Table: Undervoltage lockout, ITRIP, and ENABLE Table 4 provides the truth table for the IRS2890D. The first line shows that the UVLO for VCC has been tripped; the RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns the driver is functional. 14 Rev 1.0 www.infineon.com/gdhalfbridge 2017-03-02 IRS2890DS The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled. This condition is stored in the external RC network waiting for fault clear time. The last case shows when the HVIC has received an enable command through the RFE input to shutdown; as a result, the gate drive outputs have been disabled. VCC VBS ITRIP RFE LO HO UVLO VCC