ISOFACE™
ISO2H823V2.5
Galvanic Isolated 8 Channel High-Side Switch
Datasheet
Revision 2.0, 2015-02-12
Power Management & Multimarket
Edition 2015-02-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ISOFACE™
ISO2H823V2.5
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 2.0, 2015-02-12
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Datasheet
3
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
............................................................................... 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
2.1
2.1.1
2.1.2
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pins of Power Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pins of Serial and Parallel Logic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
4.1
4.2
4.2.1
4.2.1.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.2.4
4.2.5
4.2.5.1
4.2.5.2
4.2.6
4.2.7
4.2.8
4.2.9
4.2.9.1
4.2.9.2
4.2.10
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.3.3.5
4.3.4
4.3.4.1
4.3.4.2
4.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Redundancy Check CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Error Indication Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Update of the Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNC-Signal for Drive-Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNC-Signal for Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODIS Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LEDGOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OLOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET (Hard and Soft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resynchronization of CT-Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Transistor Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Transistor Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense and Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics in Inactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics in Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Scenarios in Dependence of Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Matrix on the Process Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Matrix on the uController Side (only in Serial Communication Mode) . . . . . . . . . . . . . . . . .
EMI-Robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Datasheet
4
10
14
14
14
19
19
19
19
21
22
23
25
26
27
28
29
29
29
32
32
32
32
32
32
33
35
35
35
35
35
35
36
37
38
39
41
41
43
43
44
46
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
4.4.1
4.4.2
4.5
4.5.1
Burst Robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RFCM-Robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
47
48
48
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions and Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Switching Capabilities and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics µController Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isolation and Safety-Related Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
49
51
53
53
54
58
59
59
60
6
6.1
µController Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
User Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7
Package : Outlines and Marking Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Datasheet
5
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Datasheet
Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power PG-VQFN-70-2 (430 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application with Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bus Configuration for Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing by Parallel Read Access (e.g. GLERR Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Timing by Parallel Write Access (e.g. DRIVE Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Parallel Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Example SPI Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Mode 0, MS0 = 0, MS1 = 0, Daisy Chain Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Mode 1, MS0 = 1, MS1 = 0, Daisy Chain Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Mode 2, MS0 = 0, MS1 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Mode 3, MS0 = 1, MS1 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Connecting Two Devices for Daisy Chain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical Timing Diagram of Daisy Chain Operation (Serial Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . 25
SYNC Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timing of Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Examples of Application of Resynchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Diagnostics Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Start Up Procedure of the Power Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LED Matrix connected to the Power Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LED Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
LED Matrix connected to the uC-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Burst-Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RFCM-Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Typ. On-State Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typ. On-State Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical Initial Peak Short Circuit Current Limit vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated . . . . . 61
Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated . . . . . 62
Maximum Allowable Inductive Switch Off Energy, Single Pulse for Each Channel . . . . . . . . . . . . 62
Typ. Transient Thermal Impedance 1s0p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typ. Transient Thermal Impedance 2s2p no vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typ. Transient Thermal Impedance 2s2p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Sticky Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PG-VQFN-70-2 (Plastic (Green) Very Thin Profile Quad Flat Non Leaded Package) . . . . . . . . . . 80
Marking Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6
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ISOFACE™
ISO2H823V2.5
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Datasheet
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for LED-Application on the uC-Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits composing the ERR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Mode (GLCFG : FRZSC = 0), Disturbance (to Channel 0) Scenario . . . . . . . . . . . . .
Isochronous Mode (GLCFG : FRZSC = 1 (RESYN = 0)), Channel 0 Disturbed, Scenarios . . . . .
Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter Time in Inactive Mode for OLIx and SCVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter Time in Active Mode for OLAx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Occurence of Diagnostics during the Disturbance : Short-Circuit-to-VBB . . . . . . . . . . . . . . . . . . .
Occurence of Diagnostics during the Disturbance : Wirebreak . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics of the Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Switching Capabilities and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting at the Configuration Pin (CLKADJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Pins (ERR, CRCERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logical Pins (RD, WR, ALE, MS0/1, CS, AD7: AD0, SCLK, SDO, SDI, SEL, SYNC, ODIS) . . .
SYNC-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESYNCH-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODIS, ALE/RST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Specific Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isolation and Safety-Related Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Access Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics Registers for Channel 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
11
13
27
30
31
36
37
38
39
40
49
51
51
52
53
53
54
54
54
55
55
55
56
57
57
58
59
65
65
75
Revision 2.0, 2015-02-12
Galvanic Isolated 8 Channel High-Side Switch
1
ISO2H823V2.5
Overview
Infineon Technologies 2nd generation ISOFACE™ 8-channel high-side
driver IC ISO2H823V2.5 offers integrated 2.5kV galvanic isolation, thus
meets the IEC 61131-2 requirements for reinforced isolation.
Concurrently, the ISO2H823V2.5 sets a new standard for system-level
diagnostics. Each of the 8 channels is equipped with 5-fold diagnostic
monitoring capabilities: Open Load (Active Mode - Driver On and Inactive
Mode - Driver Off) , Short-to-Vbb, Overcurrent (= Short-to-GND),
Overtemperature.
With the ever increasing level of complexity and integration in industrial
control systems comprehensive diagnostic monitoring is highly valuable
in a vast range of industrial applications, both for preventive maintenance
as well as to shorten costly un-scheduled down-times
PG-VQFN-70-2
Product Highlights
•
•
•
•
•
2.5 kV Galvanic isolation integrated (UL508 & CSA22.2 certified)
Meets IEC 61131-2 requirements for reinforced isolation
8 - channel high-side switches of 0.6 A each
5 different types of diagnostic feedback for each channel
µController compatible 8-bit parallel/serial interface
12 mm x 12 mm PG-VQFN-70-2 package
Key Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Interface 3.3V CMOS operation compatible
Parallel/Serial µC interface
High common mode transient immunity
Integrated Diagnostics:
– 5 different types for diagnostic feedback per output channel
– 5 types of diagnostic feedback on global level
Common output disable pin
Common error indication pin
Resynchronization to achieve a low-jitter switching on and off of high-side switches
Active output current limitation for short circuit protection
Reverse Output Voltage protection
Undervoltage shutdown with autorestart and hysteresis
Integrated clamping to switch inductive loads up to 150 mJ energy per channel
Thermal shutdown and diagnostics per channel with auto-restart
VBB range from 11 V to 35 V designed for 24 V systems
Type
Package
ISO2H823V2.5
PG-VQFN-70-2
Datasheet
8
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Overview
•
•
ESD protection
RoHS compliant
Typical Application
•
•
•
•
Isolated switch for industrial applications:
PLC, distributed control systems, industial PCs, robotics, etc.
All types of resistive, inductive and capacitive loads
µController compatible power switch for 24 V DC applications
Driver for solenoid, relays and resistive loads
Description
The ISO2H823V2.5 is a galvanically isolated 8-bit data interface in PG-VQFN-70-2 package that provides 8 fully
protected high-side power switches that are able to handle currents up to 730 mA per channel.
An 8-bit parallel µController compatible interface or a serial SPI-interface allows to connect the IC directly to a
µController system. The input interface supports also a direct control mode for writing driver information and is
designed to operate with 3.3 V CMOS compatible levels.
The data transfer from input to output side is realized by the integrated Coreless Transformer Technology.
This product is the second generation of isolated 8 channel digital output device (ISO2H823V2.5) and provides a
robust integrated diagnosis for switches with low RDSon as well as an upgraded µController interface.
uC_chip
power chip
VCC
/ODIS
µC
SYNC
/CS
e.g.
XMCxxxx
parallel
or serial
interface
I
n
t
e
r
f
a
c
e
Logic
Configuration
Register
VBB
OLADJ
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Drive
Register
C T T ransfer
/ERR
VBB
IADJ
C T T ransfer
only
in
serial
mode,
shared
pins
Control
Protection
Diagnostic Unit
LEDx0
LEDx1
LEDx2
LEDy0
LEDy1
LEDy2
Diagnostic
Registers
CLKADJ
GND
ISO2H823V2
Figure 1
VDDIO
VCORE
GNDBB
Typical Application
Infineon Ordering Code :
SP001225470
Datasheet
9
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
28
27
n.c
29
OUT0
30
VBB
31
OUT0
32
GNDBB
VCORE
33
OLADJ
GNDBB
34
VDDI O
GND
35
IADJ
GND
Pin Configuration and Functionality
GND
2
26
25
24
23
SEL
36
22
GNDBB
VCC
37
21
VBB
CLKADJ
38
20
VBB
GND
39
19
OUT1
/ODIS
40
18
OUT1
SYNC
41
17
VBB
/WR
42
16
OUT2
ALE / RST
43
15
OUT2
/RD / MS0
44
14
OUT3
MS1
45
13
OUT3
GND
46
12
VBB
GND
47
11
VBB
/ CS
48
10
OUT4
AD0 / SDI
49
9
OUT4
AD1
50
8
OUT5
AD2
51
7
OUT5
AD3
52
6
VBB
AD4 / /CRCERR
53
5
OUT6
AD 5 / SCLK
54
4
OUT6
AD6
55
3
VBB
AD7 / SDO
56
2
VBB
1
GNDBB
/ ERR
exposed pad to GND
creepage
distance
n.c. = Not Connected
57
58
59
60
61
62
63
64
65
66
67
68
69
70
GND
GND
GND
GNDBB
LEDX0
LEDX1
LEDX2
LEDY0
LEDY1
LEDY2
OUT7
OUT7
n.c.
02/09/2015
Figure 2
Datasheet
exposed pad to GNDBB
PG-VQFN-70-2 - pinout_IFX. vsd
Power PG-VQFN-70-2 (430 mil)
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Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
Table 1
Pin
Pin Configuration
Parallel Interface Mode
Symbol
Serial Interface Mode
Ctrl Type Function
1)
Symbol
Ctrl
Type Function
2)
top side pins
1
GNDBB
A
Output Stage Ground
GNDBB
2
VBB
A
Output Stage Positive
Supply
VBB
3
VBB
A
Output Stage Positive
Supply
VBB
4
OUT6
A
Switch Output 6
OUT6
5
OUT6
A
Switch Output 6
OUT6
6
VBB
A
Output Stage Positive
Supply
VBB
7
OUT5
A
Switch Output 5
OUT5
8
OUT5
A
Switch Output 5
OUT5
9
OUT4
A
Switch Output 4
OUT4
10
OUT4
A
Switch Output 4
OUT4
11
VBB
A
Output Stage Positive
Supply
VBB
12
VBB
A
Output Stage Positive
Supply
VBB
13
OUT3
A
Switch Output 3
OUT3
14
OUT3
A
Switch Output 3
OUT3
15
OUT2
A
Switch Output 2
OUT2
16
OUT2
A
Switch Output 2
OUT2
17
VBB
A
Output Stage Positive
Supply
VBB
18
OUT1
A
Switch Output 1
OUT1
19
OUT1
A
Switch Output 1
OUT1
20
VBB
A
Output Stage Positive
Supply
VBB
21
VBB
A
Output Stage Positive
Supply
VBB
22
GNDBB
A
Output Stage Ground
GNDBB
23
n.c.
24
OUT0
A
Switch Output 0
OUT0
25
OUT0
A
Switch Output 0
OUT0
26
VBB
A
VBB
Output Stage Positive
Supply, Supply of Reference
Voltages
27
GNDBB
A
Output Stage Ground
Datasheet
not connected
n.c.
not connected
GNDBB
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ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
Table 1
Pin
Pin Configuration (cont’d)
Parallel Interface Mode
Symbol
Serial Interface Mode
Ctrl Type Function
1)
Symbol
Ctrl
Type Function
2)
28
OLADJ
A
Open Load Adjust
OLADJ
29
IADJ
A
Current Reference Adjust
IADJ
30
VDDIO
A
CT Blocking Capacitor
VDDIO
31
VCORE
A
Digital Core Supply
VCORE
32
GNDBB
A
Output Stage Ground
GNDBB
gap used for creepage distance
33
GND
A
Logic Ground
GND
34
GND
A
Logic Ground
GND
35
GND
A
Logic Ground
GND
36
SEL
PD
Serial / Parallel Mode Select SEL
37
VCC
A
Positive 3.3 V logic supply
38
CLKADJ
A
Clock Frequency Adjustment CLKADJ
39
GND
A
Logic Ground
GND
40
ODIS
I
PD
Output Disable
ODIS
41
SYNC
I
PU
Synchronize and Freeze
Diagnostics
SYNC
42
WR
I
PU
Data Write Input
n.c.
high impedance “Z”
43
ALE/RST I
PD
Address Latch Enable /
Reset
RST
I
PD
Reset
44
RD
PU
Data Read Input
MS0
I
PD
SPI Mode Select bit 0
45
n.c.
not connected
MS1
I
PD
SPI Mode Select bit 1
46
GND
A
Logic Ground
GND
47
GND
A
Logic Ground
GND
48
CS
I
PU
Chip Select
CS
49
AD0
IO
PPZ
Addr-Data in/output bit0
SDI
I
PD
SPI Data input
50
AD1
IO
PPZ
Addr-Data in/output bit1
n.c.
high impedance “Z”
51
AD2
IO
PPZ
Addr-Data in/output bit2
n.c.
high impedance “Z”
52
AD3
IO
PPZ
Addr-Data in/output bit3
n.c.
high impedance “Z”
53
AD4
IO
PPZ
Addr-Data in/output bit4
CRCERR
OD
PU
CRC Error output
54
AD5
IO
PPZ
Addr-Data in/output bit5
SCLK
I
PD
SPI Shift Clock input
55
AD6
IO
PPZ
Addr-Data in/output bit6
n.c.
56
AD7
IO
PPZ
Addr-Data in/output bit7
SDO
57
ERR
OD PU
Fault indication
ERR
58
GND
A
Logic Ground
GND
59
GND
A
Logic Ground
GND
60
GND
A
Logic Ground
GND
I
I
VCC
high impedance “Z”
O
PPZ
SPI Data Output
gap used for creepage distance
Datasheet
12
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
Table 1
Pin
Pin Configuration (cont’d)
Parallel Interface Mode
Symbol
Serial Interface Mode
Ctrl Type Function
1)
Symbol
Ctrl
Type Function
2)
61
GNDBB
A
Output Stage Ground
GNDBB
62
LEDX0
A
LED Output Row 0
LEDX0
63
LEDX1
A
LED Output Row 1
LEDX1
64
LEDX2
A
LED Output Row 2
LEDX2
65
LEDY0
A
LED Output Column 0
LEDY0
66
LEDY1
A
LED Output Column 1
LEDY1
67
LEDY2
A
LED Output Column 2
LEDY2
68
OUT7
A
Switch Output 7
OUT7
69
OUT7
A
Switch Output 7
OUT7
70
n.c.
not connected
n.c.
not connected
1) Direction of the digital pins : I = input, O = output, IO = Input/Output
2) Type of the pin: A = analog, OD = Open-Drain, PU = internal Pull-Up resistor, PD = internal Pull-Down resistor,
PPZ = Push-Pull pin with High-Impedance functionality
In case of serial mode six pins can be used to drive a LED-matrix on the uC-side (Table 2). For this purpose the
bit LEDON in register GLCFG has to be set to “1”.
Table 2
Pin
Pin Configuration for LED-Application on the uC-Side
Serial Interface Mode
Symbol
Ctrl Type Function
top side pins
55
AD6
OD
LEDR0
52
AD3
OD
LEDR1
51
AD2
OD
LEDR2
42
WR
OD
LEDC0
43
ALE/RST
OD
LEDC1
50
AD1
OD
LEDC2
Datasheet
13
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
2.1
Pin Functionality
This section describes the pins of the µController Interface as well as the Process Interface.
2.1.1
Pins of Power Interface
VBB (Positive supply 11-35 V output stage)
VBB supplies the output stage. An external circuitry for reverse polarity protection is required (see Electrical
Characteristics).
A ceramic capacitor of minimum 2.2 µF must be connected between VBB and GNDBB.
GNDBB (Ground for VBB domain)
This pin acts as the ground reference for the output stage that is supplied by VBB.
OUT0... OUT7 (Output channel 0 ... 7)
Due to EMI-requirements (Radio-Frequency-Common-Mode and burst-application) a capacitor
min.10 nF (+10%, recommended value 12 nF + 10%) for each output pin has to be connected to GNDBB.
of
LEDX0... LEDX2 (LED Row output channel 0 ... 2)
Low side switches
LEDY0... LEDY2 (LED Column output channel 0 ... 2)
High side drivers
IADJ (Current Adjust)
Reference current input, must be connected to GNDBB through a reference resistor of typ. 6.81 KΩ (E96 series).
The DC-level VIADJ is 1.215 V.
OLADJ (Open Load Adjust)
The current for the Open load detection can be adjusted by connecting a resistor between this pin and GNDBB
(from the E96 series : 25 kΩ - 2.3 kΩ).The DC-level VOLADJ is 1.215 V.
VDDIO (3.3 V Supply Blocking Capacitor)
A 1 µF ceramic capacitor must be connected between VDDIO and GNDBB.
VCORE (Blocking Capacitor for 1.5 V Digital Core)
A 470 nF ceramic capacitor must be connected between VCORE and GNDBB.
2.1.2
Pins of Serial and Parallel Logic Interface
Some pins are common for both interface types, some others are specific for the parallel or serial access.
VCC (Positive 3.3 V logic supply)
VCC supplies the output interface that is electrically isolated from the output power stage. The interface can be
supplied with 3.3 V. A ceramic capacitor of minimum 2.2 µF must be connected between VCC and GND.
GND (Ground for VCC domain)
This pin acts as the ground reference for the uC-interface that is supplied by VCC.
CLKADJ (Clock Adjust)
A high precision resistor of 10 KΩ has to be connected between CLKADJ and GND. The DC-level VCLKADJ is 0.5 V.
ERR (Fault Indication)
The low active ERR signal contains the OR-wired diagnostic information depending on choosen serial or parallel
mode (VBB undervoltage or missing voltage detection, the internal data transmission failure detection unit and the
fault(s) of the output switch).The output pin ERR provides an open drain functionality.This pin has an internal PullUp resistor. In normal operation the signal ERR is high.
Datasheet
14
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
ODIS (Output Disable)
The low active ODIS signal immediately switches off the output channels OUT0-OUT7. This pin has an internal
Pull-Down resistor. In normal operation the signal ODIS is high. Setting ODIS to Low clears the DRIVE register as
well. The minimum width of the ODIS signal is 5 µs.
SEL (Serial or Parallel Mode Select)
When this pin is in a logic Low state, the IC operates in Parallel Mode. For Serial Mode operation the pin has to
be pulled into logic High state. During Start Up the IC is operating in Parallel Mode. This pin has an internal PullDown resistor and a 200 ns blanking time1).
SYNC
In isochronous mode (clock-sync-mode) the transfer of the latched output data register into the output-stages is
controlled by the SYNC signal. When the SYNC-signal is in low state, the output-stage won’t be updated any
longer, the last value is frozen. With the rising edge of SYNC the information of the latched output data registers
will be transferred to the output stages. It can be choosen by a configuration bit whether all the channel diagnostic
bits will be latched into the DIAG channel register every data cycle or only when the SYNC-signal is in high state.
In the last case when the SYNC-signal is in low state, the DIAG channel register wouldn’t be updated any longer,
the last value would be frozen. SYNC is also used for resynchronization of the data transmission with the target
to achieve a low jitter. This pin has an internal Pull-Up resistor and a 20 ns blanking time1).
CS (Chip Select)
When this pin is in a logic Low state, the IC interface is enabled and data can be transferred. This pin has an
internal Pull-Up resistor and a 20 ns blanking time1).
When the CS pin is held Low whereas the ALE pin is High for at least 100 µs, the device is reset.
The following pins are provided in the parallel interface mode
AD7:AD0 (AddressData input / output bit7 ... bit0)
The pins AD0 .. AD7 are the bidirectional input / outputs for data write and read. Depending on the state of the
ALE pin and the AD7 pin, register addresses or data can be transferred between the internal registers and e.g.
the micro-controller. By connecting CS and WR and ALE/RST pins to GND and RD to VCC, the parallel direct
mode is activated.
WR (Write )
By pulling this pin down, a write transaction is initiated on the AddressData bus and the data has to be valid on
the rising edge of WR. The AD7-bit of the register address has to be set to ‘1’. This pin has an internal Pull-Up
resistor and a 20 ns blanking time1).
RD (Read )
By pulling this pin down, a read transaction is initiated on the AddressData bus and the data becomes valid on the
rising edge of RD. The AD7-bit of the register address has to be set to ‘0’. This pin has an internal Pull-Up resistor
and a 20 ns blanking time1).
ALE (Address Latch Enable)/RST
The pin ALE is used to select between address (ALE is in a logic High state) or data (ALE is in a logic Low state).
Furthermore, a read or write transaction can be selected with the RD and WR pin. When ALE is pulled high,
address is transferred and latched over the bit AD0 to AD7. During the time interval where ALE = High RD or WR
has to be pulled to High. During the Low State of ALE all transactions hit the same address. This pin has an internal
Pull-Down resistor and a 20 ns blanking time1). For the reset-function see comment under the item: CS.
1) the signal must be stable for the duration of the blanking time before it is accepted as valid
Datasheet
15
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Pin Configuration and Functionality
The following pins are provided in the serial interface mode
MS0, MS1 (Serial Mode Select)
By driving these pins to Logic High or Low the Serial Interface Mode (number of bits - 8, 16, 24 - to be transferred,
CRC) can be selected. These pins have both an internal Pull-Down resistor and a 200 ns blanking time1).
SCLK (Serial Interface Shift Clock)
Input data are sampled with rising edge and output data are updated with the falling edge of this input clock signal.
This pin has an internal Pull-Down resistor and a 20 ns blanking time1).
SDI (Serial Interface Input Data)
SDI is put into a dedicated FIFO (clocked by SCLK) to program the DRIVE register and the internal address and
the write data. This pin has an internal Pull-Down resistor and a 20 ns blanking time1).
SDO (Serial Interface Data Output)
SDO provides the serial output data bits
CRCERR (CRC Error Output)
This pin is in a logic Low state when CRC errors or Shift-Clock errors are detected internally. This pin has an open
drain functionality and an internal Pull-Up resistor.
Datasheet
16
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Block Diagram
3
Block Diagram
The IC is divided into an uC_chip and into a power chip due to the galvanical isolation.The uC_chip contains the
uC-interface and the power chip the power switches.
uC_chip
SEL
/ODIS
/ERR
power chip
VCC
CLKADJ
VDDIO
VCORE
IADJ
VBB OLADJ
VBB
(x8)
/CS
OSC
AD0/SDI
AD4/
CRCERR
&
AD5/SCLK
IO
AD6
C
R
T
L
AD7 / SDO
RX TX CTRL
Timers
Registers &
Access Control
PARALLEL
/WR
LED
Matrix
/RD
LED
Matrix
LOGIC
ALE
DRV
DIAG
BIAS
BIAS
CT Transceiver
P
A
D
S
BIAS
VREF
OSC
CT Transceiver
AD3
VDDIO
3.3V
UVLO
AD1
AD2
DRV
DIAG
VCORE
SPI
RX TX
CTRL
SYNC GND
(x8)
Overall _Block _Diagram ._ISO 2H823
AD2 /
AD3 /
AD6
*)
AD1 /
ALE/RST /
/WR
*)
LEDY2:0
LEDX2:0
DRV
DIAG
DRV
DIAG
DIAG CTRL
DRV
DIAG
Registers
DRV
DIAG
Control
Unit
LOGIC
MS1:0
DRV
DIAG
DRV
DIAG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CHANNELS
GNDBB (x5)
*) : shared in serial mode
Figure 3
Datasheet
Block Diagram
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Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Block Diagram
uC_chip
power chip
PMU
3.3 V
1.5 V
OSC
VDDIO
VCORE
VBB
RXTX
CTRL
GNDBB
RXTX
CTRL
RST
IADJ
OLADJ
VCC
SYNC
/CS
SEL
µC
Registers
….
Diagnostic_0
e.g.
XMC4xxx
AD0,…,AD7,
/RD, /WR
Drive Control &
Diagnostics
Command
ConRegisters
figuration
L
o
g
i
c
CT Transfer
/ODIS
I
n
t
e
r
f
a
c
e
CT Transfer
/ERR
DRIVE Reg
Drive Control &
Diagnostics
….
OUT0
.
.
.
.
. OUTx
OUT7
.
.
.
.
.
.
.
Diagnostic_7
ErrorRegisters
ALE/RST
LED Matrix
CLKADJ
OSC
RESYNCH
LEDx0
LEDx1
LEDx2
LEDy0
LEDy1
LEDy2
GND
ISO2H823V2
Figure 4
Application with Parallel Interface
uC_chip
use LED
exor
RSTfunction
LED Matrix
µC
e.g.
XMCxxxx
/ODIS
SYNC
/CS
SEL
SDI
SDO
SCLK
/CRCERR
VDDIO
VCORE
VBB
GNDBB
RST
RXTX
CTRL
RXTX
CTRL
IADJ
OLADJ
VCC
/ERR
PMU
3.3 V
1.5 V
OSC
DRIVE Reg
I
n
t
e
r
f
a
c
e
Registers
….
Diagnostic_0
L
o
g
i
c
Drive Control &
Diagnostics
Command
ConRegisters
figuration
CT Transfer
AD6/LEDR0
AD3/LEDR1
AD2/LEDR2
/WR/LEDC0
ALE/RST/LEDC1
AD1/LEDC2
CT Transfer
only
in
serial
mode ,
shared
pins
power chip
….
LED Matrix
CLKADJ
OSC
OUT7
.
.
.
.
.
.
.
Diagnostic_7
Error Registers
MS0,MS1
Drive Control &
Diagnostics
OUT0
.
.
.
.
. OUTx
RESYNCH
LEDx0
LEDx1
LEDx2
LEDy0
LEDy1
LEDy2
GND
ISO2H823V2
Figure 5
Datasheet
Application with Serial Interface
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ISOFACE™
ISO2H823V2.5
Functional Description
4
4.1
Functional Description
Introduction
The IC contains 2 galvanic isolated voltage domains that are independent from each other. The input interface
(µC-chip) is supplied at VCC and the output stage (power chip) is supplied at VBB. The different voltage domains
can be switched on at different time. The output stage is only enabled once the input stage enters a stable state.
The power chip generates out of VBB two internal voltages VDDIO = 3.3 V (+ 10 %) and VCORE = 1.5 V (+ 10%)
which have to be buffered externally.
The ISOFACE ISO2H823V2.5 includes 8 high-side power switches that are controlled by means of the integrated
parallel/serial interface. The interface is 8-bit µController compatible. Furthermore a direct control mode can be
selected that allows the direct control of the outputs OUT0 … OUT7 (power chip) by means of the inputs AD0 …
AD7 (µC-chip) without any additional logic signal. The IC can replace 8 optocouplers and the 8 high-side switches
in conventional I/O-Applications as a galvanic isolation is implemented by means of the integrated coreless
transformer technology. The µController compatible interface allows a direct connection to the ports of a
microcontroller without the need for other components. Each of the 8 high-side power switches is protected against
overload, overtemperature and against overvoltage by an active zener clamp.
4.2
Microcontroller Interface
The microcontroller interface can be configured as a parallel or serial interface via the SEL pin.
4.2.1
Parallel Interface Mode
The ISO2H823V2.5 device contains a parallel interface that can be selected by pulling the SEL Pin to logic Low
state. The interface can be directly controlled by the µController output ports (see Figure 6). The output pins
AD7:AD0 are in state “Z” as long as CS=1, RD=1 and WR=1.
VCC
VCC
/CS
ALE
MCU
(e.g. XMCxxxx)
or ASIC
/RD
AD0
AD1
AD2
ISO2H823V
/WR
AD3
AD4
AD5
AD6
AD7
SEL
parallel _interface_iso2h823. vsd
Figure 6
Datasheet
Bus Configuration for Parallel Mode
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ISOFACE™
ISO2H823V2.5
Functional Description
The timing requirements for the parallel interface are shown in Figure 7 (Read), Figure 8 (Write) and Table 23.
/CS
tCSD
tRD_su
ALE
tALE_high
tRDlow
tCS_ALE
tRD_hd
tRDhigh
/RD
tAD_su tAD_hd
AD[7:0]
GLERR address (04h)
tclrrdy
tfloat
tADout
GLERR data
GLERR data
GLERR
00h
rd_timing_ifx - uc _parallel
Figure 7
Timing by Parallel Read Access (e.g. GLERR Register)
For a reading access to internal registers the MSB of the address register has to be set to “0”.
/CS
tCSD
tWR_su
ALE
tALE_high
tWRlow
tWRhigh
tCS_ALE
tWR_hd
/WR
tAD_su tAD_hd
tAD_su tAD_hd
AD[7:0]
DRIVE
OUT[7:0]
DRIVE address (80h)
DRIVE data (0Fh)
tlat
DRIVE data (0Ah)
0Fh
00h
00h
0Fh
wr_timing_ifx - uc _parallel
Figure 8
Timing by Parallel Write Access (e.g. DRIVE Register)
For a writing access to internal registers the MSB of the address register has to be set to “1”.
Datasheet
20
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
4.2.1.1
Parallel Direct Mode
The parallel interface can be also used in a direct mode that allows direct changes of the output OUT0...OUT7 by
means of the corresponding inputs D0-D7 without additional logic signals. To activate the parallel direct mode CS,
WR and ALE pins have to be wired to ground and RD has to be wired to VCC as shown in the Figure 9. Although
the diagnostics cannot be read in this operation mode, the faults as specified in Table 3 are still reported at the
ERR pin (volatile).
VCC
VCC
/CS
ALE
/RD
Host
AD0
AD1
AD2
ISO2H823V
/WR
AD3
AD4
AD5
AD6
AD7
SEL
parallel _interface_direct_iso2h823.vsd
Figure 9
Parallel Direct Mode
The direct mode is intended to be an additional parallel mode which is invoked directly after reset. In this case
internal settings have already been realized (f.e. MSB of the address register is set to “1” ).
Datasheet
21
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
4.2.2
Serial Interface Mode
The ISO2H823V2.5 device contains a serial interface that can be activated by pulling the SEL pin to logic High
state. The interface can be directly controlled by the µController output ports. The output pin SDO is in state “Z”
as long as CS=1. Otherwise, the bits at the SDI input are sampled with the rising edge of SCLK and registered
into the input FIFO buffer of length dependent on the selected SPI-mode (8, 16, 24 bits, Figure 12, Figure 13,
Figure 14, Figure 15). With every falling edge of SCLK the bits to be read are provided serially to the pin SDO.
The timing requirements for the serial interface are shown in Figure 10 and in Table 24.
inactive
/CS
t SCLK_su
active
tCSD
tSCLK
receive
edge
SCLK
t SU
transmit
edge
t HD
tCSH
MSB
SDI
LSB
tCS_valid
SDO
t SCLK_valid
MSB
tfloat
LSB
timing_def - uc _spi
Figure 10
Serial Bus Timing
Several SPI topologies are supported: pure bus topology, daisy chain and any combinations (Figure 11). Of
course independent individual control with a dedicated SPI controller interfaces for each slave IC is possible, as
well.
A
SCLK
SCLK
SDO
MISO
SDI
A
SDI
MOSI
SCLK
A
MOSI
/CS
/ CS
B
SCLK
SCLK
B
SCLK
B
SDO
SDI
/CS
C
SCLK
MCU
or
ASIC
SDI
/CS
C
SCLK
MCU
or
ASIC
C
SDI
/CS
/CS
D
SCLK
D
SCLK
SDO
MISO
SCLK
D
A
SCLK
SCLK
SDO
MISO
SDI
SDI
/CS
/CS
SCLK
B
SCLK
SDO
SDO
SDI
SDI
/CS
SDO
SDI
SCLK
SCLK
MCU
or
ASIC
/CS
C
SCLK
SDO
SDO
SDI
SDI
/CS
/ CS
SCLK
D
MCU
or
ASIC
SCLK
SDO
SDO
SDO
SDI
SDI
SDI
SDI
/CS
/CS
/ CS
/CS
spi_ topologies3.vsd
Figure 11
Datasheet
Example SPI Topologies
22
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
4.2.2.1
SPI Modes
Four different SPI-modes can be distinguished (Figure 12 - Figure 15).
/CS
SCLK
MS B
SDI
LS B
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Channel-Value (Drive Information )
MS B
CD7
SDO
LS B
CD6
CD5
CD4
CD3
CD2
CD1
CD0
Collective Diagnosis
uc_spi _mode0.vsd
Figure 12
SPI Mode 0, MS0 = 0, MS1 = 0, Daisy Chain Supported
/CS
SCLK
B it 15
B it8
B it7
MS B
LS B
MS B
DR7
SDI
SDO
DR6
DR5
DR4 DR3
DR2
DR1
DR0
0
B it 0
LS B
0
0
Channel -Values (Drive Information )
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
Collective Diagnosis
C4.
C3
C2
C1
C0
Checksum
UV
MV
CF
C4.
C3
C2
C1
C0
Diagnosis / Checksum
uc_spi_mode1.vsd
Figure 13
Datasheet
SPI Mode 1, MS0 = 1, MS1 = 0, Daisy Chain Supported
23
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
/CS
SCLK
READ
B it15
B it8
B it7
MS B
LS B
MS B
R
SDI
A6
A5
CD7
A3
A2
A1
A0
LS B
d.c .
d.c .
d.c .
Register -Address (R/W)
Read=0
SDO
A4
B it0
CD6
CD5
CD4
CD3
CD2
CD1
CD0
D7
B it8
B it7
MS B
LS B
MS B
A0
D7
A6
A5
A4
A3
A2
D6
D5
d.c.
d. c.
D4
D3
D2
D1
D0
A1
B it0
LS B
D6
D5
Register -Address (R/W)
Write=1
d.c.
Value (Read)
B it15
W
SDI
d.c.
Value : dont care
Collective Diagnosis
WRITE
d.c .
D4
D3
D2
D1
D0
d.c.
d.c .
d.c.
0
C4
Value (Write)
SDO
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
d. c.
d. c.
d.c .
d.c .
d.c.
Collective Diagnosis
uc_spi_mode2.vsd
Figure 14
SPI Mode 2, MS0 = 0, MS1 = 1
/CS
SCLK
READ
B it23
MS B
R
SDI
A6
CD7
A4
A3
A2
A1
B it16
B it15
LS B
MS B
A0
0
0
Register -Address (R/W)
Read=0
SDO
A5
CD6
CD5
CD4
CD3
CD2
CD1
CD0
0
0
0
0
0
B it8
B it7
LS B
MS B
0
0
B it0
LS B
0
Value „Zero“ for CRC
D7
D6
D5
D4
D3
D2
C2
C1
C0
C2
C1
C0
Checksum
D1
D0
UV
MV
Value (Read )
Collective Diagnosis
C3
CF
C4
C3
Checksum / Diagnosis
WRITE
B it23
MS B
W
SDI
A6
CD7
A4
A3
A2
A1
B it16
B it15
LS B
MS B
A0
D7
D6
Register -Address (R/W)
Write=1
SDO
A5
CD6
CD5
CD4
CD3
CD2
CD1
CD0
D5
D4
D3
D2
D1
B it8
B it7
LS B
MS B
D0
0
B it0
LS B
0
0
Value (Write)
d.c .
d.c .
d.c .
d.c .
d. c.
C4
C3
C2
C1
C0
C2
C1
C0
Checksum
d. c.
d. c.
d. c.
UV
MV
CF
C4
C3
Checksum / Diagnosis
Collective Diagnosis
uc_spi_mode3.vsd
Figure 15
Datasheet
SPI Mode 3, MS0 = 1, MS1 = 1
24
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
4.2.2.2
Daisy Chain Mode
Up to 4 devices can be connected together as shown in the Figure 16 to operate in the daisy chain mode. Serial
modes 0 and 1 can be operated in daisy chain mode. In this case, the SDO output of one device is directly
connected to the SDI input of the next device. The SPI chain has to be connected to the µC or Bus ASIC (MOSI,
MISO and common SCLK and CS signals). If the received SCLK pulses are not fulfilling the modulo(8)-condition
the CRCERR pin will be activated.
In the serial mode 1 the CRC-generation has to be reset after 16 SCLK-cycles. At the rising edge of CS each
connected daisy-chain-device checks its related 16 bit-stream concerning CRC-consistency.
SDO
MISO
Device A
SDI
SCLK
/CS
SDO
Device B
MOSI
SDI
SCLK
SCLK
/CS
/CS
daisy _connect - uc_spi
Figure 16
Connecting Two Devices for Daisy Chain Mode
The data shifted in the first device SDI input is shifted out at the SDO output after the first byte for the serial mode 0
(after the second byte for the mode 1) while CS remains Low as shown in the Figure 17.
/CS
SCLK
MOSI
=SDIB
DR7 A
DR6A
DR5A
DR4 A
DR3A
DR2A
DR1A
DR0A
DR7 B
DR6 B
DR5B
DRIVE A
SDOB
=SDIA
CD7B
CD6B
CD5B
CD4 B
CD7A
CD6A
CD5 A
CD4 A
DR3 B
DR2 B
DR1 B
DR0B
DRIVE B
CD3 B
CD2B
CD1B
CD0B
DR7 A
DR6 A
DR5A
COLDIAG B
MISO
=SDOA
DR4B
DR4A
DR3 A
DR2A
DR1 A
DR0A
DRIVE A
CD3A
CD2A
CD1A
CD0 A
CD7B
CD6B
CD5B
COLDIAG A
CD4 B
CD3 B
CD2B
CD1B
CD0B
COLDIAG B
daisy _mode0_timing - uc_spi
MISO
Figure 17
Datasheet
SDOA
SDIA
Device A
SDOB
SDIB
Device B
MOSI
Typical Timing Diagram of Daisy Chain Operation (Serial Mode 0)
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ISOFACE™
ISO2H823V2.5
Functional Description
4.2.2.3
Cyclic Redundancy Check CRC
To detect errors inside SPI data transmission two SPI-Modes are provided with integrated Cyclic Redundancy
Check.
The 5-Bit-CRC checksum will be calculated with the polynom X5+X4+X2+1. The bit length used for the calculation
is 11 bits for SPI-mode 1 and 19 bits for SPI-mode 3. The internal CRC-working register is loaded with “11111”
before start of the CRC-calculation.
The SPI-mode 1 supports only the write procedure for the DRIVE register (SPI-mode 1, MS1, MS0 = 01). Eight
bits of drive-information plus 3 dummy bits and the related CRC-information (5 bits based on the fed-in 11 bits)
are delivered to the CRC-engine. At the same time the COLDIAG-information in combination with the UV,MV,CFbits and the related CRC-information (based on these 11bits: COLDIAG, UV,MV,CF) are fed out of SDO. The bit
stream format is shown in Figure 13.
SPI-mode 3 provides register based access to the ISO2H823V2.5 with implemented CRC. The bit stream for a
write access to a register consists of the register address (8 bits), register data (8 bits), 3 dummy bits and the CRC
signature (5 bits) as shown in Figure 15. The total bitstream is fed into the CRC-input engines and processed
according to the underlying CRC-algorithm serially. At the same time the COLDIAG-information in combination
with the UV,MV,CF-bits and the related CRC-information (based on these 19 bits: COLDIAG, 8 dummy
bits,UV,MV,CF) are fed out of SDO.
The bit stream for a read access to a register consists of the register address (8 bits), 11 dummy bits and the CRC
signature (5 bits) as shown in Figure 15.The total bitstream is fed into the CRC-input engines and processed
according to the underlying CRC-algorithm serially. At the same time the COLDIAG-information, register data in
combination with the UV,MV,CF-bits and the related CRC-information (based on these 19 bits: COLDIAG,8 bits
register data, UV,MV,CF) are fed out of SDO.
After processing the 24 in-bits (including the CRC-signature) the result of the CRC-algorithm processing has to be
zero. In the case of another result different from zero the delivered signature is not consistent with the delivered
bit stream. This will be indicated by driving the CRCERR Pin to Low.
In both cases (SPI-mode 1 and SPI-mode 3) the status of the CRCERR pin is evaluated not at the end of the bit
sequence but with rising edge of CS. The procedure is consistent with the daisy-chain application where each
partner of the daisy chain checks its own contribution with the rising edge of CS when it is confirmed that the chain
is completely filled.
CRCERR reflects both the modulo-8-condition of the number of SCLK-signals and the correctness of the CRCsignature. Both kinds of information are evaluated only during CS is Low and reported with the rising edge of CS.
Therefore it is assured that non-active ICs (CS = High) does not report a CRCERR = Low signal in case of toggling
of SCLK.
The signal CRCERR has an internal pull-up-resistor of 50 kΩ. When releasing CRCERR the internal pull-up
resistor determines the rise time, which is about 3 µs. It is possible to reduce the rise time to around 1 µs by adding
an external pull-up resistor of 10kΩ at the CRCERR pin.
Datasheet
26
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
4.2.3
Common Error Indication Output
The dedicated ERR pin signalizes a common fault. This low-active pin has an open drain functionality with a pullup resistor.
Depending on the µController-interface mode in use, several internal status signals are OR-wired to drive the ERR
pin:
•
•
•
•
•
•
In direct mode, the OTC flag (LEDGx-bit-field of CT-transmission, OR-wired, volatile) and the volatile W4Pinformation are routed to the ERR pin.
The output stage undervoltage (UV) and missing voltage (MV) of the power-chip which are transmitted via the
integrated coreless transformer are provided at the ERR pin.
The internal data transmission error (TE) over the galvanic isolation is available as well at the ERR pin.
The signal Wait-for-Power chip (W4P) is also provided. It detects that a continuous transmission error over a
longer time has occurred e.g. when the process side is not supplied properly and that no diagnostic data are
received on the µController-interface side.
The common fault error signal (CF) is routed out to the ERR pin in parallel mode. This signal is the ORcombination of the COLDIAG register bits (sticky).
CF is not routed out to the ERR pin in any serial mode. In serial modes 1 and 3 the CF-bit is contained in the
serial telegram
The Table 3 provides the overview of the signals provided at the ERR pin and the behaviour of the bits used. The
prefix “S” specifies the bits as sticky.
During UVLO, all status signals and register bits are reset. The flags UV, MV, TE and W4P have a reset value of
1, so that by default these errors are active. As a consequence after power-up the ERR pin is by default driven
Low. The ERR pin returns to High logic level once all the signals OR-wired at this pin are Low i.e. once all the fault
conditions are not detected anymore and the bits have been cleared. This behaviour requires the external
controller to read the GLERR and INTERR to “clear” the ERR pin (except in parallel direct mode where the error
bit is simply OTC of type: volatile bit generated by oring the volatile gated-LEDGx-information of each channel and
W4P ). In some operation modes the update and the clearing of the status bits are done automatically after every
access (serial mode 0 and 1). For the other operation modes, the error bits need to be read with direct addressing
to be updated and cleared (parallel mode and serial modes 2,3).
The ERR signal differs between serial modes and parallel modes since in serial modes 1 and 3 the CF bit is
already shifted out when CRC is used. The serial or parallel mode is selected with the SEL signal whereas the
serial submodes are controlled with the SPI_MODE 2-bit signal.
Table 3
Bits composing the ERR signal
Status Bits Serial Communication
Mode-0
Mode-1
Parallel Communication
Mode-2
Mode-3
Single
Access
Repeated
Read
SUV
X
X
X
X
X
X
SMV
X
X
X
X
X
X
X
X
CF
STE
X
X
X
X
X
X
SW4P
X
X
X
X
X
X
OTC
Direct Mode
X1)
X
1) Bit is volatile in direct mode
Datasheet
27
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Functional Description
Upon reset most of the bits used in the ERR generation are reset to High, the ERR pin is pulled down on startup
and will remain Low as long as the external controller does not clear the corresponding bits (and as long as the
fault exists).
4.2.4
Update of the Diagnostic Registers
The following list describes the handling of appearing and disappearing failures and therefore the diagnostics.
•
•
•
Appearing diagnostic/failure: appearing diagnostics are stored internally within sticky registers and are OR-ed
into the register COLDIAG (except LEDGx). Therefore the appearing diagnostic/failure bit can be seen
immediately. After reading COLDIAG the diagnostic bits are transferred from the internal sticky registers to
DIAG0,...,DIAG7 from which these can be read now in detail.
Disappearing diagnostic/failure : the diagnostic bits are stored internally as sticky bits and therefore also (ored)
in COLDIAG. In the case the source for the diagnostic bits has disappeared the diagnostic bits are still
available internally and in COLDIAG until the user has read COLDIAG. Therefore the diagnostic bits never
disappear with vanishing of the source for setting the bits alone. Both conditions have to be fulfilled: vanishing
of the source of the occurence and reading of COLDIAG.
In the case the isochronous mode for the channel diagnostic values is activated with the bit FRZSC in register
GLCFG (see Chapter 4.2.5.2) the diagnostic bits are transferred from the internal sticky registers to
DIAG0,...,DIAG7 with each edge of the SYNC-signal.
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Functional Description
4.2.5
SYNC Operation
The Isochronous Mode enables the synchronization of several devices (e.g. to provide 32 channels 4 devices are
grouped in parallel). In this way the update of all the output channels as well as their diagnostics can be
synchronized and held such that the Bus ASIC or microcontroller can program a new control word of the output
channels and read the diagnostics status. In continuous mode, each device with its own built-in oscillator is
updated independently.
The Isochronous Mode is controlled by the SYNC pin and independent of the selected serial or parallel interface
(with the SEL pin). It concerns only the update of user registers in the system.
4.2.5.1
SYNC-Signal for Drive-Signals
Figure 18 explains in detail the mechanism for SYNC = High, SYNC = Low and the rising and falling edges of
SYNC for transferring the drive-information from the uC-Chip to the Power Chip.
Programmed
DRIVE[X]
SYNCsignal
to Power Chip
transferred
DRIVE[X]information
OUT[x]
continuous mode
(SYNC is in high state)
isochronous mode
(SYNC is in low state)
Page -2 - uc _isochronous _mode
Figure 18
SYNC Operation Timing
SYNC = High, Normal Mode:
The DRIVE-register can be written with new data and the contents of it is also transferred to the power chip.
SYNC = Low, Isochronous-Mode:
In isochronous mode the user can write the DRIVE-register but this value will not be transferred to the Power Chip.
Therefore the driver configuration (activation of drivers in the Power Chip) is frozen. In Figure 18 it can be clearly
seen that the toggling of the DRIVE[x]-information (SPI-data-cycle) at the right side had not been transferred to
the process side (see oval area in Figure 18).
4.2.5.2
SYNC-Signal for Diagnostics
Independent from the level of the SYNC-signal always the same reading-sequence of the diagnostics shall be
obeyed : read COLDIAG, check which channel x (in the following examples of Table 4 and Table 5 : channel 0)
shows the setting of diagnostic bits and read the related DIAG0,...,DIAG7 for checking in detail which diagnostic
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Functional Description
has been reported. Reading of COLDIAG first assures that the DIAG0,...,DIAG7-registers are loaded from the
internal sticky registers.
SYNC = High, Continuous Mode:
When the signal SYNC is High (default), the continuous mode is selected and the diagnostic registers
DIAG0,....DIAG7 are always updated after read access to COLDIAG.
Table 4 shows the typical scenario where an external disturbance (openload or short-circuit-to VBB) cause the
setting of the diagnostic registers DIAG0,...,DIAG7 (here DIAG0) and the collective diagnostic register COLDIAG.
After vanishing of the disturbance and reading of COLDIAG the internal diagnostic registers are reset. The SYNCwaveform is sketched in red (in Table 4 for the continuous mode any waveform is allowed), the disturbance in light
shaded grey (in this example strictly time limited) and the possible read-access in dark grey.
Table 4
Waveform
of SYNC
Continuous Mode (GLCFG : FRZSC = 0), Disturbance (to Channel 0) Scenario
permanently “High”
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx”1”xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
or any waveform of SYNC is allowed when GLCFG:FRZSC = 0
........”0”.....
scenario #
1
1
read results
COLDIAG
DIAG0
2
2
read results
COLDIAG
DIAG0
disturbance
read=yes
0x01
0xvalue
read=yes
0x00
0x00
disturbance
read=yes
0x01
0xvalue
read=yes
0x01
0xvalue
read=yes
0x00
0x00
SYNC = Low, Isochronous-Mode:
The isochronous mode for the channel diagnostic values is activated with the bit FRZSC in register GLCFG. If
FRZSC = 1 (RESYN = 0) the isochronous mode for diagnostics is enabled.
When SYNC is Low, the DIAG0-7 and COLDIAG (including CF) are not updated anymore (frozen). At the falling
edge of SYNC the information of the internal sticky registers is transferred to DIAG0,...,DIAG7. During SYNC =
High the information of the internal sticky registers has been mirrored and ored to COLDIAG. When isochronous
mode is activated the DIAG0,...,DIAG7-registers and COLDIAG freeze the diagnostic data. But the internal sticky
registers collect the diagnostic information independently from SYNC. With rising edge of SYNC the
DIAG0,...,DIAG7 registers and COLDIAG are updated on base of the contents of the internal sticky registers.
Table 5 shows some scenarios where an external disturbance (openload or short-circuit-to VBB) cause the setting
of the diagnostic registers DIAG0,...,DIAG7 (here DIAG0) and the collective diagnostic register COLDIAG. In all
scenarios the same procedure is sketched where a disturbance occurs and the diagnostic registers are read in the
following. The SYNC-waveform is sketched in red (in Table 5 for the isochronous mode with low and high periods),
the disturbance in light shaded grey (in this example strictly time limited at different timestamps) and the possible
read-access in dark grey. In Table 5 the occurence of the disturbance relative to the edges of the SYNC-signal is
altered. Read procedures can occur during the phase of SYNC = 0 or SYNC = 1. Dependent on the occurence of
the disturbance relative to the SYNC-edges and the read-process the diagnostic values have been already set in
COLDIAG and DIAG0,...,DIAG7 or the old values have been frozen. In the second case the new values will be
updated in COLDIAG and DIAG0,...,DIAG7 with the next rising edge of SYNC and can be read with the next readDatasheet
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Functional Description
cycle. Due to the sticky registers no diagnostic value is lost. After vanishing of the disturbance and reading the
diagnostic values are reset.
Entries in COLDIAG can be reset during SYNC = Low after a reading procedure when the disturbance had been
registered before the falling edge of SYNC and is therefore securely delivered. But DIAG0,...,DIAG7 remains
unaffected from this reading procedure.
Table 5
Waveform
of SYNC
Isochronous Mode (GLCFG : FRZSC = 1 (RESYN = 0)), Channel 0 Disturbed, Scenarios
xxxx x
High x
x
x xxxxxxx”0”xxxxxxx
Low
x xxxxxxxxx”1”xxxxxxxx
x High
x
x
x
x
x
x xxx”0”xx
Low
x xxx”1”xx
x High
x
x
scenario #
1
disturbance
1
read results
COLDIAG
DIAG0
2
read=yes
0x01
0xvalue
read=yes
0x00
0x00
read=yes =yes
0x01
0x00
0xvalue 0x
val
read=yes
0x00
0x00
disturbance
2
read results
COLDIAG
DIAG0
3
....disturbance..........
3
read results
COLDIAG
DIAG0
read=yes
0x00
0x00
4
.......disturbance............
4
read results
COLDIAG
DIAG0
read=yes
0x00
0x00
5
read=yes read=yes
0x01
0x00
0xvalue 0x00
read=yes read=yes
0x01
0x00
0xvalue 0x00
disturbance
5
read results
COLDIAG
DIAG0
6
read=yes
0x01
0xvalue
read=yes
0x00
0x00
....disturbance..........
6
read results
COLDIAG
DIAG0
Datasheet
read=yes
0x00
0x00
read=yes
0x01
0xvalue
31
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0x00
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Functional Description
Table 5
Waveform
of SYNC
Isochronous Mode (GLCFG : FRZSC = 1 (RESYN = 0)), Channel 0 Disturbed, Scenarios
xxxx x
High x
x
x xxxxxxx”0”xxxxxxx
Low
x xxxxxxxxx”1”xxxxxxxx
x High
x
x
7
.......disturbance.........
7
read results
COLDIAG
DIAG0
read=yes
0x00
0x00
4.2.6
x
x
x
x xxx”0”xx
Low
x xxx”1”xx
x High
x
x
read=yes
0x01
0xvalue
read=yes
0x00
0x00
ODIS Output Disable
The low active ODIS signal immediately switches off the output channels OUT0-OUT7. This pin has an internal
Pull-Down resistor. In normal operation the signal ODIS is High. Setting ODIS to Low clears the registers as well.
The minimum width of the ODIS signal is 5 µs.
4.2.7
LEDGOFF
The gated-LED-signal LEDGx, x=0,...,7 is per default reported in the diagnostic registers DIAG0,...,DIAG7 (not
ored in the COLDIAG-register). LEDGx is updated with a long time constant every 100ms. Therefore the bit
LEDGOFF in GLCFG offers the possibility to suppress the reporting in the diagnostic registers DIAG0,...,DIAG7.
4.2.8
OLOFF
The bit OLOFF in GLCFG offers the possibility to suppress the reporting of OLIx, OLAx in the diagnostic registers
DIAG0,...,DIAG7.
4.2.9
RESET (Hard and Soft)
4.2.9.1
Hardware Reset
The external hardware reset can be enabled or disabled by the bit RSTOFF in the register GLCFG, by default the
external hardware reset function is enabled. The external hardware reset forces the logic asynchronous reset for
the uC_chip (acts like a power-on-reset), all register are loaded with the default values. It is triggered when the
signal ALE is set High whereas the CS signal is set Low for at least 100 µs. Once an internal timer reaches the
end value of 100 µs then the hardware reset condition is fulfilled and “latched”. At the point where one of the
signals ALE and CS returns to its default value, the reset is processed. With resetting the DRIVE-register and
restarting the CT-transmission the output switches are shut down.
4.2.9.2
Soft Reset
The soft reset for the uC_chip is triggered by the bit SWRST (self clearing after performing the soft reset) in the
register GLCFG. If the soft reset is triggered the DRIVE, INTERR, GLERR, DIAG0,...,DIAG7, COLDIAG,
DIAGCFG register are set to their reset values synchronously. In addition the internal flags are cleared. The CTtransmission is restarted. The actual transmission cycle is not disturbed. With resetting the DRIVE-register and
restarting the CT-transmission the output switches are shut down.
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Functional Description
4.2.10
Resynchronization of CT-Transmission
During the CT-transmission the drive-information DRIVE for 8 power switches is sent from the uc-Chip to the
Power-Chip. Subsequently one of the diagnostic informations (status-information, OTx, OLIx, OLAx, OCLx,
SCVx or LEDGx-information for the 8 power switches) is sent back. The duration of a CT-time slot with
transmission of drive - information and back-transmission of one of the diagnostic information lasts about
5 us + 20 %. (internal operating frequency : 10 MHz, resistor at pin CLKADJ : 10 kΩ). When the user programs
the drive register a timing uncertainty arises when the specific programed switch is activated or deactivated in the
power chip. The data of the drive register can be transferred to the power chip only in the next free CT-time slot.
The goal of resynchronization is to limit the timing uncertainty due to transmission and retransmission to a value
below + 1.5 us but with a fixed latency of minimum 7.0 us . For triggering the transmission the signal SYNC is used
when GLCFG:RESYN = 1. A timing difference between switching on and off of the power transistors exists which
is already included in the timing uncertainty value above. Switching off a power transistor is delayed by up of 0.5 us
max relative to the SYNC-rising edge compared to switching on a power transistor.
Requirements on RESYNCHRONIZATION -Timing :
GLCFG:RESYN = 1
7.0 us min
SYNC
maximum time duration to finish current CT -slot 5 us
(determined by internal transmission and retransmission)
2.0 us
safety margin
…...
uC_chip
power -chip
DRIVE
Diagnostics
uC_chip
power -chip
next CT-slot
Figure 19
Timing of Resynchronization
Transmission without Resynchronization:
•
•
•
•
GLCFG:RESYN = 0 or 1
signal SYNC = 1
write the drive information into DRIVE
the contents of DRIVE is transferred via the CT to the power-chip
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Transmission with Resynchronization:
•
•
•
•
•
•
•
signal SYNC = 1
GLCFG:RESYN = 1
write the drive information into DRIVE_RESYNCH
signal SYNC = 0
the duration of the signal SYNC = 0 (minimum 7.0 us) determines the time for resynchronization and the time
until the next CT-transfer
In the meantime the pending transmission and retransmission has been finished and the contents of
DRIVE_RESYNCH has been transferred to DRIVE
set signal SYNC = 1, the CT-transfer is started from DRIVE with the rising edge of SYNC
Without any negative pulses on SYNC the CT-transfer is operated permanentely from DRIVE; the negative pulses
on SYNC are solely used for resynchronization, the isochronous mode for drive-information and for diagnostics is
inactive when GLCFG:RESYN is set to “1”.
Information for the DRIVE_RESYNCH-register can be written long before the resynchronzation trigger with falling
and rising edge of SYNC.
The user has to obey the timing requirements of the SYNC-signal. For a duration longer than 300 us + 20% the
watchdog in the power chip disables the output drivers. For a shorter duration of the SYNC-signal than
recommended the resynchronization is not guaranteed and the normal transmission fed by the register DRIVE can
be performed.
Figure 20 shows 2 different applications of resynchronization. The timing gap between two synchronizations can
be as low as 1 us. In this way the customer can decide between single synchronization steps and permanent
synchronized transmission with the drawback of reduced CTthrough put (time for waiting of new transmission).
Resynchronization of CT-Transmission
Scenario 1 : 2 resynchronization -steps after several transmissions
several transmissions and retransmissions
transmission
gap
DRIVE
Diagnostics
DRIVE
finish actual CT-slot and wait
restart
transmission
after
tresynch
…...
DRIVE
Diagnostics
Diagnostics
t resynch
SYNC
trans.
gap
DRIVE
Diagnostics
DRIVE
restart
transmission
after
tresynch
Diagnostics
t resynch
SYNC
Scenario 2 : permanent resynchronization
transmission
gap
DRIVE
Diagnostics
SYNC
DRIVE
finish actual CT-slot and wait
restart
transmission
after
tresynch
Diagnostics
trans.
gap
DRIVE
restart
transmission
after
tresynch
Diagnostics
tresynch
(min. 7.0 us)
t resynch
SYNC
t resynch_gap
(min.1 us)
Figure 20
Datasheet
Examples of Application of Resynchronization
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Functional Description
Application hint : It is not possible to select GLCFG:RESYN = 1 and isochronous mode of drive information or/and
isochronous mode of diagnostics at the same time. That means resynchronization and isochronous mode of driver
information and diagnostics at the same time is not possible. With GLCFG:RESYN = 1 edges on SYNC are used
solely for resynchronization.
4.3
Output Stage
Each channel contains a high-side power FET that is protected by embedded protection functions. The continuous
current for each channel is 600 mA nominal, which depends on the cooling conditions and the total power
dissipation.
4.3.1
Output Stage Control
Each output is independently controlled by an output latch and a common reset line via the pin ODIS that disables
all eight outputs and resets the latches.
4.3.2
Protection Functionality
4.3.2.1
Power Transistor Overvoltage Protection
Each of the eight output stages has it’s own zener clamp that causes a voltage limitation at the power transistor
when solenoid loads are switched off. VONCL is then clamped to 52 V (typ.).
4.3.2.2
Power Transistor Overload Protection
The outputs are provided with a linear current limitation, which regulates the output current to the current limit value
in case of overload. The electrical operation point does not lead to a shutdown.
The excess power dissipation in the power transistor during current limitation will lead to a rapid increase of the
junction temperature. When the junction temperature exceeds 150 °C (typ.) the output will switch off and will
switch on again when the junction temperature has cooled down by a temperature hysteresis of 15 K (typ.).
Therefore during overload a thermal on-off toggling may occur.
The thermal hysteresis is reset during inactive mode. Therefore when switching to the active mode the power
transistor is first switched on if the junction temperature is below 150 °C.
4.3.2.3
Current Sense and Limitation
To achieve an excellent accuracy for the current limitation and current referred diagnostic (OCLx) an external
reference resistor is used. The resistor must be connected between the pins IADJ (as close as possible) and
GNDBB. The nominal resistor value is 6.81 kΩ (E96; current drawn out of IADJ typ.178 µA) , the tolerance should
be within 2% to meet an overall current limit tolerance from 0.73 A to 1.3 A.
Operation with other resistor values than 6.8 kΩ ±5% is not allowed and may lead to insufficient short circuit
protection.
To offer open load diagnostics in active mode, a part of the power transistor is driven down when the drain-sourcevoltage drops below a certain limit (low load condition). The voltage drop across the remaining part is used to
evaluate an open load diagnostic.
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4.3.3
Diagnostic Functions
For each of the output stages 5 different types of diagnostics are available. Table 6 specifies the diagnostics.
Some of the diagnostics are available only in active mode, others only in inactive mode. The diagnostics OLIx,
OLAx, SCVx can be prolonged within the complementary mode. Overtemperature in inactive mode is not reported
(set to zero).
Table 6
Diagnostic
Item
Diagnostic Type
Inactive Mode
Active Mode
OTx
Overtemperature
no
yes (OTx Active)
OLIx
Open Load/Wire Break, “inactive” yes
no
OLAx
Open Load/Wire Break, “active”
no
yes
OCLx
Current Sense,
Overload Detection
no
yes
SCVx
Short Circuit to VBB
yes
not distinguishable from OLAx
VBB
VBB Monitoring
GLERR
UV
Under Voltage Detection
MV
Missing Voltage Detection
CF
Reset Voltage
Output Driver Control Unit
Driver
COLDIAG
Protection Unit
Zener Clamping
(Demag. of Induct. Loads)
Temperature Sensor
OUTx
IADJ
Current Limitation
DIAGx
Diagnostic
Unit
Overload Detection
OT
Over Temperature Detection
OLA
SCV
Filtering &
Processing
OCL
OLI
Open Load Active Detection
OLADJ
Short to VBB Detection
Open Load Inactive Detection
DIAGCFG
Diagnostics_ Overview_ ISO2H823V.vsd
Figure 21
Datasheet
Diagnostics Overview
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The diagnostics OLIx, SCVx are reported in inactive mode and OLAx is reported in active mode. When the
duration of the disturbance was not sufficient to guarantee a 6 ms blanking/filtering time these diagnostics are at
least reported when switching from one mode into the other mode. The diagnostics OLIx, OLAx and SCVx,OLAx
appear in pairs one component for the inactive mode and one component for the active mode with a delay for the
filtering. In order not to allow reporting gaps the diagnostics are prolonged until the complementay part is occurring
or until a time out counter has expired (f.e. the diagnostic OLIx (SCVx) is prolonged also during the active time
period until the filter delivers a reliable OLAx- (OLAx-) diagnostics and vice versa).
4.3.3.1
Diagnostics in Inactive Mode
When the output is in inactive mode a diagnostic current is fed to the output. If the load is connected and the load
resistance is less than 12 kΩ, the output voltage will be 300 mV or less.
If no load is connected a voltage drop of 7 V is present at the output. A voltage in the range of 5.5 V up to 9.2 V
at the output OUTx is detected and reported as open load inactive (OLIx) after filtering.
If the output is shorted to VBB the output voltage will be close to VBB level even in inactive mode, this depends upon
the type of the short circuit. A voltage level above 9.2 V at the output is detected and reported as short circuit to
VBB (SCVx) after filtering.
The window comparator for OLIx (5.5 V - 9.2 V) is realized with the analog level comparators for 5.5 V and 9.2 V
and the digital filters for OLIx and SCVx. After filtering SCVx has the priority against OLIx. By means of the digital
filters EMI-contributions shall be filtered before deciding about OLIx or SCVx.
If a capacitive load with a long RC time constant is connected to the ISO2H823V2.5 (like a 12 kΩ resistor through
a long cable with 100 nF capacitance) when switching off, the output voltage sequently passes through the
windows of short to VBB detection and broken wire detection. During a blanking time of 6 ms (typ.) the diagnostic
signals are ignored to avoid false triggering of diagnostic registers.
If the corresponding channel is switched on again before the end of the blanking time (6 ms) , the state of the
diagnostic signals present before switching on is transferred to the diagnostic registers, bypassing the blanking
window of 6 ms and filtered instead with a filtering time of 100 us, 0.5 ms, 1 ms depending on the switching
frequency.
Table 7
Filter Time in Inactive Mode for OLIx and SCVx
Duration of inactive time tOFF before switching
Filter time
0 ms < tOFF < 1.5 ms
100 us
1.5 ms < tOFF < 3 ms
0.5 ms
3 ms < tOFF < 6 ms
1 ms
tOFF > 6 ms
6 ms (OLIx), 2 ms (SCVx)
For the largest SCVx-filter a filter-length of 2.0 ms is choosen but a setting of SCVx is only possible after the
blanking window of 6 ms. No single channel over temperature diagnostics is given during inactive mode to avoid
false triggering when switching inductive loads.
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Functional Description
4.3.3.2
Diagnostics in Active Mode
If during active mode operation the remaining voltage drop of a low load condition is compared to the voltage drop
across a reference transistor biased with a reference current. The reference current can be set by the value of a
resistor connected between OLADJ and GNDBB defining the threshold for open load diagnostics. The resulting
open load threshold is inversely proportional to the connected resistor (25 kΩ - 2.3 kΩ, E96 series; current out of
the OLADJ-pin 48.6 µA - 528 µA) and can be set within 0.5 mA to 5 mA.
Like the diagnostics in inactive mode the open load diagnostics in active mode (OLAx) is ignored during a 6 ms
blanking window after switching on. If the channel is switched off before the end of the blanking window the current
state of the open load diagnostics is transferred to the diagnostic registers, bypassing the blanking window of 6
ms and filtered instead with a filtering time of 100 µs, 0.5 ms or 1.0 ms (depending on the switching frequency).
The over load diagnostic (OCLx) occurs generally if the output stage limits the load current. Therefore the
diagnostic threshold is equal to the current limiting value. An overload may and a short to GNDBB will probably
lead to a thermal shutdown. The shutdown is indicated separately by the diagnostics OTx. The standard filter time
for overload (OCLx) and overtemperature (OTx) is 50 us (for a thermal shutdown).
Table 8
Filter Time in Active Mode for OLAx
Duration of active time tON before switching
Filter time
0 ms < tON < 1.5 ms
100 us
1.5 ms < tON < 3 ms
0.5 ms
3 ms < tON < 6 ms
1 ms
tON > 6 ms
6 ms
Some loads like incandescent lamps or DC motors show an inrush current, which is normal and should not trigger
an overload diagnostic. In some cases even a transient thermal shutdown can not be avoided but an OTxmessage is avoided for the time duration of running up f.e. a cold lamp (max. 200 ms). In this case and only for
this short time duration the current limiting threshold can be set to 1.5 A and the temperature threshold to 200°C
by the internal finite state machine.
The ISO2H823V2.5 adapts filtering of over load and thermal shutdown diagnostics as well as shutdown
temperature and current limit level by evaluating the previous turn off time and the load resistance.
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Functional Description
4.3.3.3
Diagnostic Scenarios in Dependence of Switching Frequency
The Table 9 explains the occurence of diagnostics dependent on the switching frequencies for the disturbance
“Short-Circuit-to-VBB”.
Table 9
Occurence of Diagnostics during the Disturbance : Short-Circuit-to-VBB
Stable Switching Frequency : f
Reported
Diagnostic
Unwanted Diagnostics at
Onset of ............................or at Resolving of
SCVx-Disturbance
permanently “low” : f = 2 kHz
SCVx, OLAx
OLIx 2)
permanently “low”
--> permanently “high”
f f >= 2 kHz
SCVx, OLAx
OLIx 1) 2) : depends on the time of onset and resolving of
SCVx-disturbance
permanently “high”
--> permanently “low”
f >= 2 kHz --> f = 6
ms in the inactive phase. The occurence of the additional OLIx-signal depends on the relative duration of the inactive mode
and the SCVx-disturbance. It disappears at last after 4 ms or with continued switching of the power transistor. As
the user himself has caused the additional OLIx-signal by resolving the SCVx-disturbance the user can ignore this signal
for the next 4 ms or can continue switching the power transistor.
2) Depending on the onset of the SCVx-disturbance in scenarios with high or intermediate switching frequency one time an
unwanted OLIx-reporting can occur which vanishes during further switching. As in the upper case 1) the user can
ignore it as in the sequel the correct signaling occurs.
The Table 10 explains the occurence of diagnostics dependent on the switching frequencies for the disturbance
“Openload”.
Prerequisite : an external capacitor of C = 10 nF (minimum value) for enhancing the EMI-robustness is attached
to the output. VBB = 24 V.
In Table 10 the additional SCVx-diagnostic reflects the transition from active to inactive mode when the external
C (EMI-robustness) has to be decharged via a high ohmic internal resistor. During the decharging process the
output voltage is in the region of reporting SCVx.
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Table 10
Occurence of Diagnostics during the Disturbance : Wirebreak
Stable Switching Frequency : f
Reported
Diagnostic
Comment
permanently “low” : f = 2 kHz
SCVx, OLAx
instead of OLIx : SCVx2)
permanently “low”
--> permanently “high”
f f >= 2 kHz
OLIx, OLAx,
SCVx
--->
SCVx, OLAx
additionally SCVx1)
permanently “high”
--> permanently “low”
f >= 2 kHz --> f
OLIx, OLAx,
SCVx
additionally SCVx1)
Transitions in the Switching
Frequency : f
1) additionally SCVx reported, diagnostic due to decharging of the external C (EMI-robustness)
2) instead of OLIx is SCVx reported,diagnostic due to decharging of the external C (EMI-robustness)
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ISOFACE™
ISO2H823V2.5
Functional Description
4.3.3.4
Global Diagnostics
The global diagnostics include:
•
•
•
•
•
UV: undervoltage supply condition when VBB is below 16 V with 0.5 V hysteresis,
MV : missing voltage supply condition when VBB is below 13 V with 0.5 V hysteresis,
OTP: global over temperature (chip temperature outside the switch area triggers above 125 °C), the global
over temperature does not lead to thermal shutdown,
ALLOFF: all drivers in the power chip are disabled (by DRIVE-programming, ODIS-setting or temperature
shutdown of all channels),
LAMP: the load of one of the drivers behaves like a cold lamp
4.3.3.5
Power Supply
The startup procedure of the power chip is explained in Figure 22.
VVBB
Voltage
VUV
VVBBuvhys
VMV
VVBBmvhys
VRESET
VVBBhys
VVBBuvoff
VVBBuvon
VVBBmvoff
VVBBmvon
VVBBon
VVBBoff
Time
RST
MV
UV
por_uv_mv_events .vsd
Figure 22
Start Up Procedure of the Power Chip
During UVLO, all registers of the power chip are reset to their reset values as specified in the register description
(Chapter 6). As a result, the flags TE, UV as well as MV are High and the ERR pin is Low (error condition).
Immediately after the reset is released, the chip is first configured by “reading“ the logic level of the SEL, MS1,
MS0 - pins. The IC powers up as a parallel device i.e. the AD0-7 pins are high-impedance until the IC configuration
is over.
The supply voltage VBB is monitored during operation by two internal comparators (with typ. 2 ms blanking time)
detecting:
•
•
VBB Undervoltage: If the voltage drops below the UV threshold, the UV-bit in the GLERR register is set High.
The IC operates normally.
VBB Missing Voltage: If the voltage further drops below the MV threshold, lower than the previous threshold,
the MV-bit in the GLERR register is set, the Power Side of the IC is turned off when reaching the VResetthreshold whereas the Micro-Controller Side remains active.
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ISO2H823V2.5
Functional Description
Note: The driver stage is self protected in overload condition: the internal switches will be turned off as long as the
overcurrent condition is detected and the IC will automatically restart once the overload condition
disappears.
Important: Since the UV and MV (as well as the TE) bits used for generating the ERR signal are preset to High
during UVLO, the ERR pin is Low after power up. Therefore the ERR requires to be explicitly cleared after power
up. At least one read access to the GLERR and INTERR registers or one default read access in certain accessmodes (see Chapter 4.2.3) is needed to update those status bits and thus release the ERR pin.
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ISO2H823V2.5
Functional Description
4.3.4
LED Matrix
The driving signal for the LED-matrix is the drive-signal of the register DRIVE gated with the signal LEDGx of the
registers DIAG0,...,DIAG7. This signal is generated in the power chip and transferred via the CT-interface to the
uC-Chip. For suppressing a thermic toggling visible on the LED-matrix LEDGx disables the related LED for at least
100ms when an overtemperature (OTx) or overcurrent condition (OCLx) has occurred.
4.3.4.1
LED Matrix on the Process Side
Eight LEDs arranged in a 3x3 matrix can be driven through the outputs LEDx0 to LEDx2 and LEDy0 to LEDy2 of
the Power Chip. Each output channel has a corresponding status LED in the matrix showing the actual status of
the channel. When the LED lights up, the corresponding channel is in the active mode and has no thermal
shutdown and no overcurrent condition.
Series resistors must be inserted in each column line LEDy0...LEDy2 to set the LED current. The driving level on
the column lines is the VBB voltage level. The row lines are driven alternately with 1/3 duty cycle at 1000 Hz. The
resulting average current for each LED is 1/3*(VBB minus diode forward voltage)/series resistance.
If the diode matrix is used at all, all 8 LEDs must be connected for correct function of the matrix.
LEDy2
LEDy1
LEDy0
S0
S3
S6
S1
S4
S7
S2
S5
LEDx0
LEDx1
LEDx2
Figure 23
Datasheet
LED Matrix connected to the Power Chip
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ISO2H823V2.5
Functional Description
Figure 24
LED Pulse Diagram
If no LEDs are used at all it is possible (by reasons of EMI) to connect all column signals LEDY0,..,2 together and
all row-signals LEDx0,..,2 together but a connection among columns and rows is not allowed. In the case of
paralleling of channels it is possible to substitute the unused LEDs by resistors which have the only function to
dissipate the current which is delivered in case the not existing diode is accessed. If no limiting element is used
(f.e. resistor) the voltage at the LEDs of the non-activated rows can rise up to VBB if the non-existing element is
activated (the related row activated and the corresponding column activated).
4.3.4.2
LED Matrix on the uController Side (only in Serial Communication Mode)
For the driving signals on the uController-side the following pins are used for the column signals : AD1 / LEDC2,
ALE/RST / LEDC1, WR / LEDC0 and for the row-signals : AD2 / LEDR2, AD3 / LEDR1, AD6 / LEDR0. For enabling
the LED-function on the uC-Chip side the bit LEDON in the GLCFG-register has to be set. LED-operation is only
possible in the serial communication mode. If LEDON = 1 the hardware reset function is disabled.
As in the case for the LED on the power chipside a 3x3 matrix can be driven. Each output channel has a
corresponding status LED in the matrix showing the actual status of the channel. When the LED lights up, the
corresponding channel is in the active mode and has no thermal shutdown and no overcurrent condition. The 9.th
LED is connected with the ERR-signal.
Series resistors must be inserted in each column line LEDC0...LEDC2 to set the LED current. The driving level on
the column lines is the VCC voltage level. The row lines are driven alternately with 1/3 duty cycle at 1000 Hz. The
resulting average current for each LED is 1/3*(VCC minus diode forward voltage)/series resistance.
If the diode matrix is used (LEDON = 1) , all 9 LEDs must be connected for correct function of the matrix.
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ISOFACE™
ISO2H823V2.5
Functional Description
AD1 / LEDC2
ALE/RST / LEDC1
/WR / LEDC0
Figure 25
AD6 / LEDR0
S0
S3
S6
AD3 / LEDR1
S1
S4
S7
AD2 / LEDR2
S2
S5
ERR
LED Matrix connected to the uC-Chip
In the case of paralleling of channels it is possible to substitute the unused LEDs by resistors which have the only
function to dissipate the current which is delivered in case the not existing diode is accessed.
The minimum value of the VCC-voltage is 2.75 V. But this low voltage will limit the choice of the used LEDs (in the
worst case only LEDs with a lower forward voltage of around 2.2 V are possible).
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ISOFACE™
ISO2H823V2.5
Functional Description
4.4
EMI-Robustness
Care has been taken to increase the Burst- and RFCM-robustness according to the standardization requirements
referenced in
•
•
•
DIN EN 61131-2 (Programmable Controllers , Part 2 : Equipment Requirements and Tests)
IEC 61000 -4-4 (Testing and measurement techniques - electrical fast transient/burst immunity test)
IEC 61000 -4-6 (Testing and measurement techniques - immunity to conducted disturbances, induced by
radio-frequency fields)
respectively.
As the standardization document DIN EN 61131-2 gives a system-requirement we can give only recomendations
for the application with ISO2H823V2.5 for improvement the EMI-robustness. Exact values have to be evaluated
with the total system including external components and PCB-layout and wiring.
For Burst- and RFCM-robustness we consider only the driver-pins OUTx and VBB as these pins are exposed to
external disturbances. Other pins of ISO2H823V2.5 are encapsulated within the housing of the control equipment
(f.e. PLC).
The influence of HF-signals is eliminated internally with assistance of the external capacitor of min.10 nF (+ 10%)
at the output OUTx of each power transistor. To increase the safety margin if higher test voltages are applied it is
possible to increase the capacitor up to 12 nF + 10 %.The purpose is to suppress frequency contributions of the
external disturbance greater than 2 MHz.
Investigations have been done with an external load of a high value of 12 kΩ. Other critical loads consisting of a
high inductive value combined by a high resistive value (f.e. 0.8 H, 1.4 kΩ) have been also examined.
4.4.1
Burst Robustness
Figure 26 shows the test circuitry for applying burst pulses. The fat drawn equipment symbolizes the burstgenerator and the coupling of burst pulses to the OUTx-pins and/or to the VBB-pin (see the different coupling
network for OUTx, VBB as specified in IEC 61000).
Datasheet
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ISO2H823V2.5
Functional Description
Burst-Application
VBB
VBB
each OUT or VBB is
loaded separately with
burst pulses
IADJ
2.2 uF
OLADJ
CT Transfer
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Control
Protection
Diagnostic Unit
C
10 nF
min.
*)
C
10 nF
min.
*)
100 pF
10 nF
50 Ohm
50 Ohm
+
ISO2H823V2
Power Chip
VDDIO
VCORE
load
12
kOhm
C system_earth =
22 nF
GNDBB
System_GND
*) : for enhancement of EMI -robustness,
recommended value 12 nF
Figure 26
load
12
kOhm
+
-
Earth
C system_earth on application board for separation
of System_GND and Earth
Burst-Application
For burst-disturbance the standard foresees 2 repetition frequencies : 5 kHz and 100 kHz. For the repetition
frequency of 5 kHz the target is to achieve a burst-robustness of min .+ 2500 V within the system with external
elements. For a repetition frequency of 100 kHz it is much harder a give an estimation without the knowledge of
external elements. For this case no statement is given here.
4.4.2
RFCM-Robustness
Figure 27 shows the test circuitry for applying RFCM frequencies. The fat drawn equipment symbolizes the HFgenerator and the coupling of HF frequencies to the OUTx-pins and/or to the VBB-pin (the drawn coupling network
shall symbolize an effective impedance of 150 Ω regardless of the frequency as specified in IEC 61000). The HFdisturbance is an 80%-amplitude modulated signal with the carrier frequency of 10 kHz - 80 MHz and the
modulation frequency of 1 kHz.
Datasheet
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ISOFACE™
ISO2H823V2.5
Functional Description
RFCM / HF-Bestromung
VBB
VBB
each OUTx or VBB is
loaded separately
with HF signals
IADJ
2.2 uF
OLADJ
CT Transfer
OUT0
ISO2H823V2
Power Chip
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Control
Protection
Diagnostic Unit
*) : for enhancement of EMI -robustness,
recommended value 12 nF
C
10 nF
min.
*)
|Z| =
150 Ohm
C
10 nF
min.
*)
load =
12
kOhm
C system_earth
= 22 nF
VDDIO
VCORE
GNDBB
System_GND
Earth
VHF_peak_peak
0V
1 ms
Figure 27
carrier frequency : 10 kHz – 80 MHz,
modulation frequency : 1 kHz
amplitude modulation with 80%
RFCM-Application
The 80 % amplitude modulated signal is shown in Figure 27 in the lower half. With external elements on the userPCB-board it is targeted to achieve a RFCM-robustness against the defined HF-signals of VHF_peak_peak = + 25 V.
4.5
Application Hints
4.5.1
Layout Recommendations
The reference resistor for CLKADJ must be placed close to the pin 38 CLKADJ and pin 39 GND. Decoupling
capacitors should be close to VCC terminal pin 37 and directly connected to the GND plane on the PCB.
GND and GNDBB must be totally isolated in the PCB layout. A separation distance of min. 3.2mm is
recommended.
The reference resistors for OLADJ, IADJ must be placed close to their terminals of the ISO2H823V2.5 and the
connection to the referring ground plane should be as short as possible. The capacitors for VCORE and VDDIO must
be placed close the pins and directly connected to the GNDBB plane.
Datasheet
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ISO2H823V2.5
Electrical Characteristics
5
Electrical Characteristics
Note: All voltages at pins 1 to 32 as well as 61 to 70 are measured with respect to GNDBB. All voltages at pins 33
to 60 are measured with respect to GND. The voltage levels are valid if other ratings are not violated. The
two voltage domains VCC and VBB are internally galvanic isolated.
Note: All Typical Values are defined by Tj = 25°C, VBB = 24 V, VCC= 3.3V.
Note: Electrical Values are defined in the range Tj = -40 ... 125°C, VBB = 11...35 V, VCC = 2.75...3.6 V, unless
otherwise specified, Table 13 to Table 26.
5.1
Absolute Maximum Ratings
(at Tj = -40 … 135 °C, unless otherwise specified)
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin
37 (VCC) is discharged before assembling the application circuit. Operating at absolute maximum ratings can
lead to a reduced lifetime.
Absolute maximum ratings are not subject to production test.
Table 11
Absolute Maximum Ratings
Parameter
Supply voltage input interface
Symbol
VCC
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-0.5
–
3.6
V
–
1)
Supply voltage output interface
VBB
-1
–
45
V
–
Continuous voltage at data inputs
(AD0 … AD7)
VDx
-0.5
–
3.6
V
–
Continuous voltage at pin CS
VCS
-0.5
–
3.6
V
–
Continuous voltage at pin ALE
VALE
-0.5
–
3.6
V
–
Continuous voltage at pin RD
VRD
-0.5
–
3.6
V
–
Continuous voltage at pin WR
VWR
-0.5
–
3.6
V
–
Continuous voltage at pin SYNC
VSYNC
-0.5
–
3.6
V
–
Continuous voltage at pin ODIS
VODIS
-0.5
–
3.6
V
–
Continuous voltage at pin ERR
VERR
-0.5
–
3.6
V
–
Continuous voltage at pin SEL
VSEL
-0.5
–
3.6
V
–
Continuous voltage at pin MSx
VMSx
-0.5
–
3.6
V
–
Continuous voltage at pin CLKADJ
VCLKADJ
-0.5
–
3.6
V
–
Continuous voltage at pin VCORE
VVCORE
-0.5
–
1.65
V
–
Continuous voltage at pin VDDIO
VVDDIO
-0.5
–
3.6
V
–
Continuous voltage at pin IADJ
VIADJ
-0.5
–
3.6
V
–
Continuous voltage at pin OLADJ
VOLADJ
-0.5
–
3.6
V
–
Continuous voltage at pin OUTx
VOUTx
VBB -55 –
VBB
V
–
Continuous voltage at pin LEDXx
VLEDXx
-0.5
–
VBB
V
–
Continuous voltage at pin LEDYx
VLEDYx
-0.5
–
VBB
V
–
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ISO2H823V2.5
Electrical Characteristics
Table 11
Absolute Maximum Ratings (cont’d)
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
Self
limited
A
–
mA
Peak current each LED
Load current (short-circuit current)
IL
–
LED matrix driver current
ILED
-20
20
Static operating temperature
Tj stat
-40
Internal °C
limited
Static operation
Peak junction temperature
Tj per
–
175
°C
Periodic duty cycle >Tcase
3) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest VON(CL).
4) Not subject to production test, specified by design.
Datasheet
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ISO2H823V2.5
Electrical Characteristics
5.5
Electrical Characteristics µController Interface
For the Parallel Mode see Table 17, Table 19, Table 23 and Table 25
For the Serial Mode see Table 17, Table 19, Table 24 and Table 25
Timing characteristics refer to CL < 50 pF and RL > 10 kΩ
Table 17
Setting at the Configuration Pin (CLKADJ)
Parameter
Symbol
CLKADJ Pin Regulated Voltage
Table 18
Values
VCLKADJreg
Min.
Typ.
Max.
–
0.5
–
Unit
Note /
Test Condition
V
–
Unit
Error Pins (ERR, CRCERR)
Parameter
Symbol
Values
Min.
Error Voltage (ERR, CRCERR=0) VERR_CRCERR –
Error Pin Pull-Up Resistance
(ERR, CRCERR = 1)
RERR_CRCERR –
Maximum Switching Frequency
(ERR, CRCERR)2)
fSW
Typ.
Max.
Note /
Test Condition
–
0.25 VCC V
IERR_CRCERR = 5 mA1)
50
–
kΩ
–
200
–
kHz
10 kΩ external PullUp Resistor
pu
–
1) Spikes on CRCERR due to f.e. cross coupling between SCLK and CRCERR are not expected to violate this figure
VERR_CRCERR, because cross coupling pulses are very small (10 nsec), VERR_CRCERR is evaluated after the rising edge of CS
(and not during any edges of SCLK) and with a lower IERR_CRCERR (f.e. 1 mA) VERR_CRCERR is also lowered (in the example
by a factor of 5).
2) Not subject to production test, specified by design; worst case is the reading in serial mode 2 with a frequency of 500 kHz
CRCERR can toggle with 500 kHz
Table 19
Logical Pins (RD, WR, ALE, MS0/1, CS, AD7: AD0, SCLK, SDO, SDI, SEL, SYNC, ODIS)
Parameter
Min.
Typ.
Max.
Note /
Test Condition
VIH
0.7·VVCC
–
VVCC+0.3 V
–
Input Voltage Low Level
VIL
-0.3
1)
–
0.3·VVCC
V
–
Input Voltage Hysteresis
VIhys
–
mV
–
Output Voltage High Level
VOH
0.75·VVCC –
1·VVCC
V
IOH = 5 mA2)
Output Voltage Low Level
VOL
0
–
0.25·VVCC V
IOL = 5 mA
Output Voltage High Level
VOH
-
2.65
-
VVCC = 2.75V, IOH =
VOL
-
Input Voltage High Level
Output Voltage Low Level
Symbol
Values
Unit
100
V
1mA3)
0.1
-
V
VVCC = 2.75V - 3.6V,
IOL = 1mA
1) Not subject to production test, specified by design.
2) Maximum source / sink current: IOHmax = IOLmin = 5 mA; external load CL < 50 pF, RL > 10 kΩ
3) Same argumentation as for Digital Input Isoface : typical values over temperature derived for IOH = 5 mA and IOL = 5 mA.
Extrapolation to IOH = 1mA and IOL = 1mA to possible. Voltage drop scales with a factor of 1/5 with the change of 5 mA to
1 mA. Not subject to production test.
Datasheet
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ISO2H823V2.5
Electrical Characteristics
Table 20
SYNC-Timing
Parameter
Symbol
Values
Min.
Typ.
500
Unit
Note /
Test Condition
ns
1)
Max.
Minimum time interval for µCRead-Access after falling edge of
SYNC-signal
tsyncmin
400
Minimum width of SYNC-signal
tsyncw
200
ns
1)
SYNC-period
tsyncper
500
ns
1)
Minimum time interval for DirectWrite-Access after falling edge of
SYNC-signal (to ensure that the
new data are not CT-transmitted
during SYNC = low)
th
400
ns
1)
Unit
Note /
Test Condition
us
1)
us
1)
us
1)
Unit
Note /
Test Condition
400
ns
1)
tRD_PER
Read-Period for two read
accesses on the same register
(especially for COLDIAG, GLERR,
INTERR)
2000
ns
1)
CS Disable time (CS high time
between a write access and a read tCSD_WRRD
access for reading back the written
value)
400
ns
1)
500
1) not subject of production test, specified by design
Table 21
RESYNCH-Timing
Parameter
Symbol
Values
Min.
Typ.
Max.
--
240
Minimum width of SYNC-lowphase during resynchronization
tresynch
7.0
Minimum time interval between
two resynchronization processes
(minimum width of SYNC-highphase)
tresync_gap
1.0
Timing jitter of transmission of
drive-data over CT
tresynch_jitter -0.75
--
0.75
1) not subject of production test, specified by design
Table 22
Interface Timing Parameters
Parameter
Symbol
Values
Min.
CS Disable time (CS high time
between two read accesses on
different registers)
Typ.
tCSD
Max.
1) not subject of production test, specified by design
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ISO2H823V2.5
Electrical Characteristics
Table 23
Parallel Interface
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
RPU
–
50
–
kΩ
–
Input Pull Down Resistance (ALE) RPD
–
50
–
kΩ
–
Input Pull Up Resistance
(RD, WR, CS)
CS setup time related to ALE
tCS_ALE
14
ns
ALE high duration (for
addressing)
tALE_high
200
ns
WR Low duration
(for Write Data)
tWRlow
100
ns
WR High duration
(for Write Data)
tWRhigh
100
ns
Read Request Frequency
fRD
0.0331)
–
2.5
MHz
repeated read access
during CS = 0
Read Request Period (1/fRD)
tRD
400
–
300002)
ns
repeated read access
during CS = 0
tRDlow
200
tfloat
20
RD Low duration (by Read)
AD7:AD0 Output disable time
ns
80
ns
180
ns
AD0-7 Output Valid (by Read)
tADout
RD setup time
tRD_su
50
ns
WR setup time
tWR_su
50
ns
RD hold time
tRD_hd
20
ns
WR hold time
tWR_hd
20
ns
WR latency time
tlat
3)
4)
300
ns
300
ns
RD Pad to COLDIAG, GLERR
and INTERR Registers Update
(Bits Clearing)
tclrrdy
AD0-7 Data bus setup time
tAD_su
20
ns
AD0-7 Data bus hold time
tAD_hd
60
ns
Time for CS = WR = ALE = 0, RD tdirect
= 1 until direct mode is entered
30
us
1) Minimum value to guarantee that the direct control mode is not entered, see also tRD and tdirect
2) After 30 us the interface may enter the direct control mode, see also tdirect
3) not subject to production test, tlat determined by internal synchronization cycles (internal clock 10 MHz) and propagation
over CT (5 us)
4) not subject to production test, tclrrdy determined by internal synchronization cycles (internal clock 10 MHz)
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ISO2H823V2.5
Electrical Characteristics
Table 24
Serial Interface
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Input Pull Up Resistance (CS)
RPU
–
50
–
kΩ
–
Input Pull Down Resistance
(SCLK, SDI)
RPD
–
50
–
kΩ
–
Serial Clock Frequency
fSCLK
0.06
–
6
MHz
–
Serial Clock Period (1/fSCLK)
tSCLK
166
–
–
ns
–
Serial Clock High Period
tSCLKH
83
–
–
ns
–
Serial Clock Low Period
tSCLKL
83
–
–
ns
–
CS Hold time (rising edge of SCLK tCSH
to rising edge of CS)
100
ns
Data setup time (required time SDI tSU
to rising edge of SCLK)
20
ns
Data hold time (rising edge of
SCLK to SDI)
tHD
20
ns
CS falling edge to SDO output
valid time
tCS_valid
CS falling edge to first rising
SCLK edge
tSCLK_su
SCLK falling edge to SDO output
valid time
150
200
ns
tSCLK_valid
Minimum SDO Output disable time tfloat
New serial mode activation time
(MS0/MS1 change to earliest
interface access)
ns
tMS_rdy
80
ns
90
ns
400
ns
no µController access
allowed during the
change1) (CS = 1)
Values
Unit
Note /
Test Condition
kΩ
–
µs
–
µs
ALE/RST = VCC and
CS = GND
1) not subject to production test, specified by design
Table 25
ODIS, ALE/RST Timing
Parameter
Symbol
Min.
Typ.
Max.
–
Input Pull Up Resistance
(ODIS)
RPU
–
50
Minimum width of ODIS-signal
tODISW
5
–
Minimal Duration for triggering
Reset
tRSTW
100
–
Datasheet
57
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
5.6
Diagnostics
Table 26
Channel Specific Diagnostics
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Overload threshold
ITHOCL
0.73
1
1.3
A
RIADJ = 6.81 kΩ
Active open load threshold
ITHOLA1
0.1
0.35
0.55
mA
ROLADJ = 24,3 kΩ
Active open load threshold
ITHOLA2
1.8
2.4
2.9
mA
ROLADJ = 3.48 kΩ
Active open load threshold
ITHOLA3
0.9
1.4
1.9
mA
IOLADJ = 200 µA1)
Inactive bypass current
IOLI
10.0
21
32
µA
Including switch leakage
Inactive open load voltage
VOLI
5.75
6.7
7.8
V
–
Inactive open load detection, Onthreshold
VTHOLI
5
5.4
5.75
V
–
Inactive short to VBB detection, Onthreshold
VTHSCV
8.4
9.2
10
V
take care when VVBB =
VVBBmin = 11 V for stability
of VBB (good buffering)
Overload filtering normal mode2)
tFILT_OCL
–
0.5
–
ms
for the thermal shutdown
other value 50 us
Overload filtering cold lamp mode2) tFILT_COL
–
200
–
ms
–
2)
Active open load blanking
tblank_OLA
–
6
–
ms
blanking time = filter
length, other values
100us,0.5ms, 1.0ms3)
Inactive open load blanking2)
tblank_OLI
–
6
–
ms
blanking time = filter
length, values
100us,0.5ms, 1.0ms
Inactive short to VBB blanking2)
tblank_SCV
–
6
–
ms
the blanking time for SCV
is 6 ms but the internal
filterlength is 2 ms , other
values 100us, 0.5ms,
1.0ms
LEDy matrix driver on resistance
RON_LEDy
–
–
70
Ω
Load current 10 mA, VBB
= 24V
LEDx matrix driver on resistance
RON_LEDx
–
–
30
Ω
Load current 30
mA,VBB=24V
1)
A current of 200 µA is forced out of the OLADJ Pin, this is equivalent to an nominal ROLADJ of 6 kΩ.
ROLADJ = VOLADJ / IOLADJ = 1.2 V / 200 µA
2) all timing values defined and checked by design; test in production: structural test by SCAN-pattern plus test of internal
oscillator frequency (24 MHz + 17,5 %)
3) other values 100us, 0.5ms, 1.0ms are dynamically adapted to the switching frequency of the user
Datasheet
58
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
5.7
Isolation and Safety-Related Specification
Measured from input terminals to output terminals, unless otherwise specified
Table 27
Isolation and Safety-Related Specification
Parameter
Symbol
1)
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Rated dielectric isolation voltage
VISO
2500
---
–
VAC
1 - minute duration2)
Short term temporary overvoltage
VIOTM
4250
---
–
Vpk
1s
Minimum external air gap
(clearance)
–
3.5
–
mm
Shortest distance through
air
Minimum external tracking
(creepage)
–
3.5
–
mm
Shortest distance path
along body
Minimum Internal Gap
–
0.01
–
mm
Isolation distance through
insulation
1) The dielectric withstand voltage class (Nennisolationsklasse) is : 500 V.
2) The parameter is not subject to production test, verified by characterization.
Approvals
UL508, CSA C22.2 NO. 14
Certificate Number: 20090514-E329661
5.8
Reliability
For Qualification Report please contact your local Infineon Technologies office!
Datasheet
59
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
5.9
Typical Performance Characteristics
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Ϭ͕Ϯϱ
Ϭ͕Ϯ
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[
N
O
R
Ϭ͕ϭϱ
Ϭ͕ϭ
Ϭ͕Ϭϱ
ͲϱϬ
ͲϮϱ
Ϭ
Ϯϱ
T [°C]
ϱϬ
ϳϱ
ϭϬϬ
ϭϮϱ
j
Figure 28
Typ. On-State Resistance
RON = f(Tj), IL = 0.6A, VBB = 24V, Vin = high
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Ϭ͕Ϯϳϱ
Ϭ͕Ϯϱ
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/>сϬ͘ϭ͕ϭϮϱΣ
/>сϬ͘ϲ͕ϮϱΣ
/>сϬ͘ϭ͕ϮϱΣ
/>сϬ͘ϲ͕ͲϰϬΣ
/>сϬ͘ϭ͕ͲϰϬΣ
Ϭ͕ϮϮϱ
Ϭ͕Ϯ
Ω
Ϭ͕ϭϳϱ
]
[
N
O
R
Ϭ͕ϭϱ
Ϭ͕ϭϮϱ
Ϭ͕ϭ
Ϭ͕Ϭϳϱ
Ϭ͕Ϭϱ
ϭϬ
ϭϮ
ϭϰ
ϭϲ
ϭϴ
ϮϬ
ϮϮ
Ϯϰ
Ϯϲ
Ϯϴ
ϯϬ
VBB [V]
Figure 29
Typ. On-State Resistance
RON = f(VBB), IL = 0.6 A, IL = 0.1 A, Vin = high
Datasheet
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
Ϯ
ϭ͕ϴ
ϭ͕ϲ
ϭ͕ϰ
ϭ͕Ϯ
A[
]
)
p
C
S
(
L
I
ϭ
Ϭ͕ϴ
Ϭ͕ϲ
Ϭ͕ϰ
Ϭ͕Ϯ
Ϭ
ͲϱϬ
ͲϮϱ
Ϭ
Ϯϱ
ϱϬ
ϳϱ
T [°C]
ϭϬϬ
ϭϮϱ
j
Typical Initial Peak Short Circuit Current Limit vs Tj
Figure 30
IL(SCp) = f(Tj), VBB = 24 V, output switched on with a short circuit present at the output
12
10
8
L[H]
6
4
2
0
0,100
0,200
0,300
0,400
0,500
0,600
0,700
IL[A]
Figure 31
Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated
L = f(IL), Tjstart = 125 °C, VBB = 24 V, RL = 48 Ω, all channels are switching simultaneously
Datasheet
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
9
8
7
6
L[H]
5
4
3
2
1
0
0,100
0,200
0,300
0,400
0,500
0,600
0,700
IL[A]
Figure 32
Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated
L = f(IL), Tjstart = 125 °C, VBB = 24 V, RL = 0 Ω, all channels are switching simultaneously
0,45
0,4
0,35
0,3
EAS[J]
0,25
0,2
0,15
0,1
0,05
0
0,100
0,200
0,300
0,400
0,500
0,600
0,700
IL[A]
Figure 33
Maximum Allowable Inductive Switch Off Energy, Single Pulse for Each Channel
EAS = f(IL), Tjstart = 125 °C, VBB = 24 V, all channels are switching simultaneously
Single pulse means that the thermal recovery time is sufficient so that an increase of the chip temperature is
avoided or at least limited (depends on the thermal connection of chip with PCB-board, Figure 34 -Figure 36) .
Datasheet
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
10
10
2
1
D = 0.5
]
W
/
K[
10
jAht
Z
D = 0.2
D = 0.1
0
D = 0.05
D = 0.02
D = 0.01
D=0
10
-1
10
-2
10
-6
10
-5
10
-4
10
-3
10
10
-2
-1
10
0
10
1
10
2
10
3
10
4
tp [sec]
Figure 34
Typ. Transient Thermal Impedance 1s0p
ZthJA = f(tp) , Parameter: D = tp/T
Product simulated on a 76.2 x 114.3 x 1.5 mm 1s0p board according JEDEC JESD 51-3.
10
10
2
1
D = 0.5
]
/W
K[
10
jAht
Z
D = 0.2
D = 0.1
0
D = 0.05
D = 0.02
D = 0.01
D=0
10
-1
10
-2
10
-6
10
-5
10
-4
10
-3
10
10
-2
-1
10
0
10
1
10
2
10
3
10
4
tp [sec]
Figure 35
Typ. Transient Thermal Impedance 2s2p no vias
ZthJA = f(tp) , Parameter: D = tp/T
Product simulated on a 76.2 x 114.3 x 1.5 mm 2s2p board without thermal vias used in the exposed pad area
according JEDEC JESD 51-5,7.
Datasheet
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ISOFACE™
ISO2H823V2.5
Electrical Characteristics
10
10
2
1
D = 0.5
]
/W
K[
10
jAht
Z
D = 0.2
D = 0.1
0
D = 0.05
D = 0.02
D = 0.01
D=0
10
-1
10
-2
10
-6
10
-5
10
-4
10
-3
10
10
-2
-1
10
0
10
1
10
2
10
3
10
4
tp [sec]
Figure 36
Typ. Transient Thermal Impedance 2s2p
ZthJA = f(tp), Parameter: D = tp/T
Product simulated on a 76.2 x 114.3 x 1.5 mm 2s2p board with thermal vias connected to the first inner copper
layer in the exposed pad area according JEDEC JESD 51-5,7.
Datasheet
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ISOFACE™
ISO2H823V2.5
µController Interface Registers
6
µController Interface Registers
This section presents the user registers.
Access Conventions
Table 28
Register Access Definition
Type
Symbol
Description
Read
r
The bit can be read
Read only, updated by hardware
h
The bit is updated by the device itself (for instance: sticky bit)
Write
w
The bit can be written
Presentation
The User Registers are 8-bit wide and can be accessed over either the serial or the parallel interface. The
Table 29 lists the registers of the chip. The address is 8-bit whereby the MSB is used to indicate whether it is a
write access (MSB=1) or Read access (MSB=0). The address is even i.e. the LSB is ignored (for addressing). The
default selected register is the DRIVE register for write access.
Table 29
Register Overview
Register Short Name
Register Long Name
Offset Address
Page Number
µController Interface Registers, User Registers
DRIVE
Output Driver Register (rw)
00H
66
DRIVE_RESYNCH
Output Driver Register for Resynchronization (rw) 1CH
66
COLDIAG
Collective Diagnostics Register (rh)
02H
69
GLERR
Global Error Register (rh)
04H
71
DIAGCFG
Channel Diagnostics Configuration Register (rw)
06H
72
DIAG0
Diagnostics Register for Channel-0 (rh)
08H
74
DIAG1
Diagnostics Register for Channel-1 (rh)
0AH
75
DIAG2
Diagnostics Register for Channel-2 (rh)
0CH
75
DIAG3
Diagnostics Register for Channel-3 (rh)
0EH
75
DIAG4
Diagnostics Register for Channel-4 (rh)
10H
75
DIAG5
Diagnostics Register for Channel-5 (rh)
12H
75
DIAG6
Diagnostics Register for Channel-6 (rh)
14H
75
DIAG7
Diagnostics Register for Channel-7 (rh)
16H
75
INTERR
Internal Error Register (rh)
18H
76
GLCFG
Global Configuration Register (rwh)
1AH
78
The registers are addressed wordwise.
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ISO2H823V2.5
µController Interface Registers
6.1
User Registers
These registers can be accessed via the serial or parallel interface. The default selected register is the DRIVE
register for write access.
Update of the Diagnostics Registers
The different faults monitored at each output channel are filtered with blanking time units. They are then stored in
registers and sent over the Coreless Transformer to the µController-Interface chip with an update rate of 35 µs.
On the µController-Interface side, the diagnostics are stored in an intermediate register bank to be processed as
sticky bits: once a fault is detected (and received) the corresponding bit is set and remains set even if the fault
disappears. The bit can only be cleared once the fault is not detected anymore and a clear was requested by a
serial or parallel access (see Figure 37).
Original
diagnostic
Clear
strobe
Sticky bit
Registers - sticky_bit_def
Figure 37
Sticky Bit Operation
Output Driver Register
This register contains the command for the 8 output channels. When the pin ODIS is High, the output channels
are controlled as set by this register. When the ODIS is Low, the output channels are immediately turned off and
the contents of the DRIVE register is cleared.
DRIVE
Offset
Output Driver Register (rw)
Reset Value
00H
00H
7
6
5
4
3
2
1
0
SW7
SW6
SW5
SW4
SW3
SW2
SW1
SW0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
SW7
7
rw
Output Driver Control for Channel 7
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
SW6
6
rw
Output Driver Control for Channel 6
This bit field controls the state of the output driver.
The channel output is inactive.
0B
1B
The channel output is driven.
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ISO2H823V2.5
µController Interface Registers
Field
Bits
Type
Description
SW5
5
rw
Output Driver Control for Channel 5
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
SW4
4
rw
Output Driver Control for Channel 4
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
SW3
3
rw
Output Driver Control for Channel 3
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
SW2
2
rw
Output Driver Control for Channel 2
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
SW1
1
rw
Output Driver Control for Channel 1
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
SW0
0
rw
Output Driver Control for Channel 0
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
Output Driver Register for Resynchronization
This register contains the command for the 8 output channels for resynchronization. It has to be written in case a
resynchronization of the CT-transmission is desired. Then the contents of DRIVE_RESYNCH is used for the CTtransmission instead of the contents of DRIVE.
DRIVE_RESYNCH
Offset
Output Driver Register (rw)
Reset Value
00H
1CH
7
6
5
4
3
2
1
0
RW7
RW6
RW5
RW4
RW3
RW2
RW1
RW0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
RW7
7
rw
Output Driver Resynchronization Control for Channel 7
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
Datasheet
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ISOFACE™
ISO2H823V2.5
µController Interface Registers
Field
Bits
Type
Description
RW6
6
rw
Output Driver Resynchronization Control for Channel 6
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
RW5
5
rw
Output Driver Resynchronization Control for Channel 5
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
RW4
4
rw
Output Driver Resynchronization Control for Channel 4
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
RW3
3
rw
Output Driver Resynchronization Control for Channel 3
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
RW2
2
rw
Output Driver Resynchronization Control for Channel 2
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
RW1
1
rw
Output Driver Resynchronization Control for Channel 1
This bit field controls the state of the output driver.
0B
The channel output is inactive.
1B
The channel output is driven.
RW0
0
rw
Output Driver Resynchronization Control for Channel 0
This bit field controls the state of the output driver.
0B
The channel output is inactive.
The channel output is driven.
1B
Datasheet
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µController Interface Registers
Collective Diagnostics Register
This register contains the overall diagnostics for each of the 8 output channels. Each channel-bit corresponds to
the OR-combination of the SCVx, OCLx, OLIx, OLAx and OTx-bits of the enabled diagnostic function. This
register contains the state of the channel diagnostics. On read access the internal diagnostics data is cleared and
the DIAG0,...,DIAG7 registers are updated (see Update of the Diagnostics Registers). In serial modes 0 and 1
the update of the DIAG0,...,DIAG7 is generated automatically after every access whereas in serial modes 2 and
3 as well as in parallel mode the DIAG0,...,DIAG7 registers are updated after each direct access to the COLDIAG
register.
COLDIAG
Offset
Collective Diagnostics Register (rh)
Reset Value
02H
00H
7
6
5
4
3
2
1
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
CH7
7
rh
Overall Diagnostics for Channel 7
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
CH6
6
rh
Overall Diagnostics for Channel 6
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
CH5
5
rh
Overall Diagnostics for Channel 5
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
CH4
4
rh
Overall Diagnostics for Channel 4
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
CH3
3
rh
Overall Diagnostics for Channel 3
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
CH2
2
rh
Overall Diagnostics for Channel 2
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
CH1
1
rh
Overall Diagnostics for Channel 1
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
Datasheet
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ISO2H823V2.5
µController Interface Registers
Field
Bits
Type
Description
CH0
0
rh
Overall Diagnostics for Channel 0
This bit field indicates the overall diagnostics.
0B
No fault is detected.
1B
At least one failure is detected.
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ISO2H823V2.5
µController Interface Registers
Global Error Register
This register contains the overall status of the IC parameters monitored during system operation. The bits are
routed to the ERR pin as well (see Table 3). The UV and MV bits are reset to High during UVLO. In some operation
modes, the register needs to be read to clear these bits and release the ERR pin (see “Update of GLERR,
INTERR-Reg”). The CF-bit is the OR-combination of COLDIAG bits.
GLERR
Offset
Global Error Register (rh)
Reset Value
04H
16H
7
6
5
4
3
2
1
0
Vers_3
Vers_2
Vers_1
Vers_0
RES
UV
MV
CF
r
r
r
r
r
rh
rh
rh
Field
Bits
Type
Description
Vers_3
7
r
Actual :”0”
Vers_2
6
r
Actual :”1”
Vers_1
5
r
Actual :”0”
Vers_0
4
r
Actual :”0”
RES
3
r
Reserved
Returns 0 when read.
UV
2
rh
VBB Undervoltage
This bit field indicates if an undervoltage condition has been detected at VBB.
0B
No undervoltage detected.
Undervoltage detected.
1B
MV
1
rh
VBB Missingvoltage
This bit field indicates if a missingvoltage condition has been detected at VBB.
0B
No missingvoltage detected.
1B
Missingvoltage detected.
CF
0
rh
Common Diagnostics Fault
This bit field is the OR-combination of all bits of the COLDIAG register.
0B
No fault is detected.
At least one failure is detected.
1B
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ISO2H823V2.5
µController Interface Registers
Channel Diagnostics Configuration Register
This register enables the diagnostics for each channel and selects whether the channel collective diagnostic bit is
updated in the COLDIAG register (and as a consequence in the CF-bit field of the GLERR register and at the ERR
pin).
DIAGCFG
Offset
Channel Diagnostics Configuration Register
(rw)
Reset Value
FFH
06H
7
6
5
4
3
2
1
0
DIAGEN7
DIAGEN6
DIAGEN5
DIAGEN4
DIAGEN3
DIAGEN2
DIAGEN1
DIAGEN0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
DIAGEN7
7
rw
Enables Diagnostics for Channel 7
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
DIAGEN6
6
rw
Enables Diagnostics for Channel 6
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
DIAGEN5
5
rw
Enables Diagnostics for Channel 5
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
DIAGEN4
4
rw
Enables Diagnostics for Channel 4
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
DIAGEN3
3
rw
Enables Diagnostics for Channel 3
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
DIAGEN2
2
rw
Enables Diagnostics for Channel 2
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
DIAGEN1
1
rw
Enables Diagnostics for Channel 1
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
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ISO2H823V2.5
µController Interface Registers
Field
Bits
Type
Description
DIAGEN0
0
rw
Enables Diagnostics for Channel 0
This bit field enables all the channel diagnostics.
0B
All the channel diagnostics are disabled.
1B
The channel diagnostics are enabled and updated in the COLDIAG register.
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ISO2H823V2.5
µController Interface Registers
Diagnostics Registers for Channel-x
These registers contain the individual diagnostics bits. The bit field LEDGx is not used in the COLDIAG register
(and as a consequence in the CF-bit and at the ERR pin). All bits are sticky (see Update of the Diagnostics
Registers). The diagnostics are enabled with the DIAGCFG register.
DIAG0
Offset
Diagnostics Register for Channel-0 (rh)
Reset Value
08H
00H
7
6
5
4
3
2
1
0
RES
RES
LEDGx
SCVx
OCLx
OLAx
OLIx
OTx
r
r
rh
rh
rh
rh
rh
rh
Field
Bits
Type
Description
RES
7
r
Reserved
returns 0 if read.
RES
6
r
Reserved
returns 0 if read.
rh
Gated LED Drive Information of Channel x (Active Mode only)
This bit field indicates that the led of this channel is gated due to overcurrent or
over-temperature conditions.
0 : led not gated
1 : led gated
LEDGx
5
SCVx
4
rh
Short Circuit to VBB at Channel x (Inactive Mode only)
This bit field indicates that a short circuit to VBB has been detected.
0B
No short circuit to VBB detected.
1B
A short circuit to VBB has been detected.
OCLx
3
rh
Overcurrent at Channel x (Active Mode only)
This bit field indicates that an overload condition has been detected and that the
current is being limited.
0B
No overcurrent detected.
1B
An overcurrent has been detected and limited.
OLAx
2
rh
Open Load / Wire Break at Channel x (Active Mode)
This bit field indicates that an open load condition has been detected.
0B
No open load detected.
1B
An open load condition has been detected.
OLIx
1
rh
Open Load / Wire Break at Channel x (Inactive Mode)
This bit field indicates that an open load condition has been detected.
0B
No open load detected.
1B
An open load condition has been detected.
OTx
0
rh
Over-temperature at Channel x (Active Mode Only)
This bit field indicates that an over-temperature condition has been detected.
0B
No over-temperature detected.
1B
An over-temperature has been detected.
Datasheet
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ISOFACE™
ISO2H823V2.5
µController Interface Registers
Other Channel Diagnostics Registers
The other channel diagnostics registers in the table below have the same layout as DIAG0.
Their names and offset addresses are listed below:
Table 30
Diagnostics Registers for Channel 1-7
Register Short Name
Register Long Name
Offset Address
Reset Value
DIAG1
Diagnostics Register for Channel-1 (rh)
0AH
00H
DIAG2
Diagnostics Register for Channel-2 (rh)
0CH
00H
DIAG3
Diagnostics Register for Channel-3 (rh)
0EH
00H
DIAG4
Diagnostics Register for Channel-4 (rh)
10H
00H
DIAG5
Diagnostics Register for Channel-5 (rh)
12H
00H
DIAG6
Diagnostics Register for Channel-6 (rh)
14H
00H
DIAG7
Diagnostics Register for Channel-7 (rh)
16H
00H
Datasheet
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Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
µController Interface Registers
Internal Error Register
This register contains the status of internal errors monitored for safe IC operation. The TE, W4P, ALLOFF bits are
sticky and routed out to the ERR pin (according to the Table 3). The bits OTP and LAMP are volatile i.e. are
updated every 35 µs. Sticky bits are cleared every time the INTERR register is accessed or by every serial access
in mode 0 and 1.
INTERR
Offset
Internal Error Register (rh)
Reset Value
18H
07H
7
6
5
4
3
2
1
0
RES
OTC
RES
OTP
LAMP
ALLOFF
W4P
TE
r
rh
r
rh
rh
rh
rh
rh
Field
Bits
Type
Description
RES
7
r
Reserved
returns 0 if read.
OTC
6
rh
Overtemperature Common (Volatile)
This bit field indicates that an overtemperature or overcurrent condition of at least
one of the channels has been detected. Ored LEDGx-values.
0B
No overtemperature or overcurrent has been detected.
1B
An overtemperature or overcurrent condition has been detected.
RES
5
r
Reserved
returns 0 if read.
OTP
4
rh
Overtemperature Package (Volatile)
This bit field indicates that an overtemperature of the package has been detected.
0B
No package overtemperature detected.
1B
An overtemperature in the package has been detected.
LAMP
3
rh
Cold Lamp Detected (Volatile)
This bit field indicates that at least a cold lamp behaviour has been detected at one
output channel.
0B
No cold lamp behaviour detected.
At least one load at the output channels behaves as a cold lamp.
1B
ALLOFF
2
rh
All Outputs Channels are Switched Off (Sticky)
This bit field indicates that all the output channels have been switched off due to
an internal error, an over-temperature, the ODIS pin or the data of the DRIVE
(feedback from Power Chip).
0B
The ouput channels are enabled and controlled by the DRIVE register.
1B
The ouptut channels are switched off.
W4P
1
rh
Wait for Power Chip (Sticky)
This bit field indicates that the Power Chip is correctly supplied and ready for
operation.
0B
Power Chip is ready.
1B
Power Chip is not ready because of insufficient voltage or long transmission
error.
Datasheet
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Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
µController Interface Registers
Field
Bits
Type
Description
TE
0
rh
Transmission Error (Sticky)
This bit field indicates a transmission error over the galvanic isolation detected
either from the Process Side or from the µController-Interface
0B
No transmission error is detected.
1B
Transmission error has occured.
Datasheet
77
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
µController Interface Registers
Global Configuration Register
This register configures some extended functionalities of the chip.
GLCFG
Offset
Global Configuration Register (rwh)
Reset Value
1AH
00H
7
6
5
4
3
2
1
0
FRZSC
RESYN
RSTOFF
LEDON
RES
LEDGOFF
OLOFF
SWRST
rw
rw
rw
rw
rw
rw
rw
rwh
Field
Bits
Type
Description
FRZSC
7
rw
Selection of Isochronous Mode for Diagnostics
This bit field enables the isochronous mode for diagnostics. The entry is totally
ignored when RESYN = 1.
0B
Diagnostics are treated independently of SYNC-level
1B
Diagnostics are frozen with falling edge of SYNC and released with rising
edge. During SYNC = 0 DIAG0,..,DIAG7 and COLDIAG are not updated. But
read bits in COLDIAG can be reset.
RESYN
6
rw
Resynchronization of CT-Transmission
This bit field enables the resychronization of CT-transmission.
0B
functionality of SYNC is as defined by bit FRZSC.
1B
SYNC-pin is used for resynchronization of CT-transmission
Note: It is not possible to select RESYN = 1 and to use isochronous mode
for drive signals or/and diagnostics at the same time. That means
resynchronization and isochronous mode of driver information and
diagnostics at the same time is not possible. Edges on SYNC are used
solely for resynchronization. In the following the driver information can
be only transferred when SYNC = 1 when RESYN is set to “1”. A
negative pulse on SYNC initializes the resynchronization.
RSTOFF
5
rw
HW Reset of ALE Pin Disabled
This bit field disables the external reset.
0B
The HW reset at the ALE pin is enabled (default).
The HW reset is disabled.
1B
LEDON
4
rw
LED Matrix Enabled
This bit field enables the LED Matrix in serial mode. In this case the HW reset
cannot be used (activation of HW Reset is ignored).
0B
The LED matrix is disabled (default).
1B
The LED matrix is enabled in serial mode.
RES
3
rw
Reserved
Must be set to “0”
LEDGOFF
2
rw
LEDG Report Disabled
This bit field disables the report of the LEDGx-information.
0B
The LEDGx diagnostic is enabled (default).
1B
The LEDGx diagnostic is disabled and not reported in the DIAG0,..,DIAG7
registers.
Datasheet
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Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
µController Interface Registers
Field
Bits
Type
Description
OLOFF
1
rw
Open-Load Diagnostic Disabled
This bit field disables the monitoring of the Open-Load diagnostic OLAx and OLIx.
0B
The Open-Load diagnostic is enabled and updated in the DIAG0,..,DIAG7
registers (default).
1B
The Open-Load diagnostic is disabled and do not appear in the
DIAG0,..,DIAG7 registers.
SWRST
0
rwh
Soft Reset
This bit field triggers the clear of the user registers and restarts the CT
transmission. After setting the soft reset, this bit field will clear itself.
0B
No reset is generated.
1B
A clear of the user registers is generated.
Datasheet
79
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Package : Outlines and Marking Pattern
7
Package : Outlines and Marking Pattern
Figure 38
PG-VQFN-70-2 (Plastic (Green) Very Thin Profile Quad Flat Non Leaded Package)
Datasheet
80
Revision 2.0, 2015-02-12
ISOFACE™
ISO2H823V2.5
Package : Outlines and Marking Pattern
Information of Marking Pattern:
Infineon
ISOFACE TM
ISO2H823V2.5
Lotnumber
Datecode
Figure 39
Marking Pattern
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Datasheet
81
Dimensions in mm
Revision 2.0, 2015-02-12
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