ITS4060SSJNXUMA1

Smart high-side NMOS-power switch ITS4060S-SJ-N Features • CMOS compatible input • Switching all types of resistive, inductive and capacitive loads • Fast demagnetization of inductive loads • Very low standby current • Optimized Electromagnetic Compatibility (EMC) • Overload protection • Current limitation • Short circuit protection • Thermal shutdown with restart • Overvoltage protection (including load dump) • Reverse battery protection with external resistor • Loss of GND and loss of Vbb protection • Electrostatic Discharge Protection (ESD) • Green Product (RoHS compliant) Applications • All types of resistive, inductive and capacitive loads • Power switch for 12V and 24V DC applications with CMOS compatible control interface • Driver for electromagnetic relays • Power management for high-side-switching with low current consumption in OFF-mode Product validation Qualified for industrial applications according to the relevant tests of JEDEC. Description The ITS4060S-SJ-N is a protected single channel smart high-side NMOS power switch in a PG-DSO-8 package with charge pump and CMOS compatible input. The device is monolithically integrated in Smart technology. Data Sheet www.infineon.com/industrial-profets 1 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Table 1 Product summary Parameter Symbol Values Overvoltage protection VSAZmin 41 V Operating voltage range VS 5 < VS < 34V On-state resistance RDSON typ. 50 mΩ Nominal load current IL(nom) 2.6 A Operating temperature range Tj -40°C to 125°C Stand-by current ISSTB 15 µA Type Package Marking ITS4060S-SJ-N PG-DSO-8 I060SN Data Sheet 2 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Table of Contents 1 Block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.3 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Typical performance graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 6.1 6.2 6.3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Sheet 3 6 6 7 7 15 16 17 18 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Block diagram and terms 1 Block diagram and terms ITS4060S-SJ-N VS 5 6 Bias Supervision Overvoltage Protection Current Limiter 7 8 IN NC 2 Gate Control Circuit Logic ESD Protection 4 Temperature Sensor OUT 3 1 GND Figure 1 Block diagram Voltage- and Current-Definitions: Switching Times and Slew Rate Definitions: VIN H ITS4060S-SJ-N 5 IS 6 IN I IN Current Limiter Logic 8 70% VDS SROFF 40% 30% SRON 10% 4 3 OUT IOUT IL GND tON t tOFF IL RL 1 0 VS Temperature Sensor V O UT V ST +VS 90% Gate Control Circuit ESD Protection t 7 V IN NC 2 Overvoltage Protection VOUT V FD S Bias Supervision L VS 0 OFF ON OFF t GND Figure 2 Data Sheet Terms - parameter definition 4 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Pin configuration 2 Pin configuration 2.1 Pin assignment GND 1 8 VS IN 2 7 VS OUT 3 6 VS NC 4 5 VS P-DSO-8 Figure 3 Pin configuration top view, PG-DSO-8 2.2 Pin definitions and functions Pin Symbol Function 1 GND Logic ground 2 IN Input, controls the power switch; the powerswitch is ON when high 3 OUT Output to the load 4 NC Not connected 5, 6, 7, 8 VS Supply voltage (design the wiring for the maximum short circuit current and also for low thermal resistance) Data Sheet 5 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N General product characteristics 3 General product characteristics 3.1 Absolute maximum ratings Table 2 Absolute maximum ratings 1) at Tj = 25°C unless otherwise specified. Currents flowing into the device unless otherwise specified in chapter “Block Diagram and Terms” Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Supply voltage VS Voltage VS – – 40 V – 4.1.1 Voltage for short circuit protection VSSC – – 36 V -40°C < Tj < 150°C 4.1.2 IOUT – – self A limited – 4.1.3 Voltage VIN -10 – 16 V – 4.1.4 Current IIN -5 – 5 mA – 4.1.5 Junction temperature Tj -40 – 125 °C – 4.1.6 Storage temperature Tstg -55 – 125 °C – 4.1.7 P tot – – 1.5 W – 4.1.8 EAS – – 900 mJ single pulse 4.1.9 ESD susceptibility (input pin IN) VESD -1 – 1 kV HBM4) 4.1.10 ESD susceptibility (output pin OUT) VESD -6 – 6 kV HBM4) 4.1.12 kV 4) 4.1.11 Output stage OUT Output current; (short circuit current see electrical characteristics) Input IN Temperatures Power dissipation Ta = 25 °C2) Inductive load switch-off energy dissipation Tj = 125 °C; VS=13.5V; IL= 1.5A3) ESD Susceptibility ESD susceptibility (all other pins) VESD -4 – 4 HBM 1) Not subject to production test, specified by design 2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70mm thick) copper area for Vbb connection. PCB is vertical without blown air 3) Not subject to production test, specified by design 4) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) Note: Data Sheet Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” the normal operating range. Protection functions are neither designed for continuous nor repetitive operation. 6 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N General product characteristics 3.2 Functional range Table 3 Functional range Parameter Symbol Nominal operating voltage VS Values Min. Typ. Max. 5 – 34 Unit Note or Test Condition Number V VS increasing 4.2.1 Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 3.3 Thermal resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 4 Thermal resistance1) Parameter Number Min. Unit Note or Test Condition Typ. Max. – 26.7 K/W – 4.3.1 Thermal resistance - junction to RthJA_1s0p ambient - 1s0p, minimal footprint – 140.1 – K/W 2) 4.3.2 Thermal resistance - junction to RthJA_1s0p_300mm ambient - 1s0p, 300mm2 – 85.8 – K/W 3) 4.3.3 Thermal resistance - junction to RthJA_1s0p_600mm ambient - 1s0p, 600mm2 – 74.7 – K/W 4) 4.3.4 Thermal resistance - junction to RthJA_2s2p ambient - 2s2p – 78.2 – K/W 5) 4.3.5 Thermal resistance - junction to RthJA_2s2p ambient with thermal vias - 2s2p – 76.6 – K/W 6) 4.3.6 Thermal resistance - unction to pin5 Symbol Rthj-pin5 Values – 1) Not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, footprint; the product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu. 3) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, Cu, 300mm2; the product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu. 4) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, 600mm2; the product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu. 5) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). 6)Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board with two thermal vias; the product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu. The diameter of the two vias are equal 0.3mm and have a plating of 25um with a copper heatsink area of 3mm x 2mm). JEDEC51-7: The two plated-through hole vias should have a solder land of no less than 1.25 mm diameter with a drill hole of no less than 0.85 mm diameter. Data Sheet 7 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Electrical characteristics 4 Electrical characteristics Table 5 VS=13.5V; Tj = -40°C to 125°C; all voltages with respect to ground. Currents flowing into the device unless otherwise specified in chapter “Block diagram and terms”. Typical values at Vs = 13.5V, Tj = 25°C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Powerstage NMOS ON resistance RDSON – 50 60 mΩ IOUT= 2A;Tj = 25°C; 9V < VS < 34V; VIN= 5V 5.0.1 NMOS ON resistance RDSON – 95 120 mΩ IOUT= 2A;Tj = 125°C; 9V < VS < 34V; VIN= 5V 5.0.2 Nominal load current; device on PCB 1) ILNOM 2.6 3.1 – A Tpin5 = 85°C 5.0.3 Turn ON time (to 90% of Vout); L to H transition of VIN tON – 90 180 µs VS=13.5V; RL = 47Ω 5.0.4 Turn OFF time (to 10% of Vout); H to L transition of VIN tOFF – 110 230 µs VS=13.5V; RL = 47Ω 5.0.5 ON-slew rate; ∆VOUT / ∆t (10 to 30% of Vout); L to H transition of VIN SRON – 0.7 1.5 V / µs VS=13.5V; RL = 47Ω 5.0.6 OFF-slew rate; ∆VOUT / ∆t (70 to 40% of Vout); H to L transition of VIN SROFF – 0.7 1.5 V / µs VS=13.5V; RL = 47Ω 5.0.7 Timings of power stages2) Under voltage lockout (charge pump start-stop-restart) Supply undervoltage; charge pump stop voltage VSUV – – 5.5 V VS decreasing 5.0.8 Supply startup voltage; Charge pump restart voltage VSSU – 4.0 5.5 V VS increasing 5.0.9 Operating current IGND – 0.8 1.5 mA VIN= 5V 5.0.10 Standby current ISSTB – – 10 µA VIN= 0V; VOUT= 0V -40°C < Tj < 85°C 5.0.11 Standby current ISSTB – – 15 µA VIN= 0V; VOUT= 0V Tj = 125°C 5.0.12 IOUTLK – – 5 µA VIN= 0V; VOUT= 0V 5.0.13 ILSCP – – 28 A Tj = -40°C; VS = 20V VIN = 5.0V; tm =150µs 5.0.14 Current consumption Output leakage current Protection functions 3) Initial peak short circuit current limit Data Sheet 8 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Electrical characteristics Table 5 VS=13.5V; Tj = -40°C to 125°C; all voltages with respect to ground. Currents flowing into the device unless otherwise specified in chapter “Block diagram and terms”. Typical values at Vs = 13.5V, Tj = 25°C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Initial peak short circuit current limit ILSCP – 17 – A Tj = 25°C; VS = 20V VIN = 5.0V; tm =150µs 5.0.15 Initial peak short circuit current limit ILSCP 9 – – A Tj =125°C; VS = 20V VIN = 5.0V; tm =150µs 5.0.16 ILSCR Repetitive short circuit current limit Tj = TjTrip ; see timing diagrams – 12 – A VIN = 5.0V 5.0.17 Output clamp at VOUT = VS - VDSCL (inductive load switch off) VDSCL 41 47 – V IS = 4mA 5.0.18 Overvoltage protection VOUT = VS - VONCL VSAZ 41 – – V IS = 4mA 5.0.19 Thermal overload trip temperature TjTrip 150 – – °C – 5.0.20 Thermal hysteresis THYS – 10 – K – 5.0.21 Continuous reverse battery voltage VSREV - 32 – – V – 5.0.22 Forward voltage of the drainsource reverse diode VFDS – 600 – mV IFDS = 200mA; VIN= 0V; Tj = 125°C 5.0.23 Input turn-ON voltage (logic input high-level) VINON 2.2 – – V – 5.0.24 Input turn-OFF voltage (logic input low-level) VINOFF – – 0.8 V – 5.0.25 Input threshold hysteresis VINHYS – 0.3 – V – 5.0.26 Off state input current IINOFF 1 – 30 µA VIN = 0.7V 5.0.27 On state input current IINON 1 – 30 µA VIN = 5.0V 5.0.28 Input resistance RIN 1.5 3.5 5.0 kΩ – 5.0.29 4) Reverse battery Input interface; pin IN 1) Device on 50mm x 50mm x 1,5mm epoxy FR4 PCB with 6cm2 (one layer copper 70um thick) copper area for supply voltage connection. PCB in vertical position without blown air. 2) Timing values only with high slewrate input signal; otherwise slower. 3) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4) Requires a 150 Ω resistor in GND connection. The reverse load current trough the intrinsic drain-source diode of the power-MOS has to be limited by the connected load. Power dissipation is higher compared to normal operation due to the voltage drop across the drain-source diode. The temperature protection is not functional during reverse current operation! Input current has to be limited (see max ratings). Data Sheet 9 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Typical performance graphs 5 Typical performance graphs Typical characteristics Transient thermal impedance ZthJA versus pulse time tp @ 6cm2 heatsink area Transient thermal impedance ZthJA versus pulse time tp @ min. footprint D = tp / T D = tp / T On-resistance RDSONversus junction temperature Tj On-resistance RDSONversus supply voltage VS 120 70 60 100 80 RDSON [mΩ] RDSON [mΩ] 50 40 30 60 40 20 Tj=−40°C;IL=0.5A 20 10 Tj=25°C;IL=0.5A Vs=13.5V 0 −40 −25 Data Sheet 0 Tj=125°C;IL=0.5A 25 50 Tj [°C] 75 100 0 125 10 10 15 20 25 Vs[V] 30 35 40 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Typical performance graphs Typical characteristics Switch ON time tON versus junction temperature Tj Switch OFF time tOFF versus junction temperature Tj 140 180 160 120 140 100 120 tON [μs] tOFF [μs] 80 60 100 80 60 40 40 Vs=9V;RL=47Ω 20 20 Vs=13.5V;RL=47Ω Vs=9V;RL=47Ω Vs=32V;RL=47Ω 0 −40 −25 0 25 50 Tj[°C] 75 100 Vs=32V;RL=47Ω 0 −40 −25 125 ON slewrate SRON versus junction temperature Tj 0 25 50 Tj[°C] 1.8 Vs=9V;RL=47Ω 1.8 Vs=13.5V;RL=47Ω Vs=32V;RL=47Ω 1.6 1.4 1.4 1.2 1.2 1 0.8 0.6 0.6 0.4 0.4 0.2 0.2 25 50 Tj[°C] 75 100 Vs=32V;RL=47Ω 1 0.8 0 Vs=13.5V;RL=47Ω 1.6 −dV V [ ] dtoff μs dV V [ ] dton μs 125 2 Vs=9V;RL=47Ω Data Sheet 100 OFF slewrate SROFF versus junction temperature Tj 2 0 −40 −25 75 0 −40 −25 125 11 0 25 50 Tj[°C] 75 100 125 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Typical performance graphs Typical characteristics Output leakage current IOUTLK versus junction temperature Tj Standby current ISSTB versus junction temperature Tj 6 2.5 VIN=0V;Vs=32V 5 2 IOUTLK [μA] ISSTB [μA] 4 3 1.5 1 2 0.5 1 VIN=0V;Vs=32V 0 −40 −25 0 25 50 Tj [°C] 75 100 0 −40 −25 125 Initial peak short circuit current limit ILSCP versus junction temperature Tj 0 25 50 Tj [°C] 75 100 125 Initial short circuit shutdown time tSCOFF versus junction temperature Tj 25 3 2.5 20 2 ILSCP [A] tSCOFF [ms] 15 1.5 10 1 5 0.5 Vs=20V 0 −40 −25 Data Sheet 0 25 50 Tj [°C] 75 100 Vs=20V 0 −40 −25 125 12 0 25 50 Tj[°C] 75 100 125 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Typical performance graphs Typical characteristics Input current consumption IIN versus junction temperature Tj Input current consumption IIN versus input voltage VIN 12 200 Tj=−40..25°C;Vs=13.5V 180 Tj=125°C;Vs=13.5V 10 160 140 8 IIN [μA] IIN [μA] 120 6 100 80 4 60 40 2 VIN≤0.7V;Vs=13.5V 20 VIN=5V;Vs=13.5V 0 −40 −25 0 25 50 Tj [°C] 75 100 Input threshold voltage VINH,L versus junction temperature Tj 2 2 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1 2 4 VIN[V] 6 0.8 0.6 0.6 0.4 0.4 OFF;Vs=13.5V OFF;Tj=25°C 0.2 ON;Vs=13.5V 0 −40 −25 Data Sheet 0 25 50 Tj [°C] 75 100 8 1 0.8 0.2 0 Input threshold voltage VINH,L versus supply voltage VS VIN [V] VIN [V] 0 125 ON;Tj=25°C 0 125 10 15 20 25 30 35 Vs[V] 13 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Typical performance graphs Typical characteristics Max. allowable inductive single pulse switch-off energy EAS versus load current IL Max. allowable load inductance L versus load current IL 2000 1400 Tjstart=125°C;Vs=13.5V;RL=0Ω 1800 Tjstart=125°C;Vs=13.5V 1200 1600 1000 1400 EAS [mJ] L [mH] 1200 1000 800 600 800 600 400 400 200 200 0 1 Data Sheet 1.5 2 IL [A] 2.5 0 3 14 1 1.5 2 IL [A] 2.5 3 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Application information 6 Application information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. ITS4060S-SJ-N 5 Wire Harness VS 6 Bias Supervision Overvoltage Protection Current Limiter 7 8 IN NC 2 220nF Gate Control Circuit Logic ESD Protection 4 GND3 CS Temperature Sensor 3 Wire Harness OUT COUT 1 Complex LOAD 1nF GND GND1 Electronic Control Unit Figure 4 GND2 Application diagram The ITS4060S-SJ-N can be connected directly to a supply network. It is recommended to place a ceramic capacitor (e.g. CS = 220nF) between supply and GND of the ECU to avoid line disturbances. Wire harness inductors/resistors are sketched in the application circuit above. The complex load (resistive, capacitive or inductive) must be connected to the output pin OUT. A built-in current limit protects the device against destruction. The ITS4060S-SJ-N can be switched on and off with standard logic ground related logic signal at pin IN. In standby mode (IN=L) the ITS4060S-SJ-N is deactivated with very low current consumption. The output voltage slope is controlled during on and off transition to minimize emissions. Only a small ceramic capacitor COUT=1nF is recommended to attenuate RF noise. In the following chapters the main features, some typical waverforms and the protection behavior of the ITS4060S-SJ-N is shown. For further details please refer to application notes on the Infineon homepage. Note: Data Sheet This is a very simplified example of an application circuit. The function must be verified in the real application. 15 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Application information Special feature description Supply reverse voltage: R IN IN 4 ROUTPD 3 IIN ZDIN VS IRev ZDSAZ NC VBatt ZDSAZ NC 2 VDS I IN ZDIN 5-8 RIN IN ZDDSCL 2 ITS4060S-SJ-N VS 5-8 VFDS ITS4060S-SJ-N 4 OUT ROUTPD 1 3 OUT IRev1 1 VOUT GND RGND VRev Supply over voltage: ZDDSCL 6.1 GND ZL ZL RGND IRev2 If over-voltage is applied to the V S-Pin: Voltage is limited to V ZDSAZ; current can be calculated : IZDSAZ = (VS – VZDSAZ) / RGND A typical value for RGND is 150Ω. In case of ESD pulse on the input pin there is in both polarities a peak current IINpeak ~ VESD / RIN Drain-Source power stage clamper V DSCL: R IN ROUTPD 3 NC VOUT Data Sheet EBatt ZDSAZ ELoad ROUTPD GND 3 OUT EL LL ER RL LL When an inductive load is switched off a current path must be established until the current is sloped down to zero (all energy removed from the inductive load ). For that purpose the series combination Z DSCL is connected between Gate and Drain of the power DMOS acting as an active clamp . When the device is switched off , the voltage at OUT turns negative until V DSCL is reached. The voltage on the inductive load is the difference between VDSCL and VS. Figure 5 VS 4 1 IL RGND IIN OUT 1 GND 2 ZD IN VBatt ZD SAZ 4 5-8 RIN VDSCL I IN VDSCL NC IN 2 ZDIN ITS4060S-SJ-N VS ZDDSCL IN 5-8 Energy calculation: ZDDSCL ITS4060S-SJ-N If reverse voltage is applied to the device : 1.) Current via load resistance RL : IRev1 = (VRev – VFDS) / RL 2.) Current via Input pin IN and dignostic pin ST : IRev2 = IST+IIN ~ (VRev–VCC)/RIN +(VRev–VCC)/RST1,2 Current IST must be limited with the extrernal series resistor RSTS. Both currents will sum up to: IRev = IRev1+ IRev2 Energy stored in the load inductance is given by : EL= IL²*L/2 While demagnetizing the load inductance the energy dissipated by the Power-DMOS is: EAS = ES + EL – ER With an approximate solution for R L =0Ω: EAS = ½ * L * IL² * {(1- VS / (VS - VDSCL) Special feature description 16 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Application information 6.2 Typical application waveforms General Input Output waveforms: Waveforms switching a resistive load: VIN VIN H H L L t VS t VOUT +VS VDS 90% 70% t VOUT SROFF = dV/dt 40% 30% SRON = dV/dt 10% 0 0 t IL tON t t OFF IL 0 0 t OFF ON OFF t ON OFF Waveforms switching a capacitive load: ON OFF Waveforms switching an inducitive load : V IN VIN H H L L t VOUT ~ VS 0 0 t IL ILSC 0 t Figure 6 Data Sheet ON OFF t IL 0 OFF ~ VS VDSCL V OUT t ON t OFF ON OFF ON Typical application waveforms of the ITS4060S-SJ-N 17 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Application information 6.3 Protection behavior Overtemperature concept: Overtemperature behavior: VIN H TjRestart ON L TjTrip t VOUT heating up 0 OFF TJ cooling down Device Status t TJ TjTrip THYS THYS Normal Toggling t Overtemperature OFF Waveforms turn on into a short circuit : ON OFF ON OFF Waveforms short circuit during on state : VIN VIN H H L L t VOUT 0 IL ILSCP ILSCR tm Ipeak Overloaded IL OFF Data Sheet t Controlled by the current limit circuit 0 t OFF Normal operation OUT shorted to GND Shut down by overtemperature and restart by cooling (toggling ) Shut down by overtemperature and restart by cooling (toggling ) Figure 7 Ipeak ILSCR t t SCOFF OFF 0 t Controlled by the current limit circuit 0 t VOUT Protective behavior of the ITS4060S-SJ-N 18 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Package information 7 Package information B 0.1 SEATING PLANE 2) 0.41+0.1 -0.06 0.2 8 5 1 4 5 -0.2 1) M 0.64 ±0.25 6 ±0.2 A B 8x C 0.19 +0.06 8° MAX. 1.27 4 -0.21) 1.75 MAX. 0.175 ±0.07 (1.45) 0.35 x 45° 0.2 M C 8x A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area Figure 8 PG-DSO-81) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages 1) Dimensions in mm Data Sheet 19 Rev 1.1 2019-07-25 Smart high-side NMOS-power switch ITS4060S-SJ-N Revision history 8 Revision history Revision Date Changes 1.10 2019-07-25 Datasheet updated: - ESD ratings for HBM updated according ANSI/ESDA/JEDEC JS-001 - Editorial changes 1.0 12-09-01 Data Sheet Datasheet release 20 Rev 1.1 2019-07-25 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-07-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2019 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Z8F51106907 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. 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