Smart high-side NMOS-power switch
ITS4200S-SJ-D
Features
•
CMOS compatible input
•
Switching all types of resistive, inductive and capacitive loads
•
Fast demagnetization of inductive loads
•
Very low standby current
•
Optimized electromagnetic compatibility (EMC)
•
Open drain diagnostic output for overtemperature and short circuit
•
Open load detection in OFF-state with external resistor
•
Overload protection
•
Current limitation
•
Short circuit protection
•
Thermal shutdown with restart
•
Overvoltage protection (including load dump)
•
Reverse battery protection with external resistor
•
Loss of GND and loss of Vbb protection
•
Electrostatic discharge protection (ESD)
•
Green Product (RoHS compliant)
Potential applications
•
All types of resistive, inductive and capacitive loads
•
Power switch for 12V, 24V and 45V DC applications with CMOS compatible control interface
•
Open drain diagnosis feedback for overtemperature and short circuit
•
Driver for electromagnetic relays
•
Power management for high-side-switching with low current consumption in OFF-mode
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC.
Description
The ITS4200S-SJ-D is a protected 200m Ω single channel Smart High-Side NMOS-Power Switch in a PG-DSO-8
package with charge pump, CMOS compatible input and diagnostic feedback.
Data Sheet
www.infineon.com/industrial-profets
1
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Table 1
Product summary
Parameter
Symbol
Values
Overvoltage protection
VSAZmin
62 V
Operating voltage range
VS
6V < VS < 52V
On-state resistance
RDSON
typ. 150 mΩ
Nominal load current
IL(nom)
1.2 A
Operating temperature range
Tj
-40°C to 125°C
Type
Package
Marking
ITS4200S-SJ-D
PG-DSO-8
I200SD
Data Sheet
2
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Table of Contents
1
Block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Typical performance graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
6.1
6.2
6.3
6.4
6.5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical application waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Sheet
3
6
6
7
7
16
16
17
18
19
20
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Block diagram and terms
1
Block diagram and terms
ITS4200S-SJ-D
VS
5
6
Bias
Supervision
Overvoltage
Protection
Current
Limiter
7
8
IN
ST
2
Gate
Control
Circuit
Logic
ESD
Protection
4
Temperature
Sensor
OUT
3
1
GND
Figure 1
Block diagram
Voltage- and Current-Definitions:
Switching Times and Slew Rate Definitions:
VIN
H
ITS4200S-SJ-D
5
IS
6
IN
I IN
ST
Current
Limiter
Logic
8
70%
VDS
dV/tOFF
40%
30%
dV/tON
10%
4
3
OUT
IOUT
IL
GND
RL
1
0
tON
t
tOFF
IL
V IN
Temperature
Sensor
VO U T
V ST
+VS
90%
Gate
Control
Circuit
ESD
Protection
t
7
VS
IST
2
Overvoltage
Protection
VOUT
V FD S
Bias
Supervision
L
VS
0
OFF
ON
OFF
t
GND
Figure 2
Data Sheet
Terms - parameter definition
4
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Pin configuration
2
Pin configuration
2.1
Pin assignment
GND
1
8
VS
IN
2
7
VS
OUT
3
6
VS
ST
4
5
VS
P-DSO-8
Figure 3
Pin configuration top view, PG-DSO-8
2.2
Pin definitions and functions
Pin
Symbol
Function
1
GND
Logic ground
2
IN
Input, controls the power switch; the powerswitch is ON when high
3
OUT
Output to the load
4
ST
Status flag; diagnosis feedback; NMOS open drain
5, 6, 7, 8
VS
Supply voltage (design the wiring for the maximum short circuit current and also
for low thermal resistance)
Data Sheet
5
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 2
Absolute maximum ratings 1) at Tj = 25°C unless otherwise specified. Currents flowing into
the device unless otherwise specified in chapter “Block Diagram and Terms”
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note or
Number
Test Condition
Supply voltage VS
Voltage
VS
–
–
52
V
–
4.1.1
Voltage for short circuit protection
VSSC
–
–
36
V
–
4.1.2
IOUT
–
–
self
A
limited
–
4.1.3
IIN
-5
–
5
mA
–
4.1.4
IST
-5
–
5
mA
–
4.1.5
Junction temperature
Tj
-40
–
125
°C
–
4.1.6
Storage temperature
Tstg
-55
–
125
°C
–
4.1.7
P tot
–
–
1.4
W
–
4.1.8
EAS
–
–
125
mJ
single pulse
4.1.9
VESD
-1
–
1
kV
HBM4)
4.1.10
kV
4)
4.1.12
4)
4.1.11
Output stage OUT
Output current; (short circuit current
see electrical characteristics)
Input IN
Current
Status ST
Current
Temperatures
Power dissipation
Ta = 25 °C2)
Inductive load switch-off energy dissipation
Tj = 125 °C; IL= 1A3)
ESD susceptibility
ESD susceptibility (input pin IN)
ESD susceptibility (output pin OUT)
ESD susceptibility (all other pins)
VESD
VESD
-6
–
-4
–
6
4
kV
HBM
HBM
1) Not subject to production test, specified by design.
2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70mm thick) copper area for Vbb connection.
PCB is vertical without blown air.
3) Not subject to production test, specified by design.
4) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
Note:
Data Sheet
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as “outside” the normal operating
range. Protection functions are neither designed for continuous nor repetitive operation.
6
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
General product characteristics
3.2
Functional range
Table 3
Functional range
Parameter
Symbol
Nominal operating voltage
VS
Values
Min.
Typ.
Max.
6
–
52
Unit
Note or
Test Condition
Number
V
VS increasing
4.2.1
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
3.3
Thermal resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 4
Thermal resistance1)
Parameter
Symbol
Values
Number
Min.
Unit Note or
Test Condition
Typ. Max.
Thermal resistance - junction to Rthj-pin5
pin5
–
23.3
K/W –
4.3.1
Thermal resistance - junction to RthJA_1s0p
ambient - 1s0p, minimal
footprint
–
128.7 –
K/W
2)
4.3.2
Thermal resistance - junction to RthJA_1s0p_300mm
ambient - 1s0p, 300mm2
–
70.1
–
K/W
3)
4.3.3
Thermal resistance - junction to RthJA_1s0p_600mm
ambient - 1s0p, 600mm2
–
65.6
–
K/W
4)
4.3.4
Thermal resistance - junction to RthJA_2s2p
ambient - 2s2p
–
55.4
–
K/W
5)
4.3.5
Thermal resistance - junction to RthJA_2s2p
ambient with thermal vias - 2s2p
–
53.5
–
K/W
6)
4.3.6
–
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, footprint; the product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.
3) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, Cu, 300mm2; the
Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.
4) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, 600mm2; the product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.
5) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
6) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board with two thermal
vias; the Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm
Cu, 2 x 35µm Cu. The diameter of the two vias are equal 0.3mm and have a plating of 25um with a copper heatsink
area of 3mm x 2mm). JEDEC51-7: The two plated-through hole vias should have a solder land of no less than 1.25 mm
diameter with a drill hole of no less than 0.85 mm diameter.
Data Sheet
7
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Electrical characteristics
4
Electrical characteristics
Table 5
VS =12 V to 42 V; Tj = -40°C to +125°C; all voltages with respect to ground, currents flowing
into the device unless otherwise specified in chapter “Block Diagram and Terms”); typical
values at Vs = 13.5V, Tj = 25°C
Parameter
Symbol
Values
Unit Note or
Test Condition
Min. Typ. Max.
Number
NMOS ON resistance
RDSON
–
150
200
mΩ
IOUT= 1A;Tj = 25°C;
9V < VS < 52V;VIN= 5V
5.0.1
NMOS ON resistance
RDSON
–
250
350
mΩ
IOUT= 1A;Tj = 125°C;
9V < VS < 52V;VIN= 5V
5.0.2
Nominal load current;
device on PCB 1)
ILNOM
1.2
–
–
A
Tpin5 = 85°C
5.0.3
Turn ON time (to 90% of Vout);
L to H transition of VIN
tON
–
80
180
µs
VS=13.5V; RL = 47Ω
5.0.4
Turn OFF time (to 10% of Vout);
H to L transition of VIN
tOFF
–
80
200
µs
VS=13.5V; RL = 47Ω
5.0.5
ON-slew rate; ∆VOUT / ∆t;
(10 to 30% of Vout);
L to H transition of VIN
SRON
–
0.7
2.0
V / µs VS=13.5V; RL = 47Ω
5.0.6
OFF-slew rate; ∆VOUT / ∆t;
(70 to 40% of Vout);
H to L transition of VIN
SROFF
–
0.9
2.0
V / µs VS=13.5V; RL = 47Ω
5.0.7
Powerstage
Timings of power stages2)
Under voltage lockout (charge pump start-stop-restart)
Supply undervoltage;
charge pump stop voltage
VSUV
–
–
4
V
VS decreasing
-40°C < Tj < 85°C
5.0.8
Supply undervoltage;
Charge pump stop voltage
VSUV
–
–
5.5
V
VS decreasing;
Tj = 125°C
5.0.9
Supply startup voltage;
Charge pump restart voltage
VSSU
–
4
5.5
V
VS increasing
5.0.10
Operating current
IGND
–
0.8
2
mA
VIN= 5V
5.0.11
Standby current
ISSTB
–
–
15
µA
VIN= 0V; VOUT= 0V
-40°C < Tj < 85°C
5.0.12
Standby current
ISSTB
–
–
18
µA
VIN= 0V; Tj = 125°C
5.0.13
IOUTLK
–
–
5
µA
VIN= 0V; VOUT= 0V
5.0.14
Initial peak short circuit current limit
ILSCP
–
–
9
A
Tj = -40°C; VS = 20V;
VIN = 5.0V; tm = 150µs
5.0.15
Initial peak short circuit current limit
ILSCP
–
6.5
–
A
Tj = 25°C; VS = 20V;
VIN = 5.0V; tm = 150µs
5.0.16
Current consumption
Output leakage current
Protection functions
Data Sheet
3)
8
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Electrical characteristics
Table 5
VS =12 V to 42 V; Tj = -40°C to +125°C; all voltages with respect to ground, currents flowing
into the device unless otherwise specified in chapter “Block Diagram and Terms”); typical
values at Vs = 13.5V, Tj = 25°C
Parameter
Symbol
Values
Unit Note or
Test Condition
Min. Typ. Max.
Number
Initial peak short circuit current limit
ILSCP
4
–
–
A
Tj =125°C; VS = 20V;
VIN = 5.0V; tm = 150µs
5.0.17
Initial peak short circuit current limit 4) ILSCP
–
5
–
A
VS > 40V; VIN = 5.0V;
tm = 150µs
5.0.18
Repetitive short circuit current limit
Tj = TjTrip ; see timing diagrams
ILSCR
–
6
–
A
VIN = 5.0V; VS < 40V
5.0.19
Repetitive short circuit current limit
Tj = TjTrip ; see timing diagrams
ILSCR
–
4.5
–
A
VIN = 5.0V; VS > 40V
5.0.20
Output clamp at VOUT = VS - VDSCL
(inductive load switch off)
VDSCL
59
63
–
V
IS = 4mA
5.0.22
Overvoltage protection
VOUT = VS - VONCL
VSAZ
62
–
–
V
IS = 4mA
5.0.23
Thermal overload
trip temperature
TjTrip
150
–
–
°C
–
5.0.24
Thermal hysteresis
THYS
–
10
–
K
–
5.0.25
Continuous reverse battery voltage
VSREV
–
–
52
V
–
5.0.26
Forward voltage of the drain-source
reverse diode
VFDS
–
600
–
mV
IFDS = 200mA;
VIN= 0V;
Tj = 125°C
5.0.27
Input turn-ON voltage
(logic input high-level)
VINON
2.2
–
–
V
–
5.0.28
Input turn-OFF voltage
(logic input low-level)
VINOFF
–
–
0.8
V
–
5.0.29
Input threshold hysteresis
VINHYS
–
0.4
–
V
–
5.0.30
Off state input current
IINOFF
1
–
25
µA
VIN = 0.7V
5.0.31
On state input current
IINON
3
–
25
µA
VIN = 5.0V
5.0.32
Input resistance
RIN
2.0
3.5
5.0
kΩ
–
5.0.33
5)
Reverse battery
Input interface; pin IN
Status output (NMOS open drain); pin ST
Status output zener voltage
VSTZ
5.4
6.1
6.8
V
IST = 1.6mA
5.0.34
Status output low voltage
VSTLO
–
–
0.4
V
IST = 1.6mA; Tj < 25°C
5.0.35
Status output low voltage
VSTLO
–
–
0.6
V
IST = 1.6mA; Tj < 125°C 5.0.36
Status leakage current
ISTLK
–
–
2
µA
VST = 5V; Tj < 105°C
5.0.37
Status invalid time after positive input tdP
slope6)7)
–
120
160
µs
VS = 13.5V
5.0.38
Status invalid time after negative input tdN
slope 8)9)
–
250
400
µs
VS = 13.5V
5.0.39
Data Sheet
9
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Electrical characteristics
Table 5
VS =12 V to 42 V; Tj = -40°C to +125°C; all voltages with respect to ground, currents flowing
into the device unless otherwise specified in chapter “Block Diagram and Terms”); typical
values at Vs = 13.5V, Tj = 25°C
Parameter
Symbol
Values
Unit Note or
Test Condition
Min. Typ. Max.
Number
Short circuit detection voltage
VOUTSC
–
2.8
–
V
–
5.0.40
10)
Open load detection voltage
VOUTOL
–
3
4
V
–
5.0.41
11)
ROUTPD
–
200
–
kΩ
VOUT = 4V
5.0.42
Diagnostic characteristics
Internal pull down resistor
1) Device on 50mm x 50mm x 1,5mm epoxy FR4 PCB with 6cm2 (one layer copper 70um thick) copper area for supply
voltage connection. PCB in vertical position without blown air.
2) Timing values only with high slewrate input signal; otherwise slower.
3) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data
sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed
for continuous repetitive operation.
4) No subject to production test; specified by design.
5) Requires a 150 Ω resistor in GND connection. The reverse load current trough the intrinsic drain-source diode of the
power-MOS has to be limited by the connected load. Power dissipation is higher compared to normal operation due
to the voltage drop across the drain-source diode. The temperature protection is not functional during reverse
current operation! Input current has to be limited (see max ratings).
6) No delay time after overtemperature switch off and short circuit in on-state.
7) No subject to production test; specified by design.
8) No delay time after overtemperature switch off and short circuit in on-state.
9) No subject to production test; specified by design.
10) External pull up resistor required for open load detection in off state.
11) No subject to production test; specified by design.
Data Sheet
10
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Typical performance graphs
5
Typical performance graphs
Typical characteristics
Transient thermal impedance ZthJA versus
pulse time tp @ 6cm2 heatsink area
Transient thermal impedance ZthJA versus
pulse time tp @ min. footprint
D = tp / T
D = tp / T
On-resistance RDSONversus
junction temperature Tj
On-resistance RDSONversus
supply voltage VS
300
350
300
250
250
RDSON [mΩ]
RDSON [mΩ]
200
150
200
150
100
100
50
Tj=−40°C;IL=1A
50
Tj=25°C;IL=1A
Vs=13.5V
0
−40 −25
Data Sheet
0
Tj=125°C;IL=1A
25
50
Tj [°C]
75
100
0
125
11
10
20
30
Vs[V]
40
50
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Typical performance graphs
Typical characteristics
Switch ON time tON versus
junction temperature Tj
Switch OFF time tOFFversus
junction temperature Tj
140
120
120
100
100
80
tON [μs]
tOFF [μs]
80
60
60
40
40
Vs=9V;RL=47Ω
20
20
Vs=13.5V;RL=47Ω
Vs=42V;RL=47Ω
0
−40 −25
0
25
50
Tj[°C]
75
100
Vs=9..42V;RL=47Ω
0
−40 −25
125
ON slewrate SRON versus
junction temperature Tj
0
25
50
Tj[°C]
100
125
OFF slewrate SROFF versus
junction temperature Tj
2
3.5
Vs=9V;RL=47Ω
1.8
Vs=9V;RL=47Ω
Vs=13.5V;RL=47Ω
Vs=13.5V;RL=47Ω
3
Vs=42V;RL=47Ω
1.6
Vs=42V;RL=47Ω
2.5
1.4
1.2
2
−dV V
[ ]
dtoff μs
dV V
[ ]
dton μs
75
1
0.8
0.6
1.5
1
0.4
0.5
0.2
0
−40 −25
Data Sheet
0
25
50
Tj[°C]
75
100
0
−40 −25
125
12
0
25
50
Tj[°C]
75
100
125
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Typical performance graphs
Typical characteristics
Output leakage current IOUTLK versus
junction temperature Tj
Standby current ISSTB versus
junction temperature Tj
8
1.5
7
6
1
IOUTLK [μA]
ISSTB [μA]
5
4
3
0.5
2
1
VIN=0V;Vs=42V
0
−40 −25
0
25
50
Tj [°C]
75
100
VIN=0V;Vs=42V
0
−40 −25
125
Initial peak short circuit current limit ILSCP versus
junction temperature Tj
0
25
50
Tj [°C]
75
100
125
Initial short circuit shutdown time tSCOFF versus
junction temperature Tj
8
3.5
Vs=20V
7
3
6
2.5
tSCOFF [ms]
ILSCp [A]
5
4
2
1.5
3
1
2
Tj=−40°C
1
0.5
Tj=25°C
Tj=125°C
0
Data Sheet
10
20
30
Vs [V]
40
50
0
−40 −25
60
13
0
25
50
Tj[°C]
75
100
125
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Typical performance graphs
Typical characteristics
Input current consumption IIN versus
junction temperature Tj
Input current consumption IIN versus
input voltage VIN
12
50
Tj=−40..25°C;Vs=13.5V
45
Tj=125°C;Vs=13.5V
10
40
35
8
IIN [μA]
IIN [μA]
30
6
25
20
4
15
10
2
VIN≤0.7V;Vs=13.5V
5
VIN=5V;Vs=13.5V
0
−40 −25
0
25
50
Tj [°C]
75
100
Input threshold voltage VINH,L versus
junction temperature Tj
2
2
1.8
1.8
1.6
1.6
1.4
1.4
1.2
1.2
1
2
4
VIN[V]
0.8
0.6
0.6
0.4
0.4
OFF;Vs=13.5V
Data Sheet
0
25
50
Tj [°C]
75
100
8
OFF;Tj=25°C
0.2
ON;Vs=13.5V
0
−40 −25
6
1
0.8
0.2
0
Input threshold voltage VINH,L versus
supply voltage VS
VIN [V]
VIN [V]
0
125
ON;Tj=25°C
0
125
14
10
20
30
Vs[V]
40
50
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Typical performance graphs
Typical characteristics
Max. allowable Inductive single pulse Switch-off
energy EAS versus load current IL
Max. allowable load inductance L versus
load current IL
2000
1800
Tjstart=125°C;Vs=13.5V;RL=0Ω
1800
Tjstart=125°C;Vs=13.5V
1600
Tjstart=125°C;Vs=42V;RL=0Ω
1600
1400
1400
1200
EAS [mJ]
L [mH]
1200
1000
1000
800
800
600
600
400
400
200
200
0
0.4
0.6
0.8
IL [A]
1
0
1.2
Status delay time tN, P versus
supply voltage VS
0.4
0.6
0.8
IL [A]
1
1.2
Internal output pull down resistor ROUTOPD versus
supply voltage VS
300
800
Tj=−40°C
Tj=25°C
700
250
Tj=125°C
600
200
ROUTPD [kΩ]
tdON [μs]
500
150
400
300
100
200
50
100
Tj=25°C;tdN
Tj=25°C;tdP
0
Data Sheet
10
20
30
Vs [V]
40
0
50
15
10
20
30
Vs[V]
40
50
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Application information
6
Application information
6.1
Application diagram
The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty for a certain functionality, condition or quality of the device.
ITS4200S-SJ-D
5
Wire
Harness
VS
6
Bias
Supervision
Overvoltage
Protection
Current
Limiter
7
8
Control
Interface
IN
ST
2
CS
220nF
Gate
Control
Circuit
Logic
ESD
Protection
4
GND3
Temperature
Sensor
3
Wire
Harness
OUT
COUT
1
Complex
LOAD
1nF
GND
GND1
Electronic Control Unit
Figure 4
GND2
Application diagram
The ITS4200S-SJ-D can be connected directly to the battery of a supply network. It is recommended to place
a ceramic capacitor (e.g. CS = 220nF) between supply and GND of the ECU to avoid line disturbances. Wire
harness inductors/resistors are sketched in the application circuit above.
The complex load (resistive, capacitive or inductive) must be connected to the output pin OUT.
A built-in current limit protects the device against destruction.
The ITS4200S-SJ-D can be switched on and off with standard logic ground related logic signal at pin IN.
In standby mode (IN=L) the ITS4200S-SJ-D is deactivated with very low current consumption.
The output voltage slope is controlled during on and off transition to minimize emissions. Only a small
ceramic capacitor COUT=1nF is recommended to attenuate RF noise.
In the following chapters the main features, some typical waverforms and the protection behavior
of the ITS4200S-SJ-D is shown. For further details please refer to application notes on the Infineon homepage.
Data Sheet
16
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Application information
6.2
Diagnosis description
For diagnostic purpose the device provides a digital output pin ST in order to indicate fault conditions.
The status output (ST) of the ITS4200S-SJ-D is a high voltage open drain output.
In “normal” operation mode the NMOS open drain transistor is switched OFF.
The following truth table defines the status output.
Table 6
Truth table of diagnosis feature
Device operation
IN
OUT
ST
Normal operation
L
L
H
Normal operation
H
H
H
Short circuit to GND
L
L
H
Short circuit to GND
H
L
L
Short circuit to VS (in OFF state)
L
H
L
Short circuit to VS (in OFF state)
H
H
H
Overload
L
L
H
Overload
H
H
H
Overtemperature
L
L
H
Overtemperature
H
L
L
Open load in OFF state
L
Z
H
OUT=Z: high impedance;
potential depends on external circuit
Open load in OFF state
L
H
L
with external resistor between VS and OUT
Data Sheet
17
Comment
OUT=L: VOUT < VOUTSC ;
Short circuit detection voltage; typ 2.8V
OUT=H: VOUT > VOUTSC ;
Short circuit detection voltage; typ 2.8V
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Application information
Special feature description
Supply reverse voltage:
R IN
IN
I IN
4
ZDST
ROUTPD
3
ZDIN
IIN
4
R ST2
OUT
1
ZDSAZ
ST
ZDST
ROUTPD
VOUT
RGND
3
OUT
IRev1
1
VControl
GND
VS
IRev
R ST1
VBatt
ZDSAZ
ST
2
+VCC
VON
ZDIN
5-8
RIN
IN
ZDDSCL
2
ITS4200S-SJ-D
VS
5-8
VFDS
ITS4200S-SJ-D
VRev
Supply over voltage:
ZDDSCL
6.3
GND
ZL
ZL
RGND
IRev2
If over-voltage is applied to the V S-Pin:
Voltage is limited to V ZDSAZ; current can be calculated :
IZDSAZ = (VS – VZDSAZ) / RGND
A typical value for RGND is 150Ω.
In case of ESD pulse on the input pin there is in both
polarities a peak current IINpeak ~ VESD / RIN
Drain-Source power stage clamper V DSCL:
R IN
ZDST
ROUTPD
3
ST
VOUT
RGND
Data Sheet
EBatt
ZDSAZ
ELoad
ROUTPD
GND
3
OUT
EL
LL
ER
RL
LL
When an inductive load is switched off a current path must be
established until the current is sloped down to zero (all energy
removed from the inductive load ). For that purpose the series
combination Z DSCL is connected between Gate and Drain of the
power DMOS acting as an active clamp .
When the device is switched off , the voltage at OUT turns
negative until V DSCL is reached.
The voltage on the inductive load is the difference between
VDSCL and VS.
Figure 5
VS
4
1
IL
GND
IIN
ZDST
OUT
1
2
ZD IN
VBatt
ZD SAZ
4
5-8
RIN
VDSCL
I IN
VDSCL
ST
IN
2
ZDIN
ITS4200S-SJ-D
VS
ZDDSCL
IN
5-8
Energy calculation:
ZDDSCL
ITS4200S-SJ-D
If reverse voltage is applied to the device :
1.) Current via load resistance RL :
IRev1 = (VRev – VFDS) / RL
2.) Current via Input pin IN and dignostic pin ST :
IRev2 = IST+IIN ~ (VRev–VCC)/RIN +(VRev–VCC)/RST1,2
Current IST must be limited with the extrernal series
resistor RSTS. Both currents will sum up to:
IRev = IRev1+ IRev2
Energy stored in the load inductance is given by :
EL= IL²*L/2
While demagnetizing the load inductance the energy
dissipated by the Power-DMOS is:
EAS = ES + EL – ER
With an approximate solution for R L =0Ω:
EAS = ½ * L * IL² * {(1- VS / (VS - VDSCL)
Special feature description
18
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Application information
6.4
Typical application waveforms
General Input Output waveforms:
Waveforms switching a resistive load:
VIN
VIN
H
H
L
L
t
VS
t
VOUT
+VS
VDS
90%
70%
t
VOUT
SROFF = dV/dt
40%
30%
SRON = dV/dt
10%
0
0
t
IL
tON
t
t OFF
IL
0
0
t
VST
t
VST
H
H
L
L
t
OFF
ON
OFF
t
ON
OFF
Waveforms switching a capacitive load:
ON
OFF
Waveforms switching an inducitive load :
V IN
VIN
H
H
L
L
t
VOUT
~ VS
0
0
t
IL
~ VS
VDSCL
V OUT
t
ILSC
t
IL
0
0
t
VST
t
VST
H
H
L
L
t
OFF
Figure 6
Data Sheet
ON
OFF
ON
t
OFF
ON
OFF
ON
Typical application waveforms of the ITS4200S-SJ-D
19
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Application information
6.5
Protection behavior
Overtemperature concept:
Overtemperature behavior:
VIN
H
TjRestart
ON
L
TjTrip
t
VOUT
heating
up
0
OFF
TJ
cooling
down
Device
Status
t
TJ
TjTrip
THYS
THYS
Normal
Toggling
Overtemperature
t
VST
H
L
t
OFF
Waveforms turn on into a short circuit :
ON
OFF
VIN
H
H
L
L
t
VOUT
0
IL
ILSCP
ILSCR
tm
Ipeak
0
t
IL
Ipeak
t
Controlled
by the
current limit
circuit
ILSCR
0
t
t SCOFF
t
VOUT
Controlled
by the
current limit
circuit
0
t
VST
VST
H
H
t dP
L
L
t
OFF
Overloaded
OFF
t
OFF
Normal
operation
OUT shorted to GND
Shut down by overtemperature and
restart by cooling (toggling )
Shut down by overtemperature and
restart by cooling (toggling )
Data Sheet
OFF
Waveforms short circuit during on state :
VIN
Figure 7
ON
Protective behavior of the ITS4200S-SJ-D
20
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Package information
7
Package information
B
0.1
SEATING PLANE
2)
0.41+0.1
-0.06
0.2
8
5
1
4
5 -0.2 1)
M
0.64 ±0.25
6 ±0.2
A B 8x
C
0.19 +0.06
8° MAX.
1.27
4 -0.21)
1.75 MAX.
0.175 ±0.07
(1.45)
0.35 x 45°
0.2
M
C 8x
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
PG-DSO-8-16, -24, -25, -28, -31, -33, -36, -44, -49-PO V06
Figure 8
PG-DSO-81)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimensions in mm
Data Sheet
21
Rev 1.1
2019-07-25
Smart high-side NMOS-power switch
ITS4200S-SJ-D
Revision history
8
Revision history
Revision Date
Changes
1.10
2019-07-25 Datasheet updated:
- ESD ratings for HBM updated according ANSI/ESDA/JEDEC JS-001
- Editorial changes
1.0
2012-09-01 Datasheet release
Data Sheet
22
Rev 1.1
2019-07-25
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-07-25
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012-09-01 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Z8F51106903
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
For further information on technology, delivery terms
and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Please note that this product is not qualified
according to the AEC Q100 or AEC Q101 documents of
the Automotive Electronics Council.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
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