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MB90224PF-GT-368

MB90224PF-GT-368

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

  • 描述:

    IC MCU 16BIT 96KB MROM 120QFP

  • 数据手册
  • 价格&库存
MB90224PF-GT-368 数据手册
FUJITSU SEMICONDUCTOR DATA SHEET DS07-13502-5E 16-bit Proprietary Microcontroller CMOS F2MC-16F MB90220 Series MB90223/224/P224A/W224A MB90P224B/W224B/V220 ■ OUTLINE The MB90220 series of general-purpose high-performance 16-bit microcontrollers has been developed primarily for applications that demand high-speed real-time processing and is suited for industrial applications, office automation equipment, process control, and other applications. The F2MC-16F CPU is based on the F2MC*-16 Family with improved high-level language support functions and task switching functions, as well as additional addressing modes. On-chip peripheral resources include a 4-channel PWC timer, a 4-channel ICU (Input Capture Unit), a 1-channel 24-bit timer counter, an 8-channel OCU (Output Compare Unit), a 6-channel 16-bit reload timer, a 2-channel 16-bit PPG timer, a 10-bit A/D converter with 16 inputs, and a 4-channel serial port with a UART function (one channel includes the CTS function). The MB90P224B, MB90W224B, MB90224 is under development. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ PACKAGE 120-pin Plastic QFP 120-pin Ceramic QFP (FPT-120P-M03) (FPT-120C-C02) MB90220 Series ■ FEATURES F2MC-16F CPU • Minimum execution time: 62.5 ns/16 MHz oscillation (using a duty control system) • Instruction sets optimized for controllers Upward object-compatible with the F2MC-16(H) Various data types (bit, byte, word, and long-word) Instruction cycle improved to speed up operation Extended addressing modes: 25 types High coding efficiency Access method (bank access with linear pointer) Enhanced multiplication and division instructions (with signed instructions added) Higher-precision operation using a 32-bit accumulator • Extended intelligent I/O service (automatic transfer function independent of instructions) Access area expanded to 64 Kbytes • Enhanced instruction set applicable to high-level language (C) and multitasking System stack pointer Enhanced pointer-indirect instructions Barrel shift instruction Stack check function • Increased execution speed: 8-byte instruction queue • Powerful interrupt functions: 8 levels and 28 sources Peripheral resources • Mask ROM • • • • • • • • • • • • • • • • 2 : 64 Kbytes (MB90223) 96 Kbytes (MB90224) EPROM : 96 Kbytes (MB90W224A/W224B) One-time PROM : 96 Kbytes (MB90P224A/P224B) RAM: 3 Kbytes (MB90223) 4.5 Kbytes (MB90224/MB90W224A/P224A/W224B/P224B) 5 Kbytes (MB90V220) General-purpose ports: max. 102 channels ICU (Input Capture Unit): 4 channels 24-bit timer counter: 1 channel OCU (Output Compare Unit): 8 channels PWC timer with time measurement function: 4 channels 10-bit A/D converter: 16 channels UART: 4 channels (one channel includes CTS function) 16-bit reload timer Toggled output, external clock, and gate functions: 6 channels 16-bit PPG timer: 2 channels DTP/External-interrupt inputs: 8 channels (of which five have edge detection function only) Write-inhibit RAM: 0.5 Kbytes (1 Kbyte for MB90V220) Timebase counter: 18 bits Clock gear function Low-power consumption mode Sleep mode Stop mode Hardware standby mode MB90220 Series Product description • • • • MB90223/224 are mask ROM product. MB90P224A/P224B are one-time PROM products. MB90W224A/W224B are EPROM products. ES only. Operating temperature of MB90P224A/W224A is –40°C to +85°C. (However, the AC characteristics is assured in –40°C to +70°C) • Operation clock cycle of MB90223 is 10 MHz to 12 MHz. • MB90V220 is a evaluation device for the program development. ES only. ■ PRODUCT LINEUP Part number MB90223 MB90224 MB90P224A MB90P224B MB90W224A MB90W224B MB90V220 Classification Mask ROM product Mask ROM product One-time PROM product EPROM product Evaluation device ROM size 64 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes None RAM size 3 Kbytes 4.5 Kbytes 4.5 Kbytes 4.5 Kbytes 5 Kbytes Item CPU functions The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 412 8 or 16 bits 1 to 7 bytes 1, 4, 8, 16, or 32 bits 62.5 ns/16 MHz 1.0 µs/16 MHz (min.) Ports I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 16 86 102 ICU (Input Capture Unit) 24-bit timer counter OCU (Output Compare Unit) PWC timer 10-bit A/D converter Number of channels: 4 Rising edge/falling edge/both edges selectable Number of channels: 1 Overflow interrupt, intermediate bit interrupt Number of channels: 8 Pin change source (match signal causes register value transfer/general-purpose port) Number of channels: 4 16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.31 ms) 16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width measurement, inter-edge measurement, and divided-frequency measurement) Resolution: 10 bits Number of inputs: 16 Single conversion mode (conversion of each channel) Scan conversion mode (continuous conversion for up to 16 consecutive channels) Continuous conversion mode (repeated conversion of specified channel) Stop conversion mode (conversion every fixed cycle) UART Number of channels: 4 (1 channel with CTS function) Clock-synchronous transfer mode (full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps) Asynchronous transfer mode (full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps) 16-bit reload timer Number of channels: 6 16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.05 s) (Continued) 3 MB90220 Series (Continued) Part number MB90223 Item 16-bit PPG timer MB90P224A MB90P224B MB90224 MB90W224A MB90W224B MB90V220 Number of channels: 2 16-bit PPG operation (operation clock cycle: 0.25 µs to 6 s) DTP/External interrupts Number of inputs: 8 (of which five have edge detection function only) External interrupt mode (allowing interrupts to activate at four different request levels) Simple DMA transfer mode (allowing extended I2OS to activate at two different request levels) Write-inhibited RAM RAM size: 512 bytes (1 Kbyte for MB90V220) RAM write-protectable with WI pin Standby mode stop mode (activated by software or hardware) and sleep mode Gear function Machine clock operation frequency switching: 16 MHz, 8 MHz, 4 MHz, 1 MHz (at 16-MHz oscillation) Package FPT-120P-M03 FPT-120C-C02 PGA-256C-A02 Note: MB90V220 is a evaluation device, therefore, the electrical characteristics are not assured. ■ DIFFERENCES BETWEEN MB90223/224 (MASK ROM PRODUCT) AND MB90P224A/ W224A/P224B/W224B Part number Item ROM Pin functions: pin 87 4 MB90223 MB90224 MB90P224A MB90P224B MB90W224A MB90W224B Mask ROM 64 Kbytes Mask ROM 96 Kbytes OTPROM 96 Kbytes EPROM 96 Kbytes MD2 pin MD2/VPP pin MB90220 Series ■ PIN ASSIGNMENT 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RST MD0 MD1 MD2 HST P57/WI P56/RD P55/WRL P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PC5/TRG0 PC4/CTS0 PC3/SCK3 PC2/SID3 PC1/SOD3 PC0/SCK2 PB7/SID2 PB6/SOD2 PB5/SCK1 PB4/SID1 PB3/SOD1 PB2/SCK0 PB1/SID0 PB0/SOD0 VSS PA7/INT2/ATG PA6/INT1 (Top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PA5/INT0 PA4/PWC3/POT3/ASR3 PA3/PWC2/POT2/ASR2 PA2/PWC1/POT1/ASR1 PA1/PWC0/POT0 PA0/ASR0 VCC P67/AN07 P66/AN06 P65/AN05 P64/AN04 P63/AN03 P62/AN02 P61/AN01 P60/AN00 AVSS AVRL AVRH AVCC P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN09 P90/AN08 VSS P87/PPG1 P86/PPG0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P31/A09 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 VCC P40/A16 P41/A17 P42/A18 P43/A19/TIN1/INT3 P44/A20/TIN2/INT4 P45/A21/TIN3/INT5 P46/A22/TIN4/INT6 P47/A23/TIN5/INT7 P70/DOT0 P71/DOT1 P72/DOT2 P73/DOT3 P74/DOT4 P75/DOT5 P76/DOT6 P77/DOT7 P80/TOT0 P81/TOT1 P82/TOT2 P83/TOT3 P84/TOT4 P85/TOT5 VSS X0 X1 VCC P00/D00 P01/D01 P02/D02 P03/D03 P04/D04 P05/D05 P06/D06 P07/D07 P10/D08 P11/D09 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/A00 P21/A01 P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 VSS P30/A08 (FPT-120P-M03) (FPT-120C-C02) 5 MB90220 Series ■ PIN DESCRIPTION Pin no. Pin name QFP* 92, 93 Circuit type X0, X1 A Crystal oscillation pins (16 MHz) MD0 to MD2 D Operation mode specification input pins Connect directly to VCC or VSS. 90 RST G External reset request input 86 HST E Hardware standby input pin P00 to P07 C General-purpose I/O ports This function is valid only in single-chip mode. 89 to 87 95 to 102 D00 to D07 103 to 110 P10 to P17 Output pins for low-order 8 bits of the external address bus. This function is valid only in modes where the external bus is enabled. C D08 to D15 111 to 118 P20 to P27 120, 1 to 7 P30, P31 to P37 C P40 to P42 C P43 to P47 General-purpose I/O ports This function is valid either in single-chip mode or when the address mid-order control register specification is “port”. Output pins for mid-order 8 bits of the external address bus This function is valid in modes where the external bus is enabled and the address mid-order control register specification is “address”. C A16 to A18 12 to 16 General-purpose I/O ports This function is valid only in single-chip mode. Output pins for lower-order 8 bits of the external address bus This function is valid only in modes where the external bus is enabled. A08, A09 to A15 9 to 11 General-purpose I/O ports This function is valid only in single-chip mode or when the external bus is enabled and the 8-bit data bus specification has been made. I/O pins for higher-order 8 bits of the external data bus This function is valid only when the external bus is enabled and the 16-bit bus specification has been made. A00 to A07 General-purpose I/O ports This function is valid either in single-chip mode or when the address high-order control register specification is “port”. Output pins for higher-order 8 bits of the external address bus This function is valid in modes where the external bus is enabled and the address high-order control register specification is “address”. C General-purpose I/O ports This function is valid when either single-chip mode is enabled or the address higher-order control register specification is “port”. A19 to A23 Output pins for higher-order 8 bits of the external address bus This function is valid in modes where the external bus is enabled and the address higher-order control register specification is “address”. TIN1 to TIN5 16-bit reload timer input pins This function is valid when the timer input specification is “enabled”. The data on the pins is read as timer input (TIN1 to TIN5). * : FPT-120P-M03, FPT-120C-C02 6 Function (Continued) MB90220 Series Pin no. QFP* 12 to 16 78 Circuit type Function INT3 to INT7 C External interrupt request input pins When external interrupts are enabled, these inputs may be used suddenly at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. P50 C General-purpose I/O port This function is valid in single-chip mode and when the CLK output specification is disabled. Pin name CLK 79 P51 CLK output pin This function is valid in modes where the external bus is enabled and the CLK output specification is enabled. C RDY 80 P52 Ready input pin This function is valid in modes where the external bus is enabled and the ready function is enabled. C HAK 81 P53 P54 C P55 WRL * : FPT-120P-M03, FPT-120C-C02 General-purpose I/O port This function is valid in single-chip mode or external bus mode and when the hold function is disabled. Hold request input pin This function is valid in modes where the external bus is enabled and the hold function is enabled. During this operation, the input may be used suddenly at any time; therefore, it is necessary to stop output by other fuctions on this pin, except when using it for output deliberately. C WRH 83 General-purpose I/O port This function is valid in single-chip mode or when the hold function is disabled. Hold acknowledge output pin This function is valid in modes where the external bus is enabled and the hold function is enabled. HRQ 82 General-purpose I/O port This function is valid in single-chip mode or when the ready function is disabled. General-purpose I/O port This function is valid in single-chip mode, when the external bus is in 8-bit mode, or when WRH pin output is disabled. Write strobe output pin for the high-order 8 bits of the data bus This function is valid in modes where the external bus is enabled, the external bus is in 16-bit mode, and WRH pin output is enabled. C General-purpose I/O port This function is valid in single-chip mode or when WRL pin output is disabled. Write strobe output pin for the low-order 8 bits of the data bus This function is valid in modes where the external bus is enabled and WRL pin output is enabled. (Continued) 7 MB90220 Series Pin no. Pin name QFP* 84 P56 Circuit type C RD 85 P57 P60 to P67 B P70 to P77 F P80 to P85 C P86, P87 C P90 to P97 AN08 to AN15 * : FPT-120P-M03, FPT-120C-C02 8 General-purpose I/O ports This function is valid when the output specification for TOT0 to TOT5 is “disabled”. 16-bit reload timer output pins (TOT0 to TOT5) C PPG0, PPG1 34 to 41 General-purpose I/O ports This function is valid when the output specification for DOT0 to DOT7 is “disabled”. This function is valid when OCU (output compare unit) output is enabled. TOT0 to TOT5 31, 32 Open-drain I/O ports This function is valid when the analog input enable register specification is “port”. 10-bit A/D converter analog input pins This function is valid when the analog input enable register specification is “analog input”. DOT0 to DOT7 25 to 30 General-purpose I/O port This function is always valid. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. RAM write disable request input During this operation, the input may be used suddenly at any time; therefore, it is necessary to stop output by other fuctions on this pin, except when using it for output deliberately. AN00 to AN07 17 to 24 General-purpose I/O port This function is valid in single-chip mode. This function is valid in modes where the external bus is valid. Read strobe output pin for the data bus This function is valid in modes where the external bus is enabled. WI 46 to 53 Function General-purpose I/O ports This function is valid when the PPG0, and PPG1 output specification is “disabled”. 16-bit PPG timer output pins This function is valid when the PPG control/status register specification is “PPG output pins”. F Open-drain I/O ports This function is valid when the analog input enable register specification is “port”. 10-bit A/D converter analog input pins This function is valid when the analog input enable register specification is “analog input”. (Continued) MB90220 Series Pin no. QFP* 55 Pin name PA0 Circuit type C ASR0 56 57 to 59 60, 61 PA1 General-purpose I/O port This function is always valid. ICU (input capture unit) input pin This function is valid during ICU (input capture unit) input operations. C General-purpose I/O port This function is always valid. PWC0 PWC input pin During PWC0 input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. POT0 PWC output pin This function is valid during PWC output operations. PA2 to PA4 C General-purpose I/O ports This function is always valid. PWC1 to PWC3 PWC input pins This function is valid during PWC input operations. During PWC1 to PWC3 input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. POT1 to POT3 PWC output pins This function is valid during PWC output operations. ASR1 to ASR3 ICU (input capture unit) input pins This function is valid during ICU (input capture unit) input operations. PA5, PA6 B INT0, INT1 62 Function PA7 * : FPT-120P-M03, FPT-120C-C02 General-purpose I/O ports This function is always valid. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. DTP/External interrupt request input pins When DTP/external interrupts are enabled, these inputs may be used suddenly at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. B General-purpose I/O port This function is always valid. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. (Continued) 9 MB90220 Series Pin no. QFP* 62 Pin name INT2 Circuit type Function B DTP/External interrupt request input pin When DTP/external interrupts are enabled, these inputs may be used suddenly at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. ATG 64 PB0 10-bit A/D converter external trigger input pin When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. C SOD0 65 PB1 UART0 (ch.0) serial data output This function is valid when the UART0 (ch.0) serial data output specification is “enabled”. C SID0 66 PB2 PB3 C PB4 SID1 * : FPT-120P-M03, FPT-120C-C02 10 General-purpose output port This function is valid when the UART0 (ch.0) clock output specification is “disabled”. UART0 (ch.0) clock output pin The clock output function is valid when the UART0 (ch.0) clock output specification is “enabled”. UART0 (ch.0) external clock input pin. This function is valid when the port is in input mode and the UART0 (ch.0) specification is external clock mode. C SOD1 68 General-purpose I/O port This function is always valid. UART0 (ch.0) serial data input pin During UART0 (ch.0) input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. SCK0 67 General-purpose I/O port This function is valid when the UART0 (ch.0) serial data output specification is “disabled”. General-purpose I/O port This function is valid when the UART0 (ch.1) serial data output specification is “disabled”. UART0 (ch.1) serial data output pin This function is valid when the UART0 (ch.1) serial data output specification is “enabled”. C General-purpose I/O port This function is always valid. UART0 (ch.1) serial data input pin During UART0 (ch.1) input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. (Continued) MB90220 Series Pin no. QFP* 69 Pin name PB5 Circuit type Function C General-purpose I/O port This function is valid when the UART0 (ch.1) clock output specification is “disabled”. SCK1 70 PB6 UART0 (ch.1) clock output pin The clock output function is valid when the UART0 (ch.1) clock output specification is “enabled”. UART0 (ch.1) external clock input pin This function is valid when the port is in input mode and the UART0 (ch.1) specification is external clock mode. C SOD2 71 PB7 UART0 (ch.2) serial data output pin This function is valid when the UART0 (ch.2) serial data output specification is “enabled”. C SID2 72 PC0 PC1 C PC2 SID3 * : FPT-120P-M03, FPT-120C-C02 General-purpose I/O port This function is valid when the UART0 (ch.2) clock output specification is “disabled”. UART0 (ch.2) clock output pin The clock output function is valid when the UART0 (ch.2) clock output specification is “enabled”. UART0 (ch.2) external clock input pin This function is valid when the port is in input mode and the UART0 (ch.2) specification is external clock mode. C SOD3 74 General-purpose I/O port This function is always valid. UART0 (ch.2) serial data input pin During UART0 (ch.2) input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. SCK2 73 General-purpose I/O port This function is valid when the UART0 (ch.2) serial data output specification is “disabled”. General-purpose I/O port This function is valid when the UART1 serial data output specification is “disabled”. UART1 serial data output pin This function is valid when the UART1 serial data output specification is “enabled”. C General-purpose I/O port This function is always valid. UART1 serial data input pin During UART1 input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. (Continued) 11 MB90220 Series (Continued) Pin no. Pin name QFP* 75 PC3 Circuit type C SCK3 76 PC4 PC5 TRG0 C General-purpose I/O port This function is always valid. UART0 (ch.0) Clear To Send input pin When the UART0 (ch.0) CTS function is enabled, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. C General-purpose I/O port This function is always valid. 16-bit PPG timer trigger input pin This function is valid when the 16-bit PPG timer trigger input specification is enabled. The data on this pin is read as 16-bit PPG timer trigger input (TRG0). During this operation, the input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. 8, 54, 94 VCC Power Power supply for digital circuitry supply 33, 63, 91, 119 VSS Power Ground level for digital circuitry supply 42 AVCC Power Power supply for analog circuitry supply When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AVCC to VCC. During normal operation AVCC should be equal to VCC. 43 AVRH Power Reference voltage input for analog circuitry supply When turning this pin on or off, always be sure to first apply electric potential equal to or greater than AVRH to AVCC. 44 AVRL Power Reference voltage input for analog circuitry supply 45 AVSS Power Ground level for analog circuitry supply * : FPT-120P-M03, FPT-120C-C02 12 General-purpose I/O port This function is valid when the UART1 clock output specification is “disabled”. UART1 clock output pin The clock output function is valid when the UART1 clock output specification is “enabled”. UART1 external clock input pin This function is valid when the port is in input mode and the UART1 specification is external clock mode. CTS0 77 Function (Continued) MB90220 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A • Oscillation feedback resistor: Approx. 1 MΩ MB90223 MB90224 MB90P224B MB90W224B X1 X0 Standby control signal • Oscillation feedback resistor: Approx. 1 MΩ MB90P224A MB90W224A X1 X0 Standby control signal B • CMOS-level output • CMOS-level hysteresis input with no standby control Digital output Digital output R Digital input Note: The pull-up and pull-down resistors are always connected, regardless of the state. (Continued) 13 MB90220 Series Type Circuit Remarks C Digital output • CMOS-level output • CMOS-level hysteresis input with standby control Digital output R Digital input D • CMOS-level input with no standby control Mask ROM products only: MD2: with pull-down resistor MD1: with pull-up resistor MD0: with pull-down resistor R Digital input • CMOS-level input with no standby control MD2 of OTPROM products/EPROM products only R Digital input VPP power supply E • CMOS-level hysteresis input with no standby control • With input analog filter (40 ns Typ.) R Analog filter Digital input Note: The pull-up and pull-down resistors are always connected, regardless of the state. (Continued) 14 MB90220 Series (Continued) Type Circuit Remarks F • N-channel open-drain output • CMOS-level hysteresis input with A/D control and with standby control Digital output R A/D input Digital input G • CMOS-level hysteresis input with no standby control and with pull-up resistor • With input analog filter (40 ns Typ.) Pull-up resistor R MB90223, MB90224: RST pin can be set to with or without a pull-up resistor by a mask option. MB90P224A: With pull-up resistor MB90W224A: With pull-up resistor MB90P224B: With no pull-up resistor MB90W224B: With no pull-up resistor R Analog filter : P-type transistor Digital input : N-type transistor Note: The pull-up and pull-down resistors are always connected, regardless of the state. 15 MB90220 Series ■ HANDLING DEVICES 1. Preventing Latchup CMOS ICs may cause latchup when a voltage higher than VCC or lower than VSS is applied to input or output pins other than medium-and high-voltage pins, or when a voltage exceeding the rating is applied between VCC and VSS. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating. Also, take care to prevent the analog power supply (AVCC and AVRH) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Pins when A/D is not Used Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use. 4. Precautions when Using an External Input To reset the internal circuit properly by the “L” level input to the RST pin, the “L” level input to the RST pin must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input. 5. VCC and VSS Pins Apply equal potential to the VCC and VSS pins. 6. Supply Voltage Variation The operation assurance range for the VCC supply voltage is as given in the ratings. However, sudden changes in the supply voltage can cause misoperation, even if the voltage remains within the rated range. Therefore, it is important to supply a stable voltage to the IC. The recommended power supply control guidelines are that the commercial frequency (50 to 60 Hz) ripple variation (P-P value) on VCC should be less than 10% of the standard VCC value and that the transient rate of change during sudden changes, such as during power supply switching, should be less than 0.1 V/ms. 7. Notes on Using an External Clock When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation stabilization time is required even for power-on reset and wake-up from stop mode. • Use of External Clock X0 MB90220 X1 Note: When using an external clock, be sure to input external clock more than 6 machine cycles after setting the HST pin to “L” to transfer to the hardware standby mode. 16 MB90220 Series 8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN00 to AN15). When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN00 to AN15) first, then the digital power supply (VCC). When turning AVRH on or off, be careful not to let it exceed AVCC. 17 MB90220 Series ■ PROGRAMMING FOR MB90P224A/P224B/W224A/W224B In EPROM mode, the MB90P224A/P224B/W224A/W224B functions equivalent to the MBM27C1000. This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter (do not use the electronic signature mode). 1. Program Mode When shipped from Fujitsu, and after each erasure, all bits (96 K × 8 bits) in the MB90P224A/P224B/W224A/ W224B are in the “1” state. Data is written to the ROM by selectively programming “0’s” into the desired bit locations. Bits cannot be set to “1” electrically. 2. Programming Procedure (1) Set the EPROM programmer to MBM27C1000. (2) Load program data into the EPROM programmer at 08000H to 1FFFFH. Note that ROM addresses FE8000H to FFFFFFH in the operation mode in the MB90P224A/P224B/W224A/ W224B series assign to 08000H to 1FFFFH in the EPROM mode (on the EPROM programmer). FFFFFFH 1FFFFH * FE8000H 08000H * Operation mode EPROM mode (Corresponding addresses on the EPROM mode) * : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 08000H/1FFFFH. (3) Mount the MB90P224A/P224B/W224A/W224B on the adapter socket, then fit the adapter socket onto the EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting orientations. (4) Start programming the program data to the device. (5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between VCC and GND, between VPP and GND. Note: The mask ROM products (MB90223, MB90224) does not support EPROM mode. Data cannot, therefore, be read by the EPROM programmer. 18 MB90220 Series 3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer Part No. MB90P224B Package QFP-120 Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name Advantest corp. ROM-120QF-32DP-16F R4945A (main unit) + R49451A (adapter) Recommended Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111 4. Erase Procedure Data written in the MB90W224A/W224B is erased (from “0” to “1”) by exposing the chip to ultraviolet rays with a wavelength of 2,537 Å through the translucent cover. Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 µW/cm2). If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the package). The above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure; the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition, check the life span of the lamp and control the illuminance appropriately. Data in the MB90W224A/W224B is erased by exposure to light with a wavelength of 4,000 Å or less. Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure results in a much lower erasure rate than exposure to 2,537 Å ultraviolet rays. Note that exposure to such lights for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light with a wavelength of 4,000 Å or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light. Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. Although the circuit will recover normal operation when exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to such light even though the wavelength is 4,000 Å or more. 19 MB90220 Series 5. Recommended Screening Conditions High temperature aging is recommended as the pre-assembly screening procedure. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 6. Programming Yeild MB90P224A/P224B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always be guaranteed to be 100%. 7. Pin Assignments in EPROM Mode (1) Pins Compatible with MBM27C1000 MBM27C1000 Pin no. 20 Pin name MB90P224A/P224B/ MB90W224A/W224B MBM27C1000 Pin no. Pin name Pin no. Pin name 1 VPP 87 MD2 (VPP) 32 VCC 2 OE 83 P55 31 3 A15 7 P37 4 A12 4 5 A07 6 MB90P224A/P224B/ MB90W224A/W224B Pin no. Pin name 8, 54, 94 VCC PGM 84 P56 30 N.C. — — P34 29 A14 6 P36 118 P27 28 A13 5 P35 A06 117 P26 27 A08 120 P30 7 A05 116 P25 26 A09 1 P31 8 A04 115 P24 25 A11 3 P33 9 A03 114 P23 24 A16 9 P40 10 A02 113 P22 23 A10 2 P32 11 A01 112 P21 22 CE 82 P54 12 A00 111 P20 21 D07 102 P07 13 D00 95 P00 20 D06 101 P06 14 D01 96 P01 19 D05 100 P05 15 D02 97 P02 18 D04 99 P04 16 GND 17 D03 98 P03 33, 63, 91,119 VSS MB90220 Series (2) Power Supply and GND Connection Pins Type Pin no. Pin name Power supply 89 88 86 8, 54, 94 MD0 MD1 HST VCC GND 33, 63, 91, 119 44 45 80 81 90 VSS AVRL AVSS P52 P53 RST (3) Pins other than MBM27C1000-compatible Pins Pin no. Pin name Treatment 92 X0 Pull up with 4.7 KΩ resistor 93 X1 OPEN 109 110 10 to 16 42 43 46 47 48 to 53 17 to 24 25 to 32 34 to 41 55 to 61 63 to 70 71 to 76 78 79 85 103 to 108 P16 P17 P41 to P47 AVCC AVRH P60 P61 P62 to P67 P70 to P77 P80 to P82 P90 to P97 PA0 to PA7 PB0 to PB7 PC0 to PC5 P50 P51 P57 P10 to P15 Connect pull-up resistor of about 1 MΩ to each pin 21 MB90220 Series ■ BLOCK DIAGRAM 4 PWC0 to PWC3 X1 X0 RST HST MD0 to MD2 4 Clock controller 5 Write-inhibit RAM 4 CTS0 SID0 to SID2 UART0 × 3 3 SOD0 to SOD2 4 ASR0 to ASR3 Internal data bus WI POT0 to POT3 PWC timer × 4 ICU (Input Capture Unit) ×4 24-bit timer counter 3 SCK0 to SCK2 SID3 SOD3 SCK3 UART1 8 OCU (Output Compare Unit) ×4 DOT0 to DOT7 8 16-bit reload timer ×6 6 TOT0 to TOT5 TIN1 to TIN5 ATG AN00 to AN15 AVCC AVRH AVRL AVSS 5 DTP/External interrupt ×8 16 21 10-bit A/D converter 16 channels External bus interface PPG0 PPG1 TRG0 22 102 I/O ports RAM ROM 2 16-bit PPG timer ×2 2 29 F2MC-16F CPU P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 PC0 to PC5 INT0 to INT7 D00 to D15 RDY HRQ A00 to A23 CLK HAK WRH WRL RD MB90220 Series ■ PROGRAMMING MODEL Dedicated Registers AL AH Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter USPCU User stack upper register SSPCU System stack upper register USPCL User stack lower register SSPCL System stack lower register DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional bank register 8 bit 16 bit 32 bit General-purpose Registers Max.32 banks Upper R7 R6 RW 7 R5 R4 RW 6 R3 R2 RW 5 R1 R0 RW 4 RL 3 RL 2 RW3 RL 1 RW 2 Lower RW 1 RL 0 RW 0 000180H + RP × 10H 16 bit MSB Processor Status (PS) ILM RP LSB — I S T N Z V C CCR 23 MB90220 Series ■ MEMORY MAP Single chip Internal ROM and external bus ROM area ROM area ROM area ROM area FF bank image FF bank image External ROM and external bus FFFFFFH Address #1 010000H Address #2 002000H Internal register area Internal register area Write-inhibit RAM Write-inhibit RAM Internal register area 001F00H Address #3 Write-inhibit RAM Address #4 : Internal 000380H RAM Registers RAM Registers RAM Registers 000180H : External 000100H 0000C0H Peripherals Peripherals Peripherals : No access 000000H Type 24 Address #1 Address #2 Address #3 Address #4 MB90223 FF0000H 004000H 000F00H 000D00H MB90224 MB90P224A/P224B MB90W224A/W224B FE8000H 004000H 001500H 001300H MB90V220 (FE0000H) 004000H 001900H 001500H MB90220 Series ■ I/O MAP Address Register Register name Access Resouce name Initial value 000000H*3 Port 0 data register PDR0 R/W Port 0 XXXXXXXX 000001H*3 Port 1 data register PDR1 R/W Port 1 XXXXXXXX 000002H*3 Port 2 data register PDR2 R/W Port 2 XXXXXXXX H*3 000003 Port 3 data register PDR3 R/W Port 3 XXXXXXXX 000004H*3 Port 4 data register PDR4 R/W Port 4 XXXXXXXX 000005H*3 Port 5 data register PDR5 R/W Port 5 XXXXXXXX 000006H Port 6 data register PDR6 R/W Port 6 11111111 000007H Port 7 data register PDR7 R Port 7 XXXXXXXX 000008H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 000009H Port 9 data register PDR9 R/W Port 9 11111111 00000AH Port A data register PDRA R/W Port A XXXXXXXX 00000BH Port B data register PDRB R/W Port B XXXXXXXX 00000CH Port C data register PDRC R/W Port C – – XXXXXX 00000DH to 0FH (Reserved area)*1 000010H*3 Port 0 data direction register DDR0 R/W Port 0 00000000 H*3 000011 Port 1 data direction register DDR1 R/W Port 1 00000000 000012H*3 Port 2 data direction register DDR2 R/W Port 2 00000000 000013H*3 Port 3 data direction register DDR3 R/W Port 3 00000000 H*3 000014 Port 4 data direction register DDR4 R/W Port 4 00000000 000015H*3 Port 5 data direction register DDR5 R/W Port 5 00000000 000016H Port 6 analog input enable register ADER0 R/W Port 6 11111111 000017H Port 7 data direction register DDR7 R/W Port 7 11111111 000018H Port 8 data direction register DDR8 R/W Port 8 00000000 000019H Port 9 analog input enable register ADER1 R/W Port 9 11111111 00001AH Port A data direction register DDRA R/W Port A 00000000 00001BH Port B data direction register DDRB R/W Port B 00000000 00001CH Port C data direction register DDRC R/W Port C ––0 0 0 0 0 0 00001DH to 1FH (Reserved area)*1 000020H Mode control register 0 UMC0 R/W 000021H Status register 0 USR0 R/W 000022H Input data register 0 /output data register 0 UIDR0 /UODR0 R/W 00000100 UART 0 (ch.0) 00010000 XXXXXXXX (Continued) 25 MB90220 Series Address Register Register name Access Resouce name 000023H Rate and data register 0 URD0 R/W 000024H Mode control register 1 UMC1 R/W 00000100 000025H Status register 1 USR1 R/W 00010000 000026H Input data register 1 /output data register 1 UIDR1 /UODR1 R/W 000027H Rate and data register 1 URD1 R/W 0000000X 000028H Mode control register 2 UMC2 R/W 00000100 000029H Status register 2 USR2 R/W 00010000 00002AH Input data register 2 /output data register 2 UIDR2 /UODR2 R/W 00002BH Rate and data register 2 URD2 R/W 00002CH UART CTS control register UCCR R/W 00002DH (Reserved area) UART0 (ch.0) Initial value UART0 (ch.1) UART0 (ch.2) 0000000X XXXXXXXX XXXXXXXX 0000000X UART0 (ch.0) –––000–– *1 00002EH Mode register SMR R/W 00000000 00002FH Control register SCR R/W 00000100 000030H Input data register /output data register SIDR /SODR R/W 000031H Status register SSR R/W 000032H A/D channel setting register ADCH R/W 000033H A/D mode register ADMD R/W 000034H A/D control status register ADCS R/W 000035H 000036H 000037H A/D data register ADCD R 00003AH DTP/interrupt enable register ENIR R/W 00003BH DTP/interrupt source register EIRR R/W Request level setting register ELVR R/W 00003EH to 3FH 000040H 000041H 00001–00 00000000 10-bit A/D converter – – – X0 0 0 0 0000––00 10-bit A/D converter XXXXXXXX 0 0 0 0 0 0 XX (Reserved area)*1 000039H 00003DH XXXXXXXX (Reserved area)*1 000038H 00003CH UART1 00000000 DTP/external interrupt 00000000 00000000 00000000 (Reserved area)*1 Timer control status register 0 TMCSR0 R/W 16-bit reload timer 0 00000000 ––––0000 (Continued) 26 MB90220 Series Address 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H Register name Access Timer control status register 1 TMCSR1 R/W 16-bit reload timer 1 00000000 Timer control status register 2 TMCSR2 R/W 16-bit reload timer 2 00000000 Timer control status register 3 TMCSR3 R/W 16-bit reload timer 3 00000000 Timer control status register 4 TMCSR4 R/W 16-bit reload timer 4 00000000 Timer control status register 5 TMCSR5 R/W 16-bit reload timer 5 00000000 PPG control status register 0 PCNT0 R/W 16-bit PPG timer 0 00000000 PPG control status register 1 PCNT1 R/W 16-bit PPG timer 1 00000000 PWC control status register 0 PWCSR0 R/W PWC timer 0 PWC control status register 1 PWCSR1 R/W PWC timer 1 PWC control status register 2 PWCSR2 R/W PWC timer 2 PWC control status register 3 PWCSR3 R/W PWC timer 3 ICC0 R/W ICU (Input Capture Unit) 00000000 ICU (Input Capture Unit) 00000000 Register ICU control register 0 000059H 00005AH Resouce name Initial value ––––0000 ––––0000 ––––0000 ––––0000 ––––0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (Reserved area)*1 Input capture control register 1 ICC1 R/W 00005BH 00005CH (Reserved area)*1 00005DH 00005EH 00005FH 000060H 000061H OCU control register 00 CCR00 R/W OCU (Output Compare Unit) 11110000 ––––0000 (Continued) 27 MB90220 Series Address 000062H 000063H Register OCU0 control register 01 Register name Access Resouce name Initial value CCR01 R/W OCU (Output Compare Unit) 11110000 ––––0000 000064H 000065H (Reserved area)*1 000066H 000067H 000068H 000069H 00006AH 00006BH OCU0 control register 10 CCR10 ––––0000 R/W OCU (Output Compare Unit) OCU0 control register 11 CCR11 R/W 00000000 ––––0000 00000000 00006CH 00006DH (Reserved area)*1 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H Free-run timer control register TCCR Free-run timer lower-order data register TCRL 11000000 R/W ––111111 24-bit timer counter R Free-run timer upper-order data register 00000000 00000000 00000000 TCRH 00000000 000076H 000077H (Reserved area)*1 000078H 000079H 00007AH PWC divider ratio control register 0 00007BH Reserved area 00007CH PWC divider ratio control register 1 00007DH Reserved area*1 00007EH PWC divider ratio control register 2 00007FH Reserved area*1 000080H PWC divider ratio control register 3 000081H to 8DH DIVR0 R/W PWC timer 0 ––––––00 DIVR1 R/W PWC timer 1 ––––––00 DIVR2 R/W PWC timer 2 ––––––00 DIVR3 R/W PWC timer 3 ––––––00 *1 (Reserved area)*1 (Continued) 28 MB90220 Series Address 00008EH Register WI control register Register name Access WICR R/W Resouce name Initial value Write-inhibit RAM – – – X– – – – 00008FH (Reserved area)*1 000090H to 9EH DIRR R/W Delay interrupt generation module –––––––0 Standby control register STBYC R/W Low power consumption 0001* * * * 0000A3H Address mid-order control register MACR W External pin ######## 0000A4H Address higher-order control register HACR W External pin ######## 0000A5H External pin control register EPCR W External pin ##0–0#00 0000A8H Watchdog timer control register WDTC R/W Watchdog timer XXXXXXXX 0000A9H Timebase timer control register TBTC R/W Timebase timer –––00000 0000B0H Interrupt control register 00 ICR00 R/W 00000111 0000B1H Interrupt control register 01 ICR01 R/W 00000111 0000B2H Interrupt control register 02 ICR02 R/W 00000111 0000B3H Interrupt control register 03 ICR03 R/W 00000111 0000B4H Interrupt control register 04 ICR04 R/W 00000111 0000B5H Interrupt control register 05 ICR05 R/W 00000111 0000B6H Interrupt control register 06 ICR06 R/W 00000111 0000B7H Interrupt control register 07 ICR07 R/W 0000B8H Interrupt control register 08 ICR08 R/W 0000B9H Interrupt control register 09 ICR09 R/W 00000111 0000BAH Interrupt control register 10 ICR10 R/W 00000111 0000BBH Interrupt control register 11 ICR11 R/W 00000111 0000BCH Interrupt control register 12 ICR12 R/W 00000111 0000BDH Interrupt control register 13 ICR13 R/W 00000111 0000BEH Interrupt control register 14 ICR14 R/W 00000111 0000BFH Interrupt control register 15 ICR15 R/W 00000111 00009FH Delay interrupt source generation /release register 0000A0H 0000C0H to FFH 001F00H 001F01H Interrupt controller 00000111 00000111 (External area)*2 PWC data buffer register 0 PWCR0 R/W PWC timer 0 00000000 00000000 (Continued) 29 MB90220 Series Address 001F02H 001F03H 001F04H 001F05H 001F06H 001F07H Register name Access PWC data buffer register 1 PWCR1 R/W PWC timer 1 PWC data buffer register 2 PWCR2 R/W PWC timer 2 PWC data buffer register 3 PWCR3 R/W PWC timer 3 Register 001F08H to 1F0FH 001F10H 001F11H 001F12H 001F13H 001F14H 001F15H 001F16H 001F17H 001F18H 001F19H 001F1AH 001F1BH 001F1CH 001F1DH 001F1EH 001F1FH 001F20H 001F21H 001F22H 001F23H 001F24H 001F25H 001F26H 001F27H Resouce name Initial value 00000000 00000000 00000000 00000000 00000000 00000000 (Reserved area)*1 OCU compare lower-order data register 00 00000000 CPR00L R/W OCU compare higher-order data register 00 CPR00 OCU compare lower-order data register 01 CPR01L CPR01 OCU compare lower-order data register 02 CPR02L CPR02 OCU compare lower-order data register 03 CPR03L CPR03 OCU compare lower-order data register 04 CPR04L CPR04 OCU compare lower-order data register 05 CPR05L CPR05 00000000 Output compare 02 00000000 00000000 00000000 00000000 Output compare 03 00000000 00000000 00000000 00000000 Output compare 10 00000000 00000000 00000000 00000000 R/W OCU compare higher-order data register 05 00000000 00000000 R/W OCU compare higher-order data register 04 Output compare 01 00000000 R/W OCU compare higher-order data register 03 00000000 00000000 R/W OCU compare higher-order data register 02 00000000 00000000 R/W OCU compare higher-order data register 01 Output compare 00 Output compare 11 00000000 00000000 00000000 (Continued) 30 MB90220 Series Address 001F28H 001F29H 001F2AH 001F2BH 001F2CH 001F2DH 001F2EH 001F2FH 001F30H 001F31H 001F32H 001F33H 001F34H 001F35H 001F36H 001F37H 001F38H 001F39H 001F3AH 001F3BH 001F3CH 001F3DH 001F3EH 001F3FH 001F40H 001F41H 001F42H 001F43H 001F44H 001F45H 001F46H 001F47H Register OCU compare lower-order data register 06 Register name Access Resouce name 00000000 CPR06L R/W OCU compare higher-order data register 06 CPR06 OCU compare lower-order data register 07 CPR07L CPR07 16-bit timer register 0 TMR0 Output compare 12 Output compare 13 W 16-bit timer register 1 TMR1 R TMRLR1 W TMR2 R W TMR3 R 16-bit timer register 4 TMRLR3 W TMR4 R 16-bit timer register 5 TMRLR4 W TMR5 R TMRLR5 W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit reload timer 0 16-bit timer reload register 5 XXXXXXXX XXXXXXXX 16-bit reload timer 4 16-bit timer reload register 4 XXXXXXXX XXXXXXXX 16-bit reload timer 3 16-bit timer reload register 3 XXXXXXXX XXXXXXXX 16-bit reload timer 2 TMRLR2 XXXXXXXX XXXXXXXX 16-bit reload timer 1 16-bit timer register 3 00000000 XXXXXXXX R TMRLR0 16-bit timer reload register 2 00000000 00000000 16-bit reload register 0 16-bit timer register 2 00000000 00000000 16-bit reload timer 0 16-bit timer reload register 1 00000000 00000000 R/W OCU compare higher-order data register 07 Initial value XXXXXXXX XXXXXXXX XXXXXXXX (Continued) 31 MB90220 Series (Continued) Address 001F48H 001F49H 001F4AH 001F4BH 001F4CH 001F4DH 001F4EH 001F4FH 001F50H 001F51H 001F52H 001F53H 001F54H 001F55H 001F56H 001F57H 001F58H 001F59H 001F5AH 001F5BH 001F5CH 001F5DH 001F5EH 001F5FH 001F60H to 1FFFH Register PPG cycle setting register 0 Register name Access PCSR0 W Resouce name XXXXXXXX 16-bit PPG timer 0 PPG duty setting register 0 PDUT0 W PPG cycle setting register 1 PCSR1 W PDUT1 W ICU lower-order data register 0 ICRL0 R ICRH0 R ICU lower-order data register 1 ICRL1 R ICRH1 R ICU lower-order data register 2 ICRL2 R ICRH2 R ICU lower-order data register 3 ICRL3 R ICRH3 R XXXXXXXX XXXXXXXX 00000000 XXXXXXXX XXXXXXXX XXXXXXXX 00000000 XXXXXXXX XXXXXXXX XXXXXXXX 00000000 XXXXXXXX Input capture 3 ICU higher-order data register 3 XXXXXXXX XXXXXXXX Input capture 2 ICU higher-order data register 2 XXXXXXXX XXXXXXXX Input capture 1 ICU higher-order data register 1 XXXXXXXX XXXXXXXX Input capture 0 ICU higher-order data register 0 XXXXXXXX XXXXXXXX 16-bit PPG timer 1 PPG duty setting register 1 Initial value XXXXXXXX XXXXXXXX 00000000 (Reserved area)*1 Initial value 0: The initial value of this bit is “0”. 1: The initial value of this bit is “1”. X: The initial value of this bit is undefined. –: This bit is not used. The initial value is undefined. *: The initial value of this bit varies with the reset source. #: The initial value of this bit varies with the operation mode. *1: Access prohibited *2: Only this area is open to external access in the area below address 0000FFH (inclusive). All addresses which are not described in the table are reserved areas, and accesses to these areas are handled in the same manner as for internal areas. The access signal for the external bus is not generated. *3: When an external bus is enable mode, never access to resisters which are not used as general ports in areas address 000000H to 000005H or 000010H to 000015H. 32 MB90220 Series ■ INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT CONTROL REGISTERS Interrupt source EI2OS support Interrupt vector Interrupt control register No. Address ICR Address Reset × #08 08H FFFFDCH — — INT9 instruction × #09 09H FFFFD8H — — Exception × #10 0AH FFFFD4H — — External interrupt #0 #11 0BH FFFFD0H External interrupt #1 #12 0CH FFFFCCH ICR00 0000B0H External interrupt #2 #13 0DH FFFFC8H Input capture 0 #14 0EH FFFFC4H ICR01 0000B1H PWC0 count completed/overflow #15 0FH FFFFC0H PWC1 count completed/overflow/input capture 1 #16 10H FFFFBCH ICR02 0000B2H PWC2 count completed/overflow/input capture 2 #17 11H FFFFB8H PWC3 count completed/overflow/input capture 3 #18 12H FFFFB4H ICR03 0000B3H 24-bit timer, overflow #19 13H FFFFB0H 24-bit timer, intermediate bit/timebase timer, interval interrupt #20 14H FFFFACH ICR04 0000B4H Compare 0 #21 15H FFFFA8H Compare 1 #22 16H FFFFA4H ICR05 0000B5H Compare 2 #23 17H FFFFA0H Compare 3 #24 18H FFFF9CH ICR06 0000B6H Compare 4/6 #25 19H FFFF98H Compare 5/7 #26 1AH FFFF94H ICR07 0000B7H 16-bit timer 0/1/2, overflow/PPG0 #27 1BH FFFF90H 16-bit timer 3/4/5, overflow/PPG1 #28 1CH FFFF8CH ICR08 0000B8H 10-bit A/D converter count completed #29 1DH FFFF88H ICR09 0000B9H UART1 transmission completed #31 1FH FFFF80H UART1 reception completed #32 20H FFFF7CH ICR10 0000BAH UART0 (ch.1) transmission completed #33 21H FFFF78H UART0 (ch.2) transmission completed #34 22H FFFF74H ICR11 0000BBH UART0 (ch.1) reception completed #35 23H FFFF70H UART0 (ch.2) reception completed #36 24H FFFF6CH ICR12 0000BCH UART0 (ch.0) transmission completed #37 25H FFFF68H ICR13 0000BDH (Continued) 33 MB90220 Series (Continued) Interrupt source EI2OS support UART0 (ch.0) reception completed Interrupt vector Interrupt control register No. Address ICR Address #39 27H FFFF60H ICR14 0000BEH Delay interrupt generation module × #42 2AH FFFF54H ICR15 0000BFH Stack fault × #255 FFH FFFC00H — — : EI2OS is supported (with stop request). : EI2OS is supported (without stop request). : EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used for one of the two, EI2OS and ordinary interrupt are not both available for the other (with stop request). : EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used for one of the two, EI2OS and ordinary interrupt are not both available for the other (without stop request). : EI2OS is not supported. Note: Since the interrupt sources having interrupt vector Nos. 15 to 18, 20, and 25 to 28 are OR’ed, respectively, select them by means of the interrupt enable bits of each resource. If EI2OS is used with the above-mentioned interrupt sources OR’ed with the interrupt vector Nos. 15 to 18, 20, and 25 to 28, be sure to activate one of the interrupt sources. Also in this case, a request flag in the same series as the one interrupt source is likely to be cleared automatically by EI2OS. Assume for example that an interrupt for compare 4 of the interrupt vector No. 25 is activated at this time by ICR07, so that the compare 6 is disabled. If EI2OS is activated at this time by ICR07, so that the compare 6 interrupt takes place during generation of or simultaneously with the compare 4 interrupt, not only the interrupt flag for the compare 4 but also that for the compare 6 will be automatically cleared after EI2OS is automatically transferred due to the compare 4 interrupt. 34 MB90220 Series ■ PERIPHERAL RESOURCES 1. Parallel Ports The MB90220 series has 86 I/O pins and 16 open-drain I/O pins. (1) Register Configuration • Port 0 to C Data Register (PDR0 to PDRC) Register name PDR1 PDR3 PDR5 PDR7 PDR9 PDRB Address 000001 H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 000003 H 000005 H PD x 7 PD x 6 PD x 5 PD x 4 PD x 3 PD x 2 PD x 1 PD x 0 XXXXXXXX B 000007 H 000009 H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (PDR9 only: 11111111) 00000B H PDR7 only: (R) (R) (R) (R) (R) (R) (R) (R) Register name PDR0 PDR2 PDR4 PDR6 PDR8 PDRA PDRC Address 000000 H 000002 H 000004 H 000006 H 000008 H 00000A H 00000C H bit7 bit6 bit5 PD x 7 PD x 6 PD x 5 (R/W) (R/W) (R/W) bit 4 bit3 PD x 4 PD x 3 (R/W) bit2 PD x 2 (R/W) bit1 bit0 PD x 1 PD x 0 (R/W) (R/W) (R/W) Initial value XXXXXXXX B (PDR6 only: 11111111) Note: There are no register bits for bits 7 and 6 of port C. • Port 0 to C Data Register (PDR0 to PDRC) Register name DDR1 DDR3 DDR5 DDR7 DDRB Address 000011 H 000013 H 000015 H 000017 H 00001B H Register name DDR0 DDR2 DDR4 DDR8 DDRA DDRC Address 000010 H 000012 H 000014 H 000018 H 00001A H 00001C H bit15 bit14 bit13 bit12 bit11 bit10 DD x 7 DD x 6 DD x 5 DD x 4 DD x 3 DD x 2 (R/W) (R/W) bit7 (R/W) bit6 (R/W) bit5 (R/W) bit 4 bit3 (R/W) (R/W) bit8 DD x 1 DD x 0 (R/W) (R/W) bit2 DD x 7 DD x 6 DD x 5 DD x 4 DD x 3 DD x 2 (R/W) (R/W) (R/W) Note: There are no register bits for bits 7 and 6 of port C. bit9 (R/W) bit1 Initial value 00000000 B (PDR7 only: 11111111) bit0 DD x 1 DD x 0 (R/W) (R/W) Initial value 00000000 B (R/W) • Port 6, 9 Analog Input Enable Register (ADER0, ADER1) Register name Address 000016 H ADER0 Register name Address ADER1 000019 H bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0 Initial value AE07 AE06 AE05 AE04 AE03 AE02 AE01 AE00 11111111 B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0 Initial value AE15 AE14 AE13 AE12 AE11 AE10 AE09 AE08 11111111 B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 35 MB90220 Series (2) Block Diagram • I/O Port (Port 0 to 5, 8, and A to C) Internal data bus Data register read Data register Pin Data register write Direction register Direction register write Direction register read • I/O Ports with an Open-drain output (Port 6, and 9) RMW (read-modify-write instruction) Internal data bus Data register read Pin Data register Data register write ADER ADER register write ADER register read • I/O Port (Port 7) DOT0 to DOT3 (OCU) Internal data bus 4 Data register read Pin 4 Direction register Direction register write 4 Port 7 Direction register read Note: Port 7 is input port. This pin also usable as I/O port for OCU internal function. 36 MB90220 Series 2. 16-bit Reload Timer (with Event Count Function) The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from among three internal clocks and one external clock. At the output pin (TOT), the pulses in the toggled output waveform are output in the reload mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin (TIN) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock mode. The MB90220 series has six channels for this timer. (1) Register Configuration • Timer Control Status Register 0 to 5 (TMCSR0 to TMCSR5) Register name TMCSR0 TMCSR1 TMCSR2 TMCSR3 TMCSR4 TMCSR5 Address 000041 H 000043 H 000045 H 000047 H 000049 H 00004B H Register name Address 000040 H TMCSR0 000042 H TMCSR1 000044H TMCSR2 000046 H TMCSR3 000048 H TMCSR4 00004A H TMCSR5 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value - - - - 0000 B — — — — CSL1 CSL0 MOD2 MOD1 (—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W) bit4 bit3 bit2 bit1 bit7 bit6 bit5 bit0 MOD0 OUTE OUTL RELD INTE UF CNTE TRG (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) bit12 bit11 bit10 bit9 bit8 Initial value 00000000 B • 16-bit Timer Register 0 to 5 (TMR0 to TMR5) Register name TMR0 TMR1 TMR2 TMR3 TMR4 TMR5 Address 001F31 H 001F35 H 001F39H 001F3D H 001F41 H 001F45H Register name Address TMR0 001F30 H TMR1 001F34 H TMR2 001F38H TMR3 001F3C H TMR4 001F40H TMR5 001F44 H bit15 bit14 bit13 Initial value XXXXXXXX B (R) (R) (R) bit7 (R) (R) bit6 (R) (R) bit5 (R) (R) bit4 (R) (R) bit3 (R) (R) bit2 bit1 bit0 (R) (R) (R) bit10 bit9 bit8 Initial value XXXXXXXX B • 16-bit Timer Reload Register 0 to 5 (TMRLR0 to TMRLR5) Register name TMRLR0 TMRLR1 TMRLR2 TMRLR3 TMRLR4 TMRLR5 Address 001F33 H 001F37 H 001F3BH 001F3F H 001F43 H 001F47 H bit15 bit14 bit13 bit12 bit11 Initial value XXXXXXXX B (W) (W) (W) (W) (W) (W) (W) (W) 37 MB90220 Series Register name TMRLR0 TMRLR1 TMRLR2 TMRLR3 TMRLR4 TMRLR5 Address 001F32 H 001F36 H 001F3A H 001F3E H 001F42 H 001F46 H bit7 bit6 bit5 bit4 bit3 bit2 bit1 Initial value bit0 XXXXXXXX B (W) (W) (W) (W) (W) (W) (W) (W) (2) Block Diagram 16 Internal data bus 16-bit reload register 8 Reload RELD UF 16-bit down counter OUTE 16 OUTL 2 INTE OUT CTL. GATE 2 CSL1 Clock selector CSL0 UF IRQ CNTE EI2OS clear TRG Retrigger 2 EXCK φ φ φ 21 23 25 IN Port (TIN) CTL. 3 Port (TOT) Prescaler clear MOD2 MOD1 Internal clock 3 38 MOD0 A/D (timer ch3 output) UART0 (timer ch5 output) UART1 (timer ch4 output) MB90220 Series 3. UART0 UART0 is a serial I/O port for synchronous or asynchronous communication with external resources. It has the following features: • • • • • • • • • Full duplex double buffer CLK synchronous and CLK asynchronous data transfers capable Multiprocessor mode support (Mode 2) Built-in dedicated baud-rate generator (12 rates) Arbitrary baud-rate setting from external clock input or internal timer Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit)) Error detection function (Framing, overrun, parity) Interrupt function (Two sources for transmission and reception) Transfer in NRZ format The MB90220 has three of these modules on chip. (1) Register Configuration • Mode Control Register 0 to 2 (UMC0 to UMC2) Serial mode control register Register name UMC0 UMC1 UMC2 Address 000020 H 000024 H 000028 H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PEN SBL MC1 MC0 SMDE RFC SCKE SOE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) bit12 bit11 bit10 bit9 Initial value 00000100 B • Status Register 0 to 2 (USR0 to USR2) Register name USR0 USR1 USR2 Address 000021 H 000025 H 000029 H bit15 bit14 bit13 bit8 RDRF ORFE PE TDRE RIE TIE RBF TBF (R) (R) (R) (R) (R/W) (R/W) (R) (R) Initial value 00001000 B • Input Data Register 0 to 2 (UIDR0 to UIDR2)/Ouput Data Register 0 to 2 (UODR0 to UODR2) Register name UIDR0/UODR0 UIDR1/UODR1 UIDR2/UODR2 Address 000022 H 000026 H 00002A H bit7 bit6 bit5 D7 D6 D5 (R/W) (R/W) (R/W) bit4 bit3 bit2 bit1 bit0 D4 D3 D2 D1 (R/W) (R/W) (R/W) (R/W) (R/W) bit11 bit10 bit9 bit8 Initial value XXXXXXXX B D0 • Rate and Data Register 0 to 2 (URD0 to URD2) Register name Address 000023 H URD0 000027 H URD1 00002B H URD2 bit15 bit14 bit13 bit12 BCH RC3 RC2 RC1 RC0 BCH0 P D8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 0000000X B • UART CTS Control Register (UCCR) Register name Address 00002C H UCCR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — — — CTE CSP CTSE — — (—) (—) (—) (R/W) (R/W) (R/W) (—) (—) Initial value - - - 000 - - B 39 MB90220 Series (2) Block Diagram CONTROL BUS Receiving interrupt (to CPU) Dedicated baud rate clock SCK 16-bit reload timer 5 (internally connected) Transmission interrupt (to CPU) Transmitting clock Clock selector Receiving clock External clock SID Receiving controller Transmission controller Start bit detector Transmission start circuit Received bit counter Transmitted bit counter Received parity counter Transmission parity counter SOD Received status determination circuit Receiving shifter Transmitting shifter Start of transmission End of reception UODR UIDR Signal indicating occurrence of receiving error for EI2OS (to CPU) Internal data bus UMC register PEN SBL MC1 MC0 SMDE RFC SCKE SOE USR register RDRF ORFE PE TDRE RIE TIE RBF TBF URD register BCH RC3 RC2 RC1 RC0 BCH P D8 CONTROL BUS 40 MB90220 Series 4. UART1 The UART1 is a serial I/O port for asynchronous communications (start-stop synchronization) or CLK synchronized communications. It has the following features: • • • • • • • • Full-duplex double buffering Permits asynchronous (start-stop synchronization) and CLK synchronous communications Multiprocessor mode support Built-in dedicated baud rate generator Asynchronous: 9615, 31250, 4808, 2404, and 1202 bps CLK synchronization: 1 M, 500 K, 250 K bps Arbitray baud-rate setting from external clock input or internal timer Error detection function (parity errors, framing errors, and overrun errors) Transfer in format NRZ Extended supports intelligent I/O service (1) Register Configuration • Mode Register (SMR) Register name Address 00002E H SMR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE 00000000B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value PEN P SBL CL A/D REC RXE TXE 00000100B (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W) • SCR (Control Register) Register name Address 00002F H SCR • Input Data Register (SIDR)/Serial Output Data Register (SODR) Register name Address 000030 H SIDR Register name Address 000030 H SODR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB (R) (R) (R) (R) (R) (R) (R) (R) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 (W) (W) (W) (W) (W) (W) (W) (W) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value PE ORE FRE RDRF TDRE — RIE TIE 00001-00B (R) (R) (R) (R) (R) (R/W) (R/W) XXXXXXXXB • SSR (Status Register) Register name Address 000031 H SSR 41 MB90220 Series (2) Block Diagram Control signals Receiving interrupt (to CPU) Dedicated baud rate generator SCK3 16-bit reload timer 4 (internally connected) Transmission interrupt (to CPU) Transmitting clock Clock selector Receiving clock External clock SID3 Receiving controller Transmission controller Start bit detector Transmission start circuit Received bit counter Transmitted bit counter Received parity counter Transmission parity counter SOD3 Received status determination circuit Receiving shifter Transmitting shifter End of reception Start of transmission SIDR SODR Signal indicating occurrence of receiving error for EI2OS (to CPU) Internal data bus SMR register MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE Control signals 42 MB90220 Series 5. 10-bit A/D Converter The 10-bit A/D converter converts analog input voltage into a digital value. The features of this module are described below: Conversion time: 6.125 µs/channel (min.) (with machine clock running at 16 MHz) Uses RC-type sequential comparison and conversion method with built-in sample and hold circuit 10-bit resolution Analog input can be selected by software from among 16 channels Single-conversion mode: Selects and converts one channel. Scan conversion mode: Converts several consecutive channels (up to 16 can be programmed). One-shot mode: Converts the specified channel once and terminates. Continuous conversion mode: Repeatedly converts the specified channel. Stop conversion mode: Pauses after converting one channel and waits until the next startup (permits synchronization of start of conversion). • When A/D conversion is completed, an “A/D conversion complete” interrupt request can be issued to the CPU. Because the generation of this interrupt can be used to start up the EI2OS and transfer the A/D conversion results to memory, this function is suitable for continuous processing. • Startup triggers can be selected from among software, an external trigger (falling edge), and a timer (rising edge). • • • • (1) Register Configuration • A/D Channel Setting Register (ADCH) This register specfies the A/D converter conversion channel. Register name Address 000032H ADCH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 B (R/W) • A/D Mode Register (ADMD) This register specfies the A/D converter operation mode and the startup source. Register name Address 000033H ADMD bit15 bit14 bit13 — — — (—) (—) (—) bit12 bit11 Reserved MOD1 (W) (R/W) bit10 bit9 bit8 MOD0 STS1 STS0 (R/W) (R/W) (R/W) bit1 bit0 Initial value - - - X0000 B Note: Program “0” to bit 12 when write. Read value is indeterminated. • A/D Control Status Register (ADCS) This register is the A/D converter control and status register. Register name Address 000034H ADCS bit7 bit6 bit5 bit4 bit3 bit2 BUSY INT INTE PAUS — — (R/W) (R/W) (R/W) (R/W) (—) (—) (W) STRT Reserved Initial value 0000 - - 00 B (R/W) • A/D Data Register (ADCD) This register stores the A/D converter conversion data. Register name Address 000036H ADCD bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (R) (R) (R) (R) (R) (R) (R) Initial value XXXXXXXX B 43 MB90220 Series Register name ADCD Address 000037H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 — — — — — — D9 D8 (R) (R) (R) (R) (R) (R) (R) (R) Initial value 000000XX B (2) Block Diagram AVCC AVRH/AVRL AVSS MPX AN0 AN1 AN2 D/A converter AN7 AN8 AN9 AN10 AN11 AN12 AN13 Sequential comparison register Internal data bus AN5 AN6 Input circuit AN3 AN4 Comparator Sample and hold circuit AN14 AN15 A/D data register Decoder ADCD A/D channel setting register ADCH A/D mode register ADMD A/D control status register ADCS Trigger startup ATG Timer startup Operation clock Timer (16-bit reload timer 3 output) φ Machine clock 44 Prescaler MB90220 Series 6. PWC (Pulse Width Count) Timer The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using these components, the PWC timer provides the following features: • Timer functions: • Pulse-width count functions: An interrupt request can be generated at set time intervals. Pulse signals synchronized with the timer cycle can be output. The reference internal clock can be selected from among three internal clocks. The time between arbitrary pulse input events can be counted. The reference internal clock can be selected from among three internal clocks. Various count modes: “H” pulse width (↑ to ↓)/“L” pulse width (↓ to ↑) Rising-edge cycle (↑ to ↑/Falling-edge cycle (↓ to ↓) Count between edges (↑ or ↓ to ↓ or ↑) Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input pulse, with an 8 bit input divider. An interrupt request can be generated once counting has been performed. The number of times counting is to be performed (once or subsequently) can be selected. The MB90220 series has four channels for this module. (1) Register Configuration • PWC Control Status Register 0 to 3 (PWCSR0 to PWCSR3) Register name PWCSR0 PWCSR1 PWCSR2 PWCSR3 Address 000051 H 000053 H 000055 H 000057 H Register name PWCSR0 PWCSR1 PWCSR2 PWCSR3 Address 000050 H 000052 H 000054 H 000056 H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 STRT STOP EDIR EDIE OVIR OVIE ERR POUT (R/W) (R) (R/W) (R/W) (R/W) (R) (R/W) (R/W) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CKS1 CKS0 PIS1 PIS0 S/C MOD1 MOD1 MOD0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B Initial value 00000000B • PWC Data Buffer Register 0 to 3 (PWCR0 to PWCR3) Register name PWCR0 PWCR1 PWCR2 PWCR3 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 001F01 H 001F03 H 001F05 H 001F07 H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Register name PWCR0 PWCR1 PWCR2 PWCR3 Address 001F00 H 001F02 H 001F04 H 001F06 H bit7 (R/W) bit6 (R/W) bit5 (R/W) bit4 (R/W) bit3 (R/W) bit2 (R/W) bit1 (R/W) bit0 Initial value 00000000B Initial value 00000000B (R/W) 45 MB90220 Series • PWC Division Ratio Control Register 0 to 3 (DIVR0 to DIVR3) Register name DIVR0 DIVR1 DIVR2 DIVR3 Address 00007A H 00007C H 00007E H 000080 H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — — — — — — MOD1 MOD0 (—) (—) (—) (—) (—) (—) (R/W) (R/W) Initial value - - - - - - 00B (2) Block Diagram PWCR read ERR Error detector 16 PWCR Write enable 16 Internal clock (machine clock/4) 16 Reload Data transfer Overflow 16 22 Clock 16-bit up-count timer Clock divider Internal data bus 23 Timer clear Count enable CKS 1 CKS 0 Divider clear Control bit output Flag set, etc. Controller Start edge End edge Division on/off select select Count start edge Edge detector Count end edge Count end interrupt request PIS 1 CKS 1 Overflow interrupt ERR PIS 0 CKS 0 request PWC*0 PWC 1 PWC 2 PWC 3 8-bit divider PIS 1 PIS 0 15 PWCSR Divider selection 2 DIVR Overflow F.F. POT *: In the MB90220 series, only the module input PWC 0 of each channel is connected to the respective external pins. Channel 46 POT pin PWC ch. 0 PA 1/PWC 0/POT 0 PWC ch. 1 PA 2/PWC 1/POT 1/ASR 1 PWC ch. 2 PWC ch. 3 PA 3/PWC 2/POT 2/ASR 2 PA 4/PWC 3POT 3/ASR 3 MB90220 Series 7. DTP/External Interrupts DTP (Data Transfer Peripheral) is located between external peripherals and the F2MC-16F CPU. It receives a DMA request or an interrupt request generated by the external peripherals and reports it to the F2MC-16F CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of “H” and “L” for extended intelligent I/O service or, and four request levels of “H,” “L,” rising edge and falling edge for external interrupt requests. In MB90220, only parts corresponding to INT2 to INT0 are usable as external interrupt/DTP request. Parts corresponding to INT7 to INT3 cannot be used as external interrupt/DTP request, but only for edge detection at external terminals. Note: INT7 to INT3 are not usable as DTP/external interrupts. (1) Register Configuration • DTP/Interrupt Enable Register (ENIR) Register name Address 00003A H ENIR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B • DTP/Interrupt Source Register (EIRR) Register name Address 00003B H EIRR bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B • Request Level Setting Register (ELVR) Register name Address 00003D H ELVR Register name Address 00003C H ELVR bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B (2) Block Diagram Internal data bus 4 4 4 8 Interrupt/DTP enable register Gate Source F/F Edge detector 8 INT Interrupt/DTP source register Request level setting register 47 MB90220 Series 8. 24-bit Timer Counter The 24-bit timer counter consists of a 24-bit up-counter, an 8-bit output buffer register, and a control register. The count value output by this timer counter is used to generate the base time used for input capture and output compare. The interrupt functions provided are timer overflow interrupts and timer intermediate bit interrupts. The intermediate bit interrupt permits four time settings. The 24-bit timer counter value is cleared to all zeroes by a reset. (1) Register Configuration • Free-run Timer Control Register (TCCR) Register name Address 000071 H TCCR Register name Address 000070 H TCCR bit15 bit14 — — bit13 (—) (—) (W) bit12 bit11 bit10 bit9 Reserved Reserved Reserved Reserved Reserved (W) (R/W) (R/W) (R/W) bit8 PR0 Initial value - - 111111B (R/W) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CLR2 CLR IVF IVFE TIM TIME TIS1 TIS0 (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 11000000B • Free-run Timer Low-order Data Register (TCRL) Register name Address bit15 000072 H TCRL 000073 H bit0 Initial value Access R 00000000 B TCRL • Free-run Timer High-order Data Register (TCRH) Register name Address bit15 000074 H TCRH 000075 H 48 bit8 bit7 — bit0 TCRH Initial value Access R 00000000 B MB90220 Series (2) Block Diagram Internal basic clock 2 2 φ/3 φ/4 Timer counter clocks CK0 CK1 CLR (prescaler clear) CLR2 (prescaler clear, 24-bit timer counter STOP bit) PR0 2 Clear bit CLR CLR/CLR2 2 2 CLR2 CK0 CK1 2 Higher-order 8-bit counter Lower-order 16-bit counter CK0, CK1 Timer counter bit output 8 T23 to T16 16 T0 to T15 Carry 4 8 Internal data bus “0” Output buffer 16 16 16 2 10th bit 11th bit 12th bit 13th bit TIS1 TIS0 Intermediate bit interrupt cycle setting 4 IVF IVFE TIM TIME 23rd bit Interrupt enable Interrupt flag Intermediate bit interrupt request TIM Overflow interrupt request IVF 49 MB90220 Series 9. OCU (Output Compare Unit) The OCU (Output Compare Unit) consists of a 24-bit output compare register, a comparator, and a control register. The match detection signal is output when the contents of the output compare register match the contents of the 24-bit timer counter. This match detection signal can be used to change the output value of the corresponding pin, or can be used to generate an interrupt. One block consists of four output compare units, and the four output compare registers use one comparator to perform time division comparisons. (1) Register Configuration • OCUO Control Register 00, 01 (CCR00, CCR01) Register name Address 000061 H CCR00 000063 H CCR02 Register name Address 000060 H CCR00 000062 H CCR02 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 — — — — MD3 MD2 MD1 MD0 (—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W) bit7 bit6 bit5 bit4 bit3 SEL3 SEL2 SEL1 SEL0 CPE3 (R/W) (R/W) (R/W) (R/W) (R/W) bit2 CPE2 bit1 CPE1 (R/W) bit0 CPE0 (R/W) Initial value - - - - 0000 Initial value 11110000 (R/W) • OCUO Control Register 10, 11 (CCR10, CCR11) Register name CCR10 CCR11 Address 000069 H 00006B H Register name Address CCR10 000068 H CCR11 00006A H bit15 bit14 bit13 bit12 bit11 bit10 bit9 ICE3 ICE2 ICE1 ICE0 IC3 IC2 IC1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) bit7 bit6 bit5 bit4 bit3 bit2 bit8 Initial value 00000000 IC0 (R/W) bit1 — — — — DOT3 DOT2 DOT1 DOT0 (—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W) bit0 Initial value - - - - 0000 • OCU Compare Low-order Data Register 00 to 07 (CPR00L to CPR07L) 50 Register name CPR00L CPR01L CPR02L CPR03L CPR04L CPR05L CPR06L CPR07L Address 001F11 H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 001F15 H 001F19 H 001F1D H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 001F21 H (R/W) 001F25 H 001F29 H 001F2D H Register name CPR00L CPR01L CPR02L CPR03L CPR04L CPR05L CPR06L CPR07L Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001F10 H 001F14 H 001F18 H — — 001F1C H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 001F20 H 001F24 H 001F28 H 001F2C H Initial value 00000000 Initial value 00000000 MB90220 Series • Output Compare High-order Data Register 00 to 07 (CPR00H to CPR07H) Register name CPR00 CPR01 CPR02 CPR03 CPR04 CPR05 CPR06 CPR07 Address 001F13 H 001F17 H 001F1B H 001F1F H 001F23 H 001F27 H 001F2B H 001F2F H Register name CPR00 CPR01 CPR02 CPR03 CPR04 CPR05 CPR06 CPR07 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001F12 H 001F16 H 001F1A H — — 001F1E H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 001F22 H 001F26 H 001F2A H 001F2E H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 00000000 (R) (R) (R) (R) (R) (R) (R) (R) Initial value 00000000 51 MB90220 Series (2) Block Diagram 24-bit timer counter Compare unit* T2 to T23 22 4 Match signal Comparator controller MATCH0 to 3 Interrupt enable ICE0 to 3 8 14 ICE3 Output latch Output latch ICE2 8 14 ICE1 24 CPR03 CPR03L ICE0 CPR02 CPR02L IC3 CPR01 CPR01L IC2 CPR00 CPR00L Interrupt request signals 24 4 24 24 ICMP0 to 3 IC1 Output Output compare register compare register higher-order 8 bits lower-order 16 bits IC0 Interrupt flags IC0 to 3 8 4 4 4 Internal data bus Match source signals EXT0 to 3 Match detection signal selection 4 Source selector Match operation enable 8 SEL3 SEL2 SEL1 SEL0 CPE3 CPE2 CPE1 CPE0 24-bit timer counter data T0 Port general purpose/compare dedicated switching 4 MD3 MD2 MD1 Clock selector MD0 4 DOT3 DOT2 DOT1 Output latch DOT pin data output (also serves as general-purpose port data register) 4 DOT0 4 DOT0 to 3 4 4 4 Pin Data register read Direction register Direction register write Direction register read Port 7 (Continued) 52 MB90220 Series (Continued) *: There are two compare units drawn as below. Internal data bus timer count data 4 23 16 16 Compare unit MATCH 0 to 3 T1 to T23 ICOMP 0 to 3 RB15 to 0 Compare 00 to 03 DOT 0 to 3 EXT 0 to 3 OPEN MATCH 0 to 3 T1 to T23 ICOMP 0 to 3 RB15 to 0 Compare 10 to 13 DOT 0 to 3 EXT 0 to 3 Interrupt request ICOMP 0 to 3 4 Pin output DOT 0 to 3 ICOMP 0, 2 2 OR 4 4 Pin output DOT 4 to 7 2 OR Interrupt request ICOMP 4/6 ICOMP 5/7 ICOMP 1, 3 53 MB90220 Series 10. ICU (Input Capture Unit) This module detects either the rising edge, falling edge, or both edges of an externally input waveform and holds the value of the 24-bit timer counter at that time, while at the same time the module generates an interrupt request for the CPU. The module consists of a 24-bit input capture data register and a control register. There are four external input pins (ASR0 to ASR3); the operation of each input is described below. ASR0 to ASR3: Each of these input pins has a corresponding input capture register. When the specified valid edge (↑ or ↓ or ↑ ↓) is detected, the register can be used to store the 24-bit timer counter value. (1) Register Configuration • ICU Control Register 0 (ICC0) Register name ICCO Address 000058 H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B • ICU Control Register 1 (ICC1) Register name Address ICCI 00005A H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1 IR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B (R/W) • ICU Low-order Data Register (ICRL0 to ICRL3) Register name ICRL0 ICRL1 ICRL2 ICRL3 Address 001F50 H 001F54 H 001F58 H 001F5C H Register name ICRL0 ICRL1 ICRL2 ICRL3 Address 001F51 H 001F55 H 001F59 H 001F5D H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D15 D14 D13 D12 D11 D10 D09 D08 (R) (R) (R) (R) (R) (R) (R) (R) bit7 D07 (R) bit6 bit5 bit4 bit3 bit2 bit1 bit0 D06 D05 D04 D03 D02 D01 D00 (R) (R) (R) (R) (R) (R) (R) Initial value XXXXXXXXB Initial value XXXXXXXXB • ICU High-order Data Register (ICRH0 to ICRH3) 54 Register name ICRH0 ICRH1 ICRH2 ICRH3 Address 001F52 H 001F56 H 001F5A H 001F5E H Register name ICRH0 ICRH1 ICRH2 ICRH3 Address 001F53 H 001F57 H 001F5B H 001F5F H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 — — — — — — — — (R) (R) (R) (R) (R) (R) (R) (R) bit7 bit6 bit5 bit4 bit3 bit2 bit1 Initial value XXXXXXXXB bit0 D23 D22 D21 D20 D19 D18 D17 D16 (R) (R) (R) (R) (R) (R) (R) (R) Initial value 00000000B MB90220 Series (2) Block Diagram 8 EG3B Internal data bus 24-bit timer counter input T23 8 T23 to to T0 24 T16 8 EG3A EG2B EG2A EG1B EG1A EG0B EG0A Edge detection polarity (ICC0) 8 16 T15 to T00 ICRH0 ICRL0 Edge detection 0 ICRH1 ICRL1 Edge detection 1 ICRH2 ICRL2 Edge detection 2 ICRH3 ICRL3 Edge detection 3 ASR0 ASR1 ASR2 ASR3 Edge detection 0 to 3: ↑ or ↓ or ↑↓ Output latch 4 EGO0 to EGO3 4 EGI0 to EGI3 16 IR0 Interrupt request flags (ICC1) IR1 4 IRQ0 to IRQ3 IR2 IR3 4 IRE3 4 Capture IRE2 IRE1 IRE0 Interrupt enable (ICC1) 55 MB90220 Series 11. 16-bit PPG Timer This module can output a pulse synchronized with an external trigger or a software trigger. In addition, the cycle and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values. PWM function: Synchronizes pulse with trigger, and permits programming of the pulse output by overwriting the register values mentioned above. This function permits use as a D/A converter with the addition of external circuits. One-shot function: Detects the edge of trigger input, and permits single-pulse output. There is no trigger input for PPG1. This module consists of a 16-bit down-counter, a prescaler, a 16-bit synchronization setting register, a 16-bit duty register, a 16-bit control register, one external trigger input pin, and one PPG output pin. (1) Register Configuration • PPG Control Status Register (PCNT0, PCNT1) Register name Address 0004D H PCNT0 0004F H PCNT1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 CNTE STGR MDSE RTRG CKS1 CKS0 PGMS — (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B (R/W) Overwrite during operation→ Register name Address 0004C H PCNT0 0004E H PCNT1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSEL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B Overwrite during operation→ • PPG0, PPG1 Cycle Setting Register (PCSP0, PCSP1) Register name Address 001F49 H PCSP0 001F4D H PCSP1 Register name Address PCSP0 001F48 H PCSP1 001F4C H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (W) (W) (W) (W) (W) (W) (W) (W) bit7 (W) Initial value XXXXXXXXB bit6 bit5 bit4 bit3 bit2 bit1 bit0 (W) (W) (W) (W) (W) (W) (W) Initial value XXXXXXXXB • PPG0, PPG1 Duty Setting Register (PDUT0, PDUT1) Register name Address 001F4B H PDUT0 001F4F H PDUT1 Register name Address 001F4A H PDUT0 001F4E H PDUT1 bit15 bit13 bit12 bit11 bit10 bit9 bit8 Initial value XXXXXXXXB (W) bit7 (W) 56 bit14 (W) (W) (W) (W) (W) (W) (W) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (W) (W) (W) (W) (W) (W) (W) Initial value XXXXXXXXB MB90220 Series (2) Block Diagram PCSR PDUT Prescaler 1/1 1/4 cmp ck Load 1/16 16-bit down-counter 1/64 Start Borrow PPG mask S Oscillation clock Q PPG output R Reverse bit Enable TRG input Interrupt selector IRQ Edge detection Software trigger 57 MB90220 Series 12. Watchdog Timer and Timebase Timer Functions The watchdog timer consists of a 2-bit watchdog counter using carry from an 18-bit timebase timer as the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18-bit timer and an interval interrupt control circuit. (1) Register Configuration • Watchdog Timer Control Register (WDTC) Register name Address 0000A8 H WDTC bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PONR STBR WRST ERST SRST WTE WT1 WT0 (R) (R) (R) (R) (R) (W) (W) (W) Initial value XXXXXXXX • Timebase Timer Control Register (TBTC) Register name Address 0000A9 H TBTC bit15 — bit14 — bit13 — bit12 bit11 bit10 bit9 bit8 TBIE TBOF TBR TBC1 TBC0 (—) (—) (—) (R/W) (R/W) (R) (R/W) (R/W) Initial value - - - XXXXX (2) Block Diagram Oscillation clock TBTC TBC1 Selector TBC0 212 214 216 218 TBTRES Clock input Timebase timer TBR TBIE AND Q 214 216 217 218 S R Internal data bus TBOF Timebase interrupt WDTC WT1 Selector WT0 2-bit counter OF CLR Watchdog reset signal generator CLR WDGRST To internal reset signal generator WTE PONR From power-on signal generator STBR From hardware standby controller WRST 58 ERST RST pin SRST From RST bit of STBYC register MB90220 Series 13. Delay Interruupt Generation Module The delayed interrupt generation module is used to generate an interrupt task switching. Using this module allows an interrupt request to the F2MC-16F CPU to generated or cancel by software. (1) Register Configuration • Delay Interrupt Source Generation/Cancel Register (DIRR) Register name Address DIRR 00009F H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 — — — — — — — R0 (—) (—) (—) (—) (—) (—) (—) (R/W) Initial value -------0 Internal data bus (2) Block Diagram Delay interrupt source generation/cancel decoder Source latch 59 MB90220 Series 14. Write-inhibit RAM The write-inhibit RAM is write-protectable with the WI pin input. Maintaining the “L” level input to the WI pin prevents a certain area of RAM from being written. The WI pin has a 4-machine-cycle filter. (1) Register Configuration • WI Control Register (WICR) Register name Address 00008E H WICR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 — — — WI — — — — (—) (—) (—) (R/W) (—) (—) (—) (—) Initial value ---X---- (2) Write-inhibit RAM Areas Write-inhibit RAM areas: 000D00H to 000EFFH (MB90223) 001300H to 0014FFH (MB90224/P224A/P224B/W224A/W224B) 001500H to 0018FFH (MB90V220) (3) Block Diagram Other area access 4-machine cycle smoothing circuit L S 4-machine cycle smoothing circuit H R WI Q S Priority Q R Write-inhibit circuit Select RAM decoder Internal data bus 60 WR Write-inhibit RAM MB90220 Series 15. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function The MB90220 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware standby mode, and gear function. Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data. The gear function divides the external clock frequency, which is used usually as it is, to provide a lower machine clock frequency. This function can therefore lower the overall operation speed without changing the oscillation frequency. The function can select the machine clock as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16. The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode or hardware standby mode. (1) Register Configuration • Standby Control Register (STBYC) Register name Address 0000A0 H STBYC bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value STP SLP SPL RST OSC1 OSC0 CLK1 CLK0 0001* * * * (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Note: The initial value (*) of bit0 to bit3 is changed by reset source. 61 MB90220 Series (2) Block Diagram Oscillation clock Gear divider 1/1 1/2 1/4 1/16 CPU clock STBYC CPU clock generator CLK1 Selector CLK0 Peripheral clock Peripheral clock generator SLP Standby controller STP Internal data bus RST Release HST start HST pin Interrupt request or RST OSC1 Selector OSC0 20 216 217 218 Clock input Timebase timer 214 SPL RST Pin high impedance controller Internal reset signal generator 216 217 218 Pin Hi-Z RST pin Internal RST To watchdog timer WDGRST 62 MB90220 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol Pin name Value Min. Max. Unit Remarks Power supply voltage VCC VCC VSS – 0.3 VSS + 7.0 V Program voltage VPP VPP VSS – 0.3 13.0 V MB90P224A/P224B MB90W224A/W224B AVCC AVCC VSS – 0.3 VCC + 0.3 V Power supply voltage for A/D converter AVRH AVRL AVRH AVRL Analog power supply voltage VSS – 0.3 AVCC V VSS – 0.3 VCC + 0.3 V Reference voltage for A/D converter Input voltage VI*1 Output voltage VO *2 VSS – 0.3 VCC + 0.3 V “L” level output current IOL 3 * — 20 mA Rush current “L” level total output current ΣIOL *3 — 50 mA Total output current “H” level output current IOH *2 — –10 mA Rush current “H” level total output current ΣIOH *2 — –48 mA Total output current Power consumption PD — — 650 mW Operating temperature TA — –40 +105 °C MB90223/224/P224B /W224B –40 +85 °C MB90P224A/W224A –55 +150 °C Storage temperature Tstg — — *1: V1 must not exceed VCC + 0.3 V. *2: Output pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, PA0 to PA7, PB0 to PB7, PC0 to PC5 *3: Output pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5 WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 63 MB90220 Series 2. Recommended Operating Condition (VSS = AVSS = 0.0 V) Parameter Power supply voltage Analog power supply voltage Clock frequency Operating temperature Symbol Pin name Value Unit Remarks Min. Max. 4.5 5.5 V When operating 3.0 5.5 V Retains the RAM state in stop mode Power supply voltage for A/D converter VCC VCC AVCC AVCC 4.5 VCC + 0.3 V AVRH AVRH AVRL AVCC V AVRL AVRL AVSS AVRH V 10 16 MHz MB90224/P224A/W224A MB90P224B/W224B 10 12 MHz MB90223 –40 +105 °C Single-chip mode MB90223/224/P224B/ W224B –40 +85 °C Single-chip mode MB90P224A/W224A –40 +70 °C External bus mode FC TA* — — Reference voltage for A/D converter * : Excluding the temperature rise due to the heat produced. WARNING:Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 64 MB90220 Series 3. DC Characteristics Single-chip mode MB90223/224/P224B/W224B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Parameter Symbol Pin name Condition Unit Remarks Min. Typ. Max. VIH “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage Input leackage current X0 — 0.7 VCC — VCC + 0.3 V CMOS level input 1 — 0.8 VCC — VCC + 0.3 V Hysteresis input VIHS * VIHM MD0 to MD2 — VCC – 0.3 — VCC + 0.3 V VIL X0 — VSS – 0.3 — 0.3 VCC V CMOS level input 1 — VSS – 0.3 — 0.2 VCC V Hysteresis input — VSS – 0.3 — VSS + 0.3 V VILS * VILM MD0 to MD2 VOH *2 VCC = 4.5 V IOH = –4.0 mA VCC – 0.5 — VCC V VOH1 X1 VCC = 4.5 V IOH = –2.0 mA VCC – 2.5 — VCC V VOL *3 VCC = 4.5 V IOL = 4.0 mA 0 — 0.4 V VOL1 X1 VCC = 4.5 V IOL = 2.0 mA 0 — VCC – 2.5 V II *1 VCC = 5.5 V 0.2 VCC < VI < 0.8 VCC — — ±10 µA II2 X0 VCC = 5.5 V 0.2 VCC < VI2 < 0.8 VCC — — ±20 µA RST — 22 50 110 kΩ *4 MB90223/224 MB90P224A/ W224A MD1 — 22 50 150 kΩ *4 MB90223/224 MD0 MD2 — 22 50 150 kΩ *4 MB90223/224 FC = 12 MHz — 70*5 100 mA MB90223 — 5 100 mA MB90224 Pull-up resistor RpulU Pull-down resistor RpulD FC = 16 MHz ICC 70* FC = 16 MHz — 90*5 125 MB90P224A/ P224B mA MB90W224A/ W224B fC = 16 MHz*9 — — 60 mA At sleep mode VCC Power supply voltage*8 ICCS ICCH Hysteresis input Except pins with pull-up/pulldown resistor and RST pin VCC VCC — — 5 10 µA In stop mode TA = +25°C At hardware standby (Continued) 65 MB90220 Series (Continued) Parameter Analog power supply voltage Input capacitance Symbol IA IAH CIN Pin name AVCC Condition fC = 16 MHz*9 *7 Value Min. Typ. Max. — 3 7 Unit Remarks mA 6 µA pF — — — 5* — — 10 — At stop mode *1: Hysteresis input pins RST, HST, P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5 *2: Ouput pins P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, PA0 to PA7, PB0 to PB7, PC0 to PC5 *3: Output pins P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5 *4: A list of availabilities of pull-up/pull-down resistors Pin name MB90223/224 MB90P224A/W224A RST Availability of pull-up resistors is optionally defined. MD1 Pull-up resistors available Unavailable Unavailable MD0, MD2 Pull-up resistors available Unavailable Unavailable *5: *6: *7: *8: Pull-up resistors available MB90P224B/W224B Unavailable VCC = +5.0 V, VSS = 0.0 V, TA = +25°C, FC = 16 MHz The current value applies to the CPU stop mode with A/D converter inactive (VCC = AVCC = AVRH = +5.5 V). Other than VCC, VSS, AVCC and AVSS Measurement condition of power supply current; external clock pin and output pin are open. Measurement condition of VCC; see the table above mentioned. *9: FC = 12 MHz for MB90223 66 MB90220 Series 4. AC Characteristics (1) Clock Timing Standards MB90223/224/P224B/W224B : (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Single-chip mode Parameter Clock frequency Clock cycle time Symbol Pin name X0, X1 FC tC X0, X1 Value Condition Min. — — Typ. Max. Unit Remarks 10 — 16 MHz MB90224/ P224A/P224B MB90W224A/ W224B 10 — 12 MHz MB90223 62.5 — 100 ns MB90224/ P224A/P224B MB90W224A/ W224B 83.4 — 100 ns MB90223 Input clock pulse width PWH PWL X0 — 0.4 tc — 0.6 tc ns Equivalent to 60% duty ratio Input clock rising/falling times tcr tcf X0 — — — 8 ns tcr + tcf tC = 1/fC • Clock Input Timings tc 0.7 VCC 0.7 VCC 0.7 VCC 0.3 VCC PWH 0.3 VCC PWL tcr tcf • Clock Conditions When a crystal or ceramic resonator is used X0 X1 When an external clock is used X0 X1 Open C1 C2 C1 = C2 = 10 pF Select the optimum capacity value for the resonator 67 MB90220 Series • Relationship between Clock Frequency and Supply Voltage VCC [V] Single-chip mode (MB90224/P224B/W224B) (MB90223) (MB90P224A/W224A) External bus mode : TA = –40°C to +105°C, Fc = 10 to 16 MHz : TA = –40°C to +105°C, Fc = 10 to 12 MHz : TA = –40°C to +85°C, Fc = 10 to 16 MHz : TA = –40°C to +70°C, Fc = 10 to 16 MHz (Fc = 10 to 12 MHz, only for MB90223) 5.5 Operation assurance range 4.5 0 68 10 12 16 Fc [MHz] MB90220 Series (2) Clock Output Timing Symbol Parameter Machine cycle time CLK ↑ → CLK↓ tCYC tCHCL (External bus mode: VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Pin Unit Remarks name Condition Min. Typ. Max. CLK 62.5 — 1600 ns MB90224/ P224A/P224B MB90W224A/ 224B 83.4 — 1600 ns MB90223 tCYC/2 – 20 — tCYC/2 ns Load condition: 80 pF CLK tCYC = n/FC, n gear ratio (1, 2, 4, 16) tCYC tCHCL CLK 1/2 VCC (3) Reset and Hardware Standby Input Standards Single-chip mode MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Symbol Pin name Reset input time tRSTL RST Hardware standby input time tHSTL HST Parameter Condition — Value Unit Min. Typ. Max. 5 tCYC — — ns 5 tCYC — — ns Remarks * *: The machine cycle time (tCYC) at hardware standby is set to 1/16 divided oscillation. tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC 69 MB90220 Series (4) Power on Supply Specifications (Power-on Reset) MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Single-chip mode Symbol Parameter Pin name Condition Value Min. Typ. Max. Unit Power supply rising time tR VCC — — — 30 ms Power supply cut-off time tOFF VCC — 1 — — ms Remarks * * : Before power supply rising, it is required to be VCC < 0.2 V. Notes: • Power-on reset assumes the above values. • Whether the power-on reset is required or not, turn the power on according to these characteristics and trigger the power-on reset. • There are internal registers (STBYC, etc.) which is initialized only by the power-on reset in the device. • Power-on Reset tR VCC 4.5 V 0.2 V 0.2 VCC 0.2 VCC tOFF Note: Note on changing power supply Even if above characteristics are not insufficient, abrupt changes in power supply voltage may cause a poweron reset. Therefore, at the time of a momentary changes such as when power is turned on, rise the power smoothly as shown below. • Changing Power Supply Main power supply voltage Subpower supply voltage Vss 70 This rising edge should be 50 mV/ms or less MB90220 Series (5) Bus Read Timing Parameter (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Symbol Pin name Condition Unit Remarks Min. Max. Valid address → RD ↓ time tAVRL A23 to A00 RD pulse width tRLRH RD RD ↓ → Valid data input tRLDV RD ↑ → Data hold time tRHDX D15 to D00 Load condition: 80 pF A23 to A00 Valid address → Valid data input tAVDV tCYC/2 – 20 — ns tCYC – 25 — ns — tCYC – 30 ns 0 — ns — 3 tCYC/2 – 40 ns tCYC/2 – 20 — ns RD ↑ → Address valid time tRHAX Valid address → CLK ↑ time tAVCH A23 to A00 CLK tCYC/2 – 25 — ns RD ↓ → CLK ↓ time tRLCL RD, CLK tCYC/2 – 25 — ns tAVCH tRLCL 0.7 VCC 0.3 VCC CLK tAVRL tRLRH RD 0.7 VCC 0.3 VCC tRHAX A23 to A00 0.7 VCC 0.3 VCC 0.7 VCC 0.3 VCC tRLDV tRHDX tAVDV D15 to D00 0.8 VCC 0.2 VCC 0.8 VCC Read data 0.2 VCC 71 MB90220 Series (6) Bus Write Timing Parameter Symbol (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Pin name Condition Unit Remarks Min. Max. Valid address → WR ↓ time tAVWL A23 to A00 tCYC/2 – 20 — ns WR pulse width tWLWH WRL, WRH tCYC – 25 — ns D15 to D00 Load D15 to D00 condition: 80 pF A23 to A00 tCYC – 40 — ns tCYC/2 – 20 — ns tCYC/2 – 20 — ns WRL, WRH, CLK tCYC/2 – 25 — ns Valid data output → WR ↑ time tDVWH WR ↑ → Data hold time tWHDX WR ↑ → Address valid time tWHAX WR ↓ → CLK ↓ time tWLCL tWLCL 0.3 VCC CLK tWLWH WR (WRL, WRH) 0.7 VCC 0.3 VCC tAVWL A23 to A00 tWHAX 0.7 VCC 0.7 VCC 0.3 VCC 0.3 VCC tDVWH D15 to D00 72 Indeterminate 0.7 VCC 0.3 VCC tWHDX Read data 0.7 VCC 0.3 VCC MB90220 Series (7) Ready Input Timing Symbol Pin name RDY setup time tRYHS RDY RDY hold time tRYHH RDY Parameter (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Condition Unit Remarks Min. Max. Load condition: 80 pF 40 — ns 0 — ns Note: Use the auto-ready function if the RDY setup time is insufficient. CLK 0.7 VCC 0.7 VCC A23 to A00 RD/WR (WRL, WRH) tRYHH tRYHS RDY No wait tRYHS tRYHH 0.8 VCC 0.8 VCC One wait 0.8 VCC 0.8 VCC 0.2 VCC (8) Hold Timing Symbol Pin name Pin floating → HAK ↓ time tXHAL HAK HAK ↑ time → pin valid time tHAHV HAK Parameter (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Condition Unit Remarks Min. Max. Load condition: 80 pF 30 tCYC ns tCYC 2 tCYC ns Note: It takes at least one machine cycle for HAK to vary after HRQ is fetched. HRQ 0.8 VCC 0.2 VCC 0.7 VCC HAK 0.3 VCC tHAHV tXHAL Each pin High impedance 73 MB90220 Series (9) UART Timing MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Pin Symbol name Condition Unit Remarks Parameter Min. Max. Single-chip mode 8 tCYC — ns –80 80 ns 100 — ns — 60 — ns tSHSL — 4 tCYC — ns tSLSH — 4 tCYC — ns — 150 ns Serial clock cycle time tSCYC — SCLK ↓ → SOUT delay time tSLOV — Valid SIN → SCLK ↑ tIVSH — SCLK ↑ → Valid SIN hold time tSHIX Serial clock “H” pulse width Serial clock “L” pulse width Load condition: 80 pF Load condition: 80 pF SCLK ↓ → SOUT delay time tSLOV — Valid SIN → SCLK ↑ tIVSH — 60 — ns SCLK ↑ → valid SIN hold time tSHIX — 60 — ns Notes: • These AC characteristics assume in CLK synchronization mode. • “tCYC” is the machine cycle (unit: ns). 74 Internal clock operation output pin External clock operation output pin MB90220 Series • Internal Shift Clock Mode tSCYC 0.7 VCC SCK 0.3 VCC 0.3 VCC tSLOV 0.7 VCC SOD 0.3 VCC tIVSH SID tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External Shift Clock Input Mode tSLSH tSHSL 0.8 VCC SCK 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SOD 0.7 VCC 0.3 VCC tIVSH SID tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 75 MB90220 Series (10) Resourse Input Timing MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Parameter Symbol Pin name Condition Unit Remarks Min. Typ. Max. External event 4 tCYC — — ns count input mode TIN1 to TIN5 Trigger input/gate — — ns 2 tCYC input mode tTIWH PWC0 to PWC3 Load 2 tCYC — — ns Input pulse width tTIWL ASR0 to ASR3 condition: 2 tCYC — — ns 80 pF INT0 to INT7 3 tCYC — — ns — — ns TRG0 2 tCYC ATG 2 tCYC — — ns tWIWL WI 4 tCYC — — ns Single-chip mode 0.8 VCC TIN1 to TIN5 PWC0 to PWC3 ASR0 to ASR3 INT0 to INT7 WI TRG0 ATG 0.8 VCC 0.2 VCC 0.2 VCC tTIWL, tWIWL tTIWH (11) Resourse Output Timing MB90223/224/P224B/W224B: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C) MB90P224A/W224A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C) Value Parameter Symbol Pin name Condition Unit Remarks Min. Typ. Max. TOT0 to TOT5 Load PPG0 to PPG1 CLK ↑ → TOUT condition: — — 30 ns tTO POT0 to POT3 transition time 80 pF DOT0 to DOT7 Single-chip mode CLK TOUT 0.7 VCC 0.7 VCC 0.3 VCC tTO 76 MB90220 Series 5. A/D Converter Electrical Characteristics Single-chip mode MB90223/224/P224B/W224B : (AVCC = VCC = +4.5 V to +5.5 V, AVSS =VSS = 0.0 V, TA = –40°C to +105°C, +4.5 V ≤ AVRH – AVRL) MB90P224A/W224A : (AVCC = VCC = +4.5 V to +5.5 V, AVSS = VSS =0.0 V, TA = –40°C to +85°C, +4.5 V ≤ AVRH – AVRL) External bus mode : (AVCC = VCC = +4.5 V to +5.5 V, AVSS = VSS =0.0 V, TA = –40°C to +70°C, +4.5 V ≤ AVRH – AVRL) Parameter Resolution Symbol n Pin name Condition — Value Unit Min. Typ. Max. — — — 10 bit Total error — — — — — ±3.0 LSB Linearity error — — — — — ±2.0 LSB Differential linearity error — — — — — ±1.5 LSB Zero transition voltage V0T Full-scale transition voltage VFST AN00 to AN15 Conversion time*1 TCONV — TSAMP — Sampling period Analog port input current IAIN Analog input voltage VAIN Analog reference voltage Reference voltage supply current Variation between channels — IR — AVRL – 1.5 AVRL + 0.5 AVRL + 2.5 LSB — AVRH – 3.5 AVRH – 1.5 AVRH + 0.5 LSB tCYC = 62.5 ns 6.125 — — µs 98 machine cycles 3.75 — — µs 60 machine cycles AN00 to AN15 — — — ±0.1 µA — AVRL — AVRH V AVRH — AVRL — AVCC V AVRL — AVSS — AVRH V — — 200 500 µA AVRH IRH — AN00 to AN15 Remarks — — — 5* — — — 4 2 µA LSB *1: These standards in this table are for MB90224/P224A/P224B/W224A/W224B. MB90223: Minimum conversion time is 8.17 µs and minimum sampling time is 5 µs at tCYC = 83.4 ns. *2: The current value applies to the CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = +5.5 V). Notes: (1) The error becomes larger as | AVRH – AVRL | becomes smaller. (2) Use the output impedance of the external circuit for analog input under the following conditions: External circuit output impedance < approx. 10 kΩ (Sampling time approx. 3.75 µs, tCYC = 62.5 ns) (3) Precision values are standard values applicable to sleep mode. (4) If VCC/AVCC or VSS/AVSS is caused by a noise to drop to below the analog input volgtage, the analog input current is likely to increase. In such cases, a bypass capacitor or the like should be provided in the external circuit to suppress the noise. 77 MB90220 Series • Analog Input Circuit Mode C0 Analog input Comparator RON1 RON2 RON1: Approx. 1.5 kΩ RON2: Approx. 1.5 kΩ C0: Approx. 60 pF C1 C1: Approx. 4 pF Note: The values shown here are reference values. 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. Total error: Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition error, linearity error, differential linearity error, or by noise. Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Digital output 11 1111 1111 11 1111 1110 11 1111 1101 • • • • Theoretical value (VNT) Theoretical value Actual conversion value Total error N+1 N N–1 • • • • • Linearity error 00 0000 0010 00 0000 0001 00 0000 0000 AVRL V0T V1T N × 1LSB + V0T V2T VFST – V0T 1 LSB = , 1022 78 VNT V(N + 1)T V(N – 1)T 1 LSB theoretical value = AVRH (V) VFST AVRH – AVRL 1022 Linearity error = VNT– (N × 1 LSB + V0T) 1 LSB N = 0 to 1022 VNT (N = 0) = V0T VNT (N = 1022) = VFST Differential linearity error = VNT – V(N–1)T – 1 1 LSB N = 1 to 1022 Total error = VNT – {(N + 0.5) × 1 LSB theoretical value} 1 LSB theoretical value N = 0 to 1022 MB90220 Series ■ EXAMPLE CHARACTERISTICS (1) Power Supply Current ICCH vs. TA example characteristics ICCH (µA) 40 ICC vs. TA example characteristics ICC (mA) 120 Fc = 16 MHz External clock input VCC = 5.0 V 110 100 90 VCC = 5 V 30 20 MB90P224A 80 10 70 MB90223 60 0 50 40 –50 0 50 TA (°C) 100 150 –10 –50 0 50 TA (°C) 100 150 Note: These are not assured value of characteristics but example characteristics. (2) Output Voltage VOH (V) 5.5 VOL (V) 2.0 VOH vs. IOH example characteristics TA = +25°C VCC = 5.0 V 5.0 1.5 4.5 1.0 4.0 0.5 3.5 0.0 VOL vs. IOL example characteristics TA = +25°C VCC = 5.0 V –0.5 3.0 –15 –10 –5 IOH (mA) 0 5 –5 0 5 10 15 20 25 IOL (mA) Note: These are not assured value of characteristics but example characteristics. 79 MB90220 Series (3) Pull-up/Pull-down Resistor Pull-down resistor example characteristics RpulD (kΩ) 100 Pull-up resistor example characteristics RpulU (kΩ) 100 VCC = 4.5 V 90 90 VCC = 5.0 V 80 80 VCC = 5.5 V 70 70 60 60 50 50 40 40 30 30 VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V 20 –50 0 50 TA (°C) 100 150 20 –50 0 50 TA (°C) Note: These are not assured value of characteristics but example characteristics. (4) Analog Filter Analog filter example characteristics Input pulse width (ns) 80 TA = +25°C 70 60 50 40 30 Filtering enable 20 10 4.0 4.5 5.0 VCC (V) 5.5 6.0 Note: These are not assured value of characteristics but example characteristics. 80 100 150 MB90220 Series ■ INSTRUCTION SET (412 INSTRUCTIONS) Table 1 Explanation of Items in Table of Instructions Item Mnemonic Explanation Upper-case letters and symbols: Represented as they appear in assembler Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table 4 for details about meanings of letters in items. B Indicates the correction value for calculating the number of actual cycles during execution of instruction. The number of actual cycles during execution of instruction is summed with the value in the “cycles” column. Operation Indicates operation of instruction. LH Indicates special operations involving the bits 15 through 08 of the accumulator. Z: Transfers “0”. X: Extends before transferring. —: Transfers nothing. AH Indicates special operations involving the high-order 16 bits in the accumulator. *: Transfers from AL to AH. —: No transfer. Z: Transfers 00H to AH. X: Transfers 00H or FFH to AH by extending AL. I S T N Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). *: Changes due to execution of instruction. —: No change. S: Set by execution of instruction. R: Reset by execution of instruction. Z V C RMW Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: Instruction is a read-modify-write instruction —: Instruction is not a read-modify-write instruction Note: Cannot be used for addresses that have different meanings depending on whether they are read or written. 81 MB90220 Series Table 2 Explanation of Symbols in Table of Instructions Symbol A Explanation 32-bit accumulator The number of bits used varies according to the instruction. Byte: Low order 8 bits of AL Word: 16 bits of AL Long: 32 bits of AL, AH AH High-order 16 bits of A AL Low-order 16 bits of A SP Stack pointer (USP or SSP) PC Program counter SPCU Stack pointer upper limit register SPCL Stack pointer lower limit register PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 io Compact direct addressing Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) (Continued) 82 MB90220 Series (Continued) Symbol #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp Explanation 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel ear eam Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) rlst Register list 83 MB90220 Series Table 3 Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Number of bytes in address extemsion* Register direct “ea” corresponds to byte, word, and long-word types, starting from the left — 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 Register indirect 0 0C 0D 0E 0F @RW0 + @RW1 + @RW2 + @RW3 + Register indirect with post-increment 0 10 11 12 13 14 15 16 17 @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 Register indirect with 8-bit displacement 1 18 19 1A 1B @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 Register indirect with 16-bit displacemen 2 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + dip16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 * : The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the Table of Instructions. 84 MB90220 Series Table 4 Code Number of Execution Cycles for Each Form of Addressing Operand (a)* Number of execution cycles for each from of addressing Listed in Table of Instructions 00 to 07 Ri RWi RLi 08 to 0B @RWj 1 0C to 0F @RWj + 4 10 to 17 @RWi + disp8 1 18 to 1B @RWj + disp16 1 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + dip16 @addr16 2 2 2 1 * : “(a)” is used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand (b)* (c)* (d)* byte word long Internal register + 0 + 0 + 0 Internal RAM even address + 0 + 0 + 0 Internal RAM odd address + 0 + 1 + 2 Even address not in internal RAM + 1 + 1 + 2 Odd address not in internal RAM + 1 + 3 + 6 External data bus (8 bits) + 1 + 3 + 6 * : “(b)”, “(c)”, and “(d)” are used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions. 85 MB90220 Series Table 6 Mnemonic B Operation 2 2 2 3 1 1 1 2 2+ 2+ (a) 2 2 2 2 2 2 6 3 3 3 3 5 2 2 1 1 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi))+disp8) byte (A) ← ((SP)+disp8) byte (A) ←(addr24) byte (A) ← ((A)) byte (A) ← imm4 Z Z Z Z Z Z Z Z Z Z Z Z Z * * * * * * * – * * * – * – – – – – – – – – – – – – 2 2 MOVX A, dir 2 3 MOVX A, addr16 1 2 MOVX A, Ri 1 2 MOVX A, ear 2+ 2+ (a) MOVX A, eam 2 2 MOVX A, io 2 2 MOVX A, #imm8 2 2 MOVX A, @A 3 MOVX A,@RWi+disp8 2 6 MOVX A, @RLi+disp8 3 3 MOVX A, @SP+disp8 3 3 5 MOVPX A, addr24 2 2 MOVPX A, @A (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi))+disp8) byte (A) ← ((RLi))+disp8) byte (A) ← ((SP)+disp8) byte (A) ←(addr24) byte (A) ← ((A)) X X X X X X X X X X X X X * * * * * * * – * * * * – MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOVP MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, @SP+disp8 A, addr24 A, @A A, #imm4 # Transfer Instructions (Byte) [50 Instructions] cycles LH AH I S T N Z V – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * – – – – – – – – – – – – – C – – – – – – – – – – – – – RMW * * * * * * * * * * * * R – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV MOV MOV MOV MOV MOV MOV MOV MOVP dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A @SP+disp8, A addr24, A 2 2 2 3 1 1 2 2 2+ 2+ (a) 2 2 6 3 3 3 3 5 (b) (b) 0 0 (b) (b) (b) (b) (b) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi)) +disp8) ← (A) byte ((SP)+disp8) ← (A) byte (addr24) ← (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV MOV MOVP MOV MOV MOV MOV MOV MOV MOV Ri, ear Ri, eam @A, Ri ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 2 2 2+ 3+ (a) 3 2 3 2 2+ 3+ (a) 2 2 3 3 3 3 2 3 3+ 2+ (a) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) byte (Ri) ← (ear) byte (Ri) ← (eam) byte ((A)) ← (Ri) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * – – * – * * * * * * – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV @AL, AH 2 (b) byte ((A)) ← (AH) – – – – – * * – – – 2 (Continued) 86 MB90220 Series (Continued) Mnemonic XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam # cycles B 0 3 2 2+ 3+ (a) 2× (b) 0 4 2 2+ 5+ (a) 2× (b) Operation byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) LH AH Z Z – – – – – – I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 87 MB90220 Series Table 7 Mnemonic # Transfer Instructions (Word) [40 Instructions] cycles B Operation LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVW A, dir MOVW A, addr16 MOVW A, SP MOVW A, RWi MOVW A, ear MOVW A, eam MOVW A, io MOVW A, @A MOVW A, #imm16 MOVW A, @RWi+disp8 MOVW A, @RLi+disp8 MOVW A, @SP+disp8 MOVPW A, addr24 MOVPW A, @A 2 2 2 3 2 1 1 1 1 2 2+ 2+ (a) 2 2 2 2 2 3 3 2 6 3 3 3 3 5 2 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi) +disp8) word (A) ← ((RLi) +disp8) word (A) ← ((SP) +disp8 word (A) ← (addr24) word (A) ← ((A)) – – – – – – – – – – – – – – * * * * * * * – * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * MOVW dir, A MOVW addr16, A MOVW SP, # imm16 MOVW SP, A MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW @SP+disp8, A MOVPW addr24, A MOVPW @A, RWi MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) word (dir) ← (A) word (addr16) ← (A) word (SP) ← imm16 word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi) +disp8) ← (A) word ((RLi) +disp8) ← (A) word ((SP) +disp8) ← (A) word (addr24) ← (A) word ((A)) ← (RWi) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * – * – * * * * * * * * * * * * * * * * * * – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVW @AL, AH 2 2 (c) word ((A)) ← (AH) – – – – – * * – – – XCHW XCHW XCHW XCHW 0 3 2 2+ 3+ (a) 2× (c) 0 4 2 2+ 5+ (a) 2× (c) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – A, ear A, eam RWi, ear RWi, eam Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 88 MB90220 Series Table 8 Mnemonic # Transfer Instructions (Long Word) [11 Instructions] cycles 1 2 MOVL A, ear 2+ 3+ (a) MOVL A, eam 3 5 MOVL A, # imm32 4 MOVL A, @SP + disp8 3 4 5 MOVPL A, addr24 3 2 MOVPL A, @A MOVPL @A, RLi 2 5 4 MOVL @SP + disp8, A 3 4 5 MOVPL addr24, A 2 2 MOVL ear, A 2+ 3+ (a) MOVL eam, A B Operation LH AH I S T N Z V C RMW 0 (d) 0 (d) (d) (d) long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 long (A) ← ((SP) +disp8) long (A) ← (addr24) long (A) ← ((A)) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – (d) long ((A)) ← (RLi) – – – – – * * – – – (d) (d) 0 (d) long ((SP) + disp8) ← (A) long (addr24) ← (A) long (ear) ← (A) long (eam) ← (A) – – – – – – – – – – – – – – – – – – – – * * * * * * * * – – – – – – – – – – – – For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 89 MB90220 Series Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] Mnemonic # cycles B Operation LH AH I S T N Z V C RMW ADD A, #imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A 0 2 2 (b) 3 2 0 2 2 2+ 3+ (a) (b) 0 2 2 2+ 3+ (a) 2× (b) 0 2 1 0 2 2 2+ 3+ (a) (b) 0 3 1 byte (A) ← (A) +imm8 byte (A) ← (A) +(dir) byte (A) ← (A) +(ear) byte (A) ← (A) +(eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear) + (C) byte (A) ← (A) + (eam) + (C) byte (A) ← (AH) + (AL) + (C) (Decimal) Z Z Z Z – Z Z Z Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – * * – – – – SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC 0 2 2 (b) 3 2 0 2 2 2+ 3+ (a) (b) 0 2 2 2+ 3+ (a) 2× (b) 0 2 1 0 2 2 2+ 3+ (a) (b) 0 3 1 byte (A) ← (A) –imm8 byte (A) ← (A) – (dir) byte (A) ← (A) – (ear) byte (A) ← (A) – (eam) byte (ear) ← (ear) – (A) byte (eam) ← (eam) – (A) byte (A) ← (AH) – (AL) – (C) byte (A) ← (A) – (ear) – (C) byte (A) ← (A) – (eam) – (C) byte (A) ← (AH) – (AL) – (C) (Decimal) Z Z Z Z – – Z Z Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – * * – – – – ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam 0 2 1 0 2 2 2+ 3+ (a) (c) 0 2 3 0 2 2 2+ 3+ (a) 2× (c) 0 2 2 2+ 3+ (a) (c) word (A) ← (AH) + (AL) word (A) ← (A) +(ear) word (A) ← (A) +(eam) word (A) ← (A) +imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – * * – – SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam 0 2 1 0 2 2 2+ 3+ (a) (c) 0 2 3 0 2 2 2+ 3+ (a) 2× (c) 0 2 2 2+ 3+ (a) (c) word (A) ← (AH) – (AL) word (A) ← (A) – (ear) word (A) ← (A) – (eam) word (A) ← (A) –imm16 word (ear) ← (ear) – (A) word (eam) ← (eam) – (A) word (A) ← (A) – (ear) – (C) word (A) ← (A) – (eam) – (C) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – * * – – ADDL ADDL ADDL A, ear A, eam A, #imm32 5 2 2+ 6+ (a) 4 5 0 (d) 0 long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) +imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – SUBL SUBL SUBL A, ear A, eam A, #imm32 5 2 2+ 6+ (a) 4 5 0 (d) 0 long (A) ← (A) – (ear) long (A) ← (A) – (eam) long (A) ← (A) –imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 90 MB90220 Series Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] Mnemonic # cycles B Operation LH AH I S T N Z V C RMW INC INC ear eam byte (ear) ← (ear) +1 0 2 2 2+ 3+ (a) 2× (b) byte (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – * * DEC DEC ear eam byte (ear) ← (ear) –1 0 2 2 2+ 3+ (a) 2× (b) byte (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – * * INCW INCW ear eam word (ear) ← (ear) +1 0 2 2 2+ 3+ (a) 2× (c) word (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – * * DECW ear DECW eam word (ear) ← (ear) –1 0 2 2 2+ 3+ (a) 2× (c) word (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – * * INCL INCL ear eam long (ear) ← (ear) +1 0 4 2 2+ 5+ (a) 2× (d) long (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – * * DECL DECL ear eam long (ear) ← (ear) –1 0 4 2 2+ 5+ (a) 2× (d) long (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – * * For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 11 Mnemonic # Compare Instructions (Byte/Word/Long Word) [11 Instructions] cycles B Operation LH AH I S T N Z V C RMW CMP CMP CMP CMP A A, ear A, eam A, #imm8 2 1 2 2 2+ 2+ (a) 2 2 0 0 (b) 0 byte (AH) – (AL) byte (A) – (ear) byte (A) – (eam) byte (A) – imm8 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPW CMPW CMPW CMPW A A, ear A, eam A, #imm16 2 1 2 2 2+ 2+ (a) 2 3 0 0 (c) 0 word (AH) – (AL) word (A) – (ear) word (A) – (eam) word (A) – imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPL A, ear CMPL A, eam CMPL A, #imm32 3 2 2+ 4+ (a) 3 5 0 (d) 0 long (A) – (ear) long (A) – (eam) long (A) – imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 91 MB90220 Series Table 12 Mnemonic Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions] # cycles DIVU A 1 * DIVU A, ear 2 *2 DIVU A, eam 2+ *3 DIVUW A, ear 2 *4 DIVUW A, eam 2+ *5 MULU A 1 MULU A, ear 2 MULU A, eam 2+ MULUW A 1 MULUW A, ear 2 MULUW A, eam 2+ *8 *9 *10 *11 *12 *13 1 B Operation 0 word (AH) /byte (AL) Quotient → byte (AL) Remainder → byte (AH) 0 word (A)/byte (ear) Quotient → byte (A) Remainder → byte (ear) *6 word (A)/byte (eam) Quotient → byte (A) Remainder → byte (eam) 0 long (A)/word (ear) Quotient → word (A) Remainder → word (ear) *7 long (A)/word (eam) Quotient → word (A) Remainder → word (eam) 0 0 (b) 0 0 (c) byte (AH) × byte (AL) → word (A) byte (A) × byte (ear) → word (A) byte (A) × byte (eam) → word (A) word (AH) × word (AL) → long (A) word (A) × word (ear) → long (A) word (A) × word (eam) → long (A) LH AH I S T N Z V C RMW – – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – For an explanation of “(b)” and “(c), refer to Table 5, “Correction Values for Number of Cycle Used to Calculate Number of Actual Cycles.” *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: 92 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally. (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not 0. 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not 0. 3 when word (ear) is zero, and 11 when word (ear) is not 0. 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0. MB90220 Series Table 13 Mnemonic Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions] # cycles DIV A 2 * DIV A, ear 2 *2 DIV A, eam 2+ *3 DIVW A, ear 2 *4 DIVW A, eam 2+ *5 2 MUL A 2 MUL A, ear MUL A, eam 2+ MULW A 2 MULW A, ear 2 MULW A, eam 2+ *8 *9 *10 *11 *12 *13 1 B Operation 0 word (AH) /byte (AL) Quotient → byte (AL) Remainder → byte (AH) 0 word (A)/byte (ear) Quotient → byte (A) Remainder → byte (ear) *6 word (A)/byte (eam) Quotient → byte (A) Remainder → byte (eam) 0 long (A)/word (ear) Quotient → word (A) Remainder → word (ear) *7 long (A)/word (eam) Quotient → word (A) Remainder → word (eam) 0 0 (b) 0 0 (b) byte (AH) × byte (AL) → word (A) byte (A) × byte (ear) → word (A) byte (A) × byte (eam) → word (A) word (AH) × word (AL) → long (A) word (A) × word (ear) → long (A) word (A) × word (eam) → long (A) LH AH I S T N Z V C RMW Z – – – – – – * * – Z – – – – – – * * – Z – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – For an explanation of “(b)” and “(c)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally. (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally. 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation. 93 MB90220 Series Table 14 Mnemonic # cycles Logical 1 Instructions (Byte, Word) [39 Instructions] B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A, #imm8 A, ear A, eam ear, A eam, A 0 2 2 0 2 2 2+ 3+ (a) (b) 0 3 2 2+ 3+ (a) 2× (b) byte (A) ← (A) and imm8 byte (A) ← (A) and (ear) byte (A) ← (A) and (eam) byte (ear) ← (ear) and (A) byte (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – * * OR OR OR OR OR A, #imm8 A, ear A, eam ear, A eam, A 0 2 2 0 2 2 2+ 3+ (a) (b) 0 3 2 2+ 3+ (a) 2× (b) byte (A) ← (A) or imm8 byte (A) ← (A) or (ear) byte (A) ← (A) or (eam) byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – * * XOR XOR XOR XOR XOR NOT NOT NOT A, #imm8 A, ear A, eam ear, A eam, A A ear eam 0 2 2 0 2 2 2+ 3+ (a) (b) 0 3 2 2+ 3+ (a) 2× (b) 0 2 1 0 2 2 2+ 3+ (a) 2× (b) byte (A) ← (A) xor imm8 byte (A) ← (A) xor (ear) byte (A) ← (A) xor (eam) byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A) byte (A) ← not (A) byte (ear) ← not (ear) byte (eam) ← not (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * R R R R R R R R – – – – – – – – – – – * * – * * ANDW ANDW ANDW ANDW ANDW ANDW A A, #imm16 A, ear A, eam ear, A eam, A 0 2 1 0 2 3 0 2 2 2+ 3+ (a) (c) 0 3 2 2+ 3+ (a) 2× (c) word (A) ← (AH) and (A) word (A) ← (A) and imm16 word (A) ← (A) and (ear) word (A) ← (A) and (eam) word (ear) ← (ear) and (A) word (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – * * ORW ORW ORW ORW ORW ORW A A, #imm16 A, ear A, eam ear, A eam, A 0 2 1 0 2 3 0 2 2 2+ 3+ (a) (c) 0 3 2 2+ 3+ (a) 2× (c) word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – * * XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A A, #imm16 A, ear A, eam ear, A eam, A A ear eam 0 2 1 0 2 3 0 2 2 2+ 3+ (a) (c) 0 3 2 2+ 3+ (a) 2× (c) 0 2 1 0 2 2 2+ 3+ (a) 2× (c) word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A) word (A) ← not (A) word (ear) ← not (ear) word (eam) ← not (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * R R R R R R R R R – – – – – – – – – – – – – * * – * * For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 94 MB90220 Series Table 15 Mnemonic # cycles Logical 2 Instructions (Long Word) [6 Instructions] B Operation LH AH I S T N Z V C RMW ANDL A, ear ANDL A, eam 5 2 2+ 6+ (a) 0 (d) long (A) ← (A) and (ear) long (A) ← (A) and (eam) – – – – – – – – – – * * * * R R – – – – ORL ORL A, ear A, eam 5 2 2+ 6+ (a) 0 (d) long (A) ← (A) or (ear) long (A) ← (A) or (eam) – – – – – – – – – – * * * * R R – – – – XORL A, ear XORL A, eam 5 2 2+ 6+ (a) 0 (d) long (A) ← (A) xor (ear) long (A) ← (A) xor (eam) – – – – – – – – – – * * * * R R – – – – For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 16 Mnemonic Sign Inversion Instructions (Byte/Word) [6 Instructions] # cycles B 2 0 Operation byte (A) ← 0 – (A) NEG A 1 NEG NEG ear eam 2 2 0 byte (ear) ← 0 – (ear) 2+ 3+ (a) 2× (b) byte (eam) ← 0 – (eam) 2 0 word (A) ← 0 – (A) NEGW A 1 NEGW ear NEGW eam 2 2 0 word (ear) ← 0 – (ear) 2+ 3+ (a) 2× (c) word (eam) ← 0 – (eam) LH AH I S T N Z V C RMW X – – – – * * * * – – – – – – – – – – – * * * * * * * * * * – – – – – * * * * – – – – – – – – – – – * * * * * * * * * * For an explanation of “(a)”, “(b)” and “(c)” and refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 17 Mnemonic ABS A ABSW A ABSL A Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions] # cycles B Operation 2 2 2 2 2 4 0 0 0 byte (A) ← absolute value (A) word (A) ← absolute value (A) long (A) ← absolute value (A) Table 18 Mnemonic # cycles B NRML A, R0 2 * 0 LH AH Z – – – – – I S T N Z V C RMW – – – – – – – – – * * * * * * * * * – – – – – – Normalize Instructions (Long Word) [1 Instruction] Operation long (A) ← Shifts to the position at which “1” was set first byte (R0) ← current shift count LH AH – – I S T N Z V C RMW – – * – – – – – * : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases. 95 MB90220 Series Table 19 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ear eam ear eam ASR LSR LSL A, R0 A, R0 A, R0 Shift Instructions (Byte/Word/Long Word) [27 Instructions] # cycles B 2 2 2 2 0 0 2 2 0 2+ 3+ (a) 2× (b) 2 2 0 2+ 3+ (a) 2× (b) Operation LH AH I S T N Z V C RMW byte (A) ← Right rotation with carry byte (A) ← Left rotation with carry – – – – – – – – – – * * * * – – * * – – byte (ear) ← Right rotation with carry byte (eam) ← Right rotation with carry byte (ear) ← Left rotation with carry byte (eam) ← Left rotation with carry – – – – – – – – – – – – – – – – – – – – * * * * * * * * – – – – * * * * * * * * 2 2 2 *1 *1 *1 0 0 0 byte (A) ← Arithmetic right barrel shift (A, R0) – byte (A) ← Logical right barrel shift (A, R0) – byte (A) ← Logical left barrel shift (A, R0) – – – – – – – – – – * * – * * * * * * – – – * * * – – – ASR A, #imm8 3 LSR A, #imm8 3 LSL A, #imm8 3 *3 *3 *3 0 0 0 byte (A) ← Arithmetic right barrel shift (A, imm8) – byte (A) ← Logical right barrel shift (A, imm8) – byte (A) ← Logical left barrel shift (A, imm8) – – – – – – – – – – * * – * * * * * * – – – * * * – – – ASRW A LSRW A/SHRW A 1 LSLW A/SHLW A 1 2 2 2 0 0 0 word (A) ← Arithmetic right shift (A, 1 bit) word (A) ← Logical right shift (A, 1 bit) word (A) ← Logical left shift (A, 1 bit) – – – – – – – – – – – – * * * R – * * * * – – – * * * – – – ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 *1 *1 *1 0 0 0 word (A) ← Arithmetic right barrel shift (A, R0) word (A) ← Logical right barrel shift (A, R0) word (A) ← Logical left barrel shift (A, R0) – – – – – – – – – – – – * * – * * * * * * – – – * * * – – – ASRW A, #imm8 LSRW A, #imm8 LSLW A, #imm8 3 3 3 *3 *3 *3 0 0 0 word (A) ← Arithmetic right barrel shift (A, imm8) – word (A) ← Logical right barrel shift (A, imm8) – word (A) ← Logical left barrel shift (A, imm8) – – – – – – – – – – * * – * * * * * * – – – * * * – – – ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 *2 *2 *2 0 0 0 long (A) ← Arithmetic right shift (A, R0) long (A) ← Logical right barrel shift (A, R0) long (A) ← Logical left barrel shift (A, R0) – – – – – – – – – – – – * * – * * * * * * – – – * * * – – – ASRL A, #imm8 LSRL A, #imm8 LSLL A, #imm8 3 3 3 *4 *4 *4 0 0 0 long (A) ← Arithmetic right shift (A, imm8) – long (A) ← Logical right barrel shift (A, imm8) – long (A) ← Logical left barrel shift (A, imm8) – – – – – – – – – – * * – * * * * * * – – – * * * – – – 1 For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” *1: *2: *3: *4: 96 3 when R0 is 0, 3 + (R0) in all other cases. 3 when R0 is 0, 4 + (R0) in all other cases. 3 when imm8 is 0, 3 + (imm8) in all other cases. 3 when imm8 is 0, 4 + (imm8) in all other cases. MB90220 Series Table 20 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel rel rel rel rel # cycles B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 2 2+ 2 2+ 4 2 2 3 4+ (a) 3 4+ (a) 3 0 0 0 (c) 0 (d) 0 JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 CALL CALL CALL CALLV CALLP 2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 1 4 (c) 5+ (a) 2× (c) 5 (c) 5 2× (c) 7 2× (c) CALLP @eam *6 2+ 8+ (a) *2 CALLP addr24 *7 4 7 2× (c) Branch 1 Instructions [31 Instructions] Operation LH AH I S T N Z V C RMW Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 ( (V) xor (N) ) or (Z) = 1 ( (V) xor (N) ) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word (PC) ← (A) word (PC) ← addr16 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← (ear), (PCB) ← (ear +2) word (PC) ← (eam), (PCB) ← (eam +2) word (PC) ← ad24 0 to 15 (PCB) ← ad24 16 to 23 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← addr16 Vector call linstruction word (PC) ← (ear) 0 to 15, (PCB) ← (ear) 16 to 23 word (PC) ← (eam) 0 to 15, (PCB) ← (eam) 16 to 23 word (PC) ← addr 0 to 15, (PCB) ← addr 16 to 23 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – For an explanation of “(a)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” *1: *2: *3: *4: *5: *6: *7: 3 when branching, 2 when not branching. 3 × (c) + (b) Read (word) branch address. W: Save (word) to stack; R: Read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: Read (long word) branch address. Save (long word) to stack. 97 MB90220 Series Table 21 Mnemonic # CBNE A, #imm8, rel CWBNE A, #imm16, rel 3 4 CBNE ear, #imm8, rel CBNE eam, #imm8, rel CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel 4 4+ 5 5+ cycles 1 * *1 *1 *3 *1 *3 *2 DBNZ ear, rel 3 *4 DBNZ eam, rel 3+ *2 DWBNZ ear, rel 3 *4 DWBNZ eam, rel 3+ INT #vct8 INT addr16 INTP addr24 INT9 RETI RETIQ *6 2 3 4 1 1 2 LINK 2 #imm8 14 12 13 14 9 11 6 B 0 0 0 (b) 0 (c) 8× (c) 6× (c) 6× (c) 8× (c) 6× (c) *5 RET *7 RETP *8 (c) 4 5 1 1 (c) (d) LH AH I S T N Z V C RMW Branch when byte (A) ≠ imm8 – Branch when byte (A) ≠ imm16 – – – – – – – – – * * * * * * * * – – Branch when byte (ear) ≠ imm8 Branch when byte (eam) ≠ imm8 Branch when word (ear) ≠ imm16 Branch when word (eam) ≠ imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – – – – – – * * * – – – – – – – * * * – * – – – – – * * * – – – – – – – * * * – * Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt – – – – – – – – – – – – R R R R * * S S S S * * – – – – * * – – – – * * – – – – * * – – – – * * – – – – * * – – – – – – At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. – – – – – – – – – – – – – – – – – – – – Return from subroutine Return from subroutine – – – – – – – – – – – – – – – – – – – – Branch when byte (ear) = (ear) – 1, and (ear) ≠ 0 2× (b) Branch when byte (ear) = (eam) – 1, and (eam) ≠ 0 0 Branch when word (ear) = (ear) – 1, and (ear) ≠ 0 2× (c) Branch when word (eam) = (eam) – 1, and (eam) ≠ 0 (c) 1 Operation 0 5 UNLINK Branch 2 Instructions [20 Instructions] For an explanation of “(b)”, “(c)” and “(d)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” *1: *2: *3: *4: *5: *6: 4 when branching, 3 when not branching 5 when branching, 4 when not branching 5 + (a) when branching, 4 + (a) when not branching 6 + (a) when branching, 5 + (a) when not branching 3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt. High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: Return from stack (word) *8: Return from stack (long word) 98 MB90220 Series Table 22 Mnemonic PUSHW PUSHW PUSHW PUSHW A AH PS rlst Other Control Instructions (Byte/Word/Long Word) [36 Instructions] # cycles B Operation 1 1 1 2 3 3 3 *3 (c) (c) (c) *4 word (SP) ← (SP) –2, ((SP)) ← (A) word (SP) ← (SP) –2, ((SP)) ← (AH) word (SP) ← (SP) –2, ((SP)) ← (PS) (SP) ← (SP) –2n, ((SP)) ← (rlst) – – – – (c) (c) (c) *4 word (A) ← ((SP)), (SP) ← (SP) +2 word (AH) ← ((SP)), (SP) ← (SP) +2 word (PS) ← ((SP)), (SP) ← (SP) +2 (rlst) ← ((SP)) , (SP) ← (SP) I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * – – – – – * – – – * – – – * – – – * – – – * – – – * – – – * – – – – – – – * * * * * * * – LH AH POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 3 *2 JCTX @A 1 9 AND OR CCR, #imm8 2 CCR, #imm8 2 3 3 0 0 byte (CCR) ← (CCR) and imm8 – byte (CCR) ← (CCR) or imm8 – – – * * * * * * * * * * * * * * – – 2 2 2 2 0 0 byte (RP) ←imm8 byte (ILM) ←imm8 – – – – – – – – – – – – – – – – – – – – 0 0 0 0 word (RWi) ←ear word (RWi) ←eam word(A) ←ear word (A) ←eam – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV RP, #imm8 MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam 2 3 2+ 2+ (a) 2 2 2+ 1+ (a) 6× (c) Context switch instruction ADDSP #imm8 ADDSP #imm16 2 3 3 3 0 0 word (SP) ← ext (imm8) word (SP) ← imm16 – – – – – – – – – – – – – – – – – – – – MOV A, brgl MOV brg2, A MOV brg2, #imm8 2 2 3 *1 1 2 0 0 0 byte (A) ← (brgl) byte (brg2) ← (A) byte (brg2) ← imm8 Z – – * – – – – – – – – – – – * * * * * * – – – – – – – – – NOP ADB DTB PCB SPB NCC CMR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access Prefix code for no flag change Prefix code for the common register bank – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVW SPCU, #imm16 MOVW SPCL, #imm16 SETSPC CLRSPC 4 4 2 2 2 2 2 2 0 0 0 0 word (SPCU) ← (imm16) word (SPCL) ← (imm16) Stack check ooperation enable Stack check ooperation disable – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – BTSCN A BTSCNS A BTSCND A 2 2 2 *5 *6 *7 0 0 0 byte (A)← position of “1” bit in word (A) × 2 Z byte (A)← position of “1” bit in word (A) × 4 Z byte (A)← position of “1” bit in word (A) Z – – – – – – – – – – – – – – – * * * – – – – – – – – – For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5. *1: PCB, ADB, SSB, USB, and SPB: 1 cycle DTB: 2 cycles DPR: 3 cycles *2: 3 + 4 × (pop count) *3: 3 + 4 × (push count) *4: *5: *6: *7: Pop count × (c), or push count × (c) 3 when AL is 0, 5 when AL is not 0. 4 when AL is 0, 6 when AL is not 0. 5 when AL is 0, 7 when AL is not 0. 99 MB90220 Series Table 23 Bit Manipulation Instructions [21 Instructions] Mnemonic # cycles B MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp 3 4 3 3 3 3 (b) (b) (b) MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A 3 4 3 4 4 4 SETB SETB SETB dir:bp addr16:bp io:bp 3 4 3 CLRB CLRB CLRB dir:bp addr16:bp io:bp BBC BBC BBC Operation byte (A) ← (dir:bp) b byte (A) ← (addr16:bp) b byte (A) ← (io:bp) b LH AH I S T N Z V C RMW Z Z Z * * * – – – – – – – – – * * * * * * – – – – – – – – – 2× (b) bit (dir:bp) b ← (A) 2× (b) bit (addr16:bp) b ← (A) 2× (b) bit (io:bp) b ← (A) – – – – – – – – – – – – – – – * * * * * * – – – – – – * * * 4 4 4 2× (b) bit (dir:bp) b ← 1 2× (b) bit (addr16:bp) b ← 1 2× (b) bit (io:bp) b ← 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 3 4 3 4 4 4 2× (b) bit (dir:bp) b ← 0 2× (b) bit (addr16:bp) b ← 0 2× (b) bit (io:bp) b ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *1 (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *1 (b) (b) (b) Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – SBBS addr16:bp, rel 5 *2 2× (b) Branch when (addr16:bp) b = 1, bit = 1 – – – – – – * – – * WBTS io:bp 3 *3 *4 Wait until (io:bp) b = 1 – – – – – – – – – – WBTC io:bp 3 *3 *4 Wait until (io:bp) b = 0 – – – – – – – – – – For an explanation of “(b)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” *1: *2: *3: *4: 100 5 when branching, 4 when not branching 7 when condition is satisfied, 6 when not satisfied Undefined count Until condition is satisfied MB90220 Series Table 24 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # cycles B 1 1 1 1 1 1 3 2 1 2 1 2 0 0 0 0 0 0 Operation byte (A) 0 to 7 ← → (A) 8 to 15 word (AH) ← → (AL) Byte code extension Word code extension Byte zero extension Word zero extension Table 25 Mnemonic # cycles B LH AH – – X – Z – – * – X – Z I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – * * R R – – * * * * – – – – – – – – – – – – – – – – – – I S T N Z V C String Instructions [10 Instructions] Operation LH AH RMW MOVS/MOVSI MOVSD 2 2 *2 *2 *3 Byte transfer @AH+ ← @AL+, counter = RW0 *3 Byte transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – SCEQ/SCEQI SCEQD 2 2 *1 *1 *4 Byte retrieval @AH+ – AL, counter = RW0 *4 Byte retrieval @AH– – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – FILS/FILSI 2 5m +3 *5 Byte filling @AH+ ← AL, counter = RW0 – – – – – * * – – – MOVSW/MOVSWI MOVSWD 2 2 *2 *2 *6 Word transfer @AH+ ← @AL+, counter = RW0 *6 Word transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – SCWEQ/SCWEQI 2 SCWEQD 2 *1 *1 *7 Word retrieval @AH+ – AL, counter = RW0 *7 Word retrieval @AH– – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – – – – – – * * – – – FILSW/FILSWI 2 5m +3 *8 Word filling @AH+ ← AL, counter = RW0 m: RW0 value (counter value) *1: *2: *3: *4: *5: *6: *7: *8: 3 when RW0 is 0, 2 + 6 × (RW0) for count out, and 6n + 4 when match occurs 4 when RW0 is 0, 2 + 6 × (RW0) in any other case (b) × (RW0) (b) × n (b) × (RW0) (c) × (RW0) (c) × n (c) × (RW0) 101 MB90220 Series Table 26 Mnemonic # MOVM @A, @RLi, #imm8 MOVM @A, eam, #imm8 MOVM addr16, @RLi, #imm8 MOVM addr16, eam, #imm8 MOVMW @A, @RLi, #imm8 MOVMW @A, eam, #imm8 MOVMWaddr16, @RLi, #imm8 MOVMWaddr16, eam, #imm8 MOVM @RLi, @A, #imm8 MOVM eam, @A, #imm8 MOVM @RLi, addr16, #imm8 MOVM eam, addr16, #imm8 MOVMW @RLi, @A, #imm8 MOVMW eam, @A, #imm8 MOVMW@RLi, addr16, #imm8 MOVMWeam, addr16, #imm8 MOVM bnk : addr16, *5 bnk : addr16, #imm8 MOVMW bnk : addr16, *5 bnk : addr16, #imm8 Multiple Data Transfer Instructions [18 Instructions] cycles B 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 1 * *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 * *3 *3 *3 *4 *4 *4 *4 *3 *3 *3 *3 *4 *4 *4 *4 *3 7 *1 *4 3 Operation Multiple data trasfer byte ((A)) ← ((RLi)) Multiple data trasfer byte ((A)) ← (eam) Multiple data trasfer byte (addr16) ← ((RLi)) Multiple data trasfer byte (addr16) ← (eam) Multiple data trasfer word ((A)) ← ((RLi)) Multiple data trasfer word ((A)) ← (eam) Multiple data trasfer word (addr16) ← ((RLi)) Multiple data trasfer word (addr16) ← (eam) Multiple data trasfer byte ((RLi)) ← ((A)) Multiple data trasfer byte (eam) ← ((A)) Multiple data transfer byte ((RLi)) ← (addr16) Multiple data transfer byte (eam) ← (addr16) Multiple data trasfer word ((RLi)) ← ((A)) Multiple data trasfer word (eam) ← ((A)) Multiple data transfer word ((RLi)) ← (addr16) Multiple data transfer word (eam) ← (addr16) Multiple data transfer byte (bnk:addr16) ← (bnk:addr16) Multiple data transfer word (bnk:addr16) ← (bnk:addr16) LH AH S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: 5 + imm8 × 5, 256 times when imm8 is zero. *2: 5 + imm8 × 5 + (a), 256 times when imm8 is zero. *3: Number of transfers × (b) × 2 *4: Number of transfers × (c) × 2 *5: The bank register specified by “bnk” is the same as for the MOVS instruction. 102 I MB90220 Series ■ ORDERING INFORMATION Part number Type Package Remarks MB90224 MB90223 MB90P224A MB90P224B MB90224PF MB90223PF MB90P224PF MB90P224BPF 120-pin Plastic QFP (FPT-120P-M03) MB90W224A MB90W224B MB90W224ZF MB90W224BZF 120-pin Ceramic QFP (FPT-120C-C02) ES level only MB90V220 MB90V220CR 256-pin Ceramic PGA (PGA-256C-A02) For evaluation 101 MB90220 Series ■ PACKAGE DIMENSIONS 120-pin Plastic QFP (FPT-120P-M03) 32.00±0.40(1.260±.016)SQ 3.85(.152)MAX 28.00±0.20(1.102±.008)SQ 90 61 91 60 0(0)MIN (STAND OFF) 23.20 (.913) REF Details of "A" part 0.25(.010) 30.40±0.40 (1.197±.016) 0.20(.008) 0.18(.007)MAX 0.58(.023)MAX INDEX "A" Details of "B" part 31 120 30 LEAD No. 1 0.80(.0315)TYP 0.35±0.10 (.014±.004) 0.16(.006) M 0.15±0.05 (.006±.002) 0 10° 0.80±0.20(.031±.008) 0.10(.004) C "B" Dimensions in mm (inches) 1994 FUJITSU LIMITED F120004S-3C-2 120-pin Ceramic QFP (FPT-120C-C02) 32.00±0.30(1.260±.012)SQ +0.60 +.023 28.00 –0.30 1.102 –.012 SQ 3.55(.140)MAX 0.80±0.20 (.0315±.008) 23.20(.9135)REF 0.05(.002)MIN (STAND OFF) Ø12.70(.0500)REF 30.40±0.25 SQ (1.197±.010) Details of "A" part 0.10(.004) "A" INDEX AREA 0°~10° 0.80(.0315)TYP C 1994 FUJITSU LIMITED F120023SC-1-1 0.35±0.10 (.0138±.0040) 0.15±0.05(.006±.002) 1.45±0.20(.057±.008) Dimensions in mm (inches) Note: See to the latest version of Package Data Book for official package dimensions. 104 0° MB90220 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9710  FUJITSU LIMITED Printed in Japan
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