MB91133PMC-G-124K5E1

The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-16308-3E 32-Bit RISC Microcontroller CMOS FR30 MB91130 Series MB91133/MB91F133A ■ DESCRIPTION The MB91130 series, a standard single-chip microcontroller featuring various I/O resources and bus control mechanisms to incorporate the control required for high-performance high-speed CPU processes, is the core unit in the 32-bit RISC CPU (FR* family) . This unit has the optimal specifications for incorporating applications that require high-performance CPU processing power by featuring peripheral I/O resources suitable for single-lens reflex cameras, digital video cameras, etc. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited. ■ FEATURES 1. CPU • • • • • 32-bit RISC (FR30) , load/store architecture, 5-level pipeline Multi-purpose register : 32 bits × 16 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes Function entry / exit instruction, multi load / store instruction of register details : High-level language handling instruction • Register interlock function : Simplification of assembler description • Branch instruction with delay slot : Reduction in overheads in case of branching (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.10 MB91130 Series (Continued) • Multiplier is built-in / supported at instruction level. • Signed 32-bit multiplication : 5 cycles • Signed 16-bit multiplication : 3 cycles • Interruption (saving PC and PS) : 6 cycles, 16 priority levels 2. Bus Interface • • • • • 24-bit address output, 8/16-bit data input/output Basic bus cycle : 2 clock cycles Interface support for various memories Unused data and address pins can be used as input/output ports. Supports “little endian” mode 3. Built-in ROM Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB 4. Built-in RAM Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB 5. DMA Controller This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory. A maximum of 8 factors in total (internal and external) can be transferred. External factors are 3 channels. 6. Bit Search Module Searches the first “1” / “0” change bit positions within 1 cycle from MSB in 1 word 7. Timer • 16-bit reload timer × 5 channels • 16-bit OCU × 8 channels, ICU × 4 channels, free-run timer × 1 channel Output waveform adjusting function for AC motor waveforms is included in the above timer. • 8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel) External interruption and pin are shared for AIN and BIN. • 16-bit down count timer × 5 channels; can also be used as the UART baud rate timer • 16-bit PPG timer × 6 channels; out-pulse cycle / duty can be changed at random 8. D/A Converter • 8-bit × 3 channels 9. A/D Converter (Sequential comparison type) • • • • 10-bit × 8 channels Sequential conversion method (conversion time 5.0 µs at 33 MHz) Setting for single conversion, scan conversion and repeat conversion is possible. Conversion starting function using hardware or software 10. Serial I/O • UART × 5 channels; clock synchronous serial transfer with LSB / MSB switching function is possible for both. • Serial data output or serial lock output can be selected using push-pull / open-drain software. 11. Level Comparator Input • 1 channel; shared input and pins of A/D converter. 2 DS07-16308-3E MB91130 Series 12. Clock Switching Function • Base clock : Software can be used to select from two types of clock sources, namely 32 kHz and high-speed. • Gear function : Four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock ratio to the basic clock per CPU and peripheral equipment. 13. Interruption Controller • External interruption input (total 24 channels) • With pull up pin control / standby return function : 4 channels (rising / falling / H level / L level settings are possible) • With pull up pin control / standby return function; AIN / BIN pins of the up/down counter are shared : 4 channels (rising / falling / H level / L level settings are possible) • With pull up pin controln : 16 channels (rising / falling / H level / L level settings are possible) • Internal interruption factor • Interruption / delay interruption by resource 14. Others • Reset factors Power on reset, watchdog timer, software reset, external reset • Low power consumption mode Sleep/stop mode • Packages FBGA-144, LQFP-144 • CMOS technology (0.35 µm) • Power Two power sources (5 V / 3 V) 1) 5 V system : 5 V ± 10% (A/D, D/A and level comparator included) 2) 3 V system : A) 3.0 V to 3.6 V : All functions guaranteed B) 2.7 V to 3.0 V : All functions guaranteed for single-chip mode of mask devices only ■ PRODUCT LINEUP MB91133 MB91F133A MB91FV130 MASK ROM device (mass production item) FLASH ROM device (for evaluation) Piggy/EVA device (for evaluation / development) 6 KB 6 KB 6 KB CROM capacity 254 KB ⎯ ⎯ FLASH capacity ⎯ 254 KB 254 KB CRAM capacity 2 KB 2 KB 2 KB Mass production Mass production Provided CLASSIFICATION RAM capacity Others DS07-16308-3E 3 MB91130 Series ■ PIN ASSIGNMENTS • MB91FV130 (BOTTOM VIEW) 3 299 296 293 277 274 270 268 278 275 262 254 247 257 252 250 245 233 230 224 2 298 292 289 286 283 280 276 269 264 263 258 251 248 243 240 237 234 225 221 5 10 4 297 291 287 284 279 271 265 261 256 249 242 239 235 229 228 219 218 8 13 6 300 295 290 285 281 272 267 259 255 246 241 236 231 226 223 215 207 25 16 11 7 1 294 288 282 273 266 260 253 244 238 232 227 222 217 212 202 27 19 15 12 9 220 216 213 209 199 32 23 18 17 14 214 211 210 205 195 34 26 24 21 20 208 206 204 201 203 22 33 31 30 28 198 197 196 194 200 29 39 38 35 36 192 193 191 190 187 37 40 41 43 42 186 185 188 189 179 50 44 46 47 48 178 180 181 183 172 53 51 54 56 58 170 171 174 176 184 45 55 60 61 64 164 167 168 173 182 49 59 63 66 70 159 162 165 169 177 52 62 67 72 77 82 88 94 103 110 116 123 133 139 145 153 157 161 166 175 57 65 73 76 81 86 91 96 105 109 117 122 131 136 141 147 151 156 163 158 68 69 78 79 85 89 92 99 106 111 115 121 129 135 138 142 148 154 160 155 71 75 84 87 90 93 98 101 108 113 114 119 126 130 134 137 140 144 150 152 74 80 83 95 100 102 107 97 104 112 125 128 118 120 124 127 132 143 146 149 (PGA-299C-A01) 4 DS07-16308-3E MB91130 Series • MB91F133A/MB91133 (TOP VIEW) 14 108 107 106 102 99 96 92 89 85 82 79 75 74 72 13 110 109 105 103 100 97 93 88 84 81 78 76 73 71 12 111 112 113 104 101 98 91 90 86 83 80 77 69 70 11 115 114 116 95 94 87 68 67 66 10 118 117 119 65 64 63 9 121 120 122 59 62 61 60 8 125 124 126 123 58 55 57 56 7 128 129 127 130 51 54 52 53 6 132 133 134 131 50 48 49 5 135 136 137 47 45 46 4 138 139 140 44 42 43 3 142 141 5 8 11 2 143 1 4 6 1 144 2 3 A B C 15 22 23 14 18 19 26 29 32 41 40 39 9 12 16 21 25 28 31 33 37 38 7 10 13 17 20 24 27 30 34 35 36 D E F G H J K L M N P INDEX (BGA-144P-M01) DS07-16308-3E 5 P61/A17/INT17 P62/A18/INT18 P63/A19/INT19 P64/A20/INT20 P65/A21/INT21 P66/A22/INT22 P67/A23/INT23 VCC3 P80/RDY P81/BGRNT P82/BRQ P83/RD P84/WR0 P85/WR1 P86/CLK VSS PC0/INT0 PC1/INT1 PC2/INT2 PC3/INT3 PC4/AIN0/INT4 PC5/BIN0/INT5 PC6/AIN1/INT6 PC7/BIN1/INT7 PD0/INT8/TRG0 PD1/INT9/TRG1 PD2/INT10/TRG2 PD3/INT11/TRG3 PD4/INT12/TRG4 PD5/INT13/TRG5 PD6/DEOP2/INT14 PD7/ATG/INT15 PE0/ZIN0 PE1/ZIN1 PE2/IN0 PE3/IN1 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 VSS VCC5 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P60/A16/INT16 6 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 MD2 MD1 MD0 VSS X1 X0 VCC3 X1A X0A VSS RST PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0 PL1/DACK0 PL0/DREQ0 PK7/AN7/CMP PK6/AN6 PK5/AN5 PK4/AN4 PK3/AN3 PK2/AN2 PK1/AN1 PK0/AN0 AVSS AVRL AVRH AVCC DAVC DAVS DA0 DA1 DA2 MB91130 Series • MB91F133A/MB91133 (TOP VIEW) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VCC5 PH0/SIN0 PH1/SOT0 PH2/SCK0 PI0/SIN1 PI1/SOT1 PI2/SCK1 PI3/SIN2 PI4/SOT2 PI5/SCK2 PJ0/SIN3 PJ1/SOT3 PJ2/SCK3 PJ3/SIN4 PJ4/SOT4 PJ5/SCK4 VCC3 VSS PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0 PF7/RTO7 PF6/RTO6 PF5/RTO5 PF4/RTO4 PF3/RTO3 PF2/RTO2 PF1/RTO1 PF0/RTO0 PE7/DTTI PE6/FRCK PE5/IN3 PE4/IN2 (FPT-144P-M08) DS07-16308-3E MB91130 Series ■ PIN NUMBERS LIST • Device : MB91FV130 No. Pin Name Package : PGA-299C-A01 No. Pin Name No. Pin Name No. Pin Name 1 P20/D16 35 P54/A12 69 N.C. 103 PK3/AN3 2 VSS 36 P55/A13 70 N.C. 104 VCC5 3 OPEN 37 VCC5 71 VSS 105 PK4/AN4 4 P21/D17 38 P56/A14 72 N.C. 106 PK5/AN5 5 VCC5 39 P57/A15 73 N.C. 107 PK6/AN6 6 P22/D18 40 P60/A16/INT16 74 VCC5 108 PK7/AN7/CMP 7 P23/D19 41 P61/A17/INT17 75 N.C. 109 DAVC 8 VSS 42 P62/A18/INT18 76 MD0 110 DAVS 9 P24/D20 43 P63/A19/INT19 77 MD1 111 DA0 10 P25/D21 44 P64/A20/INT20 78 MD2 112 VSS 11 P26/D22 45 P65/A21/INT21 79 VCC3 113 DA1 12 P27/D23 46 P66/A22/INT22 80 VSS 114 DA2 13 P30/D24 47 P67/A23/INT23 81 X0 115 PH0/SIN0 14 P31/D25 48 P80/RDY 82 X1 116 PH1/SOT0 15 P32/D26 49 VCC3 83 VCC5 117 PH2/SCK0 16 P33/D27 50 VSS 84 RST 118 PI0/SIN1 17 P34/D28 51 P81/BGRNT 85 N.C. 119 PI1/SOT1 18 P35/D29 52 P82/BRQ 86 ICLK 120 PI2/SCK1 19 P36/D30 53 VCC5 87 ICS0 121 PI3/SIN2 20 P37/D31 54 P83/RD 88 ICS1 122 PI4/SOT2 21 P40/A00 55 P84/WR0 89 ICS2 123 PI5/SCK2 22 VCC5 56 P85/WR1 90 ICD0 124 PJ0/SIN3 23 P41/A01 57 P86/CLK 91 ICD1 125 VCC5 24 P42/A02 58 PL0/DREQ0 92 ICD2 126 PJ1/SOT3 25 P43/A03 59 PL1/DACK0 93 ICD3 127 PJ2/SCK3 26 P44/A04 60 PL2/DEOP0 94 BREAK 128 VSS 27 P45/A05 61 PL3/DREQ1 95 AVCC 129 VCC3 28 P46/A06 62 PL4/DACK1 96 AVRH 130 X0A 29 VSS 63 PL5/DEOP1 97 VSS 131 X1A 30 P47/A07 64 PL6/DREQ2 98 AVRL 132 VSS 31 P50/A08 65 PL7/DACK2 99 AVSS 133 PJ3/SIN4 32 P51/A09 66 N.C. 100 PK0/AN0 134 PJ4/SOT4 33 P52/A10 67 N.C. 101 PK1/AN1 135 PJ5/SCK4 34 P53/A11 68 VCC5 102 PK2/AN2 136 PC0/INT0 (Continued) DS07-16308-3E 7 MB91130 Series (Continued) No. Pin Name 8 No. Pin Name No. Pin Name No. Pin Name No. Pin Name 137 PC1/INT1 173 PF5/RTO5 209 TAD14 245 TDT23 281 TDT53 138 PC2/INT2 174 PF6/RTO6 210 TAD15 246 TDT24 282 TDT54 139 PC3/INT3 175 PF7/RTO7 211 VCC3 247 VSS 283 TDT55 140 PC4/INT4/AIN0 176 PG0/PPG0 212 TOE 248 TDT25 284 TDT56 141 PC5/INT5/BIN0 177 PG1/PPG1 213 TCE1 249 TDT26 285 TDT57 142 PC6/INT6/AIN1 178 PG2/PPG2 214 TADSC 250 TDT27 286 VCC3 143 VCC5 179 VSS 215 TWR 251 TDT28 287 TDT58 144 PC7/INT7/BIN1 180 PG3/PPG3 216 TDT00 252 TDT29 288 TDT59 145 PD0/INT8/TRG0 181 PG4/PPG4 217 TDT01 253 TDT30 289 TDT60 146 VSS 182 PG5/PPG5 218 VSS 254 VCC5 290 TDT61 147 PD1/INT9/TRG1 183 N.C. 219 TDT02 255 TDT31 291 TDT62 148 PD2/INT10/TRG2 184 N.C. 220 TDT03 256 TDT32 292 TDT63 149 VCC5 185 N.C. 221 VCC5 257 TDT33 293 VCC5 150 PD3/INT11/TRG3 186 N.C. 222 TDT04 258 TDT34 294 TDT64 151 PD4/INT12/TRG4 187 VCC5 223 TDT05 259 TDT35 295 TDT65 152 VSS 188 EXRAM 224 VSS 260 TDT36 296 VSS 153 PD5/INT13/TRG5 189 TAD00 225 TDT06 261 TDT37 297 TDT66 154 PD6/INT14/DEOP2 190 TAD01 226 TDT07 262 VSS 298 TDT67 155 VCC5 191 TAD02 227 TDT08 263 TDT38 299 VCC5 156 PD7/INT15/ATG 192 TAD03 228 TDT09 264 TDT39 300 TDT68 157 PE0/ZIN0 193 VCC3 229 TDT10 265 TDT40 158 VSS 194 TAD04 230 VCC5 266 TDT41 159 PE1/ZIN1 195 TAD05 231 TDT11 267 TDT42 160 PE2/IN0 196 TAD06 232 TDT12 268 TDT43 161 PE3/IN1 197 TAD07 233 VSS 269 VCC3 162 PE4/IN2 198 TAD08 234 TDT13 270 TDT44 163 PE5/IN3 199 TAD09 235 TDT14 271 TDT45 164 PE6/FRCK 200 VSS 236 TDT15 272 TDT46 165 PE7/DTTI 201 TAD10 237 TDT16 273 TDT47 166 VCC3 202 TAD11 238 TDT17 274 TDT48 167 PF0/RTO0 203 VCC5 239 TDT18 275 VCC5 168 PF1/RTO1 204 TAD12 240 VCC3 276 TDT49 169 PF2/RTO2 205 TAD13 241 TDT19 277 TDT50 170 PF3/RTO3 206 TAD14 242 TDT20 278 VSS 171 PF4/RTO4 207 TAD15 243 TDT21 279 TDT51 172 VCC5 208 TCLK 244 TDT22 280 TDT52 DS07-16308-3E MB91130 Series • Device : MB91F133A/MB91133 LQFP FBGA Pin Name Package : BGA-144P-M01/FPT-144P-M08 LQFP FBGA Pin Name LQFP FBGA Pin Name 1 B2 P20/D16 36 P1 P60/A16/INT16 71 P13 PE2/IN0 2 B1 P21/D17 37 N2 P61/A17/INT17 72 P14 PE3/IN1 3 C1 P22/D18 38 P2 P62/A18/INT18 73 N13 PE4/IN2 4 C2 P23/D19 39 P3 P63/A19/INT19 74 N14 PE5/IN3 5 C3 P24/D20 40 N3 P64/A20/INT20 75 M14 PE6/FRCK 6 D2 P25/D21 41 M3 P65/A21/INT21 76 M13 PE7/DTTI 7 D1 P26/D22 42 N4 P66/A22/INT22 77 M12 PF0/RTO0 8 D3 P27/D23 43 P4 P67/A23/INT23 78 L13 PF1/RTO1 9 E2 VSS 44 M4 VCC3 79 L14 PF2/RTO2 10 E1 P30/D24 45 N5 P80/RDY 80 L12 PF3/RTO3 11 E3 P31/D25 46 P5 P81/BGRNT 81 K13 PF4/RTO4 12 F2 P32/D26 47 M5 P82/BRQ 82 K14 PF5/RTO5 13 F1 P33/D27 48 N6 P83/RD 83 K12 PF6/RTO6 14 F3 P34/D28 49 P6 P84/WR0 84 J13 PF7/RTO7 15 G4 P35/D29 50 M6 P85/WR1 85 J14 PG0/PPG0 16 G2 P36/D30 51 L7 P86/CLK 86 J12 PG1/PPG1 17 G1 P37/D31 52 N7 VSS 87 H11 PG2/PPG2 18 G3 P40/A00 53 P7 PC0/INT0 88 H13 PG3/PPG3 19 H3 P41/A01 54 M7 PC1/INT1 89 H14 PG4/PPG4 20 H1 P42/A02 55 M8 PC2/INT2 90 H12 PG5/PPG5 21 H2 P43/A03 56 P8 PC3/INT3 91 G12 VSS 22 H4 P44/A04 57 N8 PC4/AIN0/INT4 92 G14 VCC3 23 J4 P45/A05 58 L8 PC5/BIN0/INT5 93 G13 PJ5/SCK4 24 J1 P46/A06 59 L9 PC6/AIN1/INT6 94 G11 PJ4/SOT4 25 J2 P47/A07 60 P9 PC7/BIN1/INT7 95 F11 PJ3/SIN4 26 J3 VSS 61 N9 PD0/INT8/TRG0 96 F14 PJ2/SCK3 27 K1 VCC5 62 M9 PD1/INT9/TRG1 97 F13 PJ1/SOT3 28 K2 P50/A08 63 P10 PD2/INT10/TRG2 98 F12 PJ0/SIN3 29 K3 P51/A09 64 N10 PD3/INT11/TRG3 99 E14 PI5/SCK2 30 L1 P52/A10 65 M10 PD4/INT12/TRG4 100 E13 PI4/SOT2 31 L2 P53/A11 66 P11 PD5/INT13/TRG5 101 E12 PI3/SIN2 32 L3 P54/A12 67 N11 PD6/DEOP2/INT14 102 D14 PI2/SCK1 33 M2 P55/A13 68 M11 PD7/ATG/INT15 103 D13 PI1/SOT1 34 M1 P56/A14 69 N12 PE0/ZIN0 104 D12 PI0/SIN1 35 N1 P57/A15 70 P12 PE1/ZIN1 105 C13 PH2/SCK0 (Continued) DS07-16308-3E 9 MB91130 Series (Continued) LQFP FBGA Pin Name LQFP FBGA Pin Name 106 C14 PH1/SOT0 126 C8 PL0/DREQ0 107 B14 PH0/SIN0 127 C7 PL1/DACK0 108 A14 VCC5 128 A7 PL2/DEOP0 109 B13 DA2 129 B7 PL3/DREQ1 110 A13 DA1 130 D7 PL4/DACK1 111 B12 DA0 131 D6 PL5/DEOP1 112 A12 DAVS 132 A6 PL6/DREQ2 113 C12 DAVC 133 B6 PL7/DACK2 114 B11 AVCC 134 C6 RST 115 A11 AVRH 135 A5 VSS 116 C11 AVRL 136 B5 X0A 117 B10 AVSS 137 C5 X1A 118 A10 PK0/AN0 138 A4 VCC3 119 C10 PK1/AN1 139 B4 X0 120 B9 PK2/AN2 140 C4 X1 121 A9 PK3/AN3 141 B3 VSS 122 C9 PK4/AN4 142 A3 MD0 123 D8 PK5/AN5 143 A2 MD1 124 B8 PK6/AN6 144 A1 MD2 125 A8 PK7/AN7/CMP 10 DS07-16308-3E MB91130 Series ■ PIN DESCRIPTIONS Pin No. Pin name Circuit type Function 1 2 3 4 5 6 7 8 D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 C External data bus bits 16 to 23 Only valid for external bus 16-bit mode. Can be used as ports in single-chip and external bus 8-bit modes. 10 11 12 13 14 15 16 17 D24/P30 D25/P31 D26/P32 D27/P33 D28P34 D29/P35 D30/P36 D31/P37 C External data bus bits 24 to 31 Can be used as ports in single-chip mode. 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 A00/P40 A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 A08/P50 A09/P51 A10/P52 A11/P53 A12/P54 A13/P55 A14/P56 A15/P57 F External address bus bits 0 to 15 Valid for external bus mode. Can be used as ports in single-chip mode. 36 37 38 39 40 41 42 43 A16/INT16/P60 A17/INT17/P61 A18/INT18/P62 A19/INT19/P63 A20/INT20/P64 A21/INT21/P65 A22/INT22/P66 A23/INT23/P67 O External address bus bits 16 to 23 [ INT16 to 23 ] are external interruption request inputs 16 to 23. These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. Can be used as ports when address bus and external interruption request input are not used. C External RDY input This function is valid when external RDY input is permitted. “0” is input if the bus cycle being executed is not completed. Can be used as a port when the external RDY input is not used. 45 RDY/P80 (Continued) DS07-16308-3E 11 MB91130 Series Pin No. 46 47 Pin name BGRNT/P81 BRQ/P82 Circuit type Function F External bus open reception output This function is valid when external bus open reception output is permitted. “L” is output if the external bus is opened. Can be used as a port when the external bus open reception output is prohibited. C External bus open request input This function is valid when external bus open request input is permitted. “1” is input if the external bus requests to be opened. Can be used as a port when the external bus open request input is not used. 48 RD/P83 F External bus read strobe output This function is valid when external bus read strobe output is permitted. Can be used as a port when the external bus read strobe output is prohibited. 49 WR0/P84 F External bus write strobe output This function is valid in external bus mode. Can be used as a port in single-chip mode. 50 WR1/P85 F External bus write strobe output This function is valid in external bus mode and with 16-bit buses. Can be used as a port in single-chip mode or with external 8-bit bus. 51 CLK/P86 F System clock output Outputs the same clock frequency as the external bus operation. Can be used as a port when it is not otherwise used. H External interruption request inputs 0 to 3 These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. Can be used to reset standby as input is permitted in this port under standby status.Can be used as ports when external interruption request input is not used. 53 54 55 56 57 58 59 60 INT0/PC0 INT1/PC1 INT2/PC2 INT3/PC3 AIN0/INT4/PC4 BIN0/INT5/PC5 AIN1/INT6/PC6 BIN1/INT7/PC7 External interruption request inputs 4 to 7 These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. Can be used to reset standby as input is permitted in these ports under standby status. H [ AIN, BIN ] Up/down timer input This input is always used when input is permitted, so output by ports should be stopped except when carried out intentionally. Can be used as a port when external interruption request input and up/down timer input are not used. (Continued) 12 DS07-16308-3E MB91130 Series Pin No. Pin name Circuit type Function External interruption request inputs 8 to 15 These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. [ TRG0 to 5 ] These are external trigger inputs for PPG timers. 61 62 63 64 65 66 67 68 TRG0/INT8/PD0 TRG1/INT9/PD1 TRG2/INT10/PD2 TRG3/INT11/PD3 TRG4/INT12/PD4 TRG5/INT13/PD5 DEOP2/INT14/PD6 ATG/INT15/PD7 69 70 ZIN0/PE0 ZIN1/PE1 O Up/down timer input These inputs are always used when input is permitted, so output by ports should be stopped except when carried out intentionally. Can be used as ports when up/down timer input is not used. 71 72 73 74 IN0/PE2 IN1/PE3 IN2/PE4 IN3/PE5 F Input capture input This function is valid when input capture activates input. Can be used as ports when input capture input is not used. 75 FRCK/PE6 F External clock input pin of free-run timer Can be used as a port when external clock input of free-run timer is not used. 76 DTTI/PE7 F RTOn pin level fixed input Invalid when input is permitted in the waveform generation area. Can be used as a port when RTOn pin level fixed input is not used. 77 78 79 80 81 82 83 84 RTO0/PF0 RTO1/PF1 RTO2/PF2 RTO3/PF3 RTO4/PF4 RTO5/PF5 RTO6/PF6 RTO7/PF7 F Output compare event pins/waveform output pins in the waveform generation area Can be used as ports when specification of the output compare event pin/waveform output pin of the waveform generation area is prohibited. 85 86 87 88 89 90 PPG0/PG0 PPG1/PG1 PPG2/PG2 PPG3/PG3 PPG4/PG4 PPG5/PG5 F PPG timer output This function is valid when output specification of the PPG timer is permitted. Can be used as ports when output specification of the PPG timer is prohibited. 111 110 109 DA0 DA1 DA2 ⎯ D/A converter output This function is valid when output specification of the D/A converter is permitted. O [ DEOP2 ] DMA external transfer termination output This function is valid when external transfer termination output specification of the DMA controller is permitted. [ ATG ] A/D converter external trigger input These inputs are always used when they are selected as A/D initiation factors, so output by ports should be stopped except when carried out intentionally. Can be used as ports when not otherwise used. (Continued) DS07-16308-3E 13 MB91130 Series Pin No. 107 106 105 104 103 102 101 100 99 98 97 Pin name SIN0/PH0 SOT0/PH1 SCK0/PH2 SIN1/PI0 SOT1/PI1 SCK1/PI2 SIN2/PI3 SOT2/PI4 SCK2/PI5 SIN3/PJ0 SOT3/PJ1 Circuit type Function P UART0 data input This input is always used when UART0 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART0 data input is not used. P UART0 data output This function is valid when UART0 data output specification is permitted. Can be used as a port when UART0 data output specification is prohibited. P UART0 clock input/output This function is valid when UART0 clock output specification is permitted. Can be used as a port when UART0 clock output specification is prohibited. P UART1 data input This input is always used when UART1 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART1 data input is not used. P UART1 data output This function is valid when UART1 data output specification is permitted. Can be used as a port when UART1 data output specification is prohibited. P UART1 clock input/output This function is valid when UART1 clock output specification is permitted. Can be used as a port when UART1 clock output specification is prohibited. P UART2 data input This input is always used when UART2 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART2 data input is not used. P UART2 data output This function is valid when UART2 data output specification is permitted. Can be used as a port when UART2 data output specification is prohibited. P UART2 clock input/output This function is valid when UART2 clock output specification is permitted. Can be used as a port when UART2 clock output specification is prohibited. P UART3 data input This input is always used when UART3 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART3 data input is not used. P UART3 data output This function is valid when UART3 data output specification is permitted. Can be used as a port when UART3 data output specification is prohibited. (Continued) 14 DS07-16308-3E MB91130 Series Pin No. Pin name 96 SCK3/PJ2 95 SIN4/PJ3 94 SOT4/PJ4 93 SCK4/PJ5 118 119 120 121 122 123 124 125 AN0/PK0 AN1/PK1 AN2/PK2 AN3/PK3 AN4/PK4 AN5/PK5 AN6/PK6 CMP/AN7/PK7 126 DREQ0/PL0 Circuit type Function P UART3 clock input/output This function is valid when UART3 clock output specification is permitted. Can be used as a port when UART3 clock output specification is prohibited. P UART4 data input This input is always used when UART4 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART4 data input is not used. P UART4 data output This function is valid when UART4 data output specification is permitted. Can be used as a port when UART4 data output specification is prohibited. P UART4 clock input/output This function is valid when UART4 clock output specification is permitted. Can be used as a port when UART4 clock output specification is prohibited. A/D converter analog input This is valid when the AICK register specification is analog input. N [ CMP ] level comparator input Can be used as ports when A/D converter analog input is not used. F DMA external transfer request input This input is always used if selected as the transfer factor for the DMA controller, so output by ports should be stopped except when carried out intentionally. Can be used as a port when DMA external transfer request input is not used. 127 DACK0/PL1 F DMA external transfer request reception output This function is valid when external transfer request reception output specification of the DMA controller is permitted. Can be used as a port when transfer request reception output specification of the DMA controller is prohibited. 128 DEOP0/PL2 F DMA external transfer termination output This function is valid when external transfer termination output specification of the DMA controller is permitted. F DMA external transfer request input This input is always used if selected as the transfer factor for the DMA controller, so output by ports should be stopped except when carried out intentionally. Can be used as a port when DMA external transfer request input is not used. 129 DREQ1/PL3 (Continued) DS07-16308-3E 15 MB91130 Series (Continued) Pin No. Pin name Circuit type Function 130 DACK1/PL4 F DMA external transfer request reception output This function is valid when external transfer request reception output specification of the DMA controller is permitted. Can be used as a port when transfer request reception output specification of the DMA controller is prohibited. 131 DEOP1/PL5 F DMA external transfer termination output This function is valid when external transfer termination output specification of the DMA controller is permitted. F DMA external transfer request input This input is always used if selected as the transfer factor for the DMA controller, so output by ports should be stopped except when carried out intentionally. Can be used as a port when DMA external transfer request input is not used. 132 DREQ2/PL6 133 DACK2/PL7 F DMA external transfer request reception output This function is valid when external transfer request reception output specification of the DMA controller is permitted. Can be used as a port when transfer request reception output specification of the DMA controller is prohibited. 134 RST B External reset input 136 137 X0A X1A A Oscillation pin for low-speed clock (32 kHz) 139 140 X0 X1 A Oscillation pin for high-speed clock (16.5 MHz) 142 143 144 MD0 MD1 MD2 G Mode pins Basic MCU operation mode is set by these pins. They should be directly connected to VCC or VSS for use. 112 DAVS ⎯ Ground pin of D/A converter (connected to analog ground) 113 DAVC ⎯ Power pin of D/A converter 114 AVCC ⎯ Power pin for A/D converter 115 AVRH ⎯ Reference voltage pin for A/D converter (high electric potential side) When this pin is turned on/off, AVRH or more electric potential must be supplied to VCC. 116 AVRL ⎯ Reference voltage pin for A/D converter (low electric potential side) 117 AVSS ⎯ Ground pin for A/D converter (connected to analog ground) 27, 108 VCC5 ⎯ 5 V power of digital circuit Power must be connected to all VCC5 pins for use. 44, 92 138 VCC3 ⎯ 3 V power of digital circuit Power must be connected to all VCC3 pins for use. 9, 26, 52, 91, 135, 141 VSS ⎯ Ground level of digital circuit Note : In most of the above pins, the input/output of the I/O ports and resources are multiplexed, such as xxxx/Pxx. If the output from ports and resources of those pins compete with each other, the resource is given priority. 16 DS07-16308-3E MB91130 Series ■ INPUT/OUTPUT CIRCUIT TYPES Type Circuit Remarks • High-speed oscillation feedback resistance = approximately 1 MΩ X1,X1A Xout A X0,X0A Low-speed oscillation feedback resistance = approximately 10 MΩ Standby control signal • With pull up resistance CMOS level input Pull-up resistance value = approximately 25 kΩ (Typ) B Digital input • CMOS level input/output pin Pout CMOS level output CMOS level input (with standby control) Nout C IOL = 4 mA R CMOS input Standby control • CMOS hysteresis input/output pin Pout CMOS level output CMOS hysteresis input (with standby control) Nout F IOL = 4 mA R Hysteresis input Standby control (Continued) DS07-16308-3E 17 MB91130 Series Type Circuit Remarks • CMOS level input pin CMOS level input (without standby control) G IOL = 4 mA R Digital input Pull-up control Pout R H Nout R Hysteresis input • CMOS hysteresis input/output pin with pull- up control CMOS level output CMOS hysteresis input (without standby control) Pull-up resistance value = approximately 50 kΩ (Typ) IOL = 4 mA • Analog/CMOS level input/output pin Pout Nout N R CMOS input Standby control CMOS level output CMOS level input (with standby control) Analog input (Analog input is valid when bit dealt by AIC is “1”.) IOL = 4 mA Analog input (Continued) 18 DS07-16308-3E MB91130 Series (Continued) Type Circuit Remarks Pull-up control Pout R O Nout R Hysteresis input • CMOS hysteresis input/output pin with pull-up control CMOS level output CMOS hysteresis input (with standby control) Pull-up resistance value = approximately 50 kΩ (Typ) IOL = 4 mA Standby control Pull-up control Open-drain control R P Nout R • CMOS hysteresis input/output pin with pull-up control CMOS level output (with open-drain control) CMOS hysteresis input (with standby control) Pull-up resistance value = approximately 50 kΩ (Typ) Hysteresis input Standby control DS07-16308-3E IOL = 4 mA 19 MB91130 Series ■ HANDLING DEVICES 1. Points to Note on Handling Devices (1) Latch-up prevention Latch-up may occur by CMOS IC if a voltage in excess of VCC5 or lower than VSS is applied to the input/output pins, or if the voltage exceeds the rating between VCC5 and VSS. If latch-up occurs, the electrical current increases significantly and may destroy certain components due to excessive heat, so great care must be taken to ensure that the maximum rating is not exceeded during use. (2) Handling Pins • Handling unused pins Input pins that are not used should be pulled up or down as they may cause erroneous operations if left open. • Handling N.C. pins N.C. pins must be opened for use. • Handling output pins Excessive electric current may flow if the output pin is shorted by the power source or other output pins, or connected to large loads. If such status is prolonged, the device is liable to be damaged, so great care must be taken to ensure that the usage volume does not exceed the maximum rating. • Mode pins (MD0 to MD2) Those pins must be directly connected to VCC5 or VSS for use. Pattern lengths between VCC5 or VSS and each mode pin on the printed-circuit board should be arranged to be as short as possible to prevent the test mode from being erroneously turned on due to noise, and they should be connected with low impedance. • Power pins When there are a number of VCC5/VCC3/VSS, those whose electrical potential must be the same within the device are connected to prevent erroneous operation such as latch-up for device design purposes, but those must be externally connected to a power source and earthed to follow the general output current standard and prevent erroneous operation of strobe signals due to increased ground level and reduction in unnecessary radiation. Care must also be taken to ensure that they are connected to the VCC5/VSS or VCC3/VSS of this device at the lowest possible impedance from the source of the electrical current supply. Furthermore, it is recommended that a ceramic capacitor of around 0.1 µF be used to connect the VCC5 and VSS, or VCC3 and VSS near the device as a bypass capacitor. • Crystal oscillation circuits Noise near the X0, X1, X0A or X1A pins can cause erroneous operation. The printed-circuit board must be designed so that the X0, X1, X0A and X1A pins, crystal oscillator (or ceramic oscillator) and bypass capacitor to the ground can be arranged as close as possible. Also, a printed-circuit board with grounded artwork enclosing the X0, X1, X0A and X1A pins is strongly recommended to ensure stable operation. 20 DS07-16308-3E MB91130 Series (3) Points to note on usage • External reset input “L” level should be input to the RST pin, which is required for at least five machine cycles to ensure that the internal status is reset. • External clock Use with an external clock is prohibited. A crystal (or ceramic) oscillator should be used. • Analog Power The AVCC should always be used at the same electric potential as VCC5. If the VCC5 is larger than the AVCC, electricity may flow through pins AN0 to AN7. • Points to note for using level comparator When the level comparator is used, a reference current (IR) flows even though it is stopped. The stop mode must be turned on after prohibiting action of the level comparator. 2. Points to Note on Turning On Power • RST pin handling The RST pin must be started from “L” level when the power is turned on, and when the power is adjusted to the VDD level, it should be changed to the “H” level after being left on for at least 5 cycles of the internal operation clock. • Original oscillation input The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on. • Power on reset “Power on reset” must be executed if power is turned on, but the power voltage falls below the guaranteed operating temperature and power is turned on again. • Order for turning on power Power should be turned on in the following order. VCC3 → VCC5 → AVCC → AVRH The opposite order should be used when turning off. DS07-16308-3E 21 MB91130 Series ■ BLOCK DIAGRAM FR30 CPU UART × 5 ch 15 SIN0 to SIN4 SOT0 to SOT4 SCK0 to SCK4 RAM 6 Kbyte DREQ0 toDREQ 2 DACK0 toDACK 2 DEOP0 to DEOP2 DMAC 8 ch Reload timer × 5 ch 9 Resource Bus Controller 8 bit 3 output D/A converter 5 Bus Converter 6 6 External Bus Controller A23 to A00 D31 to D16 RD WR1, WR0 RDY BRQ BGRNT CLK RAM 2 Kbyte 16 bit PPG × 6 ch DA0 toDA2 DAVC, DAVS PPG0 to PPG5 TRG0 to TRG5 Multi-Function Timer ROM 254 Kbyte 4 IN0 to IN3 16 bit ICU × 4 ch 47 Interrupt Controller 16 bit FRT X0, X1, X0A, X1A RST MD0 to MD2 AIN0, 1 BIN0, 1 ZIN0, 1 Clock Generator 8 Up/Down counter × 2 ch 6 16 bit OCU × 8 ch 24 ch external interrupt INT0 to INT23 (∗) FRCK RTO0 (U) RTO1 (X) RTO2 (V) RTO3 (Y) RTO4 (W) RTO5 (Z) RTO6 RTO7 DTTI 24 AN0 to AN7 AVRH, AVRL AVCC, AVSS CMP (AN7) 10 bit 8 input A/D converter Waveform Generator 12 level comparator * : INT23 to INT16 share pins with A23 to A16 INT15 shares pins with ATG NT14 shares pins with DEOP2 INT13 to INT8 share pins with TRG5 to TRG0 INT7 to INT4 share pins with AIN0, BIN0, AIN1 and BIN1 The total number of above pins is 133. The remainder (144 − 133 = 11 pins) are VCC5 , VCC3 and VSS. 22 DS07-16308-3E MB91130 Series ■ CPU 1. Memory Space The FR family has 4 Gbytes (232 addresses) of logic address space which the CPU accesses linearly. • Memory Map External ROM external bus mode Internal ROM external bus mode Single-chip mode 0000 0000H I/O I/O I/O I/O I/O I/O Access is prohibited Access is prohibited Access is prohibited Built-in RAM 6 KB Built-in RAM 6 KB Built-in RAM 6 KB Access is prohibited Access is prohibited Access is prohibited 0000 0400H Direct Madressing area Refer to "I/O MAP" 0000 0800H 0000 1000H 0000 2800H 0001 0000H 0001 0000H External area Access is prohibited 000C 0000H External area Built-in RAM 2KB Built-in RAM 2KB Built-in ROM 254KB Built-in ROM 254KB External area Access is prohibited 000C 0800H FFFF FFFFH 0010 0000H FFFF FFFFH * : It is impossible to access the external area on single-chip mode. When accessing the external area, select the internal ROM external bus mode. DS07-16308-3E 23 MB91130 Series 2. Registers There are two types of multi-purpose registers in the FR family. One is a dedicated purpose register that exists within the CPU and the other is a multi-purpose register that exists in the memory. • Dedicated Registers Program Counter (PC) Program Status (PS) Table Base Register (TBR) : 32-bit length; indicates instruction storage position. : 32-bit length; stores register pointers and condition codes. : Holds the starting address of the vector table to be used for Exception, Interruption and Trapping (EIT) . : Holds the address to return to from the sub-routine. : Indicates the system stuck position. : Indicates the user’s stuck position. Return Pointer (RP) System Stuck Pointer (SSP) User Stuck Pointer (USP) Multiplication and Division Results Resister (MDH/MDL) : 32-bit length; act as registers for multiplication and division. 32 bit PC Program Counter PS Program Status Initial values XXXX XXXXH (Undecided) Table Base Register 000F FC00H Return Pointer XXXX XXXXH SSP System Stuck Pointer 0000 0000H USP User Stuck Pointer XXXX XXXXH (Undecided) MDH Multiplication and Division Results Resister XXXX XXXXH (Undecided) XXXX XXXXH (Undecided) TBR RP MDL (Undecided) • Program Status (PS) PS is the register that holds the program status and is classified into three categories, namely, Condition Code Register (CCR) , System Condition Code Register (SCR) and Interruption Level Master Register (ILM) . 31 PS ⎯ 20 19 18 16 ILM4 ILM3 ILM2 ILM1 ILM0 ILM 24 17 ⎯ 10 9 8 7 6 5 4 3 2 1 0 D1 D0 T ⎯ ⎯ S I N Z V C SCR CCR DS07-16308-3E MB91130 Series • Condition Code Register (CCR) S flag : Specifies the stuck pointer to be used as R15. I flag : Controls permission and prohibition of user interruption requests. N flag : Indicates codes when computation results are defined as integers that are expressed in complements of 2. Z flag : Indicates whether or not a result of the computation is “0” . V flag : Operands used for computation are defined as integers expressed in complements of 2, and indicate whether or not an overflow is generated as a result of the computation. C flag : Indicates whether carrying or borrowing is generated from the highest bit as a result of the computation. • System Condition Code Register (SCR) T flag : Specifies whether or not the step trace trap will be valid. • Interruption Level Mask Register (ILM) ILM4 to ILM0 : Holds the interruption level mask values, and those values that are held by the ILM are used for the level mask. Interruption requests can be accepted only when the interruption levels handled within the interruption requests to be input into the CPU are stronger than the levels shown by the ILM. ILM4 ILM3 ILM2 ILM1 ILM0 Interruption level Strength 0 0 0 0 0 0 Strong 0 1 0 0 0 15 1 1 1 1 1 31 DS07-16308-3E Weak 25 MB91130 Series ■ MULTI-PURPOSE REGISTERS The multi-purpose registers are CPU registers R0 to R15 which are used as accumulators for various computations and memory access pointers (fields that indicate the address) . • Register bank configuration 32-bit R0 Initial value XXXX XXXXH R1 R12 R13 AC (Accumulator) R14 FP (Frame Pointer) XXXX XXXXH R15 SP (Stack Pointer) 0000 0000H Special purposes are assumed for the following 3 of the 16 registers. Thus, some instructions are emphasized. R13 : Virtual accumulator (AC) R14 : Frame Pointer (FP) R15 : Stack Pointer (SP) Initial values for R0 to R14 on resetting are unspecified. The initial value of R15 will be 0000 0000H (SSP value) . 26 DS07-16308-3E MB91130 Series ■ MODE SETTING 1. Pins • Mode pins and set mode Mode pins Mode name MD2 MD1 MD0 Reset vector access areas External data bus width Bus modes 0 0 0 External vector mode 0 External 8-bit 0 0 1 External vector mode 1 External 16-bit 0 1 0 ⎯ ⎯ ⎯ 0 1 1 Internal vector mode Internal (Mode register) 1 ⎯ ⎯ ⎯ ⎯ ⎯ External ROM external bus mode Setting is prohibited Single chip mode Usage is prohibited 2. Register Mode register (MODR) and set mode Address 0000 07FFH M1 M0 * * * * * * Initial value Access XXXX XXXXB W Bus mode set bit W : Write only X : Undecided * : “0” should always be written for bits other than M1 and M0. • Bus mode set bit and its functions M1 M0 Functions 0 0 Single chip mode 0 1 Internal ROM external bus mode 1 0 External ROM external bus mode 1 1 DS07-16308-3E ⎯ Remarks Setting is prohibited 27 MB91130 Series ■ I/O MAP Register Address 000000H +0 PDR3 +1 (R/W) PDR2 XXXXXXXX 000004H ⎯ 000008H ⎯ +2 (R/W) (R/W) 000014H 000018H 00001CH 000020H 000024H 000028H PDRF (R/W) XXXXXXXX ⎯ ⎯ 00003CH 000040H PDRE XXXXXXXX PDRJ PDRI - - XXXXXX LVLC (R/W) (R/W) ⎯ SIDR0/SODR0 (R/W) 0 0 0 0 1 -00 SSR1 (R/W) XXXXXXXX SIDR1/SODR1 (R/W) 0 0 0 0 1 -00 SSR2 (R/W) (R/W) - - XXXXXX XXXX 0 0 0 0 SSR0 (R/W) XXXXXXXX (R/W) PDR4 (R/W) XXXXXXXX PDR8 (R/W) - XXXXXXX XXXXXXXX SIDR2/SODR2 (R/W) PDRD (R/W) XXXXXXXX PDRH (R/W) - - - - - XXX PDRL (R/W) XXXXXXXX SCR0 (R/W) 00000100 SCR1 (R/W) 00000100 SCR2 (R/W) PDRC XXXXXXXX PDRG (R/W) - - XXXXXX PDRK (R/W) XXXXXXXX SMR0 (R/W) 0 0 0 0 0-0 0 SMR1 (R/W) 0 0 0 0 0-0 0 SMR2 (R/W) XXXXXXXX 00000100 0 0 0 0 0-0 0 TMRLR (W) TMR (R) XXXXXXXX XXXXXXXX ⎯ TMRLR XXXXXXXX XXXXXXXX UART0 UART1 UART2 Reload Timer 0 (R) XXXXXXXX XXXXXXXX (R/W) Reload Timer 1 ----0000 0 0 0 0 0 0 0 0 (R/W) 0 0 1 0 1 - XX XXXXXXXX (W) XXXXXXXX XXXXXXXX ⎯ TMR TMCSR ⎯ TMRLR (R/W) Level Comparator ----0000 0 0 0 0 0 0 0 0 (W) ADCR XXXXXXXX XXXXXXXX TMCSR Port Data Register (R/W) 0 0 0 0 1 -00 000034H 000038H (R/W) ⎯ 00002CH 000030H PDR5 XXXXXXXX 00000CH 000010H ⎯ XXXXXXXX PDR6 Block +3 ADCS1 (R/W) ADCS0 (R/W) 00000000 00000000 TMR (R) XXXXXXXX XXXXXXXX TMCSR (R/W) A/D Converter (Sequential type) Reload Timer 2 ----0000 0 0 0 0 0 0 0 0 (Continued) 28 DS07-16308-3E MB91130 Series Register Address 000044H 000048H +0 +1 +2 +3 IPCP1 (R) IPCP0 (R) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP3 IPCP2 (R) XXXXXXXX XXXXXXXX ICS23 ⎯ 00004CH (R/W) 00000000 OCCP1 OCCP3 (R/W) XXXXXXXX XXXXXXXX OCCP5 00005CH (R/W) XXXXXXXX XXXXXXXX OCCP7 000060H (R/W) XXXXXXXX XXXXXXXX OCS32 000064H (R/W) XXX 0 0 0 0 0 0 0 0 0 XX 0 0 OCS76 000068H (R/W) XXX 0 0 0 0 0 0 0 0 0 XX 0 0 TCDT 00006CH 00007CH (R/W) XXXXXXXX XXXXXXXX 000058H 000078H ICS01 ⎯ (R/W) 00000000 Reserved OCCP0 (R/W) SIDR3/SODR3 (R/W) 0 0 0 0 1 0 00 SSR4 (R/W) XXXXXXXX SIDR4/SODR4 (R/W) 0 0 0 0 1 0 00 CDCR1 XXXXXXXX (R/W) ⎯ 0 ---0 0 0 0 CDCR3 (R/W) ⎯ 0 ---0 0 0 0 000080H ⎯ (R/W) XXXXXXXX XXXXXXXX OCCP2 (R/W) XXXXXXXX XXXXXXXX OCCP4 (R/W) XXXXXXXX XXXXXXXX OCCP6 (R/W) 16-bit OCU XXXXXXXX XXXXXXXX OCS10 (R/W) XXX 0 0 0 0 0 0 0 0 0 XX 0 0 OCS54 (R/W) XXX 0 0 0 0 0 0 0 0 0 XX 0 0 TCCS (R/W) 0------- 0 0 0 0 0 0 0 0 00000000 00000000 SSR3 16-bit ICU (R/W) ⎯ 000054H 000074H (R) XXXXXXXX XXXXXXXX 000050H 000070H Block SCR3 (R/W) 00000100 SCR4 (R/W) 00000100 CDCR0 (R/W) 0 ---0 0 0 0 CDCR2 (R/W) 0 ---0 0 0 0 CDCR4 (R/W) 0 ---0 0 0 0 SMR3 (R/W) 0 0 0 0 0-0 0 SMR4 (R/W) 0 0 0 0 0-0 0 16-bit Free-run Timer UART3 UART4 ⎯ ⎯ Communication Pre-scalar ⎯ (Continued) DS07-16308-3E 29 MB91130 Series Register Address 000084H 000088H 00008CH +0 RCR1 +1 (W) 00000000 CCRH0 (R/W) 00000000 CCRH1 (R/W) -0 0 0 0 0 0 0 +2 RCR0 (W) CCRL0 000098H 00009CH 0000A0H (R/W) EIRR0 (R/W) ENIR0 (R/W) 00000000 CSR1 00000000 Reserved EIRR1 (R/W) ENIR1 (R/W) 00000000 ELVR0 (R/W) ELVR1 (R/W) 00000000 00000000 EIRR2 (R/W) ENIR2 00000000 00000000 (R/W) 00000000 00000000 ELVR2 (R/W) DACR2 ⎯ DACR1 -------0 ⎯ DTCR1 (R/W) DADR2 (R/W) 00000000 TMRR1 DADR1 (R/W) XXXXXXXX (R/W) DTCR0 XXXXXXXX SIGCR ⎯ (R/W) -------0 XXXXXXXX (R/W) (R/W) 00000000 (R/W) DTCR2 00000000 (R/W) 00000000 DACR0 (R/W) -------0 DADR0 (R/W) PCRE ⎯ PCRJ ------0 0 (R/W) --0 0 0 0 0 0 OCRJ (R/W) (R/W) PCRI (R/W) --0 0 0 0 0 0 OCRI (R/W) D/A Converter XXXXXXXX TMRR0 (R/W) XXXXXXXX TMRR2 (R/W) Waveform Generator XXXXXXXX ⎯ 0000C0H Ext Int ⎯ 00000000 00000 000 ⎯ 8-/16-bit U/D Counter (R/W) 00000000 0000B4H to 0000BCH 0000CCH (R/W) 00000000 0000B0H 0000C8H CSR0 00000000 0000A8H 0000C4H 00000000 ⎯ -0 0 0 1 0 0 0 (R) ⎯ 0000A4H 0000ACH UDCR0 ⎯ -0 0 0 1 0 0 0 CCRL1 (R) 00000000 (R/W) 000090H 000094H UDCR1 00000000 Block +3 Reserved PCRD (R/W) 00000000 PCRH PCRC 00000000 (R/W) (R/W) --0 0 0 0 0 0 --0 0 0 0 0 0 -----0 0 0 ⎯ ⎯ ⎯ Pull-up Control ⎯ -----0 0 0 OCRH (R/W) ⎯ AICK Open-drain Control (R/W) 00000000 Analog Input Control (Continued) 30 DS07-16308-3E MB91130 Series Register Address 0000D0H 0000D4H +0 DDRF +1 (R/W) 00000000 DDRJ (R/W) DDRE +2 (R/W) 00000000 DDRI (R/W) --0 0 0 0 0 0 --0 0 0 0 0 0 ⎯ ⎯ GCN1 (R/W) 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH DDRD 00000000 (R) 11111111 11111111 PDUT0 (W) XXXXXXXX XXXXXXXX PTMR1 (R) 11111111 11111111 PDUT1 (W) XXXXXXXX XXXXXXXX PTMR2 (R) 11111111 11111111 PDUT2 (W) XXXXXXXX XXXXXXXX PTMR3 (R) 11111111 11111111 PDUT3 (W) XXXXXXXX XXXXXXXX PTMR4 (R) 11111111 11111111 PDUT4 (W) XXXXXXXX XXXXXXXX PTMR5 (R) 11111111 11111111 PDUT5 (W) XXXXXXXX XXXXXXXX (R/W) -----0 0 0 DDRL (R/W) 00000000 DDRC (R/W) 00000000 DDRG (R/W) --0 0 0 0 0 0 DDRK 00000000 (R/W) 00000000 PCSR0 (R/W) PCNL0 (R/W) 0000000- 00000000 PCSR1 (W) XXXXXXXX XXXXXXXX PCNH1 (R/W) PCNL1 (R/W) 0000000- 00000000 PCSR2 (W) XXXXXXXX XXXXXXXX PCNH2 (R/W) PCNL2 (R/W) 0000000- 00000000 PCSR3 (W) XXXXXXXX XXXXXXXX PCNH3 (R/W) PCNL3 (R/W) 0000000- 00000000 PCSR4 (W) XXXXXXXX XXXXXXXX PCNH4 (R/W) PCNL4 (R/W) 0000000- 00000000 PCSR5 (W) XXXXXXXX XXXXXXXX PCNH5 (R/W) 0000000- PPG ctl (W) XXXXXXXX XXXXXXXX PCNH0 Data Direction Register (R/W) GCN2 ⎯ 00110010 00010000 PTMR0 (R/W) DDRH Block +3 PCNL5 (R/W) PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 00000000 (Continued) DS07-16308-3E 31 MB91130 Series Register Address 000110H +0 +1 +2 +3 TMRLR (W) TMR (R) XXXXXXXX XXXXXXXX 000118H XXXXXXXX XXXXXXXX TMCSR ⎯ 000114H (W) TMR XXXXXXXX XXXXXXXX TMCSR ⎯ -------- -------- 00000000 -------- 00000000 DATCR XXXX0 0 0 0 XXXX0 0 0 0 ⎯ 000210H to 0003ECH ⎯ XXXXXXXX BSD1 0003E4H XXXXXXXX XXXXXXXX XXXXXXXX BSRR 0003FCH 000408H XXXXXXXX BSDC 0003F8H 000404H XXXXXXXX XXXXXXXX ICR00 (R/W) ----1 1 1 1 ICR04 (R/W) ----1 1 1 1 ICR08 (R/W) ----1 1 1 1 XXXXXXXX ICR01 (R/W) ----1 1 1 1 ICR05 (R/W) ----1 1 1 1 ICR09 (R/W) ----1 1 1 1 00000000 (R/W) 00020CH BSD0 -0 0 0 0 0 0 0 (R/W) 00000000 XXXXXXXX Reserved (R/W) DACSR 0003F0H Reload Timer 4 ----0000 0 0 0 0 0 0 0 0 DPDP 000208H 000400H (R/W) ⎯ 000200H Reload Timer 3 (R) XXXXXXXX XXXXXXXX 000120H to 0001FCH 000204H (R/W) ----0000 0 0 0 0 0 0 0 0 TMRLR 00011CH Block DMAC XXXX0 0 0 0 Reserved (W) XXXXXXXX XXXXXXXX (R/W) XXXXXXXX XXXXXXXX Bit Search Module (W) XXXXXXXX XXXXXXXX (R) XXXXXXXX ICR02 XXXXXXXX (R/W) ----1 1 1 1 ICR06 (R/W) ----1 1 1 1 ICR10 (R/W) ----1 1 1 1 ICR03 (R/W) ----1 1 1 1 ICR07 (R/W) ----1 1 1 1 ICR11 Interrupt Control Unit (R/W) ----1 1 1 1 (Continued) 32 DS07-16308-3E MB91130 Series Register Address 00040CH 000410H 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H +0 ICR12 +1 (R/W) ----1 1 1 1 ICR16 (R/W) ----1 1 1 1 ICR20 (R/W) ----1 1 1 1 ICR24 (R/W) ----1 1 1 1 ICR28 (R/W) ----1 1 1 1 ICR32 (R/W) ----1 1 1 1 ICR36 (R/W) ----1 1 1 1 ICR40 (R/W) ----1 1 1 1 ICR44 (R/W) ----1 1 1 1 DICR (R/W) -------0 ICR13 +2 (R/W) ----1 1 1 1 ICR17 000484H 000488H ICR18 ----1 1 1 1 ICR21 (R/W) ICR39 (R/W) ICR46 ICR43 (R/W) (R/W) ----1 1 1 1 (R/W) ICR47 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 ⎯ ---1 1 1 1 1 Delay Int ⎯ RSRR/WTCR (R/W) 1 XXXX - 0 0 GCR (R/W) 1 1 0 0 1 1-1 CT STCR (R/W) WPR (R/W) CTBR ----0 0 0 0 (W) (W) XXXXXXXX Clock Control Unit ⎯ XXXXXXXX (R/W) ⎯ 0 0--0-0 0 00048CH to 0005FCH Reserved PDRR 0 0 0 1 1 1-- Interrupt Control Unit ----1 1 1 1 (R/W) ICR42 ----1 1 1 1 HRCL ICR35 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 (R/W) ICR38 ----1 1 1 1 ICR45 ICR31 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 (R/W) ICR34 ----1 1 1 1 ICR41 ICR27 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 (R/W) ICR30 ----1 1 1 1 ICR37 ICR23 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 (R/W) ICR26 ----1 1 1 1 ICR33 ICR19 ----1 1 1 1 (R/W) (R/W) ----1 1 1 1 (R/W) ICR22 ----1 1 1 1 ICR29 ICR15 ----1 1 1 1 ----1 1 1 1 ICR25 (R/W) ----1 1 1 1 (R/W) 000434H to 00047CH 000480H ICR14 Block +3 ⎯ PLL Control Reserved (Continued) DS07-16308-3E 33 MB91130 Series Register Address 000600H +0 DDR3 (W) 00000000 000604H ⎯ 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H +1 DDR2 DDR6 ⎯ (W) DDR5 (W) 00000000 ⎯ ⎯ ⎯ ASR1 (W) AMR1 00000000 00000001 ASR2 (W) ASR3 (W) ---0 0 1 1 1 AMD5 (W) (W) AMR4 (W) 00000000 00000000 (W) AMD1 (W) 00000000 00000000 AMR5 00000000 00000101 (R/W) (W) -0 0 0 0 0 0 0 AMR3 00000000 00000100 AMD0 DDR8 Data Direction Register 00000000 00000000 00000000 00000011 ASR5 (W) 00000000 AMR2 (W) ASR4 DDR4 Block 00000000 00000000 00000000 00000010 (W) 00000000 00000000 (R/W) AMD32 0--0 0 0 0 0 (R/W) AMD4 00000000 (R/W) T-unit (R/W) 0--0 0 0 0 0 ⎯ 0--0 0 0 0 0 EPCR0 (W) EPCR1 ----1 1 0 0 -1------ (W) -------- 1 1 1 1 1 1 1 1 ⎯ PCR6 ⎯ (R/W) ⎯ 00000000 000634H to 0007BCH 0007C8H to 0007F8H ⎯ 00000000 00000000 000630H 0007C4H +3 (W) 00062CH 0007C0H +2 ⎯ FLCR (R/W) Reserved ⎯ 000X0000 FWTC Pull-up Control FLASH Control (R/W) ⎯ -----0 0 0 ⎯ Reserved (Continued) 34 DS07-16308-3E MB91130 Series (Continued) Address Register +0 +1 +2 LER 0007FCH ⎯ Block +3 (W) MODR -----0 0 0 (W) XXXXXXXX Little Endian Register Mode Register *1 : Do not execute RMW instructions to registers with write-only bits. *2 : Do not execute write access to read-only or reserved registers except for particular requests. *3 : Data in areas with “-” or reserved ones are unspecified. *4 : RMW instructions (RMW : Read / Modify / Write) AND Rj, @Ri OR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri DS07-16308-3E EOR EORH EORB BEORL BEORH Rj, @Ri Rj, @Ri Rj, @Ri #u4, @Ri #u4, @Ri 35 MB91130 Series ■ INTERRUPTION VECTOR Causes of MB91130 series interruptions and allocation of interruption vectors and interruption control registers are described in the interruption vector table. Interruption number Interruption Address *2 Offset Interruption sauce *1 of TBR default level Decimal Hexadecimal Reset 0 00 ⎯ 3FCH 000FFFFCH System reservation 1 01 ⎯ 3F8H 000FFFF8H System reservation 2 02 ⎯ 3F4H 000FFFF4H System reservation 3 03 ⎯ 3F0H 000FFFF0H System reservation 4 04 ⎯ 3ECH 000FFFECH System reservation 5 05 ⎯ 3E8H 000FFFE8H System reservation 6 06 ⎯ 3E4H 000FFFE4H System reservation 7 07 ⎯ 3E0H 000FFFE0H System reservation 8 08 ⎯ 3DCH 000FFFDCH System reservation 9 09 ⎯ 3D8H 000FFFD8H System reservation 10 0A ⎯ 3D4H 000FFFD4H System reservation 11 0B ⎯ 3D0H 000FFFD0H System reservation 12 0C ⎯ 3CCH 000FFFCCH System reservation 13 0D ⎯ 3C8H 000FFFC8H Exceptions to undefined instructions 14 0E ⎯ 3C4H 000FFFC4H System reservation 15 0F ⎯ 3C0H 000FFFC0H External interruption 0 16 10 ICR00 3BCH 000FFFBCH External interruption 1 17 11 ICR01 3B8H 000FFFB8H External interruption 2 18 12 ICR02 3B4H 000FFFB4H External interruption 3 19 13 ICR03 3B0H 000FFFB0H External interruption 4 20 14 ICR04 3ACH 000FFFACH External interruption 5 21 15 ICR05 3A8H 000FFFA8H External interruption 6 22 16 ICR06 3A4H 000FFFA4H External interruption 7 23 17 ICR07 3A0H 000FFFA0H External interruption 8 to 15 24 18 ICR08 39CH 000FFF9CH External interruption 16 to 23 25 19 ICR09 398H 000FFF98H UART0 (Reception completion) 26 1A ICR10 394H 000FFF94H UART1 (Reception completion) 27 1B ICR11 390H 000FFF90H UART2 (Reception completion) 28 1C ICR12 38CH 000FFF8CH UART3 (Reception completion) 29 1D ICR13 388H 000FFF88H UART4 (Reception completion) 30 1E ICR14 384H 000FFF84H (Continued) 36 DS07-16308-3E MB91130 Series Interruption sauce Interruption number Interruption level *1 Decimal Hexadecimal Offset Address *2 of TBR default UART0 (Transmission completion) 31 1F ICR15 380H 000FFF80H UART1 (Transmission completion) 32 20 ICR16 37CH 000FFF7CH UART2 (Transmission completion) 33 21 ICR17 378H 000FFF78H UART3 (Transmission completion) 34 22 ICR18 374H 000FFF74H UART4 (Transmission completion) 35 23 ICR19 370H 000FFF70H DMAC (end, error) 36 24 ICR20 36CH 000FFF6CH Reload timer 0 37 25 ICR21 368H 000FFF68H Reload timer 1 38 26 ICR22 364H 000FFF64H Reload timer 2 39 27 ICR23 360H 000FFF60H Reload timer 3 40 28 ICR24 35CH 000FFF5CH Reload timer 4 41 29 ICR25 358H 000FFF58H A/D (sequential type) 42 2A ICR26 354H 000FFF54H PPG0 43 2B ICR27 350H 000FFF50H PPG1 44 2C ICR28 34CH 000FFF4CH PPG2 45 2D ICR29 348H 000FFF48H PPG3 46 2E ICR30 344H 000FFF44H PPG4/5 47 2F ICR31 340H 000FFF40H Waveform generator 48 30 ICR32 33CH 000FFF3CH U/D counter 0 (compare/ underflow-overflow, up/down invert) 49 31 ICR33 338H 000FFF38H U/D counter 1 (compare/ underflow-overflow, up/down invert) 50 32 ICR34 334H 000FFF34H ICU0 (load) 51 33 ICR35 330H 000FFF30H ICU1 (load) 52 34 ICR36 32CH 000FFF2CH ICU2 (load) 53 35 ICR37 328H 000FFF28H ICU3 (load) 54 36 ICR38 324H 000FFF24H OCU0 (matched) 55 37 ICR39 320H 000FFF20H OCU1 (matched) 56 38 ICR40 31CH 000FFF1CH OCU2 (matched) 57 39 ICR41 318H 000FFF18H OCU3 (matched) 58 3A ICR42 314H 000FFF14H OCU4/5 (matched) 59 3B ICR43 310H 000FFF10H OCU6/7 (matched) 60 3C ICR44 30CH 000FFF0CH Level comparator 61 3D ICR45 308H 000FFF08H 16-bit freerun timer 62 3E ICR46 304H 000FFF04H Delay interruption factor bit 63 3F ICR47 300H 000FFF00H (Continued) DS07-16308-3E 37 MB91130 Series (Continued) Interruption sauce Interruption number Interruption level *1 Decimal Hexadecimal Offset Address *2 of TBR default System reservation (used under REALOS *3) 64 40 ⎯ 2FCH 000FFEFCH System reservation (used under REALOS *3) 65 41 ⎯ 2F8H 000FFEF8H Used under INT instruction 66 42 ⎯ 2F4H 000FFEF4H Used under INT instruction 67 43 ⎯ 2F0H 000FFEF0H Used under INT instruction 68 44 ⎯ 2ECH 000FFEECH Used under INT instruction 69 45 ⎯ 2E8H 000FFEE8H Used under INT instruction 70 46 ⎯ 2E4H 000FFEE4H Used under INT instruction 71 47 ⎯ 2E0H 000FFEE0H Used under INT instruction 72 48 ⎯ 2DCH 000FFEDCH Used under INT instruction 73 49 ⎯ 2D8H 000FFED8H Used under INT instruction 74 4A ⎯ 2D4H 000FFED4H Used under INT instruction 75 4B ⎯ 2D0H 000FFED0H Used under INT instruction 76 4C ⎯ 2CCH 000FFECCH Used under INT instruction 77 4D ⎯ 2C8H 000FFEC8H Used under INT instruction 78 4E ⎯ 2C4H 000FFEC4H Used under INT instruction 79 4F ⎯ 2C0H 000FFEC0H Used under INT instruction 80 to 255 50 to FF ⎯ 2BCH to 000H 000FFEBCH to 000FFC00H *1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller. ICR is prepared in accordance with each interruption request. *2 : TBR is the register that indicates the starting address of the vector table for EIT. Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses. *3 : 40H, 41H interruptions for system codes are used in the event that REALOS/FR is used. 38 DS07-16308-3E MB91130 Series ■ PERIPHERAL RESOURCES 1. Bus Interface The bus interface controls the interface with external memory and external I/O. • • • • • • • Bus Interface Characteristics 24-bit (16 MB) address output 16/8-bit bus width can be set. Insertion of programmable “automatic memory wait” (maximum of 7 cycles) Supports “little endian” mode Unused addresses / data pins can be used as I/O ports. Clock doubled should be used if the external bus exceeds 25 MHz. Bus speed is 1/2 of the CPU speed. • Areas A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be randomly arranged per 64 KB at least using area selection registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) in an area of 4 GB. The area 0 is allocated to space outside the area specified by ASR1 to ASR5. External areas other than 00010000H to 0005FFFFH are deemed area 0 on resetting. There is no chip selection output pin so no setting is required. Setting it has no effect on usage. “Area Arrangement Example 1” shows an example in which areas 1 to 5 are arranged from 00100000H to 0014FFFFH in 64 KB units. Also, “Area Arrangement Example 2” shows an example in which area 1 is arranged as 00000000H to 0007FFFFH in 512 KB and areas 2 to 5 are arranged as 00100000H to 004FFFFFH in 1-MB units. 00000000H 00000000H 00080000H 00080000H CS0 (1 Mbyte) CS1 (512 Kbyte) CS0 (512 Kbyte) 000FFFFFH CS2 (1 Mbyte) 000FFFFFH 001FFFFFH CS1 (64 Kbyte) 0010FFFFH CS3 (1 Mbyte) CS2 (64 Kbyte) 0011FFFFH 0012FFFFH 002FFFFFH CS3 (64 Kbyte) CS4 (1 Mbyte) CS4 (64 Kbyte) 0013FFFFH CS5 (64 Kbyte) 003FFFFFH 0014FFFFH CS5 (1 Mbyte) 004FFFFFH CS0 Area Arrangement Example 1 DS07-16308-3E CS0 Area Arrangement Example 2 39 MB91130 Series A - Out DATA BUS ADDRESS BUS • Block Diagram write buffer switch read buffer switch M U X External DATA Bus DATA BLOCK ADDRESS BLOCK +1 or +2 address buffer External Address Bus shifter inpage CS0 - CS5 comparator ASR AMR External pin control area RD WR0. WR1 Controls all blocks registers & Control 40 BRQ BGRNT RDY DS07-16308-3E MB91130 Series • Register List Address 15 8 7 0 0000060CH ASR1 Area Select Register 1 0000060EH AMR1 Area Mask Register 1 00000610 H ASR2 Area Select Register 2 00000612 H AMR2 Area Mask Register 2 00000614 H ASR3 Area Select Register 3 00000616 H AMR3 Area Mask Register 3 00000618 H ASR4 Area Select Register 4 0000061AH AMR4 Area Mask Register 4 0000061CH ASR5 Area Select Register 5 0000061EH AMR5 Area Mask Register 5 00000620 H AMD0 AMD1 Area Mode Register 0 / Area Mode Register 1 00000622 H AMD32 AMD4 Area Mode Register 32 / Area Mode Register 4 00000624 H AMD5 ⎯ Area Mode Register 5 00000626 H RFCR ReFresh Control Register 0000062CH DMCR4 DRAM Control Register 4 0000062EH DMCR5 DRAM Control Register 4 00000688 H EPCR0 EPCR1 External Pin Control Register 000007FEH LER MODR Little Endian Register / MODe Register Note : Functional pins have not been prepared in the shaded area for MB91130 series, so these registers should not be accessed. DS07-16308-3E 41 MB91130 Series 2. I/O Port MB91130 series can be used as an I/O port when the setting for resources dealing with each pin does not use the pin for input/output. As regards the read value of the port (PDR) , the pin level is read out when input is set for the port. If output is set, the data register value is read out. This is the same for reading under Read Modify Write. If the input setting is changed to output setting, output data should be set first. If Read Modify Write instructions (i.e. bit set) are used in this case, the data that is read out is the input data from the pin and is not the latch value of the data register, so care must be taken. • Basic I/O Port Block Diagram Data bus Resource input 0 1 PDR read pin 0 PDR Resource output DDR 1 Resource output permission PDR : Port Data Register DDR : Data Direction Register • I/O Port Register The I/O port consists of the Port Data Register (PDR) and Port Direction Register (DDR) . • In case of input mode (DDR = “0”) When PDR reads : Level of external pins handled is read out. When PDR writes : Set value is written in PDR. • In case of output mode (DDR = “1”) When PDR reads : PDR values are read out. When PDR writes : PDR values are output to the external pin handled. • Switching control for resources and ports of the analog pin (A/D) • Resources and ports of the analog pin (A/D) are switched using the Analog Input Control register on Port K (AICK) . This controls whether Port K is used as an analog or general-purpose port. 0 : General-purpose port 1 : Analog input (A/D) 42 DS07-16308-3E MB91130 Series • Block Diagram of Input/Output Port (with Pull-up Resistance) Data bus Resource input 0 Pull up resistance 1 PDR read (approximately 50 kΩ) pin 0 PDR Resource output DDR 1 Resource output permission PCR PDR : Port Data Register DDR : Data Direction Register PCR : Pull-up Control Register • Pull-up resistance control register (PCR) R/W Turns pull-up resistance ON/OFF. 0 : Pull-up resistance turned off 1 : Pull-up resistance turned on Notes : • The pull-up resistance control register setting is handled as a priority in stop mode (HIZ = 1) as well. • Use of the pull-up resistance control function is prohibited when the pin concerned is used as the external bus pin. “1” should not be written in this register. DS07-16308-3E 43 MB91130 Series • Block Diagram of Input / Output Port (Open-drain Output Function with Pull-up Resistance) Data bus Resource input 0 1 PDR read pin 0 PDR Resource output 1 Resource output permission DDR ODCR PCR PDR : Port Data Register DDR : Data Direction Register ODCR : OpenDrain Control Register PCR : Pull-up Control Register • Pull-up resistance control register (PCR) R/W Controls pull up resistance ON/OFF. 0 : Without pull-up resistance 1 : With pull-up resistance • Open-drain control register (ODCR) R/W Controls open-drain in output mode. 0 : Standard output port in output mode 1 : Open-drain output port in output mode Notes : • This has no meaning in input mode (output Hi-Z) . Input/output mode is decided by the Direction Register (DDR) . • Pull-up resistance control register setting is handled as the priority in stop mode (HIZ = 1) as well. • Use of both the pull-up resistance control function and open-drain control function are prohibited when the pin concerned is used as an external bus pin. “1” should not be written in both registers. 44 DS07-16308-3E MB91130 Series • Port Data Register (PDR) PDR2 7 6 5 4 3 2 1 0 Initial value Access P24 P23 P22 P21 P20 XXXXXXXXB R/W Address : 000001H P27 P26 P25 PDR3 7 6 5 4 3 2 1 0 Initial value Access Address : 000000H P37 P36 P35 P34 P33 P32 P31 P30 XXXXXXXXB R/W PDR4 7 6 5 4 3 2 1 0 Initial value Access Address : 000007H P47 P46 P45 P44 P43 P42 P41 P40 XXXXXXXXB R/W PDR5 7 6 5 4 3 2 1 0 Initial value Access Address : 000006H P57 P56 P55 P54 P53 P52 P51 P50 XXXXXXXXB R/W PDR6 7 6 5 4 3 2 1 0 Initial value Access Address : 000005H P67 P66 P65 P64 P63 P62 P61 P60 XXXXXXXXB R/W PDR8 7 6 5 4 3 2 1 0 Initial value Access Address : 00000BH ⎯ P86 P85 P84 P83 P82 P81 P80 - XXXXXXXB R/W PDRC 7 6 5 4 3 2 1 0 Initial value Access Address : 000013H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 XXXXXXXXB R/W PDRD 7 6 5 4 3 2 1 0 Initial value Access Address : 000012H PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 XXXXXXXXB R/W PDRE 7 6 5 4 3 2 1 0 Initial value Access Address : 000011H PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 XXXXXXXXB R/W PDRF 7 6 5 4 3 2 1 0 Initial value Access Address : 000010H PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 XXXXXXXXB R/W PDRG 7 6 5 4 3 2 1 0 Initial value Access Address : 000017H ⎯ ⎯ PG5 PG4 PG3 PG2 PG1 PG0 - - XXXXXXB R/W PDRH 7 6 5 4 3 2 1 0 Initial value Access Address : 000016H ⎯ ⎯ ⎯ ⎯ ⎯ PH2 PH1 PH0 - - - - - XXXB R/W PDRI 7 6 5 4 3 2 1 0 Initial value Access Address : 000015H ⎯ ⎯ PI5 PI4 PI3 PI2 PI1 PI0 - - XXXXXXB R/W PDRJ 7 6 5 4 3 2 1 0 Initial value Access Address : 000014H ⎯ ⎯ PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 - - XXXXXXB R/W PDRK 7 6 5 4 3 2 1 0 Initial value Access Address : 00001BH PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 XXXXXXXXB R/W PDRL 7 6 5 4 3 2 1 0 Initial value Access Address : 00001AH PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 XXXXXXXXB R/W PDR2 to PDR6, PDR8, PDRC to PDRL are input/output data registers of the I/O port. Input/output control is carried out by DDR2 to DDR6, DDR8, DDRC to DDRL that are handled. DS07-16308-3E 45 MB91130 Series • Data Direction Register (DDR) DDR2 7 6 5 4 3 2 1 0 Address : 000601H P27 P26 P25 P24 P23 P22 P21 P20 DDR3 7 6 5 4 3 2 1 0 Address : 000600H P37 P36 P35 P34 P33 P32 P31 P30 DDR4 7 6 5 4 3 2 1 0 Address : 000607H P47 P46 P45 P44 P43 P42 P41 P40 DDR5 7 6 5 4 3 2 1 0 Address : 000606H P57 P56 P55 P54 P53 P52 P51 P50 DDR6 7 6 5 4 3 2 1 0 Address : 000605H P67 P66 P65 P64 P63 P62 P61 P60 7 6 5 4 3 2 1 0 Address : 00060BH ⎯ P86 P85 P84 P83 P82 P81 P80 DDRC 7 6 5 4 3 2 1 0 Address : 0000D3H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 DDRD 7 6 5 4 3 2 1 0 Address : 0000D2H PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DDRE 7 6 5 4 3 2 1 0 Address : 0000D1H PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 7 6 5 4 3 2 1 0 Address : 0000D7H ⎯ ⎯ PG5 PG4 PG3 PG2 PG1 PG0 DDRH 7 6 5 4 3 2 1 0 Address : 0000D6H ⎯ ⎯ ⎯ ⎯ ⎯ PH2 PH1 PH0 7 6 5 4 3 2 1 0 Address : 0000D5H ⎯ ⎯ PI5 PI4 PI3 PI2 PI1 PI0 DDRJ 7 6 5 4 3 2 1 0 Address : 0000D4H ⎯ ⎯ PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 DDRK 7 6 5 4 3 2 1 0 Address : 0000DBH PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRL 7 6 5 4 3 2 1 0 Address : 0000DAH PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 DDR8 DDRF Address : 0000D0H DDRG DDRI Initial value Access 00000000B W Initial value Access 00000000B W Initial value Access 00000000B W Initial value Access 00000000B W Initial value Access 00000000B W Initial value Access - 0000000B W Initial value Access 00000000B R/W Initial value Access 00000000B R/W Initial value Access 00000000B R/W Initial value Access 00000000B R/W Initial value Access - - 000000B R/W Initial value Access - - - - - 000B R/W Initial value Access - - 000000B R/W Initial value Access - - 000000B R/W Initial value Access 00000000B R/W Initial value Access 00000000B R/W DDR2 to DDR6, DDR8, DDRC to DDRL control input/output direction of the I/O ports handled per bit. DDR = 0 : Port input DDR = 1 : Port output “0” must be written into the empty bit. 46 DS07-16308-3E MB91130 Series • Pull up Control Register (PCR) PCR6 7 6 5 4 3 2 1 0 Address : 000631H P67 P66 P65 P64 P63 P62 P61 P60 PCRC 7 6 5 4 3 2 1 0 Address : 0000C3H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCRD 7 6 5 4 3 2 1 0 Address : 0000C2H PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PE1 PE0 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ PH2 PH1 PH0 7 6 5 4 3 2 1 0 ⎯ ⎯ PI5 PI4 PI3 PI2 PI1 PI0 7 6 5 4 3 2 1 0 ⎯ ⎯ PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PCRE Address : 0000C1H PCRH Address : 0000C6H PCRI Address : 0000C5H PCRJ Address : 0000C4H Initial value Access 00000000B R/W Initial value Access 00000000B R/W Initial value Access 00000000B R/W Initial value Access - - - - - - 00B R/W Initial value Access - - - - - 000B R/W Initial value Access - - 000000B R/W Initial value Access - - 000000B R/W DDR6, DDRC to DDRE, DDRH to DDRJ carry out pull-up resistance control of the I/O ports handled. PCR = 0 : Pull-up resistance turned off PCR = 1 : Pull-up resistance turned on • Open-drain Control Register (ODCR) OCRH Address : 0000CAH OCRI Address : 0000C9H OCRJ Address : 0000C8H 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ PH2 PH1 PH0 7 6 5 4 3 2 1 0 ⎯ ⎯ PI5 PI4 PI3 PI2 PI1 PI0 7 6 5 4 3 2 1 0 ⎯ ⎯ PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Initial value Access - - - - - 000B R/W Initial value Access - - 000000B R/W Initial value Access - - 000000B R/W OCRH to OCRJ carry out open-drain control in output mode of the I/O ports handled. OCR = 0 : Standard output port in output mode OCR = 1 : Open-drain output port in output mode This has no meaning in input mode (output Hi-z) . DS07-16308-3E 47 MB91130 Series • Analog Input Control Register (AICR) AICK 7 6 5 4 3 2 1 0 Address : 0000CFH PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Initial value Access 00000000B R/W AICK controls each pin of the I/O ports handled as follows. AIC = 0 : Analog input mode AIC = 1 : Port input mode Set to “0” when reset. 48 DS07-16308-3E MB91130 Series 3. 8/16-bit Up/Down Counter / Timer 8/16-bit up/down counter / timer is configured of event input pins × 6, 8-bit up/down counters × 2, 8-bit reload / compare registers × 2 and their control circuits. • Characteristics of 8/16-bit Up/Down Counter / Timer • Counting from (0) d to (256) d is possible using an 8-bit counting register. (Counting from (0) d to (65535) d is possible in 16-bit × 1 operation mode.) • 4 types of counting mode can be selected by the count clock • Selection can be made from two types of internal clock as the count clock in timer mode. • Detection edge of the external pin input signals can be selected in up/down count mode. • Phase difference count mode is suited to count encoders such as motors. Turning angle and turning number, etc., can easily and accurately be counted by separately inputting phase A, B and Z outputs of the encoder. • Selection can be made from two function types for the ZIN pin (valid for all modes) . • Compare and reload functions are featured, and each function can be used alone or in combination. Up/down counting with random width can be carried out using both functions in combination. • The count direction directly before can be identified by the count direction flag. • Generation of interruptions in case of compared match, reload (underflow) or overflow and in cases where the count direction is changed can be controlled separately. DS07-16308-3E 49 MB91130 Series • Block Diagram 8/16-bit Up/Down Counter / Timer (ch.0) Data bus 8 bit Reload / Compare Register 0 (RCR0) CGE1 CGE0 C/GS ZIN0 RCUT Edge/level detection Reload control UCRE RLDE Counter clear UDCC 8 bit Up/Down Count Register 0 (UDCR0) Carry CES1 CES0 UDFF OVFF CMS1 CMS0 CITE AIN0 BIN0 Up/down count clock selection Pre-scalar CMPF UDIE Count clock UDF1 UDF0 CDCF CFIE CSTR Interruption output CLKS 50 DS07-16308-3E MB91130 Series 8/16-bit Up/Down Counter / Timer (ch.1) Data bus 8 bit Reload / Compare Register 1 (RCR1) CGE1 CGE0 C/GS ZIN1 Edge/level detection UDCC RCUT Reload control UCRE RLDE Counter clear 8 bit Up/Down Count Register 1 (UDCR1) CMPF UDFF OVFF CMS1 CMS0 CES1 CES0 M16E CITE Carry UDIE Count clock AIN1 BIN1 Up/down count clock selection Pre-scalar UDF1 UDF0 CDCF CFIE CSTR Interruption output CLKS DS07-16308-3E 51 MB91130 Series • Register List bit 31 24 23 16 15 0 RCR0 UDCR1 UDCR0 CCRH0 CCRL0 ⎯ CSR0 CCRH1 CCRL1 ⎯ CSR1 Up/down count register ch.0 (UDCR0) bit 7 6 Address : 000087H D07 D06 5 4 3 2 1 0 D05 D04 D03 D02 D01 D00 Up/down count register ch.1 (UDCR1) bit 15 14 Address : 000086H D17 D16 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 Reload compare register ch.0 (RCR0) bit 7 6 Address : 000085H D07 D06 Reload compare register ch.1 (RCR1) bit 15 14 Address : 000084H D17 D16 5 4 3 2 1 0 D05 D04 D03 D02 D01 D00 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 3 2 1 0 OVFF UDFF UDF1 UDF0 3 2 1 0 UDCC CGSC CGE1 CGE0 Counter Status register ch.0, ch.1 (CSR0, CSR1) bit 7 6 5 4 00008BH Address : CSTR CITE UDIE CMPF 00008FH Counter control register ch.0, ch.1 (CCRL0, CCRL1) bit 7 6 5 4 000089H Address : ⎯ CTUT UCRE RLDE 00008DH 52 8 7 RCR1 Counter control register ch.0 (CCRH0) bit 15 14 Address : 000088H M16E CDCF 13 12 11 10 9 8 CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register ch.1 (CCRH1) bit 15 14 Address :00008CH ⎯ CDCF 13 12 11 10 9 8 CFIE CLKS CMS1 CMS0 CES1 CES0 DS07-16308-3E MB91130 Series 4. 16-bit Reload Timer The 16-bit timer is configured with a 16-bit down counter, 16-bit reload register, pre-scalar to prepare the internal count clock and control register. Selection can be made from three types of internal clocks (Peripheral clock 2 / 8 / 32 cycles) as the input clock. DMA transfer can be initiated by interruption. The MB91130 series features a 5-channel timer. • Block Diagram 16 16-bit reload register 8 Reload RELD 16 OUTE UF 16-bit down counter OUTL 2 OUT CTL. R - BUS GATE INTE 2 IRQ UF CSL1 CNTE Clock selector CSL0 Re-trigger 2 TRG IN CTL. EXCK φ φ φ 21 23 25 Pre-scalar clear 3 PWM (ch.0, ch.1) A/D (ch.2) MOD2 MOD1 Peripheral Clock MOD0 3 Channel 2 TO output of the reload timer is connected to the A/D converter inside the LSI. Thus, A/D conversion can be started up at the cycle set in the reload register. DS07-16308-3E 53 MB91130 Series 5. PPG Timer The PPG timer can efficiently output accurate PWM waveforms. The MB91130 series features a 6-channel PPG timer. • PPG Timer Characteristics • Each channel is configured with a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty setting buffer and pin control area. • Selection can be made from four types of count clocks for 16-bit down counters. Internal clock φ, φ4, φ16, φ64 • Counter values can be initialized to “FFFFH” by resetting and counter borrowing. • PWM output is available per channel. • Register outline Cycle setting register : Reloading register with buffer Duty setting register : Compare register with buffer Transfer from buffer is carried out by counter borrowing. • Pin control outline Set to “1” by duty match. (Priority) Resets to “0” by counter borrowing. All “L” (or “H”) can simply be output by using the output values fixing mode. Polarization can also be specified. • Interruption request can be generated by selecting from the following combinations. Initiation of this timer Counter borrow generation (cycle match) Duty match generation Counter borrow generation (cycle match) or duty match generation DMA transfer can be initiated by the above interruption requests. • Simultaneous initiation of a number of channels can be set by software or other interval timers. Re-start during operation can also be set. 54 DS07-16308-3E MB91130 Series • Block Diagram Overall Block Diagram of PPG Time 16-bit reload timer ch.0 TRG input PWM timer ch.0 PWM0 16-bit reload timer ch.1 TRG input PWM timer ch.1 PWM1 4 TRG input PWM timer ch.2 PWM2 4 TRG input PWM timer ch.3 PWM3 External TRG4 PWM timer ch.4 PWM4 External TRG5 PWM timer ch.5 PWM5 General control register 2 General control register 1 (factor selection) External TRG0 to 3 DS07-16308-3E 55 MB91130 Series Block Diagram of PPG Timer for 1 Channel PCSR PDUT Pre-scalar 1/1 1/4 1 / 16 1 / 64 CMP Load CK 16-bit down counter Start Borrow PPG mask S Peripheral system clock Q PWM OUTPUT R Reverse bit Enable TRG input Edge detection Interruption selection IRQ Soft trigger 56 DS07-16308-3E MB91130 Series • Register list Address 15 0 GCN1 000000DCH 000000DFH GCN2 R/W General control register 1 R/W General control register 2 000000E0H PTMR R ch.0 Timer register 000000E2H PCSR W ch.0 Peripheral setting register 000000E4H PDUT W ch.0 Duty setting register R/W ch.0 Control status register 000000E6H PCNL PCNH 000000E8H PTMR R ch.1 Timer register 000000EAH PCSR W ch.1 Peripheral setting register 000000ECH PDUT W ch.1 Duty setting register R/W ch.1 Control status register 000000EEH PCNH PCNL 000000F0H PTMR R ch.2 Timer register 000000F2H PCSR W ch.2 Peripheral setting register 000000F4H PDUT W ch.2 Duty setting register R/W ch.2 Control status register 000000F6H PCNL PCNH 000000F8H PTMR R ch.3 Timer register 000000FAH PCSR W ch.3 Peripheral setting register 000000FCH PDUT W ch.3 Duty setting register R/W ch.3 Control status register 000000FEH PCNH PCNL (Continued) DS07-16308-3E 57 MB91130 Series (Continued) Address 0 00000100H PTMR R ch.4 Timer register 00000102H PCSR W ch.4 Peripheral setting register 00000104H PDUT W ch.4 Duty setting register R/W ch.4 Control status register 00000106H PCNL PCNH 00000108H PTMR R ch.5 Timer register 0000010AH PCSR W ch.5 Peripheral setting register 0000010CH PDUT W ch.5 Duty setting register R/W ch.5 Control status register 0000010EH 58 15 PCNH PCNL DS07-16308-3E MB91130 Series 6. Multifunction Timer The multifunction timer unit is configured of a 16-bit freerun timer × 1, 16-bit output compare × 8, 16-bit input capture × 4, 16-bit PPG timer × 6 ch and waveform generation area modules. 12 independent waveform outputs based on a 16-bit free-run timer are possible using this function and measurement of input pulse width and external clock cycle is also possible. • Multifunction Timer Configuration • 16-bit free-run timer ( × 1) The 16-bit free-run timer consists of a 16-bit up counter, control register, 16-bit compare clear register and pre-scalar. Output values of this counter are used as the base timer for output compare and input capture. • Counter operation clocks can be selected from six types. Six types of internal clocks (φ2, φ4, φ8, φ16, φ32, φ64) φ : Peripheral clock • Interruption can be generated by overflow of the counter value and a compared match with compare clear register. (Mode setting is required for a compared match.) • Counter value can be initialized to “0000H” by a compared match with the reset, software clear or the compare clear register. • Output compare ( × 8) Output compare is configured of 16-bit compare register × 8, latch for compare output and control register. Interruption can be generated as well as reversing output level when the 16-bit free-run timer value and compare register value match. • 8 compare registers can be operated independently. Output pins and interruption flags support each compare register. • Output pins can be controlled by pairing two compare registers. Output pins are reversed using two compare registers. • Initial value of each output pin can be set. • Interruption can be generated by matching compare. • Input capture ( × 4) Input capture is configured with four independent external input pins , supported capture and control register. 16-bit free-run timer value is held in the capture register by detecting the random edge of signals that are input by the external input pin, and interruption can simultaneously be generated. • Valid edges (rising edge, falling edge, both edges) of external input signals can be selected. • Four input captures can be operated independently. • Interruption can be generated by the valid edges of external input signals. • 16-bit PPG timer ( × 6) Refer to PPG timer DS07-16308-3E 59 MB91130 Series • Waveform Generation Area The waveform generation area is configured with 8-bit timer × 3, 8-bit reload register × 3, timer control register × 3 and 8-bit waveform control register. This control circuit controls the waveform of the 16-bit PPG timer and real-time output, and DC chopper output and non-overlapping 3-phase waveform output to be used for inverter control are possible. • Non-overlapping pulse output of the PPG timer is possible by setting dead time of the 8-bit timer (dead time timer function) . • Real timer output is operated by the 2-channel mode and non-overlapping output of the waveform is possible by setting the dead time of the 8-bit timer (dead time timer function) . • Operation of PPG timer can easily be started/stopped by generating a GATE signal for the PPG timer operation through match detection of real-time output compare (GATE function). • The 8-bit timer is operated by match detection of real-time output compare, and operation of the PPG timer can easily be started/stopped by generating a GATE signal for the PPG timer until the 8-bit timer is stopped (GATE function) . • Pin output can be forcibly controlled by input to the DTTI pin. Pins can be controlled externally even if oscillations stop due to lack of clocks for inputs to this pin. (Each pin level can be set by the program .) If this function is used, the port should be set to output (DDR = 1) and the output value should be described in the PDR beforehand. 60 DS07-16308-3E MB91130 Series • Block Diagram Block Diagram of PPG Timer for 1 Channel φ Interruption IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Cycle device Clock 16-bit free-run timer 16-bit compare clear register (Ch. 6 compare register) Compare register 0/2/4 ICLR MSI3 to MSI0 Compare circuit Compare register 1/3/5 Interruption Compare circuit ICRE R-BUS T Q RT0/2/4 To waveform generation area T Q RT1/3/5 To waveform generation area CMOD Compare circuit IOP1 IOP0 IOE1 IOE0 Interruption Interruption IN 0/2 Edge detection Capture data register 0/2 EG11 Capture data register 1/3 EG10 EG01 Edge detection ICP0 ICP1 ICE0 EG00 IN 1/3 ICE1 Interruption Interruption DS07-16308-3E 61 MB91130 Series Block Diagram of Waveform Generation Area φ DCK2 DCK1 DCK0 TMD1 TMD0 NRSL DTIL DTIE DTTI control circuit DTTI Cycle divider GATE 0/1 Clock RT0 Waveform generation area TO0 TO1 RT1 8-bit timer Compare circuit 8-bit timer register 0 Selector Selector Dead time generation RTO0/U RTO1/X U X R−BUS GATE 2/3 Waveform generation area RT2 TO2 TO3 RT3 8-bit timer Compare circuit 8-bit timer register 1 Selector Selector Dead time generation RTO2/V RTO3/Y V Y GATE 4/5 Waveform generation area RT4 TO4 TO5 RT5 8-bit timer Compare circuit 8-bit timer register 2 62 Selector Selector Dead time generation RTO4/W RTO5/Z W Z DS07-16308-3E MB91130 Series • Registers List Address 15 8 7 000044H to 4BH (R) IPCP 00004DH, 4FH ICS (R/W) 000054H to 63H OCCP (R/W) 000064H to 6BH OCS (R/W) 00006CH, 6DH TCDT (R/W) 00006EH, 6FH TCCS (R/W) 0000ACH, AEH B2H 0000ADH, AFH B3H 0000B1H DS07-16308-3E 0 (R/W) DTCR TMRR (R/W) STGCR (R/W) 63 MB91130 Series 7. External Interruption The external interruption control area is the block that controls the external interruption requests input in INT0 to INT23. The level of request to be detected can be selected from “H”, “L”, “Rising edge” or “ Falling edge”. • Block diagram R-BUS 24 Interruption requests Interruption permission register 24 Factor F/F Gate 24 Edge detection circuit 24 INT0 to INT23 Interruption factor register 48 Request level setting register • Register List External interruption permission register (ENIR) bit 7 6 5 ER7 ER6 4 3 2 1 0 ER4 ER3 ER2 ER1 ER0 12 11 10 9 8 ER5 ER4 ER3 ER2 ER1 ER0 5 4 3 2 1 0 LB2 LA2 LB1 LA1 LB0 LA0 ER5 External interruption factor register (EIRR) 15 14 13 bit ER7 ER6 Request level setting register (ELVR) 7 6 bit LB3 bit LA3 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 There are three sets of the above registers (for 8 channels) for a total of 24 channels. 64 DS07-16308-3E MB91130 Series 8. Delay Interruption Module The delay interruption module generates interruptions for task switching. Interruption requests to the CPU can be generated / cancelled using software with this module. • Block Diagram Refer to “9.(2) Block Diagram of Interruption Controller” for the block diagram of the delay interruption generation area. • Register List Address : 00000430H bit 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DLYI DICR R/W DS07-16308-3E 65 MB91130 Series 9. Interruption Controller The interruption controller carries out interruption reception and arbitration. • Hardware configuration of the interruption controller This module consists of the following items. • ICR register • Interruption priority judgement circuit • Interruption level, interruption number (vector) generation area • Cancellation request generation area for HOLD request • Major interruption controller functions This module has the following functions. • Detection of interruption requests • Priority grade judgement (depending on the level and number) • Transferring interruption level of factors for the judgement results (to CPU) • Transferring interruption number of factors for the judgement results (to CPU) • Recovery instruction from stop mode by generating interruption • Cancellation of HOLD request to the bus master • Resetting Interruption Factors There are restrictions between RETI instructions and those for resetting interruption factors in the interruption routine. 66 DS07-16308-3E MB91130 Series • Block Diagram INT0 IM Priority grade judgement OR 5 NMI LEVEL4 to 0 NMI processing 4 LEVEL judgement ICR00 RI00 VECTOR judgement 6 Generation of LEVEL / VECTOR HLDREQ (Holding request) HLDCAN VCT5 to 0 ICR47 RI47 (DLYIRQ) DLYI R-BUS Note : DLYI shown in the figure indicates delay interruption area. (Refer to the chapter on the delay interruption module for details.) INT0 is the wake-up signal to the clock control area in case of sleep or stop. HLDCAN is the bus vacation request signal to bus masters other than the CPU. There is no NMI function in this model. DS07-16308-3E 67 MB91130 Series • Register List bit 7 6 5 4 3 2 1 0 Address : 00000400H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR00 Address : 00000401H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR01 Address : 00000402H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR02 Address : 00000403H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR03 Address : 00000404H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR04 Address : 00000405H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR05 Address : 00000406H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR06 Address : 00000407H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR07 Address : 00000408H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR08 Address : 00000409H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR09 Address : 0000040AH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR10 Address : 0000040BH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR11 Address : 0000040CH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR12 Address : 0000040DH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR13 Address : 0000040EH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR14 Address : 0000040FH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR15 Address : 00000410H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR16 Address : 00000411H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR17 Address : 00000412H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR18 Address : 00000413H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR19 Address : 00000414H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR20 Address : 00000415H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR21 Address : 00000416H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR22 Address : 00000417H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR23 Address : 00000418H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR24 Address : 00000419H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR25 Address : 0000041AH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR26 Address : 0000041BH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR27 Address : 0000041CH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR28 Address : 0000041DH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR29 Address : 0000041EH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR30 Address : 0000041FH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR31 R/W R/W R/W R/W (Continued) 68 DS07-16308-3E MB91130 Series (Continued) bit 7 6 5 4 3 2 1 0 Address : 00000420H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR32 Address : 00000421H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR33 Address : 00000422H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR34 Address : 00000423H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR35 Address : 00000424H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR36 Address : 00000425H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR37 Address : 00000426H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR38 Address : 00000427H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR39 Address : 00000428H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR40 Address : 00000429H ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR41 Address : 0000042AH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR42 Address : 0000042BH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR43 Address : 0000042CH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR44 Address : 0000042DH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR45 Address : 0000042EH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR46 Address : 0000042FH ⎯ ⎯ ⎯ ⎯ ICR3 ICR2 ICR1 ICR0 ICR47 R/W R/W R/W R/W LVL3 LVL2 LVL1 LVL0 R/W R/W R/W R/W Address : 00000431H DS07-16308-3E ⎯ ⎯ ⎯ ⎯ HRCL 69 MB91130 Series 10. Clock Generation Area (low power consumption mechanism) Clock generation area is a module with the following functions. • CPU clock generation (including gear function) • Peripheral clock generation (including gear function) • Reset generation and holding factors • Standby function (including hardware standby) • PLL (Phase Locked Loop) is built in • Register list Address 70 7 0 Reset factor / watchdog cycle control register 000480H RSRR/WTCR 000481H STCR Standby control register 000482H PDRR DMA request blocking register 000483H CTBR Time base timer clear register 000484H GCR Gear control register 000485H WPR Watchdog reset generation postponement register 000488H PCTR PLL / 32-K clock control register DS07-16308-3E MB91130 Series • Block diagram [ Gear control area ] GCR register CPU gear Peripheral gear X0A X1A Oscillation circuit 1/2 X0 X1 Oscillation circuit PLL Internal clock generation circuit M P X CPU clock Internal bus clock Internal peripheral clock 32-kHz selection circuit [ Stop/sleep control area ] Internal interruption Internal reset STCR register STOP status SLEEP status CPU hold request DMA request PDRR register Status transfer control circuit Reset generation F/F Internal reset Power on detection circuit [ Reset factor circuit ] VCC3 R GND RSRR register RST pin [ Watchdog control area ] WPR register Watchdog F/F Count clock CTBR register Time base timer DS07-16308-3E 71 MB91130 Series 11. 8-/10-bit A/D Converter The 8-/10-bit A/D converter features functions that convert analog input voltages to 10- or 8-bit digital values using the RC sequential comparison conversion method. The input signal is selected from 8-channel analog input pins and three types of conversion initiation can be selected from software, internal clock, or external pin trigger. • characteristics of 8-/10-bit A/D converter The A/D conversion function for converting analog voltages (input voltages) input into the analog input pins to digital values has the following characteristics. • Conversion time is minimum 5.0 µs (including sampling time when peripheral clock is 33 MHz) . • Conversion method is RC sequential comparison conversion method with sample holding circuit. • 10- or 8-bit resolution can be selected. • Analog input pin can be selected from 8 channels using the program. • interruption request can be generated when A/D conversion ends. • Data is not lost even during continuous conversion as conversion data protection function works while interruptions are permitted. • Initiation factors for conversion can be selected from software, 16-bit reload timer 2 (rising edge) , or external pin trigger (L level detection) . There are three types of conversion modes. Conversion Modes Conversion Modes of 8-/10-bit A/D Converter Table Single Conversion Operation Scan Conversion Operation Single conversion mode Converts the specified channel (1 channel Converts a series of channels (up to 8 only) once and ends. channels can be specified) once and ends. Consecutive conversion mode Repeatedly converts the specified channel Repeatedly converts a series of channels (1 channel only) . (up to 8 channels can be specified) . Stop conversion mode 72 Suspends after converting the specified channel (1 channel only) once and waits until the next one is initiated. Converts a series of channels (up to 8 channels can be specified) but is suspended between each channel conversion and waits until the next one is initiated. DS07-16308-3E MB91130 Series • Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter is configured with the following 9 blocks. • A/D control status register (ADCS1, 2) • A/D data register (ADCR) • Clock selector (input clock selector to initiate A/D conversion) • Decoder • Analog channel selector • Sample holding circuit • D/A converter • Comparator • Control circuit • Block Diagram AVSS AVR± AVSS MPX D/A converter AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit Sequential comparison register R - BUS Comparator Sample and holding circuit Data register ADCR Decoder A/D control register 1 A/D control register 2 16-bit reload timer 2 ADCS1, 2 External pin trigger Operation clock φ Pre-scalar • Register List 15 14 13 12 11 10 9 8 7 0000CFH 00003AH 000038 H DS07-16308-3E 6 5 4 3 2 1 0 AICK ADCS1 ADCS0 ADCR 73 MB91130 Series 12. 8-bit D/A Converter The 8-bit D/A converter is an R-2R type D/A converter with 8-bit resolution. • Characteristics of the 8-bit D/A converter The MB91130 series features a 3-channel D/A converter and output control can be carried out individually by the D/A control register. • Block Diagram of 8-bit D/A Converter The 8-bit D/A converter is configured with the following three blocks. • 8-bit resistance ladder • Data register • Control register • Block Diagram R − BUS DA27 to DA20 DA17 to DA10 DAVC DAVC DAVC DA27 DA17 DA07 DA20 DA10 DA00 DAE Standby control DA output 74 DA07 to DA00 DAE Standby control DA output DAE Standby control DA output DS07-16308-3E MB91130 Series • 8-bit D/A Converter Pins D/A converter pins are dedicated pins. • Registers of 8-bit D/A Converter The 8-bit D/A converter has the following two registers. D/A control register (DACR0, 1, 2) D/A data register (DADR2, 1, 0) • Register list D/A converter data register 0 bit 7 DADR0 DA07 00000ABH D/A converter data register 1 bit 15 DADR1 DA17 00000AAH D/A converter data register 2 bit 23 DADR2 DA27 00000A9H 6 5 4 3 2 1 0 DA06 DA05 DA04 DA03 DA02 DA01 DA00 14 13 12 11 10 9 8 DA16 DA15 DA14 DA13 DA12 DA11 DA10 22 21 20 19 18 17 16 DA26 DA25 DA24 DA23 DA22 DA21 DA20 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DAE0 15 14 13 12 11 10 9 8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DAE1 23 22 21 20 19 18 17 16 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DAE2 D/A control register 0 bit DACR0 00000A7H D/A control register 1 bit DACR1 00000A6H D/A control register 2 bit DACR2 00000A5H DS07-16308-3E 75 MB91130 Series 13. 4-bit Level Comparator The 4-bit level comparator is the module that compares input levels (large/small) and compares the size of the analog input voltage with 4-bit digital values. • Functions of the 4-bit level comparator Compares analog voltage that has been input to the analog input pins (input voltage) with 4-bit digital value and has the following characteristics. • Conversion time is minimum 1 µs (including sampling time) . • Sampling time is minimum 0.5 µs. • Interruption requests can be generated when analog comparison ends. • Interruption of 4-bit level comparator Interruption number #61 (3DH) Interruption and DMAC of 4-bit level comparator Table Interruption control register TBR default Offset address Register name Address ICR45 00042DH 308H 000FFF08H DMAC × × : Initiation is impossible 76 DS07-16308-3E MB91130 Series • Block Diagram of 4-bit Level Comparator The 4-bit level comparator is configured with the following three blocks. • Comparator • 4-bit resistance ladder • Control register • Block diagram AVCC AVR± AVSS 4-bit D/A (resistance ladder) RD3 - 0 Sample & holding circuit CPLV INT INTE CPEN FR30 R - BUS Comparator AN7 Interruption Reload timer Operation clock DS07-16308-3E φ 77 MB91130 Series • Registers of 4-bit Level Comparator • Register list bit 31 bit 24 bit 23 0000-0018H Control register (LVLC) bit 0000018H 78 bit 16 LVLC 31 30 29 28 27 26 25 24 RD3 RD2 RD1 RD0 CPLV INT INTE CPEN R/W (X) R/W (X) R/W (X) R/W (X) R/W (0) R/W (0) R/W (0) R/W (0) Attribute Initial value DS07-16308-3E MB91130 Series 14. UART UART is the general-purpose serial data communications interface to carry out synchronous or asynchronous communication (start-stop synchronization) with external systems. It has a master/slave-type communications function (multiprocessor mode: supporting only master side) as well as normal bi-directional communications function (normal mode). • UART Functions UART is the general-purpose serial data communications interface that sends and receives serial data to/from other CPUs and peripheral equipment, and has functions shown in “UART Functions Table”. UART Functions Table Functions Data buffer Transfer mode Baud rate Data length Signal method Reception error detection Interruption request Master/slave-type communications function (Multiprocessor mode) Full-duplex double buffer • Clock synchronous (without start-stop bit) • Clock asynchronous (start-stop cycle) • Dedicated baud rate generator is available. Can be selected from 8 types. • External clock input is possible. • Internal clock (Internal clocks that are provided from 16-bit reload timer supporting each channel can be used.) • 7-bit (in case of asynchronous normal mode only) • 8-bit Non Return to Zero (NRZ) method • Framing error • Overrun error • Parity error (impossible in case of multiprocessor mode) • Reception interruption (reception completion, reception error detection) • Transmission interruption (transmission completion) Communication between 1 (master) and n (slaves) is possible (Only supports master side) Note : Start / stop bits are not added by UART and only data is transferred. Operations mode 0 1 UART Operations Mode Table Data length Synchronization method Without parity With parity Normal mode Multiprocessor mode 2 Normal mode ⎯ : Setting is impossible 7-bit or 8-bit 8 + 1* 8 1 Asynchronous ⎯ Asynchronous ⎯ Synchronous Stop bit length 1-bit or 2-bit *2 N/A *1 : “ + 1” is address / data selection bit (A/D) to be used to control communications. *2 : 1-bit only can be detected for stop bit in case of reception. DS07-16308-3E 79 MB91130 Series • UART Block Diagram UART is configured with the following 11 blocks. • Clock selector • Mode register (SMR0 to SMR4) • Reception control circuit • Control register (SCR0 to SCR4) • Transmission control circuit • Status register (SSR0 to SSR4) • Reception status judgement circuit • Input data register (SIDR0 to SIDR4) • Shift register for reception • Output data register (SODR0 to SODR4) • Sift register for transmission • Block Diagram Control bus Reception interruption signals #26 to 30 * Dedicated baud rate generator 16-bit reload timer Reception interruption signals #31 to 35 * Transmission clock Clock selector Reception clock Pin Reception control circuit Transmission control circuit Start bit detection circuit Transmission start circuit Reception bit counter Transmission bit counter Reception parity counter Transmission parity counter Shift register for reception Shift register for transmission Pin Pin Reception status judgement circuit SIDR0 ∼ 4 Reception ends SODR0 ∼ 4 Transmission starts Reception error Generation signal (to CPU) Internal data bus SMR0 to 4 registers MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0 to 4 registers PEN P SBL CL A/D REC RXE TXE SSR0 to 4 registers PE ORE FRE RDRF TDRE BDS RIE TIE * : Interruption number 80 DS07-16308-3E MB91130 Series • Block Diagram of UART Pins Data bus Resource input 0 1 PDR read pin 0 PDR Resource output 1 Resource output permission DDR ODCR PCR PDR : Port Data Register DDR : Data Direction Register ODCR : Open-drain Control Register PCR : Pull-up Control Register • Register List Address ch.0 : 0000_001EH, ch.1 : 0000_0022H, ch.2 : 0000_0026H, ch.3 : 0000_0072H, ch.4 : 0000_0076H, ch.0 : 0000_001CH, ch.1 : 0000_0020H, ch.2 : 0000_0024H, ch.3 : 0000_0070H, ch.4 : 0000_0074H, ch.0 : 0000_007AH ch.1 : 0000_0078H ch.2 : 0000_007EH ch.3 : 0000_007CH ch.4 : 0000_0082H DS07-16308-3E bit 8 bit 15 1FH 23H 27H 73H 77H 1DH 21H 25H 71H 75H bit 7 bit 0 Control register (SCR) Mode register (SMR) Status register (SSR) Input/output data register (SIDR/SODR) Communications pre-scalar control register (CDCR) Vacant 81 MB91130 Series 15. DMA Controller The DMA controller is the built-in module of the MB91130 series that carrie out direct memory access (DMA) transfers. • • • • • • • • Characteristics of the DMA Controller 8 channels 3 transfer mode types : single/block transfer, burst transfer, continuous transfer Transfer between overall address areas Maximum 65,536 transfers Interruption function when transfer ends Increase/decrease in transfer addresses can be selected using software 3 external transfer request input/output pins and 3 external transfer end output pins • Block Diagram DREQ0 to DREQ2 3 Edge / level detection circuit 3 3 3 Sequencer DACK0 to DACK2 DEOP0 to DEOP2 8 Interruption request Built-in resource transfer request 5 Data buffer Switcher DACSR Data bus DPDP DATCR Mode BLK DEC BLK DMACT INC / DEC SADR DADR 82 DS07-16308-3E MB91130 Series • Register List (In DMAC : DMAC internal registers) 31 0 00000200H DPDP 00000204H DACSR 00000208H DATCR (On RAM : DMA descriptors) bit 31 DPDP + 0H DPDP + 0CH DPDP + 54H bit 0 DMA ch.0 Descriptor DMA ch.1 Descriptor DMA ch.7 Descriptor Note : In MB91130 series, using the DMA transfer with external DREQ signal and setting the DREQ sense mode to the level sense are not allowed. When using MB91130 series, use sense of the DREQ signal at the edge sense.(the DMAC continuous transfer mode can be used at the DREQ level sense only, this mode cannot be used because of this restriction) DS07-16308-3E 83 MB91130 Series 16. Bit Search Module The bit search module searches for 0, 1 or change points on data that has been written in the input register, and returns the detected bit position. • Block Diagram D-BUS Input latch Address decoder Detection mode Changing to 1 detection data Bit search circuit Detection results • Register List 31 84 0 Address : 000003F0H BSD0 Data register for 0 detection Address : 000003F4H BSD1 Data register for 1 detection Address : 000003F8H BSDC Data register for change point detection Address : 000003FCH BSRR Detection results register DS07-16308-3E MB91130 Series 17. FLASH Memory The MB91130 series have a 254-KB (2 Mbit) capacity and feature a FLASH memory that can write each halfword (16 bits) using the FR-CPU, delete individual sectors sector and delete groups of sectors together using a single 3-V power source. • Outline of FLASH Memory This is a built-in 3-V 254-KB FLASH memory. This FLASH memory is the same as our 2-Mbit (256 K × 8 / 128 K × 16) FLASH memory MBM29LV400C and writing is possible from outside the device using a ROM writer. If used as a built-in ROM of the FR-CPU, as well as having an equivalent function to the MBM29LV400C, instructions / data can be read per word (32 bits) and high-speed operation of the device can be realized. Refer to the MBM29LV400C data sheet as well as this manual. The following functions can be realised in MB91130 series by combining the FLASH memory macro and FRCPU interface circuits. • Functioning as memory for CPU program / data storage Access is possible with 32-bit bus width when used as ROM Reading / writing and erasing (automatic program algorithm *) are possible using CPU • MBM29LV400C-equivalent function of single FLASH memory products Reading / writing and erasing (automatic program algorithm *) are possible using ROM writer A case where this FLASH memory is used from FR-CPU is described in this section. Refer to the ROM writer manual separately for details if this FLASH memory is used from ROM writer. * : Automatic program algorithm = Embedded Algorithm • Block Diagram Rising edge detection Control signal generation RDY/BUSY RESET BYTE OE FLASH memory 2 Mbit (254 K × 8/127 K × 16) WE INTE RDYINT RDY WE Bus control signal Interruption request CE FA18 - 0 Address buffer CA18 - 0 DI15 - 0 DO31 - 0 Data buffer CD31 - 0 FR-C bus (instruction / data) DS07-16308-3E 85 MB91130 Series • Memory Map FLASH memory mode and CPU mode for address mapping of FLASH memory are different. Mapping under each mode is shown as follows. • Memory map in FLASH memory mode 0FFFFFH SA9 SA8 SA7 2 M-FLASH Memory image SA6 SA5 SA4 SA3 0C0000H SA2 SA1 SA0 ( SAn : sector address n ) 010000H 000000H • Memory map in CPU memory mode 0FFFFFH 0FFFFFH SA4 SA9 SA3 SA8 SA2 SA7 SA1 SA6 SA0 SA5 0F8000H 0F4000H FLASH memory area 0F0000H 0E0000H 0C0800H RAM area 2 KByte 0C0000H ( SAn : sector address n ) 0007C0H Status register 0C0800H 000000H 0C0000H 86 CPU mode DS07-16308-3E MB91130 Series • Sector address table Sector Address Address Area Position of bit handled Sector Capacity SA5 000C0802, 3H to 000DFFFE, FH (LSB side 16 bit) bit15 to bit0 63 Kbyte SA6 000E0002, 3H to 000EFFFE, FH (LSB side 16 bit) bit15 to bit0 32 Kbyte SA7 000F0002, 3H to 000F3FFE, FH (LSB side 16 bit) bit15 to bit0 8 Kbyte SA8 000F4002, 3H to 000F7FFE, FH (LSB side 16 bit) bit15 to bit0 8 Kbyte SA9 000F8002, 3H to 000FFFFE, FH (LSB side 16 bit) bit15 to bit0 16 Kbyte SA0 000C0800, 1H to 000DFFFC, DH (MSB side 16 bit) bit31 to bit16 63 Kbyte SA1 000E0000, 1H to 000EFFFC, DH (MSB side 16 bit) bit31 to bit16 32 Kbyte SA2 000F0000, 1H to 000F3FFC, DH (MSB side 16 bit) bit31 to bit16 8 Kbyte SA3 000F4000, 1H to 000F7FFC, DH (MSB side 16 bit) bit31 to bit16 8 Kbyte SA4 000F8000, 1H to 000FFFFC, DH (MSB side 16 bit) bit31 to bit16 16 Kbyte • Registers of FLASH Memory There are two types of FLASH memory registers, namely status register (FLCL) and wait register (FWTC). • Status Register (FLCR) (CPU mode) This register indicates the operation status of the FLASH memory. It controls interruption to the CPU and writing to the FLASH memory. Access is possible only in CPU mode. This register must not be accessed under Read / Modify / Write instructions. 0007C0H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 INTE RDYINT WE RDY ⎯ ⎯ ⎯ LPM R/W (0) R/W (0) R/W (0) R (X) ⎯ (X) ⎯ (X) ⎯ (X) R/W (0) • Wait Register ( FWTC) Carries out wait control of the FLASH memory in CPU mode. Also, controls access to high-speed reading (33MHz) of FLASH memory. Configuration of Wait Register (FWTC) is as follows : 0007C4H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ⎯ ⎯ ⎯ ⎯ ⎯ FACH WTC1 WTC0 ⎯ (⎯) ⎯ (⎯) ⎯ (⎯) ⎯ (⎯) W (0) R/W (0) R/W (0) ⎯ (⎯) Note : FACH bit should be set to 1 or WTC1/0 should be set to 01b to operate CPU clock exceeding 25 MHz. DS07-16308-3E 87 MB91130 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol Rating Min Max Unit Remarks Power voltage VCC5 VSS − 0.3 VSS + 6.5 V Power voltage VCC3 VSS − 0.3 VSS + 3.8 V Analog power voltage AVCC VSS − 0.3 VSS + 6.5 V *1 AVRH,AVRL VSS − 0.3 VSS + 6.5 V *1 Input voltage VI5 VSS − 0.3 VCC5 + 0.3 V Input voltage VI3 VSS − 0.3 VCC3 + 0.3 V Analog pin input voltage VIA VSS − 0.3 AVCC + 0.3 V Output voltage VO VSS − 0.3 VCC5 + 0.3 V Maximum “L” level output current IOL ⎯ 10 mA *2 Average “L” level output current IOLAV ⎯ 4 mA *3 Maximum total “L” level output current ΣIOL ⎯ 100 mA Average “L” level total output current ΣIOLAV ⎯ 50 mA *4 IOH ⎯ −10 mA *2 Average “H” level output current IOHAV ⎯ −4 mA *3 Maximum total “H” level output current ΣIOH ⎯ −50 mA ΣIOHAV ⎯ −20 mA PD ⎯ 500 mW Tstg −55 +150 °C Standard analog voltage Maximum “H” level output current Average “H” level total output current Electricity consumption Storage temperature X0, X1, X0A, X01A *4 *1 : Care must be taken that AVCC, AVRH and AVRL do not exceed VCC5 + 0.3 V when the power is turned on. Also, care must be taken that AVRH and AVRL do not exceed AVCC, and keep AVRH ≥ AVRL. Set AVCC and VCC5 to the same electrical potential. *2 : Peak value of the pin concerned is regulated as the maximum output current. *3 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current. *4 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 88 DS07-16308-3E MB91130 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Common EVA FLASH Power voltage MASK ROM Symbol VCC5 VCC3 VCC3 Value Min Max 4.5 5.5 3.0 3.6 3.15 3.6 3.0 3.6 2.7 3.6 2.7 3.6 Unit V Remarks Under normal operation Under normal operation (32 kHz ≤ fcp ≤ 24 MHz) V Under normal operation (27 MHz < fcp ≤ 33 MHz) RAM status kept in the case of stop V Under normal operation RAM status kept in the case of stop Analog power voltage AVCC VSS + 4.5 VSS + 5.5 V Standard analog voltage AVRH AVSS − 0.3 AVCC V TA 0 +70 °C TA −40 +70 °C In single-chip mode Operating temperature In external ROM external bus / internal ROM external bus modes WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-16308-3E 89 MB91130 Series 3. DC Characteristics (1) DC Value Parameter “H” level input voltage “L” level input voltage (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value ReSymPin name Conditions Unit bol marks Min Typ Max VIH Input excluding following (*1) ⎯ 0.7 VCC5 ⎯ VCC5 + 0.3 V VIHS *1 Hysteresis input pin ⎯ VCC5 − 0.4 ⎯ VCC5 + 0.3 V VIL Input excluding following (*1) ⎯ VSS − 0.3 ⎯ 0.2 VCC5 V VILS *1 Hysteresis input pin ⎯ VSS − 0.3 ⎯ VSS + 0.4 V “H” level output voltage VOH ⎯ VCC5 = 5.0 V, IOH = −4.0 mA 2.6 ⎯ ⎯ V “L” level output voltage VOL ⎯ VCC5 = 5.0 V, IOL = 4.0 mA ⎯ ⎯ 0.6 V ILI ⎯ VCC5 = 5.0 V, VSS < VI < VDD −5 ⎯ 5 µA ⎯ 50 ⎯ kΩ Input leak current Pull up RPULL resistance value RST ICC5 VCC5 VCC5 = 5.0 V ⎯ 15 20 mA ICC3 VCC3 VCC3 = 3.0 V ⎯ 50 100 mA ICCS5 VCC5 VCC5 = 5.0 V ⎯ 15 20 mA ICCS3 VCC3 VCC3 = 3.0 V ⎯ 24 85 mA ICCH5 VCC5 VCC5 = 5.0 V, TA = +25 °C ⎯ 10 100 µA ICCH3 VCC3 VCC3 = 3.0 V, TA = +25 °C ⎯ 10 250 µA Power current ⎯ Power current (FLASH models) ICC3 VCC3 VCC3 = 3.3 V ⎯ 80 120 mA ICCS3 VCC3 VCC3 = 3.3 V ⎯ 50 90 mA Input capacity CIN Other than VCC, AVCC, AVSS, AVRH and VSS ⎯ 10 ⎯ pF ⎯ *2 *2 *3 *1 : Refer to “PIN FUNCTION DESCRIPTIONS” *2 : In case of CLK pin output only (CL = 80 pF) *3 : Output pin OPEN 90 DS07-16308-3E MB91130 Series (2) Flash Memory Write/Erase Characteristics Parameter Condition Sector erase time Chip erase time TA = + 25 °C, VCC3 = 3.0 V Half word (16 bit width) writing time Value Unit Remarks 15 s Excludes 00H programming prior erasure 10 ⎯ s Excludes 00H programming prior erasure ⎯ 16 3,600 µs Excludes system-level overhead Min Typ Max ⎯ 1 ⎯ Write/erase cycle ⎯ 10,000 ⎯ ⎯ cycle Data holding time ⎯ 100,000 ⎯ ⎯ h DS07-16308-3E 91 MB91130 Series 4. AC Characteristics (1) Clock Timing Standard (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value SymCondiUnit Remarks Parameter Pin name bol tions Min Max Clock frequency (high-speed, self-oscillation) Clock frequency (high-speed, PLL usage) fC X0, X1 fCA X0A, X1A Clock cycle time tC ⎯ CPU system fCP Bus system fCPB Peripheral system Internal operation clock cycle time 32 ⎯ fCPP ⎯ CPU system tCP Bus system tCPB Peripheral system 16.5 MHz ⎯ Clock frequency (low-speed) Internal operation clock frequency 9 tCPP ⎯ kHz Self oscillation available area PLL usable area by self-oscillation input Self oscillation 30.3 31250 ns 0.032 33 0.032 25 0.032 25 Excluding analog area * 1 25 Analog area * 30.3 31250 40 31250 40 31250 Excluding analog area * 40 1000 Analog area * MHz ns * : The targeted analog areas are the A/D converter and level comparator. 92 DS07-16308-3E MB91130 Series tC VCC3 0.8 VCC3 0.2 VCC3 VSS Peripheral system clock setting permitted area (A/D, D/A level comparator : 5 V ± 10%) < FLASH model > < MASK ROM model > VCC3 VCC3 Guaranteed operating range fCP 3.0 fCPP Power voltage (V) Power voltage (V) Guaranteed operating range 3.6 3.6 fCP 2.7 fCPP 32 k 1 M 25 M 27 M 33 M Frequency (Hz) DS07-16308-3E 32 k 1 M 25 M 33 M Frequency (Hz) 93 MB91130 Series The relationship between the internal clock set by the CHC/CCK1/CCK0 bit of the Gear Control Register (GCR) and X0 input is as follows. X0 input • Original oscillation × 1 (CHC bit of GCR : 0 setting) (a) Gear × 1 Internal clock CCK1/CCK0 : 00 (b) Gear × 1/2 Internal clock CCK1/CCK0 : 01 tCYC tCYC tCYC (c) Gear × 1/4 Internal clock CCK1/CCK0 : 10 tCYC (d) Gear × 1/8 Internal clock CCK1/CCK0 : 11 • Original oscillation × 1/2 (CHC bit of GCR : 1 setting) (a) Gear × 1 Internal clock CCK1/CCK0 : 00 (b) Gear × 1/2 Internal clock CCK1/CCK0 : 01 (c) Gear × 1/4 Internal clock CCK1/CCK0 : 10 (d) Gear × 1/8 Internal clock CCK1/CCK0 : 11 94 tCYC tCYC tCYC tCYC DS07-16308-3E MB91130 Series (2) Reset Input Standards (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value Pin CondiParameter Symbol Unit Remarks name tions Min Max Reset input time ⎯ RST tRSTL tCP × 5 ⎯ ns tRSTL RST 0.2 VCC (3) Power On Reset Parameter Power startup time Power cut time (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value SymPin Conditions Unit Remarks bol name Min Max fR VCC tOFF ⎯ tR VhhR ⎯ 20 ms 2 ⎯ ms tOFF 0.9 × VCC3 0.2 V If the power voltage is changed rapidly, “Power On Reset” may be initiated. To start up smoothly, controlling any voltage fluctuations that may occur during operation is recommended. VCC Holding RAM data Controling inclination at initiation to 50 mV/ms or less is recommended. VSS VCC RST tRSTL DS07-16308-3E When power is turned on, start while the RST pin is set to “L” level, after which wait for tRSTL minutes and change the level to “H” once the VCC power level is reached. 95 MB91130 Series (4) Serial I/O (CH0 to 4) Parameter (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value Pin Symbol Conditions Unit Remarks name Min Max Serial clock cycle time tSCYC ⎯ 8 tCPP ⎯ ns SCK ↓ → SO delay time tSLOV ⎯ −10 50 ns Valid SI → SCK ↑ tIVSH ⎯ 50 ⎯ ns SCK ↑ → Valid SI holding time tSHIX ⎯ 50 ⎯ ns Serial clock H pulse width tSHSL ⎯ 4 tCPP − 10 ⎯ ns Serial clock L pulse width tSLSH ⎯ 4 tCPP − 10 ⎯ ns SCK ↓ → SO delay time tSLOV ⎯ 0 50 ns Valid SI → SCK ↑ tIVSH ⎯ 50 ⎯ ns 50 ⎯ ns ⎯ 6 tCPP ns Internal clock External clock SCK ↑ → Valid SI holding time tSHIX ⎯ Serial busy period tBUSY ⎯ SCS ↓ → SCK, SO delay time tCLZO ⎯ ⎯ 50 ns SCS ↓ → SCK input MASK time tCLSL ⎯ ⎯ 3 tCPP ns SCS ↑ → SCK, SO Hi-Z time tCHOZ ⎯ 50 ⎯ ns * *: Will be Min 1 tCPP − 10 if pre-scalar setting is CS2, CS1, CS0 = 000. 96 DS07-16308-3E MB91130 Series Internal shift clock mode tSCYC SCK tSLOV SO SI tSHIX tIVSH External shift clock mode tCLZO tSLSH tSHSL tBUSY tCHOZ SCK tSLOV SO SI tIVSH tSHIX SCS tCLSL DS07-16308-3E 97 MB91130 Series (5) External Bus Measurement Conditions The following conditions apply to items without specific regulations. • Alternating current standard measurement condition VCC : 5.0 V ± 10% Input Output VCC VIH VOH VIL VOL 0V VIH 2.4 V VOH 2.4V VIL 0.8 V VOL 0.8V (Rise/fall time of input is 10 ns or less) • Load condition Output pin C = 50 pF ( VCC : 5.0 V ± 10% ) • Load capacity − Delay time characteristic (Internally-based output delay) [nS] 35 30 25 5 V Fall 20 15 5 V Rise 10 5 0 0 98 20 40 50 60 80 100 120 C[pF] DS07-16308-3E MB91130 Series (6) Normal Bus Access Read/Write Operation (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = 0 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = 0 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = 0 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value SymParameter Pin name Conditions Unit Remarks bol Min Max Address delay time tCHAV CLK A23 to A00 ⎯ 15 ns Data delay time tCHDV CLK D31 to D16 ⎯ 15 ns RD delay time tCLRL ⎯ 10 ns RD delay time tCLRH CLK RD ⎯ 10 ns WR0, WR1 delay time tCLWL ⎯ 10 ns WR0, WR1 delay time tCLWH ⎯ 10 ns Valid address / valid data input time tAVDV ⎯ 3/2× tCYC − 25 ns *1, *2 RD ↓ → valid data input time tRLDV ⎯ tCYC − 15 ns *1 15 ⎯ ns 0 ⎯ ns Data setup → RD ↑ time tDSRH RD ↑ → Data holding time tRHDX CLK WR0, WR1 A23 to A00 D31 to D16 RD D31 to D16 ⎯ *1 : Time (tCYC × number of cycles extended) needs to be added to this standard if the bus is extended by automatic waiting insertion and RDY input. *2 : Values of this standard are in case of gear cycle × 1. If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. • Calculation formula : (2 − n / 2) × tCYC − 25 DS07-16308-3E 99 MB91130 Series tCYC BA1 BA2 VOH VOH VOL CLK VOL tCHAV VOH VOL A23 - A00 VOH VOL tCLRL tCLRH VOH RD VOL tRLDV tRHDX tAVDV tDSRH VIH VIL D31 - D16 tCLWL Read VIH VIL tCLWH VOH WR0 , WR1 VOL tCHDV D31 - D16 100 VOH VOL Write VOH VOL DS07-16308-3E MB91130 Series (7) Ready Input Timing Parameter (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = 0 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = 0 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = 0 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value Pin Symbol Conditions Unit Remarks name Min Max RDY setup time → CLK ↓ CLK ↓ → RDY holding time tRDYS RDY CLK tRDYH RDY CLK 15 ⎯ ns 0 ⎯ ns ⎯ tCYC VOH VOH CLK tRDYS RDY If "wait" is executed VIL RDY If "wait" is not executed VIH DS07-16308-3E VOL VOL tRDYH tRDYS tRDYH VIH VIL 101 MB91130 Series (8) Holding timing Parameter (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = 0 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = 0 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = 0 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value Pin Symbol Conditions Unit Remarks name Min Max BGRNT delay time tCHBGL BGRNT delay time tCHBGH Pin floating → BGRNT ↓ time tXHAL BGRNT ↑ → Pin valid time tHAHV CLK BGRNT ⎯ BGRNT ⎯ 6 ns ⎯ 6 ns tCYC − 10 tCYC + 10 ns tCYC − 10 tCYC + 10 ns Note : It takes at least one cycle from loading the BRQ to when BGRNT is changed. tcyc VOH VOH VOH VOH CLK BRQ tCHBGL tCHBGH VOH BGRNT VOL tHAHV tXHAL Each pin High impedance 102 DS07-16308-3E MB91130 Series (9) DMA Controller Timing (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max DREQ input pulse width tDRWH DREQ0 to DREQ2 2 tCYC ⎯ ns DACK delay time (Normal bus) tCLDL CLK DACK0 to DACK2 ⎯ 6 ns ⎯ 6 ns ⎯ 6 ns ⎯ 6 ns ⎯ n / 2 × tCYC ns ⎯ 6 ns ⎯ n / 2 × tCYC ns ⎯ 6 ns DEOP delay time (Normal bus) DACK delay time DEOP delay time tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH CLK DEOP0 to DEOP2 ⎯ CLK DACK0 to DACK2 CLK DEOP0 to DEOP2 tcyc VOH VOH CLK VOL VOL tCLDH tCLDL tCLEH tCLEL DACK0 - 2 DEOP0 - 2 (Normal bus) VOH VOL tCHDH DACK0 - 2 DEOP0 - 2 tCHDL VOH VOL tCHEL tDRWH DREQ0 - 2 VIH DS07-16308-3E VIH 103 MB91130 Series 5. A/D Transition Parameter (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value ReSym- Pin Conditions Unit mark bol name Min Typ Max s Resolution ⎯ ⎯ Conversion time ⎯ ⎯ Total tolerance ⎯ ⎯ Straight-line tolerance ⎯ ⎯ Differential straight-line tolerance ⎯ ⎯ Zero transition voltage VOT Full-scale transition voltage VFST Analog input current IAIN AN0 to AN7 AN0 to AN7 VAIN Standard voltage AVRH AVRH Standard voltage current supplied AVCC = 5.0 V, AVRH = 5.0V, AVRL = 0.0 V AN0 to AN7 AVCC = 5.0 V, AVRH = 5.0V, AN0 to AVRL = 0.0 V AN7 Analog input voltage Power current ⎯ ⎯ IA When conversion is stopped IAH When conversion is activated IR When conversion is stopped IRH AVCC = 5.0 V, AVRH AVRH = 5.0V, AVRL = 0.0 V ⎯ AN0 to AN7 Tolerance between channels ⎯ 5.0 ⎯ −4.0 ⎯ 4.0 LSB −3.5 ⎯ 3.5 LSB −2.0 ⎯ 2.0 LSB AVRL− 1.5 LSB AVRL+ 0.5 LSB AVRL+ 2.5 LSB V AVRH − 5.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB V ⎯ 0.1 10 µA AVSS ⎯ AVRH V ⎯ ⎯ AVCC V ⎯ 3.0 5.0 mA ⎯ ⎯ 5.0 µA ⎯ 2.0 3.0 mA ⎯ ⎯ 10 µA ⎯ ⎯ 4 LSB 10 Bit µs ⎯ When conversion is activated AVCC ⎯ AVCC = 5.0 V ⎯ Notes : • As the |AVRH−AVRL| becomes smaller, the tolerance becomes larger. • Output impedance of external circuits other than analog input must be used if output impedance of external circuits < approx. 7 kΩ If the output impedance of the external circuits is too high, the sampling time for the analog voltage may be insufficient. (Sampling time = 1.6 µs at 33 MHz) 104 DS07-16308-3E MB91130 Series • Definition of A/D Converter Terms • Resolution : Analog changes that can be identified by A/D converter • Straight-line tolerance : Difference between the straight line linking the zero transition point (00 0000 0000 ←→ 00 0000 0001) to the full-scale transition point (11 1111 1110 ←→ 11 1111 1111) and actual conversion characteristics. • Differential straight-line tolerance : Difference compared to the ideal input voltage value required to change the output code 1 LSB • Total tolerance : Indicates the difference between the actual and theoretical values and includes zero transition tolerance, fullscale transition tolerance, and straight-line tolerance. Total tolerance 3FF 3FE Digital output 3FD Actual conversion characteristics {1 LSB ( N − 1 ) + 0.5 LSB} 1.5 LSB 004 VNT (Actual measured value) Actual conversion characteristics 003 002 Ideal characteristics 001 0.5 LSB AVRH AVRL Total tolerance of digital output N = 1 LSB (Ideal value) = Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB’} 1 LSB AVRH − AVRL [V] 1024 VOT (Ideal value) = AVRL + 0.5 LSB’ [V] VFST (Ideal value) = AVRH − 1.5 LSB’ [V] VNT : Voltage of digital output transferred from (N + 1) to N (Continued) DS07-16308-3E 105 MB91130 Series (Continued) Straight-line tolerance Differential straight-line tolerance 3FF Actual conversion characteristics N+1 {1 LSB ( N − 1 ) + VOT} VFST (Actual measured value) Digital output 3FD Digital output 3FE 004 VNT (Actual measured value) 003 Actual conversion characteristics N Ideal characteristics N−1 VFST (Actual measured VNT value) (Actual measured value) Actual conversion characteristics Ideal characteristics 002 N−2 001 Actual conversion characteristics VOT (Actual measured value) AVRL AVRL AVRH Analog input Straight-line tolerance = VNT − {1 LSB × (N − 1) + VOT} 1 LSB of digital output N Differential straight-line tolerance = of digital output N 1LSB (Ideal value) = V (N + 1) T − VNT 1 LSB VFST − VOT 1022 AVRH Analog input −1 [LSB] [LSB] [V] VOT : Voltage with digital output transferred from (000) H to (001) H VFST : Voltage with digital output transferred from (3FE) H to (3FF) H 6. D/A Transition Parameter (All products : VCC5 = AVCC = DAVC = 5.0 V ± 10 %, VSS = AVSS = 0 V) (Mask model : VCC3 = 2.7 V to 3.6 V, TA = − 40 °C to + 70 °C) (Flash model : VCC3 = 3.0 V to 3.6 V, TA = − 40 °C to + 70 °C (32 kHz ≤ fcp ≤ 27 MHz) ) (Flash model : VCC3 = 3.15 V to 3.6 V, TA = − 40 °C to + 70 °C (27 MHz < fcp ≤ 33 MHz) ) Value RePin CondiUnit Symbol marks name tions Min Typ Max Resolution ⎯ ⎯ ⎯ ⎯ ⎯ 8 Bit Differential straight-line tolerance ⎯ ⎯ ⎯ ⎯ ⎯ ±0.9 LSB Conversion time ⎯ ⎯ ⎯ ⎯ 10 20 µs Analog output impedance ⎯ ⎯ ⎯ ⎯ 28 ⎯ kΩ * *: CL = 20 pF 106 DS07-16308-3E MB91130 Series ■ EXAMPLE CHARACTERISTICS VOL VOH TA = 25 °C, IOL = 4 mA 400 350 250 VOH (V) VOL (mV) 300 200 150 100 50 0 3 4 5 VCC (V) 6 7 TA = 25 °C, IOH = −4 mA 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3 ICC31 (mA) ICC31 (mA) TA = 25 °C, f = 33 MHz 2 2.5 3 3.5 1 4 7 10 Frequency (MHz) 100 ICC5 ICC5 TA = 25 °C, f = 33.0 MHz VCC3 = 3.0 V, VCC5 = 5.0 V, TA = 25 °C 40 35 30 ICC5 (mA) ICC5 (mA) 6 VCC = 3.0 V, TA = 25 °C 160 140 120 100 80 60 40 20 0 VCC (V) 40 35 30 25 20 15 10 5 0 3.5 5 VCC (V) ICC31 ICC31 100 90 80 70 60 50 40 30 20 10 0 4 25 20 15 10 5 4 4.5 5 VCC (V) 5.5 6 6.5 0 1 10 Frequency (MHz) 100 (Continued) DS07-16308-3E 107 MB91130 Series Pull up resistance TA = 25 °C 125 Pull up resistance (kΩ) 100 75 50 25 0 3 4 5 6 7 VCC (V) (Continued) 108 DS07-16308-3E MB91130 Series (Continued) MB91133 Linearity error TA = 25 °C VCC = 4.5 V AVCC = 4.5 V Linearity error [LSB] 3 2 1 0 −1 −2 1024 960 896 832 768 704 640 576 512 448 384 320 256 192 128 64 0 −3 CODE MB91133 Differential linearity error VCC = 4.5 V AVCC = 4.5 V 3 2 1 0 −1 −2 960 1024 960 1024 896 832 768 704 640 576 512 448 384 320 256 192 128 64 −3 0 Differential linearity error [LSB] TA = 25 °C CODE MB91133 Total error TA = 25 °C VCC = 4.5 V AVCC = 4.5 V Total error [LSB] 3 2 1 0 −1 −2 CODE DS07-16308-3E 896 832 768 704 640 576 512 448 384 320 256 192 128 64 0 −3 109 MB91130 Series ■ ORDERING INFORMATION Part number Package MB91133PMC-XXX 144-pin plastic LQFP (FPT-144P-M08) MB91133PBT-XXX 144-pin plastic FBGA (BGA-144P-M01) MB91F133APMC 144-pin plastic LQFP (FPT-144P-M08) MB91F133APBT 144-pin plastic FBGA (BGA-144P-M01) MB91FV130CR-ES 299-pin ceramic PGA (PGA-299) 110 Remarks DS07-16308-3E MB91130 Series ■ PACKAGE DIMENSIONS 144-pin plastic FBGA Ball pitch 0.80 mm Ball matrix 14 × 14 Package width × package length 12.00 × 12.00 mm Sealing method Plastic mold Mounting height 1.45 mm MAX Ball size ∅ 0.45 Weight 0.310g (BGA-144P-M01) 144-pin plastic FBGA (BGA-144P-M01) 12.00±0.10(.472±.004)SQ +0.20 +.008 1.25 –0.10 .049 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 10.40(.409)REF 0.80(.031)TYP 14 13 12 11 10 9 8 7 INDEX 6 5 0.10(.004) 4 INDEX 3 2 1 P N M L K J H G F E D C B A 144-Ø0.45±0.10 (144-Ø.018±.004) C 2000-2008 FUJITSU MICROELECTRONICS LIMITED B144001S-c-3-4 0.08(.003) M Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07-16308-3E 111 MB91130 Series (Continued) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.20g Code (Reference) P-LFQFP144-20×20-0.50 Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 Lead pitch 0.145±0.055 (.006±.002) 73 109 72 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 0˚~8˚ INDEX 144 37 "A" LEAD No. 1 36 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) M ©2003-2008 FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7 C 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 112 DS07-16308-3E MB91130 Series ■ MAIN CHANGES IN THIS EDITION Page Section ⎯ ⎯ 53 ■ PERIPHERAL RESOURCES 4. 16-bit Reload Timer 59 ■ PERIPHERAL RESOURCES 6. Multifunction Timer 72 ■ PERIPHERAL RESOURCES 11. 8-/10-bit A/D Converter 83 ■ PERIPHERAL RESOURCES 15. DMA Controller Change Results Changed the series name; MB91133/MB91F133A → MB91130 series Changed the operating clock name of the peripheral resources. machine clock → peripheral clock Added the note of About the external DREQ signal. ■ ELECTRICAL CHARACTERISTICS Changed the following names. 5. A/D Transition Zero transition tolerance → Zero transition voltage Full-scale transition tolerance → Full-scale transition voltage 104 Changed the items of “Zero transition voltage” and “Full-scale transition voltage”. Unit : LSB → V AVSS/AVRH± value → AVRL/AVRH ± value LSB Changed the name of a reference voltage (low voltage side) of “Definition of A/D Converter Terms”. AVSS → AVRL 105, 106 ■ ORDERING INFORMATION 110 Changed the order informations. MB91133PMT2-XXX → MB91133PMC-XXX MB91F133APMT2 → MB91F133APMC The vertical lines marked in the left side of the page show the changes. DS07-16308-3E 113 MB91130 Series MEMO 114 DS07-16308-3E MB91130 Series MEMO DS07-16308-3E 115 MB91130 Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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