MB95F582KPF-G-SNE2

MB95560H Series MB95570H Series MB95580H Series New 8FX 8-bit Microcontrollers The MB95560H/570H/580H Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. Features ■ ■ ■ ❐ There are four standby modes as follows: • Stop mode • Sleep mode • Watch mode • Time-base timer mode ❐ In standby mode, the device can be made to enter either normal standby mode or deep standby mode. F2MC-8FX CPU core ❐ Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. ■ Clock (The main oscillation clock and the suboscillation clock are only available on MB95F562H/F562K/F563H/F563K/ F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.) ❐ Selectable main clock source • Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) • External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) • Main CR clock (4 MHz  2%) - The main CR clock frequency becomes 8 MHz when the PLL multiplication rate is 2. - The main CR clock frequency becomes 10 MHz when the PLL multiplication rate is 2.5. - The main CR clock frequency becomes 12 MHz when the PLL multiplication rate is 3. - The main CR clock frequency becomes 16 MHz when the PLL multiplication rate is 4. ❐ Selectable subclock source • Suboscillation clock (32.768 kHz) • External clock (32.768 kHz) • Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) Timer 8/16-bit composite timer  2 channels (only one channel on MB95F572H/F572K/F573H/F573K/F574H/F574K/F582H/ F582K/F583H/F583K/F584H/F584K) ❐ Time-base timer  1 channel ❐ Watch prescaler  1 channel ❐ ■ ■ LIN-UART (only available on MB95F562H/F562K/F563H/ F563K/F564H/F564K/F582H/F582K/F583H/F583K/F584H/ F584K) ❐ Full duplex double buffer ❐ Capable of clock synchronous serial data transfer and clock asynchronous serial data transfer External interrupt Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ❐ Can be used to wake up the device from different low power consumption (standby) modes - General-purpose I/O ports (CMOS I/O): 15 - General-purpose I/O ports (N-ch open drain): 1 ❐ ❐ ■ ❐ • MB95F572K/F573K/F574K (maximum no. of I/O ports: 5) - General-purpose I/O ports (CMOS I/O): 3 - General-purpose I/O ports (N-ch open drain): 2 ❐ MB95F582H/F583H/F584H (maximum no. of I/O ports: 12) - General-purpose I/O ports (CMOS I/O): 11 - General-purpose I/O ports (N-ch open drain): 1 ❐ MB95F582K/F583K/F584K (maximum no. of I/O ports: 13) - General-purpose I/O ports (CMOS I/O): 11 - General-purpose I/O ports (N-ch open drain): 2 ■ On-chip debug 1-wire serial control ❐ Serial writing supported (asynchronous mode) ❐ ■ Hardware/software watchdog timer Built-in hardware watchdog timer ❐ Built-in software watchdog timer ❐ ■ Power-on reset A power-on reset is generated when the power is switched on. ❐ ■ ■ Low-voltage detection reset circuit (only available on MB95F562K/F563K/F564K/F572K/F573K/F574K/F582K/ F583K/F584K) ❐ Built-in low-voltage detector Clock supervisor counter Built-in clock supervisor counter function ❐ ■ Dual operation Flash memory The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. ❐ ■ Flash memory security function Protects the content of the Flash memory. ❐ Low power consumption (standby) modes Cypress Semiconductor Corporation Document Number: 002-04629 Rev. *A MB95F572H/F573H/F574H (maximum no. of I/O ports: 4) - General-purpose I/O ports (CMOS I/O): 3 - General-purpose I/O ports (N-ch open drain): 1 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. MB95F562K/F563K/F564K (maximum no. of I/O ports: 17) - General-purpose I/O ports (CMOS I/O): 15 - General-purpose I/O ports (N-ch open drain): 2 ❐ ■ I/O port MB95F562H/F563H/F564H (maximum no. of I/O ports: 16) ❐ 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 29, 2016 MB95560H Series MB95570H Series MB95580H Series Contents 16. Block Diagram (MB95580H Series) ......................... 28 Features............................................................................. 1 1. Product Line-up ............................................................ 3 2. Packages And Corresponding Products.................... 7 3. Differences Among Products And Notes On Product Selection ............................................................. 8 17. CPU Core................................................................... 29 18. I/O Map (MB95560H Series) ..................................... 30 19. I/O Map (MB95570H Series) ..................................... 34 20. I/O Map (MB95580H Series) ..................................... 37 21. Interrupt Source Table (MB95560H Series)............ 40 4. Pin Assignment ............................................................ 9 22. Interrupt Source Table (MB95570H Series)............ 41 5. Pin Functions (MB95560H Series, 32 pins) .............. 11 23. Interrupt Source Table (MB95580H Series)............ 42 6. Pin Functions (MB95560H Series, 20 pins) .............. 13 24. Electrical Characteristics......................................... 24.1 Absolute Maximum Ratings............................... 24.2 Recommended Operating Conditions ............... 24.3 DC Characteristics ............................................ 24.4 AC Characteristics............................................. 24.5 A/D Converter.................................................... 24.6 Flash Memory Program/Erase Characteristics.. 7. Pin Functions (MB95570H Series, 8 pins) ................ 15 8. Pin Functions (MB95580H Series, 32 pins) .............. 16 9. Pin Functions (MB95580H Series, 16 pins) .............. 18 10. I/O Circuit Type ......................................................... 20 11. Handling Precautions............................................... 11.1 Precautions for Product Design......................... 11.2 Precautions for Package Mounting ................... 11.3 Precautions for Use Environment...................... 21 21 23 24 43 43 45 46 49 63 67 25. Sample Characteristics............................................ 68 26. Mask Options ............................................................ 74 27. Ordering Information................................................ 75 12. Notes On Device Handling....................................... 24 28. Package Dimension.................................................. 77 13. Pin Connection ......................................................... 25 29. Major Changes In This Edition ................................ 84 Document History Page ................................................. 87 Sales, Solutions, and Legal Information ...................... 88 14. Block Diagram (MB95560H Series) ......................... 26 15. Block Diagram (MB95570H Series) ......................... 27 Document Number: 002-04629 Rev. *A Page 2 of 88 MB95560H Series MB95570H Series MB95580H Series 1. Product Line-up • MB95560H Series Part number MB95F562H MB95F563H MB95F564H MB95F562K MB95F563K MB95F564K Parameter Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Power-on reset Yes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 17 • I/O ports (Max) : 16 General• CMOS I/O : 15 • CMOS I/O : 15 purpose I/O • N-ch open drain: 2 • N-ch open drain: 1 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ Main oscillation clock at 10 MHz: 105 ms (Min) software watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace 3 bytes of data. • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. LIN-UART • Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled. • The LIN function can be used as a LIN master or a LIN slave. 8/10-bit A/D 6 channels converter 8-bit or 10-bit resolution can be selected. 2 channels • The timer can be configured as an "8-bit timer  2 channels" or a "16-bit timer  1 channel". • It has the following functions: interval timer function, PWC function, PWM function and input 8/16-bit composite timer capture function. • Count clock: it can be selected from internal clocks (7 types) and external clocks. • It can output square wave. 6 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing (asynchronous mode). Document Number: 002-04629 Rev. *A Page 3 of 88 MB95560H Series MB95570H Series MB95580H Series Part number MB95F562H MB95F563H MB95F564H MB95F562K MB95F563K MB95F564K Parameter Watch prescaler Eight different time intervals can be selected. • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 10000 100000 20 years 10 years 5 years Standby mode Sleep mode, stop mode, watch mode, time-base timer mode LCC-32P-M19 Package FPT-20P-M09 FPT-20P-M10 • MB95570H Series Part number MB95F572H MB95F573H MB95F574H MB95F572K MB95F573K MB95F574K Parameter Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Power-on reset Yes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 4 • I/O ports (Max) : 5 General• CMOS I/O :3 • CMOS I/O :3 purpose I/O • N-ch open drain: 1 • N-ch open drain: 2 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) Hardware/ • Reset generation cycle Main oscillation clock at 10 MHz: 105 ms (Min) software watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace 3 bytes of data. LIN-UART No LIN-UART 8/10-bit A/D 2 channels converter 8-bit or 10-bit resolution can be selected. Document Number: 002-04629 Rev. *A Page 4 of 88 MB95560H Series MB95570H Series MB95580H Series Part number MB95F572H MB95F573H MB95F574H MB95F572K MB95F573K MB95F574K Parameter 1 channel • The timer can be configured as an "8-bit timer  2 channels" or a "16-bit timer  1 channel". • It has the following functions: interval timer function, PWC function, PWM function and input 8/16-bit composite timer capture function. • Count clock: it can be selected from internal clocks (7 types) and external clocks. • It can output square wave. 2 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing (asynchronous mode). Watch prescaler Eight different time intervals can be selected. • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 10000 100000 20 years 10 years 5 years Standby mode Sleep mode, stop mode, watch mode, time-base timer mode DIP-8P-M03 Package FPT-8P-M08 • MB95580H Series Part number MB95F582H MB95F583H MB95F584H MB95F582K MB95F583K MB95F584K Parameter Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Power-on reset Yes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 12 • I/O ports (Max) : 13 General• CMOS I/O : 11 • CMOS I/O : 11 purpose I/O • N-ch open drain: 1 • N-ch open drain: 2 Document Number: 002-04629 Rev. *A Page 5 of 88 MB95560H Series MB95570H Series MB95580H Series Part number MB95F582H MB95F583H MB95F584H MB95F582K MB95F583K MB95F584K Parameter Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) Hardware/ • Reset generation cycle software Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace 3 bytes of data. • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. LIN-UART • Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled. • The LIN function can be used as a LIN master or a LIN slave. 5 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 1 channel • The timer can be configured as an "8-bit timer  2 channels" or a "16-bit timer  1 channel". 8/16-bit • It has the following functions: interval timer function, PWC function, PWM function and input composite timer capture function. • Count clock: it can be selected from internal clocks (7 types) and external clocks. • It can output square wave. 6 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing (asynchronous mode). Watch prescaler Eight different time intervals can be selected. • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 10000 100000 20 years 10 years 5 years Standby mode Sleep mode, stop mode, watch mode, time-base timer mode LCC-32P-M19 Package FPT-16P-M08 FPT-16P-M23 Document Number: 002-04629 Rev. *A Page 6 of 88 MB95560H Series MB95570H Series MB95580H Series 2. Packages And Corresponding Products • MB95560H Series Part number MB95F562H MB95F562K MB95F563H MB95F563K MB95F564H MB95F564K    X X X X    X X X X    X X X X    X X X X    X X X X    X X X X MB95F572H MB95F572K MB95F573H MB95F573K MB95F574H MB95F574K X X X X X   X X X X X   X X X X X   X X X X X   X X X X X   X X X X X   MB95F582H MB95F582K MB95F583H MB95F583K MB95F584H MB95F584K  X X   X X  X X   X X  X X   X X  X X   X X  X X   X X  X X   X X Package LCC-32P-M19 FPT-20P-M09 FPT-20P-M10 FPT-16P-M08 FPT-16P-M23 DIP-8P-M03 FPT-8P-M08 • MB95570H Series Part number Package LCC-32P-M19 FPT-20P-M09 FPT-20P-M10 FPT-16P-M08 FPT-16P-M23 DIP-8P-M03 FPT-8P-M08 • MB95580H Series Part number Package LCC-32P-M19 FPT-20P-M09 FPT-20P-M10 FPT-16P-M08 FPT-16P-M23 DIP-8P-M03 FPT-8P-M08 : Available X: Unavailable Document Number: 002-04629 Rev. *A Page 7 of 88 MB95560H Series MB95570H Series MB95580H Series 3. Differences Among Products And Notes On Product Selection • Current consumption When using the on-chip debug function, take account of the current consumption of Flash memory program/erase. For details of current consumption, see “Electrical Characteristics”. • Package For details of information on each package, see “Packages And Corresponding Products” and “Package Dimension”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see “Electrical Characteristics”. • On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection method, refer to “CHAPTER 21 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New 8FX MB95560H/570H/580H Series Hardware Manual”. Document Number: 002-04629 Rev. *A Page 8 of 88 MB95560H Series MB95570H Series MB95580H Series 32 31 30 29 28 27 26 25 NC NC NC NC NC NC NC NC 4. Pin Assignment X1/PF1 X0/PF0 1 2 VSS X1A/PG2 3 4 X0A/PG1 Vcc LCC-32P-M19 (MB95560H Series) C 5 6 7 RST/PF2 8 The number of usable pins is 20. X0/PF0 X1/PF1 1 2 Vss X1A/PG2 3 4 X0A/PG1 Vcc C RST/PF2 TO10/P62 TO11/P63 5 6 7 8 9 10 Document Number: 002-04629 Rev. *A 9 10 11 12 13 14 15 16 TO11/P63 TO10/P62 NC NC NC NC P00/AN00 P64/EC1 (TOP VIEW) (TOP VIEW) FPT-20P-M09 FPT-20P-M10 (MB95560H Series) 24 23 22 21 20 19 P07/INT07 P12/EC0/DBG P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT 18 P02/INT02/AN02/SCK 17 P01/AN01 20 19 P12/EC0/DBG P07/INT07 18 17 P06/INT06/TO01 P05/INT05/AN05/TO00 16 15 14 13 12 11 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1 Page 9 of 88 RST/PF2 8 X0/PF0 1 X1/PF1 Vss 2 3 X1A/PG2 X0A/PG1 Vcc RST/PF2 C 4 5 6 7 8 Vss Vcc C RST/PF2 1 2 3 4 Document Number: 002-04629 Rev. *A NC NC NC NC NC NC NC NC 25 LCC-32P-M19 (MB95580H Series) The number of usable pins is 16. 16 C 5 6 7 NC X0A/PG1 Vcc 14 15 3 4 NC NC VSS X1A/PG2 (TOP VIEW) 9 10 11 12 13 1 2 NC NC NC NC NC X1/PF1 X0/PF0 32 31 30 29 28 27 26 MB95560H Series MB95570H Series MB95580H Series (TOP VIEW) FPT-16P-M08 FPT-16P-M23 (MB95580H Series) (TOP VIEW) DIP-8P-M03 FPT-8P-M08 (MB95570H Series) 24 23 22 21 20 19 P07/INT07 P12/EC0/DBG P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT 18 P02/INT02/AN02/SCK 17 P01/AN01 16 P12/EC0/DBG 15 14 P07/INT07 P06/INT06/TO01 13 12 11 10 9 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P01/AN01 P02/INT02/AN02/SCK 8 7 6 5 P12/EC0/DBG P06/INT06/TO01 P05/AN05/TO00 P04/INT04/AN04/EC0 Page 10 of 88 MB95560H Series MB95570H Series MB95580H Series 5. Pin Functions (MB95560H Series, 32 pins) Pin no. 1 2 3 4 5 6 7 8 9 Pin name PF1 X1 PF0 X0 VSS PG2 X1A PG1 X0A VCC C PF2 RST P63 I/O circuit type* B B — C C — — A E TO11 10 P62 E TO10 11 12 13 14 15 NC P00 — D AN00 16 P64 E EC1 17 P01 D AN01 P02 18 INT02 AN02 SCK D Document Number: 002-04629 Rev. *A Function General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Decoupling capacitor connection pin General-purpose I/O port Reset pin Dedicated reset pin on MB95F562H/F563H/F564H General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin Page 11 of 88 MB95560H Series MB95570H Series MB95580H Series Pin no. Pin name I/O circuit type* P03 19 20 INT03 AN03 SOT P04 INT04 AN04 SIN EC0 D D P05 21 INT05 AN05 TO00 D P06 22 23 24 INT06 TO01 P12 EC0 DBG P07 E F E INT07 25 26 27 28 29 30 31 32 NC — Function General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART data output pin General-purpose I/O port External interrupt input pin A/D converter analog input pin LIN-UART data input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin DBG input pin General-purpose I/O port High-current pin External interrupt input pin It is an internally connected pin. Always leave it unconnected. *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-04629 Rev. *A Page 12 of 88 MB95560H Series MB95570H Series MB95580H Series 6. Pin Functions (MB95560H Series, 20 pins) Pin no. 1 2 3 4 5 6 7 8 9 Pin name PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A VCC C PF2 RST P62 I/O circuit type* B B — C C — — A E TO10 10 P63 E TO11 11 P64 E EC1 12 P00 D AN00 13 P01 D AN01 P02 14 INT02 AN02 SCK D P03 15 INT03 AN03 SOT D Document Number: 002-04629 Rev. *A Function General-purpose I/O port Main clock input oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Decoupling capacitor connection pin General-purpose I/O port Reset pin Dedicated reset pin on MB95F562H/F563H/F564H General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART data output pin Page 13 of 88 MB95560H Series MB95570H Series MB95580H Series Pin no. Pin name 16 P04 INT04 AN04 SIN EC0 I/O circuit type* D P05 17 INT05 AN05 TO00 D P06 18 19 20 INT06 TO01 P07 INT07 P12 EC0 DBG E E F Function General-purpose I/O port External interrupt input pin A/D converter analog input pin LIN-UART data input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-04629 Rev. *A Page 14 of 88 MB95560H Series MB95570H Series MB95580H Series 7. Pin Functions (MB95570H Series, 8 pins) Pin no. Pin name I/O circuit type* 1 VSS — Power supply pin (GND) 2 VCC — Power supply pin 3 C — Decoupling capacitor connection pin PF2 4 RST General-purpose I/O port A P04 5 6 INT04 AN04 D External interrupt input pin A/D converter analog input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin AN05 D INT06 General-purpose I/O port High-current pin E TO01 External interrupt input pin 8/16-bit composite timer ch. 0 output pin P12 EC0 A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin P06 8 Reset pin Dedicated reset pin on MB95F572H/F573H/F574H General-purpose I/O port TO00 7 Function General-purpose I/O port F DBG 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-04629 Rev. *A Page 15 of 88 MB95560H Series MB95570H Series MB95580H Series 8. Pin Functions (MB95580H Series, 32 pins) Pin no. 1 2 3 4 5 Pin name PF1 X1 PF0 X0 VSS PG2 X1A PG1 X0A I/O circuit type* B B — C C Function General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin 6 VCC — Power supply pin 7 C — Decoupling capacitor connection pin PF2 8 RST General-purpose I/O port A Reset pin Dedicated reset pin on MB95F582H/F583H/F584H — It is an internally connected pin. Always leave it unconnected. D General-purpose I/O port High-current pin 9 10 11 12 13 NC 14 15 16 17 P01 AN01 A/D converter analog input pin General-purpose I/O port High-current pin P02 18 19 INT02 D External interrupt input pin AN02 A/D converter analog input pin SCK LIN-UART clock I/O pin P03 General-purpose I/O port High-current pin INT03 D External interrupt input pin AN03 A/D converter analog input pin SOT LIN-UART data output pin Document Number: 002-04629 Rev. *A Page 16 of 88 MB95560H Series MB95570H Series MB95580H Series Pin no. 20 21 Pin name I/O circuit type* P04 General-purpose I/O port INT04 External interrupt input pin AN04 D LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin INT05 D A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin INT06 E EC0 External interrupt input pin 8/16-bit composite timer ch. 0 output pin P12 24 External interrupt input pin AN05 TO01 23 A/D converter analog input pin SIN P06 22 Function General-purpose I/O port F 8/16-bit composite timer ch. 0 clock input pin DBG DBG input pin P07 General-purpose I/O port High-current pin E INT07 External interrupt input pin 25 26 27 28 29 NC — It is an internally connected pin. Always leave it unconnected. 30 31 32 *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-04629 Rev. *A Page 17 of 88 MB95560H Series MB95570H Series MB95580H Series 9. Pin Functions (MB95580H Series, 16 pins) Pin no. 1 2 3 4 5 6 Pin name PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A VCC I/O circuit type* B B — C C — PF2 7 8 RST C 10 INT02 General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Reset pin Dedicated reset pin on MB95F582H/F583H/F584H — Decoupling capacitor connection pin General-purpose I/O port High-current pin D External interrupt input pin AN02 A/D converter analog input pin SCK LIN-UART clock I/O pin P01 General-purpose I/O port High-current pin D A/D converter analog input pin General-purpose I/O port High-current pin P03 12 Main clock input oscillation pin A AN01 11 General-purpose I/O port General-purpose I/O port P02 9 Function INT03 D External interrupt input pin AN03 A/D converter analog input pin SOT LIN-UART data output pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 D A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin Document Number: 002-04629 Rev. *A Page 18 of 88 MB95560H Series MB95570H Series MB95580H Series Pin no. Pin name I/O circuit type* General-purpose I/O port High-current pin P05 13 INT05 D A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin INT06 E TO01 15 16 External interrupt input pin AN05 P06 14 Function P07 External interrupt input pin 8/16-bit composite timer ch. 0 output pin E General-purpose I/O port High-current pin INT07 External interrupt input pin P12 General-purpose I/O port EC0 F DBG 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-04629 Rev. *A Page 19 of 88 MB95560H Series MB95570H Series MB95580H Series 10. I/O Circuit Type Type Circuit A Remarks Reset input / Hysteresis input Reset output / Digital output • N-ch open drain output • Hysteresis input • Reset output N-ch B P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input Clock input • Oscillation circuit • High-speed side Feedback resistance: approx. 1 M • CMOS output • Hysteresis input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input C Port select R Pull-up control P-ch P-ch • Oscillation circuit • Low-speed side Feedback resistance: approx.10 M Digital output N-ch Digital output Standby control Hysteresis input • CMOS output • Hysteresis input • Pull-up control available Clock input X1A X0A Standby control / Port select Port select R Pull-up control Digital output P-ch Digital output N-ch Digital output Standby control Hysteresis input Document Number: 002-04629 Rev. *A Page 20 of 88 MB95560H Series MB95570H Series MB95580H Series Type Circuit Remarks D Pull-up control R P-ch Digital output P-ch • • • • CMOS output Hysteresis input Pull-up control available Analog input Digital output N-ch Analog input A/D control Standby control Hysteresis input E Pull-up control R P-ch • CMOS output • Hysteresis input • Pull-up control available Digital output P-ch Digital output N-ch Standby control Hysteresis input F Standby control Hysteresis input • N-ch open drain output • Hysteresis input Digital output N-ch 11. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 11.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Document Number: 002-04629 Rev. *A Page 21 of 88 MB95560H Series MB95570H Series MB95580H Series  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence.  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Document Number: 002-04629 Rev. *A Page 22 of 88 MB95560H Series MB95570H Series MB95580H Series 11.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: Document Number: 002-04629 Rev. *A Page 23 of 88 MB95560H Series MB95570H Series MB95580H Series (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 11.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. 12. Notes On Device Handling • Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "24.1 Absolute Maximum Ratings" of "Electrical Characteristics" is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Document Number: 002-04629 Rev. *A Page 24 of 88 MB95560H Series MB95570H Series MB95580H Series Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. 13. Pin Connection • Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latchups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a decoupling capacitor between the VCC pin and the VSS pin at a location close to this device. • DBG pin Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. • RST pin Connect the RST pin to an external pull-up resistor of 2 k or above. To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit in the SYSC register. • C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. Document Number: 002-04629 Rev. *A Page 25 of 88 MB95560H Series MB95570H Series MB95580H Series • DBG/RST/C pins connection diagram DBG C RST Cs 14. Block Diagram (MB95560H Series) F2MC-8FX CPU PF2*1/RST*2 Dual operation Flash with security function (8/12/20 Kbyte) Reset with LVD PF1/X1*2 PF0/X0*2 PG2/X1A*2 Oscillator circuit CR oscillator RAM (240/496 bytes) PG1/X0A*2 Interrupt controller Clock control On-chip debug Wild register P02*3/INT02 to P07*3/INT07 Internal bus (P12*1/DBG) (P05*3/TO00) 8/16-bit composite timer ch. 0 (P06*3/TO01) P12*1/EC0, (P04/EC0) 8/10-bit A/D converter (P00*3/AN00 to P05*3/AN05) External interrupt (P62*3/TO10) (P02*3/SCK) (P03*3/SOT) 8/16-bit composite timer ch. 1 LIN-UART (P63*3/TO11) P64*3/EC1 (P04/SIN) C Port Port Vcc Vss *1: PF2 and P12 are N-ch open drain pins. *2: Software option *3: P00 to P03, P05 to P07 and P62 to P64 are high-current pins. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. Document Number: 002-04629 Rev. *A Page 26 of 88 MB95560H Series MB95570H Series MB95580H Series 15. Block Diagram (MB95570H Series) F2MC-8FX CPU PF2*1/RST*2 Dual operation Flash with security function (8/12/20 Kbyte) Reset with LVD RAM (240/496 bytes) CR oscillator Clock control (P12*1/DBG) On-chip debug Internal bus Interrupt controller (P05*3/TO00) 8/16-bit composite timer ch. 0 (P06*3/TO01) P12*1/EC0, (P04/EC0) Wild register 8/10-bit A/D converter P04/INT04, P06*3/INT06 P05*3/AN05, (P04/AN04) External interrupt C Port Port Vcc Vss *1: PF2 and P12 are N-ch open drain pins. *2: Software option *3: P05 and P06 are high-current pins. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. Document Number: 002-04629 Rev. *A Page 27 of 88 MB95560H Series MB95570H Series MB95580H Series 16. Block Diagram (MB95580H Series) F2MC-8FX CPU PF2*1/RST*2 Dual operation Flash with security function (8/12/20 Kbyte) Reset with LVD PF1/X1*2 PF0/X0*2 PG2/X1A*2 Oscillator circuit CR oscillator RAM (240/496 bytes) PG1/X0A*2 Interrupt controller Clock control On-chip debug Wild register P02*3/INT02 to P07*3/INT07 Internal bus (P12*1/DBG) (P05*3/TO00) 8/16-bit composite timer ch. 0 (P06*3/TO01) P12*1/EC0, (P04/EC0) 8/10-bit A/D converter (P01*3/AN01 to P05*3/AN05) External interrupt (P02*3/SCK) (P03*3/SOT) LIN-UART (P04/SIN) C Port Port Vcc Vss *1: PF2 and P12 are N-ch open drain pins. *2: Software option *3: P01 to P03 and P05 to P07 are high-current pins. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. Document Number: 002-04629 Rev. *A Page 28 of 88 MB95560H Series MB95570H Series MB95580H Series 17. CPU Core • Memory space The memory space of the MB95560H/570H/580H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95560H/570H/580H Series are shown below. • Memory maps MB95F562H/F562K/F572H/ F572K/F582H/F582K MB95F563H/F563K/F573H/ F573K/F583H/F583K 0000H 0000H I/O area 0080H 0090H 0100H 0180H Access prohibited RAM 240 bytes Register Access prohibited 0F80H Flash 4 Kbyte Access prohibited F000H FFFFH Access prohibited Flash 4 Kbyte Document Number: 002-04629 Rev. *A I/O area 0F80H C000H Access prohibited Extension I/O area 1000H Access prohibited B000H Access prohibited RAM 496 bytes Register 0200H 0280H Extension I/O area 1000H Access prohibited C000H Access prohibited RAM 496 bytes 0080H 0090H 0100H Register 0200H 0280H Extension I/O area B000H 0000H I/O area 0080H 0090H 0100H 0F80H 1000H MB95F564H/F564K/F574H/ F574K/F584H/F584K Flash 4 Kbyte Access prohibited B000H Access prohibited Flash 20 Kbyte E000H Flash 8 Kbyte FFFFH FFFFH Page 29 of 88 MB95560H Series MB95570H Series MB95580H Series 18. I/O Map (MB95560H Series) Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH to 0015H 0016H 0017H 0018H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH to 0048H Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC SYCC2 STBC2 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 Standby control register 2 — PDR6 DDR6 (Disabled) Port 6 data register Port 6 direction register — PDRF DDRF PDRG DDRG PUL0 (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register — PUL6 — PULG T01CR1 T00CR1 T11CR1 T10CR1 (Disabled) Port 6 pull-up register (Disabled) Port G pull-up register 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 8/16-bit composite timer 11 status control register 1 8/16-bit composite timer 10 status control register 1 — Document Number: 002-04629 Rev. *A (Disabled) R/W Initial value R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B — — R/W 11111111B R/W 000X0000B R/W XXX11011B R/W 00000000B R/W 000XXXXXB R/W 00000000B R/W 00000000B R/W 00XX0000B R/W XXXX0011B R/W 00000000B — — R/W R/W 00000000B 00000000B — — R/W R/W R/W R/W R/W 00000000B 00000000B 00000000B 00000000B 00000000B — — R/W — R/W R/W R/W R/W R/W 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B — — Page 30 of 88 MB95560H Series MB95570H Series MB95580H Series Address 0049H 004AH 004BH 004CH, 004DH 004EH 004FH 0050H 0051H 0052H 0053H Register Register name abbreviation EIC10 External interrupt circuit control register ch. 2/ch. 3 EIC20 External interrupt circuit control register ch. 4/ch. 5 EIC30 External interrupt circuit control register ch. 6/ch. 7 — LVDR — SCR SMR SSR RDR TDR ESCR ECCR 0054H 0055H 0056H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 FSR4 WREN WROR 0078H — 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 — WRARH0 WRARL0 WRDR0 (Disabled) LVDR reset voltage selection ID register (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART receive data register LIN-UART transmit data register LIN-UART extended status control register LIN-UART extended communication control register — (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper) 8/10-bit A/D converter data register (lower) (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 Flash memory status register 4 Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 Document Number: 002-04629 Rev. *A R/W Initial value R/W R/W R/W 00000000B 00000000B 00000000B — — R/W — R/W R/W R/W R/W R/W R/W R/W 00000000B — 00000000B 00000000B 00001000B 00000000B 00000000B 00000100B 000000XXB — — R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B — — R/W 00000000B R/W 000X0000B R/W 00000000B R 000XXXXXB R/W 00000000B R/W 00000000B R/W 00000000B — — R/W R/W R/W R/W R/W R/W — R/W R/W R/W 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B — 00000000B 00000000B 00000000B Page 31 of 88 MB95560H Series MB95570H Series MB95580H Series Address Register abbreviation 0F83H WRARH1 Wild register address setting register (upper) ch. 1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (lower) ch. 1 R/W 00000000B 0F85H WRDR1 Wild register data setting register ch. 1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (lower) ch. 2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch. 2 R/W 00000000B 0F89H to 0F91H — — — 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register R/W 00000000B 0F95H T00DR 8/16-bit composite timer 00 data register R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 00000000B 0F97H T11CR0 8/16-bit composite timer 11 status control register 0 R/W 00000000B 0F98H T10CR0 8/16-bit composite timer 10 status control register 0 R/W 00000000B 0F99H T11DR 8/16-bit composite timer 11 data register R/W 00000000B 0F9AH T10DR 8/16-bit composite timer 10 data register R/W 00000000B 0F9BH TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 00000000B 0F9CH to 0FBBH — — — 0FBCH BGR1 LIN-UART baud rate generator register 1 R/W 00000000B 0FBDH BGR0 LIN-UART baud rate generator register 0 R/W 00000000B 0FBEH to 0FC2H — — — 0FC3H AIDRL R/W 00000000B 0FC4H to 0FE3H — — — 0FE4H CRTH Main CR clock trimming register (upper) R/W 000XXXXXB 0FE5H CRTL Main CR clock trimming register (lower) R/W 000XXXXXB 0FE6H — 0FE7H CRTDA 0FE8H Register name (Disabled) (Disabled) (Disabled) A/D input disable register (lower) (Disabled) (Disabled) R/W Initial value — — Main CR clock temperature dependent adjustment register R/W 000XXXXXB SYSC System configuration register R/W 11000011B 0FE9H CMCR Clock monitoring control register R/W 00000000B 0FEAH CMDR Clock monitoring data register R 00000000B Document Number: 002-04629 Rev. *A Page 32 of 88 MB95560H Series MB95570H Series MB95580H Series Address Register abbreviation 0FEBH WDTH Watchdog timer selection ID register (upper) R XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (lower) R XXXXXXXXB 0FEDH to 0FFFH — — — Register name (Disabled) R/W Initial value • R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Document Number: 002-04629 Rev. *A Page 33 of 88 MB95560H Series MB95570H Series MB95580H Series 19. I/O Map (MB95570H Series) Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH to 0027H 0028H 0029H 002AH, 002BH 002CH 002DH to 0035H 0036H 0037H 0038H to 0049H 004AH 004BH 004CH, 004DH 004EH 004FH to 006BH Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC SYCC2 STBC2 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 Standby control register 2 — PDRF DDRF (Disabled) Port F data register Port F direction register — PUL0 (Disabled) Port 0 pull-up register — T01CR1 T00CR1 (Disabled) 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 — EIC20 EIC30 (Disabled) External interrupt circuit control register ch. 4/ch. 5 External interrupt circuit control register ch. 6/ch. 7 — LVDR (Disabled) LVDR reset voltage selection ID register — Document Number: 002-04629 Rev. *A (Disabled) R/W Initial value R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B — — R/W 11111111B R/W 000X0000B R/W XXX11011B R/W 00000000B R/W 000XXXXXB R/W 00000000B R/W 00000000B R/W 00XX0000B R/W XXXX0011B R/W 00000000B — — R/W R/W 00000000B 00000000B — — R/W 00000000B — — R/W R/W 00000000B 00000000B — — R/W R/W 00000000B 00000000B — — R/W 00000000B — — Page 34 of 88 MB95560H Series MB95570H Series MB95580H Series 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H Register abbreviation ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 FSR4 WREN WROR 0078H — 0079H 007AH 007BH, 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H to 0FC2H ILR0 ILR1 Address Register name 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper) 8/10-bit A/D converter data register (lower) (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 Flash memory status register 4 Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 — ILR4 ILR5 — WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 (Disabled) Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2 — T01CR0 T00CR0 T01DR T00DR TMCR0 (Disabled) 8/16-bit composite timer 01 status control register 0 8/16-bit composite timer 00 status control register 0 8/16-bit composite timer 01 data register 8/16-bit composite timer 00 data register 8/16-bit composite timer 00/01 timer mode control register — Document Number: 002-04629 Rev. *A (Disabled) R/W Initial value R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B — — R/W 00000000B R/W 000X0000B R/W 00000000B R 000XXXXXB R/W 00000000B R/W 00000000B R/W 00000000B — — R/W R/W 11111111B 11111111B — — R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W 11111111B 11111111B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — — R/W R/W R/W R/W R/W 00000000B 00000000B 00000000B 00000000B 00000000B — — Page 35 of 88 MB95560H Series MB95570H Series MB95580H Series Address Register abbreviation 0FC3H AIDRL 0FC4H to 0FE3H — 0FE4H CRTH Main CR clock trimming register (upper) R/W 000XXXXXB 0FE5H CRTL Main CR clock trimming register (lower) R/W 000XXXXXB 0FE6H — 0FE7H CRTDA 0FE8H Register name A/D input disable register (lower) (Disabled) (Disabled) R/W Initial value R/W 00000000B — — — — Main CR clock temperature dependent adjustment register R/W 000XXXXXB SYSC System configuration register R/W 11000011B 0FE9H CMCR Clock monitoring control register R/W 00000000B 0FEAH CMDR Clock monitoring data register R 00000000B 0FEBH WDTH Watchdog timer selection ID register (upper) R XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (lower) R XXXXXXXXB 0FEDH to 0FFFH — — — (Disabled) • R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Document Number: 002-04629 Rev. *A Page 36 of 88 MB95560H Series MB95570H Series MB95580H Series 20. I/O Map (MB95580H Series) Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0034H 0035H 0036H 0037H 0038H to 0048H 0049H 004AH 004BH 004CH, 004DH 004EH 004FH Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC SYCC2 STBC2 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 Standby control register 2 — PDRF DDRF PDRG DDRG PUL0 (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register — PULG T01CR1 T00CR1 (Disabled) Port G pull-up register 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 — EIC10 EIC20 EIC30 (Disabled) External interrupt circuit control register ch. 2/ch. 3 External interrupt circuit control register ch. 4/ch. 5 External interrupt circuit control register ch. 6/ch. 7 — LVDR — (Disabled) LVDR reset voltage selection ID register (Disabled) Document Number: 002-04629 Rev. *A R/W Initial value R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B — — R/W 11111111B R/W 000X0000B R/W XXX11011B R/W 00000000B R/W 000XXXXXB R/W 00000000B R/W 00000000B R/W 00XX0000B R/W XXXX0011B R/W 00000000B — — R/W R/W R/W R/W R/W 00000000B 00000000B 00000000B 00000000B 00000000B — — R/W R/W R/W 00000000B 00000000B 00000000B — — R/W R/W R/W 00000000B 00000000B 00000000B — — R/W — 00000000B — Page 37 of 88 MB95560H Series MB95570H Series MB95580H Series Address 0050H 0051H 0052H 0053H 0054H 0055H 0056H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H Register abbreviation SCR SMR SSR RDR TDR ESCR ECCR Register name LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART receive data register LIN-UART transmit data register LIN-UART extended status control register LIN-UART extended communication control register — ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 FSR4 WREN WROR 0078H — 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H ILR0 ILR1 ILR2 — ILR4 ILR5 — WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper) 8/10-bit A/D converter data register (lower) (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 Flash memory status register 4 Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 (Disabled) Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2 Document Number: 002-04629 Rev. *A R/W Initial value R/W R/W R/W R/W R/W R/W R/W 00000000B 00000000B 00001000B 00000000B 00000000B 00000100B 000000XXB — — R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B — — R/W 00000000B R/W 000X0000B R/W 00000000B R 000XXXXXB R/W 00000000B R/W 00000000B R/W 00000000B — — R/W R/W R/W — R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W 11111111B 11111111B 11111111B — 11111111B 11111111B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B Page 38 of 88 MB95560H Series MB95570H Series MB95580H Series Address 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H to 0FBBH 0FBCH 0FBDH 0FBEH to 0FC2H 0FC3H 0FC4H to 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH to 0FFFH Register abbreviation Register name — (Disabled) T01CR0 T00CR0 T01DR T00DR TMCR0 8/16-bit composite timer 01 status control register 0 8/16-bit composite timer 00 status control register 0 8/16-bit composite timer 01 data register 8/16-bit composite timer 00 data register 8/16-bit composite timer 00/01 timer mode control register — BGR1 BGR0 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 — AIDRL (Disabled) A/D input disable register (lower) — CRTH CRTL — CRTDA SYSC CMCR CMDR WDTH WDTL (Disabled) Main CR clock trimming register (upper) Main CR clock trimming register (lower) (Disabled) Main CR clock temperature dependent adjustment register System configuration register Clock monitoring control register Clock monitoring data register Watchdog timer selection ID register (upper) Watchdog timer selection ID register (lower) — (Disabled) R/W Initial value — — R/W R/W R/W R/W R/W 00000000B 00000000B 00000000B 00000000B 00000000B — — R/W R/W 00000000B 00000000B — — R/W 00000000B — — R/W R/W — R/W R/W R/W R R R 000XXXXXB 000XXXXXB — 000XXXXXB 11000011B 00000000B 00000000B XXXXXXXXB XXXXXXXXB — — • R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Document Number: 002-04629 Rev. *A Page 39 of 88 MB95560H Series MB95570H Series MB95580H Series 21. Interrupt Source Table (MB95560H Series) Vector table address Priority order of Bit name of interrupt sources interrupt level of the same level (occurring setting register simultaneously) Interrupt request number Upper Lower External interrupt ch. 4 IRQ00 FFFAH FFFBH L00 [1:0] External interrupt ch. 5 IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 FFEEH FFEFH L06 [1:0] LIN-UART (reception) IRQ07 FFECH FFEDH L07 [1:0] LIN-UART (transmission) IRQ08 FFEAH FFEBH L08 [1:0] — IRQ09 FFE8H FFE9H L09 [1:0] — IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — IRQ13 FFE0H FFE1H L13 [1:0] IRQ14 FFDEH FFDFH L14 [1:0] — IRQ15 FFDCH FFDDH L15 [1:0] — IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] IRQ21 FFD0H FFD1H L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 FFCEH FFCFH L22 [1:0] Flash memory IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — 8/16-bit composite timer ch. 1 (upper) — Document Number: 002-04629 Rev. *A High Low Page 40 of 88 MB95560H Series MB95570H Series MB95580H Series 22. Interrupt Source Table (MB95570H Series) Vector table address Priority order of Bit name of interrupt sources interrupt level of the same level (occurring setting register simultaneously) Interrupt request number Upper Lower IRQ00 FFFAH FFFBH L00 [1:0] IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 FFEEH FFEFH L06 [1:0] — IRQ07 FFECH FFEDH L07 [1:0] — IRQ08 FFEAH FFEBH L08 [1:0] — IRQ09 FFE8H FFE9H L09 [1:0] — IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — IRQ13 FFE0H FFE1H L13 [1:0] — IRQ14 FFDEH FFDFH L14 [1:0] — IRQ15 FFDCH FFDDH L15 [1:0] — IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] — IRQ21 FFD0H FFD1H L21 [1:0] — IRQ22 FFCEH FFCFH L22 [1:0] IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 4 — — External interrupt ch. 6 — — — Flash memory Document Number: 002-04629 Rev. *A High Low Page 41 of 88 MB95560H Series MB95570H Series MB95580H Series 23. Interrupt Source Table (MB95580H Series) Vector table address Priority order of Bit name of interrupt sources interrupt level of the same level (occurring setting register simultaneously) Interrupt request number Upper Lower External interrupt ch. 4 IRQ00 FFFAH FFFBH L00 [1:0] External interrupt ch. 5 IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 FFEEH FFEFH L06 [1:0] LIN-UART (reception) IRQ07 FFECH FFEDH L07 [1:0] LIN-UART (transmission) IRQ08 FFEAH FFEBH L08 [1:0] — IRQ09 FFE8H FFE9H L09 [1:0] — IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — IRQ13 FFE0H FFE1H L13 [1:0] — IRQ14 FFDEH FFDFH L14 [1:0] — IRQ15 FFDCH FFDDH L15 [1:0] — IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] — IRQ21 FFD0H FFD1H L21 [1:0] — IRQ22 FFCEH FFCFH L22 [1:0] IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — Flash memory Document Number: 002-04629 Rev. *A High Low Page 42 of 88 MB95560H Series MB95570H Series MB95580H Series 24. Electrical Characteristics 24.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage*1 Input voltage* 1 Output voltage* 1 Maximum clamp current Total maximum clamp current “L” level maximum output current Rating VCC VSS  0.3 VSS  6 V VI VSS  0.3 VSS  6 V *2 VO VSS  0.3 VSS  6 V *2 ICLAMP 2 2 mA Applicable to specific pins*3 |ICLAMP| — 20 mA Applicable to specific pins*3 IOL — 15 mA 4 — “L” level average current IOLAV2 “L” level total average output current “H” level maximum output current mA IOL — 100 mA IOLAV — 50 mA IOH — 15 mA “H” level average current 4 — mA IOH — 100 mA IOHAV — 50 mA Power consumption Pd — 320 mW Operating temperature TA 40 85 °C Storage temperature Tstg 55 150 °C “H” level total average output current Total average output current= operating current  operating ratio (Total number of pins) Other than P00 to P03, P05 to P07, P62 to P64*4 Average output current= operating current  operating ratio (1 pin) P00 to P03, P05 to P07, P62 to P64*4 Average output current= operating current  operating ratio (1 pin) 8 IOHAV2 Other than P00 to P03, P05 to P07, P62 to P64*4 Average output current= operating current  operating ratio (1 pin) P00 to P03, P05 to P07, P62 to P64*4 Average output current= operating current  operating ratio (1 pin) 12 IOHAV1 “H” level total maximum output current Remarks Max IOLAV1 “L” level total maximum output current Unit Min Total average output current= operating current  operating ratio (Total number of pins) *1: These parameters are based on the condition that VSS is 0.0 V. Document Number: 002-04629 Rev. *A Page 43 of 88 MB95560H Series MB95570H Series MB95580H Series *2: VI and VO must not exceed VCC  0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/ from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Applicable to the following pins: P00 to P07, P62 to P64, PF0, PF1, PG1, PG2 (P00, and P62 to P64 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. P01, P02, P03, P07, PF0. PF1, PG1, and PG2 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.) • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit: • Input/Output equivalent circuit Protective diode VCC P-ch Limiting resistor HV(High Voltage) input (0 V to 16 V) N-ch R *4: P62 and P63 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-04629 Rev. *A Page 44 of 88 MB95560H Series MB95570H Series MB95580H Series 24.2 Recommended Operating Conditions (VSS = 0.0 V) Parameter Power supply voltage Symbol VCC Decoupling capacitor CS Operating temperature TA Value Min Max 2.4*1, *2 5.5*1 2.3 5.5 2.9 5.5 2.3 5.5 0.022 1 40 85 5 35 Unit Remarks In normal operation V Other than on-chip debug Hold condition in stop mode mode In normal operation Hold condition in stop mode On-chip debug mode µF *3 °C Other than on-chip debug mode On-chip debug mode *1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: The minimum power supply voltage becomes 2.88 V when a product with the low-voltage detection reset is used. *3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram * DBG C RST Cs *: Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-04629 Rev. *A Page 45 of 88 MB95560H Series MB95570H Series MB95580H Series 24.3 DC Characteristics Parameter Symbol (VCC = 5.0 V  10%, VSS = 0.0 V, TA = 40 °C to 85 °C) Pin name “H” level output voltage “L” level output voltage Input leak current (Hi-Z output leak current) Internal pull-up resistor Input capacitance Remarks Max — 0.7 VCC — VCC  0.3 V Hysteresis input VIHS P00* to P03* , P05 to P07*4, P12, P62 to P64*3, PF0*4, PF1*4, PG1*4, PG2*4 — 0.8 VCC — VCC  0.3 V Hysteresis input VIHM PF2 — 0.8 VCC — VCC  0.3 V Hysteresis input VIL P04 — VSS  0.3 — 0.3 VCC V Hysteresis input VILS P00* to P03* , P05 to P07*4, P12, P62 to P64*3, PF0*4, PF1*4, PG1*4, PG2*4 — VSS  0.3 — 0.2 VCC V Hysteresis input VILM PF2 — VSS  0.3 — 0.2 VCC V Hysteresis input VD P12, PF2 — VSS  0.3 — VSS  5.5 V P04 3 Open-drain output application voltage Unit Typ 3 “L” level input voltage Value Min VIH "H" level input voltage Condition 4 4 VOH1 P04, PF0*4, PF1*4, PG1*4, PG2 IOH = 4 mA VCC  0.5 — — V VOH2 P00*3 to P03*4, P05 to P07*4, IOH = 8 mA P62 to P64*3 VCC 0.5 — — V VOL1 P04, P12, PF0 to PF2*4, PG1*4, PG2*4 — — 0.4 V VOL2 P00*3 to P03*4, P05 to P07*4, IOL = 12 mA P62 to P64*3 — — 0.4 V All input pins 5 — 5 When the internal µA pull-up resistor is disabled P00*3 to P07*4, P62 to P64*3, VI = 0 V PG1*4, PG2*4 25 50 100 When the internal k pull-up resistor is enabled Other than VCC f = 1 MHz and VSS — 5 15 pF ILI RPULL CIN Document Number: 002-04629 Rev. *A IOL = 4 mA 0.0 V < VI < VCC Page 46 of 88 MB95560H Series MB95570H Series MB95580H Series (VCC = 5.0 V  10%, VSS = 0.0 V, TA = 40 °C to 85 °C) Parameter Symbol Pin name Condition Value Min — FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) 3.5 Unit Remarks 4.4 Except during Flash memory mA programming and erasing — 7.4 9.8 During Flash memory mA programming and erasing — 5.1 6.4 mA At A/D conversion — 1.2 1.5 mA — 65 71 µA ICCLS*6 FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = 25 °C — 5.4 7 µA In deep standby mode ICCT*6 FCL = 32 kHz Watch mode TA = 25 °C — 4.8 6.9 µA In deep standby mode ICCMCR FCRH = 4 MHz FMP = 4 MHz Main CR clock mode — 1.1 1.4 mA ICCSCR Sub-CR clock mode (divided by 2) TA = 25 °C — 58 64 µA ICCTS FCH = 32 MHz Time-base timer mode TA = 25 °C — 290 340 µA In deep standby mode — 4.1 6.5 µA In deep standby mode ICC FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) ICCS ICCL Power supply current*5 Typ*1 Max*2 VCC (External clock FCL = 32 kHz operation) FMPL = 16 kHz Subclock mode (divided by 2) TA = 25 °C VCC ICCH VCC Main stop mode (External clock (single external operation) clock product)/ Substop mode (dual external clock product) TA = 25 °C Document Number: 002-04629 Rev. *A Page 47 of 88 MB95560H Series MB95570H Series MB95580H Series Parameter Power supply current*5 Symbol Pin name Condition (VCC = 5.0 V  10%, VSS = 0.0 V, TA = 40 °C to 85 °C) Value Unit Remarks Min Typ*1 Max*2 ILVD Current consumption for the low-voltage detection circuit — 3.6 6.6 µA ICRH Current consumption for the main CR oscillator — 220 280 µA ICRL Current consumption for the sub-CR oscillator oscillating at 100 kHz — 5.1 9.3 µA Current consumption difference between normal standby mode and deep standby mode TA = 25 °C — 20 30 µA VCC INSTBY *1: VCC = 5.0 V, TA =  25 °C *2: VCC = 5.5 V, TA =  85 °C (unless otherwise specified) *3: P00, P62, P63 and P64 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. *4: P01, P02, P03, P07, PF0, PF1, PG1 and PG2 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/ F582H/F582K/F583H/F583K/F584H/F584K. *5: • The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. • See “24.4 AC Characteristics: Clock Timing” for FCH and FCL. • See “24.4 AC Characteristics: Source Clock / Machine Clock” for FMP and FMPL. *6: In sub-CR clock mode, the power supply current value is the sum of adding ICRL to ICCLS or ICCT. In addition, when the sub-CR clock mode is selected with FMPL being 50 kHz, the current consumption increases accordingly. Document Number: 002-04629 Rev. *A Page 48 of 88 MB95560H Series MB95570H Series MB95580H Series 24.4 AC Characteristics 24.4.1 Clock Timing Parameter Symbol Pin name Condition X0, X1 FCH X0 X0, X1 — X1: open * Min 1 1 1 3.92 FCRH — — 3.8 7.84 7.6 9.8 Clock frequency 9.5 FMCRPLL — — 11.76 11.4 15.68 15.2 — FCL X0A, X1A — — FCRL — Document Number: 002-04629 Rev. *A — 50 (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) Value Unit Remarks Typ Max When the main oscillation — 16.25 MHz circuit is used — 12 MHz When the main external clock — 32.5 MHz is used Operating conditions 4 4.08 MHz • The main CR clock is used. • 0 °C TA 70 °C Operating conditions • The main CR clock is used. 4 4.2 MHz • 40 °C  TA < 0 °C, 70 °C