D a t a S h e et , R e v . 2 .0 , A p r . 20 0 5
FlexiSLIC
Subscriber Line Interface Circuit
PBL 38630/2, Version 2
Wireline Communications
N e v e r
s t o p
t h i n k i n g .
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,
FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,
MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®,
SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, FlexiSLIC™, VDSLite™ are trademarks of Infineon
Technologies AG. Microsoft® is a registered trademark of Microsoft Corporation, Linux®
of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
The information in this document is subject to change without notice.
Edition 2005-04-14
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
FlexiSLIC
Revision History:
2005-04-14
Previous Version:
DS1
Rev. 2.0
Page
Subjects (major changes since last revision)
all
Package P-DSO-24-1 changed to P-/PG-DSO-24-8
all
Package type abbreviation SOIC changed to PDSO
all
Package P-LCC-28-2 changed to P-/PG-LCC-28-3
all
Package P-SSOP-24-1 changed to P-/PG-SSOP-24-1
Page 17
Table 5: Thermal resistance for 24-pin PDSO changed from 80.2 °C/W to
50.3 °C/W
Page 27
Figure 8: SLIC/codec circuitry changed
Page 28
Table 6: values of RR, RT, RRX, RTX, RB changed, RFB removed
Page 33
Figure 10 changed
FlexiSLIC
PBL 38630/2
Table of Contents
Page
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
3.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Characterictics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
4.1
4.2
Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Design Supporting Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-Wire Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four-Wire to Two-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Longitudinal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitors CTC and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC - DC Separation Capacitor, CHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-pass Transmit Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitor CLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
31
31
32
32
32
34
34
34
34
34
6
6.1
6.2
6.3
Battery Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CODEC Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Overhead Voltage (POV) . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Temperature Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
39
40
7
7.1
7.2
Loop Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Loop Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Ring Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8
Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9
9.1
9.2
9.3
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Circuit (C2, C1 = 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ringing (C2, C1 = 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10.1
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overvoltage Protection - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Sheet
4
42
42
42
42
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Table of Contents
Page
10.2
Secondary Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12
Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13
13.1
13.2
13.3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-pin SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-pin PDSO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
45
45
46
47
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Data Sheet
Page
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view)..
Overhead Level, VTRO, Two-Wire Port . . . . . . . . . . . . . . . . . . . . . . . . .
Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance . . . . .
Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE . . . . .
Overhead Level, VTXO, Four-Wire Transmit Port . . . . . . . . . . . . . . . . .
Frequency Response, Insertion Loss, Gain Tracking . . . . . . . . . . . . .
Application Example of PBL 38630/2 with SICOFI®4 Codec . . . . . . . .
Simplified AC Model of PBL 38630/2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Codec Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Overhead Voltage (POV). RL= 600 Ω or Infinite . . . . .
P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package) . . . . . . . . .
P-/PG-DSO-24-8 (Plastic Dual Small Outline Package) . . . . . . . . . . .
P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package) . . . . . . . . . .
6
10
11
24
25
25
25
26
27
30
33
37
38
40
45
46
47
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Data Sheet
Page
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLIC Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feeding Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bias Current of RSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
11
14
15
16
17
28
28
29
35
36
37
Rev. 2.0, 2005-04-14
FlexiSLIC
Subscriber Line Interface Circuit
PBL 38630/2
Version 2
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
24-pin SSOP package
High and low battery with automatic switching
65 mW on-hook power dissipation in active state
On-hook transmission
Long loop battery feed tracks Vbat for maximum line
voltage
Selectable transmit gain (1x or 0.5 x)
No power-up sequence
43 V open loop voltage @ -48 V battery feed
Close tolerance current feeding
Constant loop voltage for line leakage < 5 mA
(RLeak ~ > 10 kΩ @ -48 V)
Full longitudinal current capability during
on-hook state
Longitudinal balance > 60 dB
Analog overtemperature protection permits transmission while the protection circuits is active
Integrated Ring Relay driver
Programmable signal headroom
-40 oC to +85 oC ambient temperature range
1.2
•
•
Typical Applications
P-/PG-SSOP-24-1
P/PG-SSOP-24-1
P-SSOP-24-1
P-/PG-DSO-24-8
P-DSO-24-1, -3
P-/PG-LCC-28-3
P-LCC-28-2
P/PG-LCC-28-3
Basic functionality Central Office Line card
Digital Loop Carriers (DLC)
Type
Package
PBL 38630/2 SH
P-/PG-SSOP-24-1
PBL 38630/2 SO
P-/PG-DSO-24-8
PBL 38630/2 QN
P-/PG-LCC-28-3
Data Sheet
8
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Overview
1.3
Description
The PBL 38630/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in PBX, Terminal adapters and other telecommunications equipment. The
PBL 38630/2 SLIC has been optimized for low total line interface cost and for a high
degree of flexibility in different applications.
The PBL 38630/2 SLIC emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with short loop current limiting adjustable to maximum 45 mA. In the
current limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30 kΩ.
A second lower battery voltage may be connected to the device to reduce short loop
power dissipation. The SLIC automatically switches between the two battery supply
voltages without need for external components or external control.
The SLIC incorporates loop current and ring-trip detection functions. The PBL 38630/2
is compatible with loop start signalling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with
a programmable CODEC/filter, for example SiCoFi PEB 2466. The programmable twowire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 38630/2 SLIC package options are 24-pin SSOP, 24-pin PDSO or 28-pin
PLCC.
Data Sheet
9
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Overview
1.4
Block Diagram
DT
DR
RRLY
VCC
AGND
Ring Trip
Comparator
Ring Relay
Driver
Ground Key
Detector
TIPX
HP
Two-wire
Interface
RINGX
C1
C2
DET
Line Feed
Controller
and
Longitudinal
Signal
Suppression
POV
PSG
PLC
LP
Off - Hook
Detector
PLD
VF signal
Transmission
BGND
Input
Decoder
and
Control
VBAT
REF
RSN
VTX
PTG
VBAT2
bl_sch_30
Figure 1
Data Sheet
Block Diagram
10
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Pin Configuration
Pin Configuration
RINGX 4
21 REF
BGND 5
TIPX 6
24-pin PDSO
and
24- pin SSOP
VBAT 7
3
2
1 28 27 26
R SN
4
VT X
PT G
22 RSN
R RLY
HP 3
HP
23 AGND
RRLY 2
AGND
24 VTX
PTG 1
NC
2
RINGX
5
25 NC
20 PLC
BGND
6
24 REF
19 POV
TIPX
7
18 PLD
23 PLC
28-pin PLCC
VBAT
8
22 POV
VBAT2
9
21 PLD
VBAT2 8
17 VCC
PSG
10
20 VCC
PSG 9
16 DET
NC
11
19 NC
DET
C1
13 NU
C2
DR 12
NU
14 C2
DR
DT 11
12 13 14 15 16 17 18
DT
15 C1
LP
LP 10
pinout_30
Figure 2
Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view).
Table 1
Pin Definition and Functions
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name
Pin
Function
Type
1
1
PTG
–
Programmable transmit gain. Left open
transmit gain = 0.0 dB, connected to AGND
transmit gain = -6.02 dB.
2
2
RRLY
O
Ring relay driver output. The relay coil may
be connected to maximum +14 V.
3
3
HP
–
Connection for high pass filter capacitor, CHP.
Other end of CHP connects to TIPX.
Data Sheet
11
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name
Pin
Function
Type
4
5
RINGX
–
The RINGX pin connects to the ring lead of
the two-wire interface via over voltage
protection components and ring relay (and
optional test relay).
5
6
BGND
–
Battery ground, should be tied together with
AGND.
6
7
TIPX
–
The TIPX pin connects to the tip lead of the
two-wire interface via over voltage protection
components and ring relay (and optional test
relay).
7
8
VBAT
–
Battery supply voltage. Negative with respect
to GND.
8
9
VBAT2
–
An optional second (2) Battery Voltage
connects to this pin via an external diode.
9
10
PSG
–
Programmable saturation guard. The
resistive part of the DC feed characteristics is
programmed by a resistor connected from
this pin to VBAT.
10
12
LP
–
Connection for low pass filter capacitor, CLP.
Other end of CLP connects to VBAT.
11
13
DT
I
Input to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
12
14
DR
I
Input to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
13
15
NU
–
Pin not used. Must be connected to AGND.
14
16
C2
I
15
17
C1
I
C1and C2 are digital inputs (positive logic,
internal pull-up), which control the SLIC
operating states. Refer to Table 2 for details.
Data Sheet
12
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name
Pin
Function
Type
16
18
DET
O
Detector output. Active low when indicating
loop or ring-trip detection, active high when
indicating ground key detection.
17
20
VCC
–
+5 V power supply.
18
21
PLD
–
Programmable loop detector threshold. The
loop detection threshold os programmed by a
resistor connected from this pin to AGND.
19
22
POV
–
Programmable overhead voltage. If pin is left
open: The overhead voltage is internally set
to min 2.7 V in off- hook and min 1.1 V in onhook. If a resistor is connected between this
pin and AGND: The overhead voltage can be
set to higher values.
20
23
PLC
–
Programmable line current, the constant
current part of the DC feed characteristic is
programmed by a resistor connected from
this pin to AGND.
21
24
REF
–
A reference, 49.9 kΩ, resistor should be
connected from this pin to AGND.
22
26
RSN
–
Receive summing node. 200 times the AC
current flowing into this pin equals the
metallic (transversal) AC current flowing from
RINGX to TIPX. Programming networks for
two-wire impedance and receive gain
connect to the receive node. A resistor should
be connected from this pin to AGND.
23
27
AGND
–
Analog ground, should be tied together with
BGND.
Data Sheet
13
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name
Pin
Function
Type
24
28
VTX
O
Transmit vf output. The AC voltage difference
between TIPX and RINGX, the AC metallic
voltage, is reproduced as an unbalanced
GND referenced signal at VTX with a gain of
one (or one half, see pin PTG). The two-wire
impedance programming network connects
between VTX and RSN.
–
4, 11, 19, NC
25
–
Not Connected.
Table 2
SLIC Operating States
State
C2
C1
SLIC Operating
State
Active Detector
(DET Response)
0
0
0
Open circuit
No active detector
(DET is set high)
1
0
1
Ringing
Ring-trip detector
(DET active low)
2
1
0
Active
Loop detector
(DET active low)
3
1
1
Not applicable
–
Data Sheet
14
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
3
Electrical Characteristics
Table 3
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
TStg
TAmb
-55
–
150
°C
–
-40
–
110
°C
–
TJ
-40
–
140
°C
–
VCC with respect to A/BGND VCC
VBAT2 with respect to
VBAT2
-0.4
–
6.5
V
–
VBAT
–
0.4
V
–
VBAT with respect to
VBAT
-75
–
0.4
V
–
VBAT with respect to
VBAT
-80
–
0.4
V
–
PD
–
–
1.5
W
TAmb ≤ +85
°C
-0.3
–
0.3
V
–
–
–
BGND
+14
V
–
-
AGND
V
–
-
5
mA
–
-0.4
–
V
–
-0.4
–
VCC
VCC
V
–
Temperature, Humidity
Storage temperature range
Operating temperature
range
Operating junction
temperature range1)
Power Supply (-40 °C ≤ TAmb ≤ +85 °C)
A/BGND
A/BGND, continuous
A/BGND, 10 ms
Power Dissipation
Continuous power
dissipation
Ground
Voltage between AGND and VG
BGND
Relay Driver
Ring relay supply voltage
–
Ring Trip Comparator
Input voltage
Input current
VDT, VDR VBAT
IDT, IDR -5
Digital Inputs, Outputs (C1, C2, DET)
Input voltage
Output voltage
Data Sheet
VID
VOD
15
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 3
Absolute Maximum Ratings (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Note/Test
Condition
TIPX and RINGX Terminals (-40 °C ≤ TAmb ≤ +85 °C, VBAT = -50 V)
TIPX or RINGX current
TIPX or RINGX voltage,
continuous (referenced to
AGND)2)
TIPX or RINGX2)
ITIPX,
-100
IRINGX
VTA, VRA -80
–
100
mA
–
–
2
V
–
VTA, VRA VBAT
–
5
V
pulse <
10 ms,
tRep > 10 s
VTA, VRA VBAT
–
10
V
pulse < 1 µs,
tRep > 10 s
VTA, VRA VBAT
–
15
V
pulse <
250 ns,
tRep > 10 s
- 10
TIPX or RINGX2)
- 25
TIP or RING2)3)
- 35
1) The circuit includes thermal protection. Operation above max. junction temperature may degrade device
reliability.
2) With the diodes DVB and DVB2 included, see Figure 8.
3) RF1 and RF2 > 20 Ω is also required. Pulse is supplied to RING and TIP outside RF1 and RF2.
Attention: Stresses above those values listed here may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these
values may cause irreversible damage to the integrated circuit.
Table 4
Operating Range
Parameter
Symbol
TAmb
VCC with respect to AGND
VCC
VBAT with respect to AGND
VBAT
AGND with respect to BGND VG
Ambient temperature
Data Sheet
Values
Min.
Typ.
Unit Note/Test
Condition
Max.
-40
–
85
°C
–
4.75
–
5.25
V
–
-58
–
-8
V
–
-100
–
100
mV
–
16
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
3.1
Characterictics
The specification is made with following setup: -40 °C ≤ TAmb ≤ +85 °C, PTG = open (see
pin description), VCC = +5 V ± 5%, VBAT = -58 V to -40 V, VBAT2 = -32 V, RLC = 32.4 kΩ,
IL = 27 mA, RL = 600 Ω, RF1 = RF2 = 0, RREF = 49.9 kΩ, CHP = 47 nF, CLP = 0.15 µF,
RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 52.3 kΩ, ROV = infinite.
Current definition: current is positive if flowing into a pin unless stated otherwise.
Table 5
Characteristics
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
2.7
–
–
VPeak
–
1.1
–
–
VPeak
On-Hook,
ILDC ≤ 5 mA
Two-Wire Port
Overhead level1),
18 mA ≤ ILDC
Active, 1% THD
ROV = infinite
see Figure 3
VTRO
Input impedance2)
ZTRX
–
ZT /
200
–
Ω
–
Longitudinal impedance
ZLOT,
ZLOR
–
20
35
Ω/wire
0 < f < 100 Hz
Longitudinal current limit ILOT,
ILOR
28
–
–
mArms/
wire
Active
Longitudinal to metallic BLM
balance (IEEE standard
455-1985), ZTRX = 736 Ω
63
66
–
dB
0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
60
66
–
dB
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
60
66
55
66
Data Sheet
17
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
–
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 5
Parameter
Characteristics (cont’d)
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
63
66
–
dB
0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
60
66
–
dB
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
60
66
55
66
–
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
63
66
–
dB
0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
60
66
–
dB
1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
60
66
55
66
–
dB
1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Metallic to longitudinal
BMLE
balance
BMLE = 20 × log|VTR/VLO|,
ERX = 0 V, see Figure 5
40
50
–
dB
0.2 kHz < f <
3.4 kHz
Four-wire to longitudinal BFLE
balance
BFLE = 20 × log|ERX/VLO|,
see Figure 5
40
50
–
dB
0.2 kHz < f <
3.4 kHz
Longitudinal to metallic BLME
balance
BLME = 20 × log|ELO/VTR|,
see Figure 4
Longitudinal to four-wire BLFE
balance
BLFE = 20 × log|ELO/VTX|,
see Figure 4
Data Sheet
18
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
30
35
–
dB
0.2 kHz < f <
1.0 kHz
20
22
–
dB
1.0 kHz < f <
3.4 kHz
Two-wire return loss3)
Z TRX + Z L
r = 20 × log ----------------------Z TRX – Z L
r
TIPX idle voltage
VTI
–
-1.3
–
V
Active, IL < 5 mA
RINGX idle voltage
VRI
–
VBAT+ –
3.0
V
Active, IL < 5 mA
Open loop voltage
VTR
–
VBAT+ –
4.3
V
Active, IL < 5 mA
2.7
–
–
VPeak
IL > 18 mA
1.1
–
–
VPeak
On-Hook, IL ≤
5 mA,
Four-Wire Transmit Port (VTX)
Overhead level4),
Load imp. > 20 kΩ
1% THD
see Figure 6
VTXO
Output offset voltage
∆VTX
-100
–
100
mV
–
Output impedance
ZTX
–
15
50
Ω
0.2 kHz < f <
3.4 kHz
Four-Wire Receive Port (receive summing node = RSN)
1.15
1.25
1.35
V
IRSN = -55 µA
–
8
20
Ω
0.2 kHz < f <
3.4 kHz
αRSN
–
200
–
ratio
0.3 kHz < f <
3.4 kHz
Two-wire to four-wire,
relative to 0 dBm,
1.0 kHz, ERX = 0 V,
see Figure 7
g2-4
-0.20
–
0.10
dB
0.3 kHz < f <
3.4 kHz
-1.0
–
0.1
dB
f = 8 kHz, 12 kHz,
16 kHz
Four-wire to two-wire,
relative to 0 dBm,
1.0 kHz, EL = 0 V,
see Figure 7
g4-2
-0.2
–
0.1
dB
0.3 kHz < f <
3.4 kHz
-1.0
–
0
dB
f = 8 kHz, 12 kHz
-2.0
–
0
dB
f = 16 kHz
RSN DC voltage
VRSNdc
RSN impedance
RSN current (IRSN ) to
metallic loop current (IL)
gain
Frequency Response
Data Sheet
19
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
g4-4
-0.2
–
0.1
dB
0.3 kHz < f <
3.4 kHz
Two-wire to four-wire5),
G2-4 = 20 × log|VTX/VTR|
0 dBm, 1.0 kHz
ERX = 0 V
G2-4
-0.2
–
0.2
dB
PTG = Open
see Figure 7
-6.22
-6.02
-5.82
dB
PTG = AGND
Four-wire to two-wire6),
G4-2 = 20 × log|VTR/VRX|,
EL = 0 V, see Figure 7
G4-2
-0.2
–
0.2
dB
0 dBm, 1.0 kHz
Two-wire to four-wire7),
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1
–
0.1
dB
-40 dBm to
+3 dBm
-0.2
–
0.2
dB
-55 dBm to 40 dBm
Four-wire to two-wire,
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1
–
0.1
dB
-40 dBm to
+3 dBm
-0.2
–
0.2
dB
-55 dBm to 40 dBm
–
–
12
dBrnC
C-message
weighting
–
–
-78
dBmp
Psophometrical
weighting
Two-wire to four-wire,
see Figure 7
–
-67
-50
dB
Four-wire to two-wire
–
-67
-50
dB
0 dBm
0.3 kHz < f <
3.4 kHz
Four-wire to four-wire,
relative to 0 dBm,
1.0 kHz, EL = 0 V,
see Figure 7
Insertion Loss
Gain Tracking
Noise
Idle channel noise at
two-wire port8) (TIPXRINGX) or four-wire
(VTX) output
Harmonic Distortion
Data Sheet
20
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
0.92
×
IL
IL
1.08
×
IL
mA
18 mA ≤ IL ≤ 45 mA
-100
0
100
µA
RL = 0 Ω
0.85
×
ILTh
ILTh
1.15
×
ILTh
mA
RLD in kΩ,
7 mA ≤ ILTh
Battery Feed Characteristics
Loop current in the
current limited region,
reference A, B & C
see Figure 12
IL
Open circuit loop current ILOC
Loop Detector
Programmable
threshold,
ILTh = 500/RLD
ILTh
Ringing Trip Comparator
Offset voltage
∆VDTDR
-20
0
20
mV
Source
resistance,
RS = 0 Ω
Input bias current
IB
-200
-20
200
nA
IB=(IDT +IDR)/2
Input common mode
range
VDT, VDR VBAT
+1
–
-1
V
–
–
0.2
0.5
V
IOL = 50 mA
–
–
10
µA
VOH = 12 V
Ring Relay Driver
Saturation voltage
VOL
Off state leakage current ILK
Digital Inputs (C1, C2)
Input low voltage
VIL
0
–
0.5
V
–
Input high voltage
VIH
2.5
–
VCC
V
–
Input low current
IIL
–
–
-50
µA
VIL = 0.5 V
Input high current
IIH
–
–
50
µA
VIH = 2.5 V
VOL
–
–
0.7
V
IOL = 0.5 mA
–
15
–
kΩ
–
15
mW
Open circuit
Detector Output (DET)
Output low voltage
Internal pull-up resistor
to VCC
Power Dissipation (VBAT -48 V, VBAT2 = -32 V)
Power Dissipation
Data Sheet
P1
–
10
21
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note/Test
Condition
Power Dissipation
P2
–
65
85
mW
Active (On-hook)
Long current =
0 mA
Power Dissipation
P3
–
730
–
mW
Active (Off-hook)
RL = 300 Ω
Power Dissipation
P4
–
360
–
mW
Active (Off-hook)
RL = 800 Ω
Power Supply Currents (VBAT = -48 V)
VCC current
ICC
–
1.2
2.0
mA
Open circuit (C1,
C2, C3 = 0)
VBAT current
IBAT
-0.1
-0.05
–
mA
Open circuit (C1,
C2, C3 = 0)
VCC current
ICC
–
2.8
4.0
mA
Active, On-hook,
Long current =
0 mA
VBAT current
IBAT
-1.5
-1.0
–
mA
Active, On-hook,
Long current =
0 mA
VCC to 2- or 4-wire port
30
42
–
dB
Active, f = 1 kHz,
Vn = 100 mV
VBAT2 to 2- or 4-wire port
40
60
–
dB
Active, f = 1 kHz,
Vn = 100 mV
VBAT to 2- or 4-wire port
36
45
–
dB
Active, f = 1 kHz,
Vn = 100 mV
Power Supply Rejection Ratios
Data Sheet
22
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Values
Unit
Note/Test
Condition
Min.
Typ.
Max.
TJG
–
145
–
°C
–
Rth, jp
–
55
–
°C/W
–
Rth, jA
–
66.9
–
°C/W
P-/PG-SSOP-241,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
Rth, jp
–
43
–
°C/W
–
Rth, jA
–
50.3
–
°C/W
P-/PG-DSO-24-8,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
Rth, jp
–
39
–
°C/W
–
Rth, jA
–
50.4
–
°C/W
P-/PG-LCC-28-3,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
Temperature Guard
Junction threshold
temperature
Thermal Resistance
24-pin SSOP
24-pin PDSO
28-pin PLCC
1) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the two-wire port with the signal source at the four-wire receive port.
Data Sheet
23
Rev. 2.0, 2005-04-14
FlexiSLIC
PBL 38630/2
Electrical Characteristics
2) The two-wire impedance is programmable by selection of external component values according to:
ZTRX = ZT/(|G2-4S × αRSN|) where:
ZTRX = impedance between the TIPX and RINGX terminals
ZT = programming network between the VTX and RSN terminals
G2-4S = transmit gain, nominally = 1 (or 0.5, see pin PTG)
αRSN = receive current gain, nominally 200 (current defined as positive flowing into the receive summing node,
RSN, and when flowing from ring to tip).
3) Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating
impedance programming resistance, for example by dividing RT into two equal halves and connecting a
capacitor from the common point to ground.
4) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the four-wire transmit port, (VTX) with the signal source at the two-wire port. Note that the gain
from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5, see pin PTG).
5) Pin PTG = Open sets transmit gain to nom. 0.0 dB.
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary protection resistor RF (see Figure 8) impacts the insertion loss as explained in Chapter 5. The
specified insertion loss is valid for RF = 0.
6) The specified insertion loss tolerance does not include errors caused by external components.
7) The level is specified at the two-wire port.
8) The two-wire idle noise is specified with the port terminated in 600 Ω (RL), and with the four-wire receive port
grounded (ERX = 0; see Figure 7). The four-wire idle noise at VTX is specified with the two-wire port terminated
in 600 Ω (RL). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX.
The four-wire receive port is grounded (ERX = 0).
C
TIPX
RL
V TRO
I LDC
VTX
PBL 38630
RINGX
RT
E RX
RSN
R RX
Fig3_30
Figure 3
Overhead Level, VTRO, Two-Wire Port
1/ωC
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