PSB3186FV1.4

D at a Sh e e t , D S 1 , Ja n . 2 00 3 ISAC-SX TE ISDN Subscriber Access Controller for Terminals PSB 3186, V 1.4 Wired Communications N e v e r s t o p t h i n k i n g . ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®, 10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft Corporation. Linux® is a registered trademark of Linus Torvalds. The information in this document is subject to change without notice. Edition 2003-01-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet Revision History: 2003-01-30 Previous Version: Data Sheet, DS1, V1.3, 2000-08-23 Page Subjects (major changes since last revision) Chapter 1 Comparison ISAC-S TE/ISAC-SX TE Chapter 3.3.6.2 S- Transceiver Synchronization New Chapter 3.3.10 Test Functions extended Chapter 3.7.1.1 CDA Handler Description extended Chapter 3.7.5.1 TIC Bus Access Control: Note added Chapter 5.6 IOM-2 Interface Timing: Explanation added Chapter 5.7.2 Parallel Microcontroller Interface Timing: Explanation added Chapter 5.9 S-Transceiver Chapter 5.10 Recommended Transformer Specification: Changed Chapter 5.11 Line Overload Protection added Chapter 5.12 EMC/ESD added DS1 ISAC-SX TE PSB 3186 Table of Contents Page 1 1.1 1.2 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 3.1 3.2 3.2.1 3.2.1.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.7 3.3.8 3.3.9 3.3.10 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.1.3 3.5.1.4 3.5.2 3.6 3.6.1 Description of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer and Delay between IOM-2 and S/T . . . . . . . . . . . . . . . . Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T Interface Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of the Receive PLL (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Clock Output C768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Transition Diagram (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . States (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Codes (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infos on S/T (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/ Indicate Channel Codes (C/I0) - Overview . . . . . . . . . . . . . Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 4 12 15 17 18 25 25 27 28 29 31 33 34 35 38 39 40 42 44 45 46 47 47 50 50 50 51 52 54 55 55 56 57 59 59 61 63 65 66 67 67 2003-01-30 ISAC-SX TE PSB 3186 Table of Contents Page 3.7 3.7.1 3.7.1.1 3.7.2 3.7.2.1 3.7.2.2 3.7.3 3.7.3.1 3.7.3.2 3.7.3.3 3.7.3.4 3.7.3.5 3.7.3.6 3.7.4 3.7.5 3.7.5.1 3.7.5.2 3.7.6 3.8 3.8.1 3.8.2 3.8.2.1 3.8.2.2 3.8.3 3.8.3.1 3.8.3.2 3.8.4 3.8.5 3.8.6 3.9 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Serial Data Strobe Signal and Strobed Data Clock . . . . . . . . . . . . . . . 82 Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MONITOR Channel Programming as a Master Device . . . . . . . . . . . 91 MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . 91 Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . 95 S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . . 97 Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . 100 HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . 104 Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . 112 Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Access to IOM-2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-channel HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . RFIFOD - Receive FIFO D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . XFIFOD - Transmit FIFO D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . ISTAD - Interrupt Status Register D-Channel . . . . . . . . . . . . . . . . . . . MASKD - Mask Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . STARD - Status Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . CMDRD - Command Register D-channel . . . . . . . . . . . . . . . . . . . . . . MODED - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXMD1- Extended Mode Register D-channel 1 . . . . . . . . . . . . . . . . . TIMR1 - Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 5 121 128 128 128 128 130 130 131 132 134 135 135 2003-01-30 ISAC-SX TE PSB 3186 Table of Contents 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.1.16 4.1.17 4.1.18 4.1.19 4.1.20 4.1.21 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.4.1 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 4.3.16 Page SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RBCLD - Receive Frame Byte Count Low D-Channel . . . . . . . . . . . . RBCHD - Receive Frame Byte Count High D-Channel . . . . . . . . . . . TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSTAD - Receive Status Register D-Channel . . . . . . . . . . . . . . . . . . TMD -Test Mode Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TR_CONF0 - Transceiver Configuration Register 0 . . . . . . . . . . . . . . TR_CONF1 - Transceiver Configuration Register 1 . . . . . . . . . . . . . . TR_CONF2 - Transmitter Configuration Register 2 . . . . . . . . . . . . . . TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . SQRR1 - S/Q-Channel Receive Register 1 . . . . . . . . . . . . . . . . . . . . SQXR1- S/Q-Channel TX Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . SQRR2 - S/Q-Channel Receive Register 2 . . . . . . . . . . . . . . . . . . . . . SQRR3 - S/Q-Channel Receive Register 3 . . . . . . . . . . . . . . . . . . . . ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . ACFG2 - Auxiliary Configuration Register . . . . . . . . . . . . . . . . . . . . . IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) . . . TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1) DCI_CR - Control Register for D and CI1 Handler (IOM_CR.CI_CS=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . SDS_CR - Control Register Serial Data Strobe . . . . . . . . . . . . . . . . . IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . SDS_CONF - Configuration Register for Serial Data Strobe . . . . . . . MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . Data Sheet 6 136 136 137 137 138 138 140 140 141 142 142 144 144 145 145 146 147 147 148 148 148 149 149 151 151 151 152 153 154 154 156 156 157 159 159 160 160 161 161 162 162 2003-01-30 ISAC-SX TE PSB 3186 Table of Contents Page 4.3.17 4.3.18 4.3.19 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . Interrupt and General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUXI - Auxiliary Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . AUXM - Auxiliary Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR2 - Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 163 164 165 165 166 166 167 167 169 169 170 170 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.8 5.9 5.10 5.11 5.12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Transformer Specification . . . . . . . . . . . . . . . . . . . . . . . Line Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMC / ESD Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 172 173 174 175 176 177 179 179 180 184 185 186 187 188 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Data Sheet 7 2003-01-30 ISAC-SX TE PSB 3186 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Data Sheet Page Logic Symbol of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications of the ISAC-SX TE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . Data Delay between IOM-2 and S/T Interface . . . . . . . . . . . . . . . . . . . Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . Connection of Line Transformers and Power Supply to the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock System of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Relationships of ISAC-SX TE Clock Signals . . . . . . . . . . . . . . Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Transition Diagram (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Transition Diagram of Unconditional Transitions (TE) . . . . . . . . Example of Activation/Deactivation Initiated by the Terminal . . . . . . . IOMÒ-2 Frame Structure in Terminal Mode . . . . . . . . . . . . . . . . . . . . Architecture of the IOM Handler (Example Configuration). . . . . . . . . . Data Access via CDAx1 and CDAx2 Register Pairs . . . . . . . . . . . . . . Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 8 17 18 19 26 28 29 32 33 34 36 37 37 38 38 40 41 41 44 45 46 46 47 48 49 50 51 52 54 55 56 57 58 60 61 67 69 71 73 74 75 76 2003-01-30 ISAC-SX TE PSB 3186 List of Figures Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Data Sheet Page Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 79 Examples for the Synchronous Transfer Interrupt Control with one Enabled STIxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01H . 84 Examples of MONITOR Channel Applications in IOM -2 TE Mode . . . 85 MONITOR Channel Protocol (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . . 87 Monitor Channel, Transmission Abort requested by the Receiver. . . . 90 Monitor Channel, Transmission Abort requested by the Transmitter. . 90 Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 90 MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . . 96 Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 97 Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 98 D-Channel Access Control on the S-Interface . . . . . . . . . . . . . . . . . . . 99 Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Data Reception Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Interrupt Status Registers of the HDLC Controllers . . . . . . . . . . . . . . 118 Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Register Mapping of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . 121 Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 176 IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 178 SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9 2003-01-30 ISAC-SX TE PSB 3186 Figure 83 Figure 84 Data Sheet Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10 2003-01-30 ISAC-SX TE PSB 3186 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Data Sheet Page Comparison of the ISAC-SX TE with the previous version ISAC-S TE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ISAC-SX TE Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . 20 Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ISAC-SX TE Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 S/Q-Bit Position Identification and Multiframe Structure . . . . . . . . . . . 42 IOM-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 79 CDA Register Combinations with Correct Read/Write Access . . . . . . 81 Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 HDLC Controller Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Receive Byte Count with RBC11...0 in the RBCHD/RBCLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Receive Information at RME Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 111 XPR Interrupt (availability of XFIFOD) after XTF, XME Commands . 113 11 2003-01-30 ISAC-SX TE PSB 3186 Overview 1 Overview The ISDN Subscriber Access Controller for Terminals ISAC-SX TE integrates a D-channel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN. It is based on the ISAC-S TE PSB 2186, and provides enhanced features and functionality. The system integration is simplified by several configurations of the parallel microcontroller interface selected via pin strapping. They include multiplexed and demultiplexed interface selection as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. The ISAC-SX TE also provides a serial control interface (SCI). The FIFO size of the cyclic D-channel buffer is 64 bytes per direction with programmable block size (threshold). The S-transceiver supports terminals mode (TE), activation/ deactivation, timing recovery and D-channel access control and priority control. One LED output which is capable to indicate the activation status of the S-interface automatically or can be programmed by the host. The ISAC-SX TE is produced in advanced CMOS technology. Data Sheet 12 2003-01-30 ISAC-SX TE PSB 3186 Overview Table 1 Comparison of the ISAC-SX TE with the previous version ISAC-S TE: ISAC-SX TE PSB 3186 ISAC-S TE PSB 2186 Operating modes TE TE Supply voltage 3.3 V ± 5% 5 V ± 5% Technology CMOS CMOS Package P-MQFP-64 / P-TQFP-64 P-MQFP-64 / P-LCC-44 / P-DIP-40 Transceiver Transformer ratio for the transmitter receiver 1:1 1:1 2:1 2:1 Test Functions - Dig. loop via Layer 2 (TLP) - Dig. loop via Layer 2(TLP) - Layer 1 disable (DIS_TR) - Layer 1 disable (DIS_TR) - Analog loop (ARL) - Analog loop (LP_A- bit EXLP- bit, ARL) Microcontroller Interface Serial interface (SCI) Not provided 8-bit parallel interface: Motorola Mux Siemens/Intel Mux Siemens/Intel Non-Mux direct/ indirect Addressing 8-bit parallel interface: Motorola Mux Siemens/Intel Mux Siemens/Intel Non-Mux Command structure of the Header/address/data register access (SCI) Address/data Crystal 7.68 MHz 7.68 MHz Buffered 7.68 MHz output Provided Not provided Controller data access to IOM-2 timeslots All timeslots; various possibilities of data access Restricted access to B- and IC-channel Data control and manipulation Various possibilities of data control and data manipulation (enable/ disable, shifting, looping, switching) B- and IC-channel looping Data Sheet 13 2003-01-30 ISAC-SX TE PSB 3186 Overview ISAC-SX TE PSB 3186 ISAC-S TE PSB 2186 IOM-2 Interface Double clock (DCL), bit clock pin (BCL), serial data strobe (SDS) Double clock (DCL), bit clock (BCL), serial data strobe (SDS) Monitor channel programming Provided (MON0, 1, 2, ..., 7) Provided (MON0 or 1) C/I channels CI0 (4 bit), CI1 (4/6 bit) CI0 (4 bit), CI1 (6 bit) Layer 1 state machine With changes for correspondence with the actual ITU specification Layer 1 state machine in software Not possible Not possible HDLC support D- and B-channel timeslots; non-auto mode, transparent mode 1-3, extended transparent mode D-channel timeslot; auto mode, non-auto mode, transparent mode 1-3 D-channel FIFO size 64 bytes cyclic buffer per 2x32 bytes buffer per direction with programmable direction FIFO thresholds Reset Signals RES input signal RSTO output signal RST input/output signal Reset Sources RES Input Watchdog C/I Code Change EAW Pin Software Reset RST Input Watchdog C/I Code Change EAW Pin Interrupt Output Signals INT low active (open drain) by default, reprogrammable to high active (push-pull) Low active INT Pin SCLK 1.536 MHz 512 kHz IOM-2 Data Sheet 14 2003-01-30 ISDN Subscriber Access Controller for Terminals ISAC-SX TE PSB/PSF 3186 V 1.4 1.1 Features • Full duplex 2B + D S/T interface transceiver according to ITU-T I.430 • Successor of ISAC-S TE PSB 2186 in 3.3 V technology • 8-bit parallel microcontroller interface, P-MQFP-64-1, -2, -3, -8 Motorola and Siemens/Intel bus type multiplexed or non-multiplexed, P-MQFP-64-1 direct-/indirect register addressing • Serial control interface (SCI) • Microcontroller access to all IOM-2 timeslots • Various types of protocol support (Non-auto mode, transparent mode, extended transparent mode) • D-channel HDLC controller with 2 x 64 byte FIFOs • IOM-2 interface in TE mode, single/double clocks • One serial data strobe signal (SDS) • Monitor channel handler (master/slave) • IOM-2 MONITOR and C/I-channel protocol to control P-TQFP-64-1 peripheral devices • Conversion of the frame structure between the S/T-interface and IOM-2 • Receive timing recovery • D-channel access control • Activation and deactivation procedures with automatic activation from power down state • Access to S and Q bits of S/T-interface • Adaptively switched receive thresholds • Two programmable timers • Watchdog timer • Software Reset Type Package PSB 3186 H P-MQFP-64-1 PSB 3186 F P-TQFP-64-1 Data Sheet 15 2003-01-30 ISAC-SX TE PSB 3186 Overview • • • • • • One LED pin automatically indicating layer 1 activated state Test loops Sophisticated power management for restricted power mode Power supply 3.3 V 3.3 V output drivers, inputs are 5 V safe Advanced CMOS technology Data Sheet 16 2003-01-30 ISAC-SX TE PSB 3186 Overview 1.2 Logic Symbol The logic symbol gives an overview of the ISAC-SX TE functions. IOM-2 Interface +3.3V 0V DD DU FSC DCL BCL SDS 0V VDD VSS TP VDDA VSSA RD / DS C768 WR / R/W 7.68 MHz output ALE Host Interface A0...7 XTAL2 AD0...4 XTAL1 7.68 MHz ± 100ppm AD5 / SCL AD6 / SDR SR1 AD7 / SDX SR2 CS S Interface SX1 INT SX2 RES RSTO Figure 1 Data Sheet ACL AMODE EAW LED Output Address Mode Setting External Awake 3186_17 Logic Symbol of the ISAC-SX TE 17 2003-01-30 ISAC-SX TE PSB 3186 Overview 1.3 Typical Applications The ISAC-SX TE is designed for the user area of the ISDN basic access, especially for subscriber terminal equipment with S interface. Figure 2 illustrates the general application fields of the ISAC-SX TE. PBX (NT2) TE(1) TE(8) S CP SN TE(1) U T LT-S LT-T NT1 LT-S CP = Central Processor Line Card TE(1) TE(8) R SN = Switching Network Direct Subscriber Access (point-to-point, short and extended passive Bus) = ISAC -SSX TETE U S NT1 ITS05407 Figure 2 Data Sheet Applications of the ISAC-SX TE 18 2003-01-30 ISAC-SX TE PSB 3186 Pin Configuration 2 Pin Configuration P-MQFP-64-1 VSS VDD XTAL1 AMODE VSS XTAL2 WR / R/W RD / DS n.c. ALE SX2 SX1 VDDA VSSA SR2 SR1 P-TQFP-64-1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BCL DU 49 DD FSC 54 55 27 26 C768 A7 25 A6 24 23 A5 DCL VSS VSS VDD 32 res_c 50 31 51 52 53 30 29 28 res_c res_c ISAC-SX TE PSB 3186 56 res_l EAW 57 58 ACL res_c 59 22 A4 A3 60 61 21 20 A2 A1 62 19 63 18 A0 VDD 64 17 VSS Data Sheet SDR / AD6 SDX / AD7 SCL / AD5 AD4 AD3 AD1 AD2 8 9 10 11 12 13 14 15 16 AD0 VSS 6 7 VDD 2 3 4 5 INT n.c. 1 RES RSTO res_c res_c res_c CS TP res_c Figure 3 SDS res. 3186_22 Pin Configuration of the ISAC-SX TE 19 2003-01-30 ISAC-SX TE PSB 3186 Pin Configuration Table 2 ISAC-SX TE Pin Definitions and Functions Pin No. Symbol MQFP-64 TQFP-64 Input (I) Function Output (O) Open Drain (OD) Host Interface 19 20 21 22 23 24 25 26 A0 A1 A2 A3 A4 A5 A6 A7 I I I I I I I I • Non-Multiplexed Bus Mode: Address Bus Address bus transfers addresses from the microcontroller to the ISAC-SX TE. For indirect address mode only A0 is valid (A1-A7 to be connected to VDD). • Multiplexed Bus Mode: Not used in multiplexed bus mode. In this case A0-A7 should directly be connected to VDD. 9 10 11 12 13 AD0 AD1 AD2 AD3 AD4 I/O I/O I/O I/O I/O • Multiplexed Bus Mode: Address/data bus Transfers addresses from the microcontroller to the ISAC-SX TE and data between the microcontroller and the ISAC-SX TE. • Non-Multiplexed Bus Mode: Data bus Transfers data between the microcontroller and the ISAC-SX TE. 14 AD5 I/O • Multiplexed Bus Mode: Address/data bus Address/data line AD5 if the parallel interface is selected. • Non-Multiplexed Bus Mode: Data bus Data line D5 if the parallel interface is selected. SCL I SCI - Serial Clock Clock signal of the SCI interface if a serial interface is selected. Data Sheet 20 2003-01-30 ISAC-SX TE PSB 3186 Pin Configuration Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP-64 TQFP-64 15 16 39 40 Input (I) Function Output (O) Open Drain (OD) AD6 I/O • Multiplexed Bus Mode: Address/data bus Address/data line AD6 if the parallel interface is selected. • Non-Multiplexed Bus Mode: Data bus Data line D6 if the parallel interface is selected. SDR I SCI - Serial Data Receive Receive data line of the SCI interface if a serial interface is selected. AD7 I/O • Multiplexed Bus Mode: Address/data bus Address/data line AD7 if the parallel interface is selected. • Non-Multiplexed Bus Mode: Data bus Data line D7 if the parallel interface is selected. SDX OD SCI - Serial Data Transmit Transmit data line of the SCI interface if a serial interface is selected. RD I DS I Read Indicates a read access to the registers (Siemens/ Intel bus mode). Data Strobe The rising edge marks the end of a valid read or write operation (Motorola bus mode). WR I R/W I Data Sheet Write Indicates a write access to the registers (Siemens/ Intel bus mode). Read/Write A HIGH identifies a valid host access as a read operation and a LOW identifies a valid host access as a write operation (Motorola bus mode). 21 2003-01-30 ISAC-SX TE PSB 3186 Pin Configuration Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP-64 TQFP-64 Input (I) Function Output (O) Open Drain (OD) 41 ALE I Address Latch Enable A HIGH on this line indicates an address on the external address/data bus (multiplexed bus type only). ALE also selects the microcontroller interface bus type (multiplexed or non multiplexed). 3 CS I Chip Select A low level indicates a microcontroller access to the ISAC-SX TE. 1 INT OD (O) Interrupt Request INT becomes active low (open drain) if the ISAC-SX TE requests an interrupt. The polarity can be reprogrammed to high active with push-pull characteristic. 5 RES I Reset A LOW on this input forces the ISAC-SX TE into a reset state. 38 AMODE I Address Mode Selects between direct (0) and indirect (1) register access mode. IOM-2 Interface 52 FSC O Frame Sync 8-kHz frame synchronization signal. 53 DCL O Data Clock IOM-2 interface data clock signal 1.536 MHz (double bit clock). 49 BCL O Bit Clock IOM-2 interface bit clock signal 768 kHz (single bit clock). 51 DD O (OD) Data Downstream IOM-2 data signal in downstream direction. Data Sheet 22 2003-01-30 ISAC-SX TE PSB 3186 Pin Configuration Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP-64 TQFP-64 Input (I) Function Output (O) Open Drain (OD) 50 DU I Data Upstream IOM-2 data signal in upstream direction. 29 SDS O Serial Data Strobe Programmable strobe signal for time slot and/or D-channel indication on IOM-2. Miscellaneous 43 44 SX1 SX2 O O S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) 47 48 SR1 SR2 I I S-Bus Receiver Input S-Bus Receiver Input 35 XTAL1 I 36 XTAL2 O Crystal 1 Connection for a crystal or used as external clock input. 7.68 MHz clock or crystal required. Crystal 2 Connection for a crystal. Not connected if an external clock is supplied to XTAL1. 58 EAW I External Awake If a falling edge on this input is detected, the ISACSX TE generates an interrupt and, if enabled, a reset pulse. 59 ACL O Activation LED This pin can either function as a programmable output or it can automatically indicate the activated state of the S interface by a logic ’0’. An LED with pre-resistance may directly be connected to ACL. 27 C768 O Clock Output A 7.68 MHz clock is output to support other devices. This clock is not synchronous to the S interface. 6 RSTO OD Reset Output Low active reset output, either from a watchdog timeout or programmed by the host. Data Sheet 23 2003-01-30 ISAC-SX TE PSB 3186 Pin Configuration Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP-64 TQFP-64 Input (I) Function Output (O) Open Drain (OD) 4 TP I Test Pin Must be connected to VSS. 2, 42 n.c. I not connected 28 res. 57 res_l I reserved, connect LOW This pin is reserved and must be connected to VSS. 30, 31, res_c 32, 60, 61, 62, 63, 64 I reserved, connect HIGH or LOW These pins are reserved and must be connected either to VSS or VDD. reserved This pin is reserved and should be left not connected. Power Supply 8, 18, 33, 56 VDD – Digital Power Supply Voltage (3.3 V ± 5 %) 46 VDDA – Analog Power Supply Voltage (3.3 V ± 5 %) – Digital ground (0 V) – Analog ground (0 V) 7, 17, VSS 34, 37, 54, 55 45 VSSA Data Sheet 24 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks 3 Description of Functional Blocks 3.1 General Functions and Device Architecture Figure 4 shows the architecture of the ISAC-SX TE containing the following functions: • S/T-interface transceiver supporting TE mode • Different host interface modes: - Parallel microcontroller interface (Siemens/Intel multiplexed, Siemens/Intel non multiplexed, Motorola modes) - Serial Control Interface (SCI) • Optional indirect register address mode reduces number of registers to be accessed to two locations • One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable FIFO block size (threshold) of 4, 8, 16 or 32 byte (receive) and 16 or 32 byte (transmit). • IOM-2 interface for terminal mode (TE) • One serial data strobe signals (SDS) • IOM handler with controller data access registers (CDA) allows flexible access to IOM timeslots for reading/writing, looping and shifting data • Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots • MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange • C/I-channel handler and TIC bus access controller • D-channel access mechanism • LED connected to pin ACL indicates S-interface activation status automatically or can be controlled by the host • Level detect circuit on the S interface reduces power consumption in power down mode • Two timers for periodic or single interrupts (periods between 1 ms and 14.336 s) • Clock and timing generation • Digital PLL to synchronize the transceiver to the S/T interface • Buffered 7.68 MHz oscillator clock output allows connection of further devices and saves another crystal on the system board • Reset generation (watchdog timer) Data Sheet 25 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks Peripheral Devices IOM-2 Interface IOM-2 Handler S Transceiver D-channel HDLC MON Handler TIC C/I RX/TX FIFOs DPLL Host Interface 8-bit parallel Reset Interrupt -generation SCI OSC 3186_18 Host Figure 4 Data Sheet Functional Block Diagram of the ISAC-SX TE 26 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks 3.2 Microcontroller Interfaces The ISAC-SX TE supports a serial or a parallel microcontroller interface. For applications where no controller is connected to the ISAC-SX TE microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In such applications the ISAC-SX TE operates in the IOM-2 slave mode (refer to the corresponding chapter of the IOM-2 MONITOR handler). This mode is suitable for control functions (e.g. programming registers of the S/T transceiver), but the bandwidth is not sufficient for access to the HDLC controllers. The interface selections are all done by pinstrapping (see Table 3). The selection pins are evaluated when the reset input RES is active. For the pin levels stated in the tables the following is defined: ’High’, ’Low’: dynamic pin; value must be ’High’ or ’Low’ only during reset static pin; pin must statically be strapped to ’High’ or ’Low’ level VDD, VSS: edge: dynamic pin; any transition (’High’ to ’Low’, ’Low’ to ’High’) has occured Table 3 Host Interface Selection PINS WR (R/W) RD (DS) Serial /Parallel PINS Interface CS ALE VDD ’High’ ’High’ Parallel ‘High’ VSS edge VSS VSS Serial ’High’ VSS VSS No Host Interface VSS Interface Type/Mode Motorola Siemens/Intel Non-Mux Siemens/Intel Mux Serial Control Interface(SCI) IOM-2 MONITOR Channel (Slave Mode) Note: For a selected interface mode which doesn’t need all input selection and address pins the unused pins must be tied to VDD or VSS. The interfaces contain all circuitry necessary for the access to programmable registers, status registers and HDLC FIFOs. The mapping of all these registers can be found in Chapter 4. The microcontroller interface also provides an interrupt request at pin INT which is low active by default but can be reprogrammed to high active, a reset input pin RES and a reset output pin RSTO. The interrupt request pin INT becomes active if the ISAC-SX TE requests an interrupt and this can occur at any time. Data Sheet 27 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks 3.2.1 Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the lines SDR and SDX at the rate given by SCL. The falling edge of CS indicates the beginning of a serial access to the registers. The ISAC-SX TE latches incoming data at the rising edge of SCL and shifts out at the falling edge of SCL. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB first. Figure 5 shows the timing of a one byte read/write access via the serial control interface. Write Access CS SCL Header SDR Address Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 '0' write SDX Read Access CS SCL Header SDR Address 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 '1' read Data 7 6 5 4 3 2 1 0 SDX 21150_19 Figure 5 Data Sheet Serial Control Interface Timing 28 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks 3.2.1.1 Programming Sequences The basic structure of a read/write access to the ISAC-SX TE registers via the serial control interface is shown in Figure 6. write sequence: write byte 2 0 header SDR 7 address 0 7 6 read sequence: byte 3 write data 0 7 0 read byte 2 header SDR 7 1 address 0 7 6 0 7 SDX Figure 6 byte 3 0 read data Serial Control Interface Timing A new programming sequence starts with the transfer of a header byte. The header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the ISAC-SX TE. The possible sequences for access to the complete address range 00H-7FH are listed in Table 4 and described after that. Table 4 Header Byte Header Byte Code Sequence 40H/44H 48H/4CH Alternating Read/Write (non-interleaved) Adr-Data-Adr-Data 43H/47H 41H/45H 49H/4DH Sequence Type Alternating Read/Write (interleaved) Read-only/Write-only (constant address) Adr-Data-Data-Data Read and following Write-only (non-interleaved) Read and following Write-only (interleaved) Note: In order to access the address range 00H-7FH bit 2 of the header byte must be set to ’0’ (header bytes 40H, 48H, 43H, 41H, 49H), and for the addresses 80H-FFH bit 2 must be set to ’1’ (header bytes 44H, 4CH, 47H, 45H, 4DH). Data Sheet 29 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks Header 40H: Non-interleaved A-D-A-D Sequences The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one line. Example for a read/write access with header 40H: SDR header wradr wrdata rdadr SDX rdadr rddata wradr wrdata rdata Header 48H: Interleaved A-D-A-D Sequences The interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. This mode allows a time optimized access to the registers by interleaving the data on SDX and SDR (SDR and SDX must not be connected together). Example for a read/write access with header 48H: SDR header wradr wrdata rdadr SDX rdadr wradr wrdata rddata rddata Header 43H: Read-/Write- only A-D-D-D Sequence (Constant Address) This mode can be used for a fast access to the HDLC FIFO data. Any address (rdadr, wradr) in the range 00H-1FH and 6AH/7AH gives access to the current FIFO location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 43H: SDR header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata (wradr) (wradr) (wradr) (wradr) (wradr) (wradr) (wradr) SDX Example for a read access with header 43H: SDR header rdadr SDX rddata rddata rddata rddata rddata rddata rddata (rdadr) Data Sheet (rdadr) (rdadr) 30 (rdadr) (rdadr) (rdadr) (rdadr) 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks Header 41H: Non-interleaved A-D-D-D Sequence This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 41H: SDR header rdadr wradr wrdata wrdata wrdata rdadr (wradr) SDX rddata (wradr) (wradr) rddata Header 49H: Interleaved A-D-D-D Sequence This sequence allows in front of the A-D-D-D write access an interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of the CS line. Example for a read/write access with header 49H: SDR header rdadr rdadr wradr wrdata wrdata wrdata (wradr) SDX 3.2.2 (wradr) (wradr) rddata rddata Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows easy and fast microcontroller access. The parallel interface of the ISAC-SX TE provides three types of mP buses which are selected via pin ALE. The bus operation modes with corresponding pins are listed in Table 5. Table 5 Bus Operation Modes Bus Mode Pin ALE Control Pins (1) Motorola VDD CS, R/W, DS (2) Siemens/Intel non-multiplexed VSS CS, WR, RD (3) Siemens/Intel multiplexed Edge CS, WR, RD, ALE The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is issued. Data Sheet 31 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks Note: If the multiplexed address/data bus type (3) is selected, the unused address pins A0-A7 must be tied to VDD. A read/write access to the ISAC-SX TE registers can be done in multiplexed or nonmultiplexed mode: • In non-multiplexed mode the register address must be applied to the address bus (A0A7) for the data access via the data bus (AD0-AD7). • In multiplexed mode the address on the address/data bus (AD0-AD7) is latched in by ALE before a data read/write access via the same bus is performed. The ISAC-SX TE provides two different ways to address the register contents which is selected with the AMOD pin (’0’ = direct mode, ’1’ = indirect mode). Figure 7 illustrates both register addressing modes. Direct address mode (AMOD = ’0’): The register address to be read or written is directly set in the way described above. Indirect address mode (AMOD = ’1’): Only the LSB of the address is used to select either the address register (A0 = ’0’) or the data register (A0 = ’1’). The microcontroller writes the register address to the ADDRESS register before it reads/writes data from/to the corresponding DATA register. In indirect address mode the ISAC-SX TE evaluates no address line except the least significant address bit. The remaining address lines must not be left open but have to be tied to logical ’1’. Indirect Address Mode MODE2:AMOD=1 Address A0 Direct Address Mode MODE2:AMOD=0 Data AD0-7 Address A0-7 Data AD0-7 8Fh 8Eh Address 1h 0h Data : : 01h 00h DATA ADDRESS 21150_11 Figure 7 Data Sheet Direct/Indirect Register Address Mode 32 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks 3.2.3 Interrupt Structure Special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the device. The structure of the interrupt status registers is shown in Figure 8. MASK ISTA ST ST CIC CIC AUX AUX TRAN TRAN MOS MOS ICD ICD Interrupt STI STOV21 ASTI STOV20 STOV20 STOV11 STOV11 STOV10 STOV10 STI21 STI21 ACK21 STI20 STI20 ACK20 STI11 STI11 ACK11 STI10 STI10 ACK10 RME RME RPF RPF RFO RFO CIX1 CIR0 CIC0 CI1E CIC1 EAW EAW LD WOV WOV RIC RIC TIN2 TIN2 SQC SQC TIN1 LD SQW MASKTR SQW ISTATR XPR XPR XMR XMR MRE XDU MASKD XDU ISTAD MIE MDA MOCR MAB MOSR D-channel Figure 8 MSTI STOV21 AUXM TIN1 AUXI MDR MER 3186_16.vsd Interrupt Status and Mask Registers All six interrupt bits in the ISTA register point at interrupt sources in the D-channel HDLC Controller (ICD), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary interrupts (AUXI). All these interrupt sources are described in the corresponding chapters. After the device has requested an interrupt activating the interrupt pin (INT), the host must read first the device interrupt status register (ISTA) in the associated interrupt service routine. The interrupt pin of the device remains active until all interrupt sources are cleared by reading the corresponding interrupt register. Therefore it is possible that the interrupt pin is still active when the interrupt service routine is finished. Each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the MASK register. For some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the end of the interrupt service routine (writing FFH into the MASK register) and write back the old mask to the MASK register. Data Sheet 33 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks 3.2.4 Reset Generation Figure 9 shows the organization of the reset generation of the device. . RSS1 125µs £ t £ 250µs C/I Code Change (Exchange Awake) ³1 EAW (Subscriber Awake) 125µs £ t £ 250µs '0' (reserved) RSS2,1 '1x' '1' '01' '00' ³1 ' 01 ' RSS2,1 125µs £ t £ 250µs Watchdog Software Reset Register (SRES) Pin RSTO ³1 125µs £ t £ 250µs D, C/I-channel (00H-2FH) Transceiver (30H-3FH) Reset Functional IOM-2 (40H-5BH) Block MON-channel (5CH-5FH) General Config (60H-6FH) Reset MODE1 Register Pin RES Internal Reset of all Registers 3186_21 Figure 9 Reset Generation Reset Source Selection The internal reset sources C/I code change, EAW and Watchdog can be output at the low active reset pin RSTO. The selection of these reset sources can be done with the RSS2,1 bits in the MODE1 register according Table 6. The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the MODE1 register to its reset value. Table 6 Reset Source Selection RSS2 Bit 1 RSS1 Bit 0 C/I Code Change EAW Watchdog Timer 0 0 -- -- -- 0 1 1 0 x x -- 1 1 -- -- x Data Sheet reserved 34 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks • C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates an external reset pulse of 125 µs £ t £ 250 µs. • EAW (Subscriber Awake) A low level on the EAW input starts the oscillator from the power down state and generates a reset pulse of 125 µs £ t £ 250 µs. • Watchdog Timer After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer: 1. 2. WTC1 WTC2 1 0 0 1 If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse of 125 µs is generated. Deactivation of the watchdog timer is only possible with a hardware reset. External Reset Input At the RES input an external reset can be applied forcing the device in the reset state. This external reset signal is additionally fed to the RSTO output. The length of the reset signal is specified in Chapter 5.8. After an external reset from the RES pin all registers of the device are set to its reset values (see register description in Chapter 4). Software Reset Register (SRES) Every main functional block of the device can be reset separately by software setting the corresponding bit in the SRES register. A reset to external devices can also be controlled in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip logic resets this bit again automatically after 4 BCL clock cycles. The address range of the registers which will be reset at each SRES bit is listed in Figure 9. 3.2.5 Timer Modes The ISAC-SX TE provides two timers which can be used for various purposes. Each of them provides two modes (Table 7), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. Data Sheet 35 2003-01-30 ISAC-SX TE PSB 3186 Description of Functional Blocks Table 7 Address 24H 65H ISAC-SX TE Timers Register TIMR1 TIMR2 Modes Period Periodic 64 ... 2048 ms Count Down 64 ms ... 14.336 s Periodic 1 ... 63 ms Count Down 1 ... 63 ms When the programmed period has expired an interrupt is generated and indicated in the auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI (TIN1, TIN2) and each of the interrupt sources can be masked in AUXM. MASK ST CIC AUX TRAN MOS ICD ISTA AUXM EAW WOV TIN2 TIN1 ST CIC AUX TRAN MOS ICD AUXI EAW WOV TIN2 TIN1 Interrupt Figure 10 Timer Interrupt Status Registers Timer 1 The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is generated continuously if CNT= 7 or a single interrupt is generated after timer period T if CNT