PTAC240502FC
Thermally-Enhanced High Power RF LDMOS FET
50 W, 28 V, 2300 – 2400 MHz
Description
The PTAC240502FC is a 47-watt LDMOS FET with an
asymmetrical design intended for use in multi-standard cellular
power amplifier applications in the 2300 to 2400 MHz frequency
band. Features include dual-path design, input matching, high gain
and thermally-enhanced package with earless flanges. Manufactured with Infineon's advanced LDMOS process, this device
provides excellent thermal performance and superior reliability.
Two-carrier WCDMA Drive-up
Gain (dB)
15
•
Input matched
•
Asymmetric Doherty design
- Main: P1dB = 17 W Typ
- Peak: P1dB = 33 W Typ
•
Typical Pulsed CW performance, 2350 MHz,
28 V, 160 µs pulse width, 10% duty cycle,
Doherty Configuration
- Output power at P1dB = 45.7 W
- Efficiency = 46.2%
- Gain = 14.6 dB
•
Typical single-carrier WCDMA performance,
2350 MHz, 28 V, 8.4 dB PAR @ 0.01% CCDF
- Output power = 8.91 W
- Efficiency = 44.2%
- Gain = 14.2 dB
- ACPR = –31 dBc @ 5 MHz
•
Capable of handling 10:1 VSWR @28 V, 50 W
(CW) output power
•
Integrated ESD protection : Human Body Model,
Class 1B (per JESD22-A114)
•
Low thermal resistance
•
Pb-free and RoHS compliant
50
Gain
14
40
13
30
Efficiency
12
Features
60
20
Drain Efficiency (%)
16
VDD = 28 V, IDQ = 120 mA, VGS1 = 2.6 V,
VGS2 = 1.3 V, ƒ = 2400 MHz, 3GPP WCDMA
signal, PAR = 8 dB, 10 MHz carrier spacing,
BW 3.84 MHz
PTAC240502FC
Package H-37248-4
10
11
10
ptac240502fc_g1
26
30
34
38
42
0
46
Output Power (dBm)
RF Characteristics
Two-carrier WCDMA Specifications (tested in Infineon Doherty test fixture)
VDD = 28 V, IDQ = 120 mA, POUT = 10 W avg, VGS2 = 1.3 V, ƒ1 = 2345 MHz, ƒ2 = 2355 MHz, 3GPP signal,
channel bandwidth = 3.84 MHz, peak/average = 8 dB @ 0.01% CCDF
Characteristic
Symbol
Min
Typ
Max
Unit
Linear Gain
Gps
13
14.3
—
dB
Drain Efficiency
D
41
44
—
%
Intermodulation Distortion
IMD
—
–33
–25
dBc
All published data at TCASE = 25°C unless otherwise indicated
ESD: Electrostatic discharge sensitive device—observe handling precautions!
Data Sheet
1 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC
DC Characteristics
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
Drain-Source Breakdown Voltage
VGS = 0 V, IDS = 10 mA
V(BR)DSS
65
—
—
V
Drain Leakage Current
VDS = 28 V, VGS = 0 V
IDSS
—
—
1
µA
VDS = 63 V, VGS = 0 V
IDSS
—
—
10
µA
On-State Resistance (main)
VGS = 10 V, VDS = 0.1 V
RDS(on)
—
0.4
—
On-State Resistance (peak)
VGS = 10 V, VDS = 0.1 V
RDS(on)
—
0.2
—
Operating Gate Voltage (main)
VDS = 28 V, IDQ = 120 mA
VGS
2.6
2.7
2.8
V
Operating Gate Voltage (peak)
VDS = 28 V, IDQ = 0 mA
VGS
1.2
1.3
1.5
V
Gate Leakage Current
VGS = 10 V, VDS = 0 V
IGSS
—
—
1
µA
Maximum Ratings
Parameter
Symbol
Value
Unit
Drain-Source Voltage
VDSS
65
V
Gate-Source Voltage
VGS
–6 to +10
V
Operating Voltage
VDD
0 to +32
V
TJ
225
°C
Storage Temperature Range
TSTG
–65 to +150
°C
Thermal Resistance (TCASE = 60°C, 50 W CW)
RJC
1.29
°C/W
Junction Temperature
Ordering Information
Type and Version
Order Code
Package Description
Shipping
PTAC240502FC V1
PTAC240502FCV1XWSA1
H-37248-4, earless flange
Tray
PTAC240502FC V1 R250
PTAC240502FCV1R250XTMA1
H-37248-4, earless flange
Tape & Reel, 250 pcs
Data Sheet
2 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC
Typical Performance (data taken in a production test fixture)
Two-carrier WCDMA Drive-up
Two-carrier WCDMA Drive-up
IMD Low
IMD Up
ACPR
Efficiency
50
-20
40
-30
30
-40
20
-50
30
34
38
42
-25
-30
2300 IMDL
2300 IMDU
2350 IMDL
2350 IMDU
2400 IMDL
2400 IMDU
-35
-40
-45
10
ptac240502fc_g2
26
-20
46
ptac240502fc_g3
26
30
VDD = 28 V, IDQ = 120 mA
75
20
65
18
55
14
45
13
35
Power Gain (dB)
15
Efficiency (%)
Gain (dB)
Gain
25
2300 MHz
2350 MHz
11
46
IDQ = 120 mA, ƒ = 2400 MHz
17
Efficiency
42
CW Performance
at various VDD
CW Performance
12
38
Output Power (dBm)
Output Power (dBm)
16
34
65
VDD = 24V
VDD = 28V
VDD = 32V
16
55
45
Gain
14
35
12
25
15
10
5
8
Efficiency (%)
-10
VDD = 28 V, IDQ = 120 mA, VGS1 = 2.6 V,
VGS2 = 1.3 V, 3GPP WCDMA signal,
PAR = 8 dB, 10 MHz carrier spacing,
BW 3.84 MHz
-15
60
IMD (dBc)
IMD & ACPR (dBc)
0
Drain Efficiency (%)
VDD = 28 V, IDQ = 120 mA, VGS1 = 2.6 V,
VGS2 = 1.3 V, ƒ = 2400 MHz, 3GPP WCDMA
signal, PAR = 8 dB, 10 MHz carrier spacing,
BW 3.84 MHz
15
Efficiency
2400 MHz
10
ptac240502fc_g4
26
30
34
38
42
46
50
30
34
38
42
46
50
Output Power (dBm)
Output Power (dBm)
Data Sheet
5
ptac240502fc_g5
26
3 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC
Typical Performance (cont.)
Small Signal CW Performance
Gain & Input Return Loss
VDD = 28 V, IDQ = 120 mA
-5
Gain
Power Gain (dB)
16
-10
15
-15
14
-20
13
-25
IRL
Input Return Loss (dB)
17
12
-30
2200 2250 2300 2350 2400 2450 2500 2550
ptac240502fc_g6
Frequency (MHz)
Load Pull Performance
Main Side Load Pull Performance – Pulsed CW signal: 160 µs, 10% duty cycle, 28 V, 114 mA
P1dB
Max Output Power
Max PAE
Freq
[MHz]
Zs
[]
Zl
[]
Gain
[dB]
POUT
[dBm]
POUT
[W]
PAE
[%]
Zl
[]
Gain
[dB]
POUT
[dBm]
POUT
[W]
PAE
[%]
2300
10–j31
9.4–j11.6
20.96
42.89
19.45
53.2
4.7–j8.3
22.8
41.03
12.68
61.5
2350
12.7–j35
9.7–j12.2
20.7
42.83
19.19
52.7
5.1–j9.4
22.4
41.34
13.61
62.1
2400
16.2–j38
9.31–j12.6
20.8
42.65
18.41
52.6
5.2–j10.2
22.2
41.45
13.96
61.3
Peak Side Load Pull Performance – Pulsed CW signal: 160 µs, 10% duty cycle, 28 V, 252 mA
P1dB
Max Output Power
Max PAE
Freq
[MHz]
Zs
[]
Zl
[]
Gain
[dB]
POUT
[dBm]
POUT
[W]
PAE
[%]
Zl
[]
Gain
[dB]
POUT
[dBm]
POUT
[W]
PAE
[%]
2300
5.6–j22
3.0–j7.0
18.2
46.50
44.67
52.1
2.2–j5.8
20.5
45.20
33.11
56.9
2350
6.7–j25
2.9–j7.9
17.4
46.46
44.26
48.5
2.2–j5.9
21.1
44.91
30.97
55.9
2400
9.7–j29
3.3–j7.9
17.9
46.62
45.92
49.6
2.2–j6.2
20.8
45.31
33.96
57.2
Data Sheet
4 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC
Reference Circuit , 2300 – 2400 MHz
VG1
VDD
PTAC240502FC
IN_01_D
RO4350, .020
(194)
C213
C214
RO4350, .020
C105
C212
(194)
C201
C103
R102
R103
C205
C104
RF_IN
C208
C207
U1
R105
RF_OUT
C203
C106
C206
R104
C204
R101
C102
C202
C101
C209
C210
VG2
OUT_01_D
PTAC240502FC
C211
VDD
p t a c 2 4 0 5 0 2 f c _ C D _ 1 1 - 0 5 - 2 0 1 3
Reference circuit assembly diagram (not to scale)
Data Sheet
5 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC
Reference Circuit (cont.)
Reference Circuit Assembly
DUT
PTAC240502FC V1
Test Fixture Part No.
LTA/PTAC240502FC V1
PCB
Rogers 4350, 0.508 mm [0.020”] thick, 2 oz. copper, r = 3.66, ƒ = 2300 – 2400 MHz
Find Gerber files for this test fixture on the Infineon Web site at http://www.infineon.com/rfpower
Components Information
Component
Description
Suggested Manufacturer
P/N
Input
C101, C105
Capacitor, 4.7 µF
Murata Electronics North America
GRM32ER71H475KA88L
C102, C103, C104,
C106
Capacitor, 18 pF
ATC
ATC800A180JT250T
R101, R102
Resistor, 10
Panasonic Electronic Components
ERJ-8GEYJ100V
R103
Resistor, 50
Anaren
060120A15Z50
R104
Resistor, 300
Venkel
CR0603-16W-3010FB
R105
Resistor, 12.1
Venkel
CR0603-16W-12R1FB
U1
Directional coupler
Anaren
X3C25P1-05S
C201, C202, C203,
C204, C206, C208
Capacitor, 18 pF
ATC
ATC800A180JT250T
C205
Capacitor, 0.5 pF
ATC
ATC800A180JT250T
C207, C210, C214
Capacitor, 4.71 µF
Murata Electronics North America
GRM32ER71H475KA88L
C209, C212
Capacitor, 10 µF
Taiyo Yuden
UMK325C7106MM-T
C211, C213
Capacitor, 100 µF
Panasonic Electronic Components
EEE-FP1V101AP
Output
Pinout Diagram (top view)
Peak
Main
D1
D2
G1
G2
S
Pin
D1
D2
G1
G2
S
H-37248-4__do_pd_10-10-2012
Description
Drain device 1 (Peak)
Drain device 2 (Main)
Gate device 1 (Peak)
Gate device 2 (Main)
Source (flange)
Lead connections for PTAC240502FC
Data Sheet
6 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC
Package Outline Specifications
Package H-37248-4
>@
>@
;;
>;@
> 5
@
;5
;
> @
)/$1*(
>@
&/
'
'
/,'
>@
>@
&/
*
*
;
>@
;
>@
63+
>@
>@
>@
>@ $
+BSRBB
>@
6
&/
>@
Diagram Notes—unless otherwise specified:
1. Interpret dimensions and tolerances per ASME Y14.5M-1994.
2. Primary dimensions are mm. Alternate dimensions are inches.
3. All tolerances ± 0.127 [.005] unless specified otherwise.
4. Pins: D1, D2 – drains; G1, G2 – gates; S – source.
5. Lead thickness: 0.10 + 0.076/–0.025 mm [0.004+0.003/–0.001 inch].
6. Gold plating thickness: 1.14 ± 0.38 micron [45 ± 15 microinch].
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/rfpower
Data Sheet
7 of 8
Rev. 02.2, 2014-05-14
PTAC240502FC V1
Revision History
Revision
Date
Data Sheet Type
Page
Subjects (major changes since last revision)
01
2013-07-16
Advance
All
Data Sheet reflects advance specification for product development
02
2013-11-13
Production
All
Data Sheet reflects released product specification
02.1
2013-11-27
Production
1
Revised ESD classification
02.2
2014-05-14
Production
2
Revised juntion temperature in Maximum Ratings table
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
highpowerRF@infineon.com
To request other information, contact us at:
+1 877 465 3667 (1-877-GO-LDMOS) USA
or +1 408 776 0600 International
Edition 2014-05-14
Published by
Infineon Technologies AG
85579 Neubiberg, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the
application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com/rfpower).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in question,
please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device
or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be
implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is
reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet
8 of 8
Rev. 02.2, 2014-05-14
