S25FL064L
6 4 M b ( 8 M B ) F L- L f l a s h
SPI multi-I/O, 3.0 V
General description
The FL-L family devices are flash non-volatile memory products using:
• Floating gate technology
• 65-nm process lithography
The FL-L family connects to a host system via a serial peripheral interface (SPI). Traditional SPI single bit serial
input and output (single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide
Quad I/O (QIO), and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR)
Read commands for QIO and QPI that transfer address and read data on both edges of the clock.
The architecture features a page programming buffer that allows up to 256 bytes to be programmed in one
operation and provides individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read
transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while
reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a
variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space,
signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial
flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing
re-programmable data.
Features
• Serial peripheral interface (SPI) with multi-I/O
- Clock polarity and phase modes 0 and 3
- Double data rate (DDR) option
- Quad peripheral interface (QPI) option
- Extended addressing: 24- or 32- bit address options
- Serial command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S, and S25FS-S SPI
families
- Multi I/O command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families
• Read
- Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR Quad I/O
- Modes: Burst wrap, Continuous (XIP), QPI
- Serial flash discoverable parameters (SFDP) for configuration information
• Program architecture
- 256-bytes page programming buffer
- Program suspend and resume
• Erase architecture
- Uniform 4 KB sector erase
- Uniform 32 KB half block erase
- Uniform 64 KB block erase
- Chip erase
- Erase suspend and resume
• 100,000 program-erase cycles, minimum
• 20 year data retention, minimum
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Features
• Security features
- Status and Configuration Register protection
- Four Security Regions of 256-bytes each outside the main flash array
- Legacy block protection: Block range
- Individual and region protection
• Individual block lock: Volatile individual sector/block
• Pointer region: Non-volatile sector/block range
• Power supply lock-down, password, or permanent protection of Security Regions 2 and 3 and pointer region
• Technology
- 65-nm floating gate technology
• Single supply voltage with CMOS I/O
- 2.7 V to 3.6 V
• Temperature range / grade
- Industrial (–40°C to +85°C)
- Industrial Plus (–40°C to +105°C)
- Automotive, AEC-Q100 grade 3 (–40°C to +85°C)
- Automotive, AEC-Q100 grade 2 (–40°C to +105°C)
- Automotive, AEC-Q100 grade 1 (–40°C to +125°C)
• Packages (all Pb-free)
- 8-lead SOIC 208 mil (SOC008)
- 16-lead SOIC 300 mil (SO3016)
- USON 4 × 4 mm (UNF008)
- WSON 5 × 6 mm (WND008)
- BGA-24 6 × 8 mm
• 5 × 5 ball (FAB024) footprint
• 4 × 6 ball (FAC024) footprint
- Known good die (KGD) and known tested die
Datasheet
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002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Performance summary
Performance summar y
Table 1
Maximum read rates SDR
Command
Clock rate (MHz)
MBps
Read
50
6.25
Fast Read
108
13.5
Dual Read
108
27
Quad Read
108
54
Clock rate (MHz)
MBps
54
54
Table 2
Maximum read rates DDR
Command
DDR Quad Read
Table 3
Typical program and erase rates
Operation
KBps
Page programming
569
4 KB sector erase
61
32 KB half block erase
106
64 KB block erase
142
Table 4
Typical current consumption
Operation
Typical current
Unit
Read 50 MHz
10
mA
Fast read 5MHz
10
mA
Fast read 10 MHz
10
mA
Fast read 20 MHz
10
mA
Fast read 50 MHz
15
mA
Fast read 108 MHz
20
mA
Quad I/O / QPI read 108 MHz
20
mA
Quad I/O / QPI DDR read 33 MHz
15
mA
Quad I/O / QPI DDR read 54 MHz
17
mA
Program
17
mA
Erase
17
mA
Standby SPI
20
µA
Standby QPI
35
µA
Deep power down
2
µA
Datasheet
3
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Performance summary ......................................................................................................................3
Table of contents ...............................................................................................................................4
1 Product overview ...........................................................................................................................6
1.1 Migration notes .......................................................................................................................................................6
2 Connection diagrams ......................................................................................................................8
2.1 SOIC 16-lead............................................................................................................................................................8
2.2 8- Connector packages ...........................................................................................................................................8
2.3 BGA ball footprint ...................................................................................................................................................9
3 Signal descriptions .......................................................................................................................10
3.1 Serial peripheral interface with multiple input / output (SPI-MIO)....................................................................10
3.2 Input/output summary.........................................................................................................................................10
3.3 Multiple input / output (MIO) ...............................................................................................................................11
3.4 Serial Clock (SCK)..................................................................................................................................................11
3.5 Chip Select (CS#)...................................................................................................................................................11
3.6 Serial Input (SI) / IO0.............................................................................................................................................11
3.7 Serial Output (SO) / IO1 ........................................................................................................................................12
3.8 Write Protect (WP#) / IO2......................................................................................................................................12
3.9 IO3 / RESET#..........................................................................................................................................................12
3.10 RESET#.................................................................................................................................................................13
3.11 Voltage Supply (VCC) ..........................................................................................................................................13
3.12 Supply and Signal Ground (VSS) .........................................................................................................................13
3.13 Not Connected (NC) ............................................................................................................................................13
3.14 Reserved for Future Use (RFU) ...........................................................................................................................13
3.15 Do Not Use (DNU)................................................................................................................................................13
4 Block diagram ..............................................................................................................................14
4.1 System block diagrams ........................................................................................................................................14
5 Signal protocols............................................................................................................................16
5.1 SPI clock modes ....................................................................................................................................................16
5.2 Command protocol...............................................................................................................................................17
5.3 Interface states .....................................................................................................................................................22
5.4 Data protection .....................................................................................................................................................26
6 Address space maps ......................................................................................................................27
6.1 Overview................................................................................................................................................................27
6.2 Flash memory array ..............................................................................................................................................27
6.3 ID address space ...................................................................................................................................................28
6.4 JEDEC JESD216 serial flash discoverable parameters (SFDP) space .................................................................28
6.5 Security Regions address space...........................................................................................................................28
6.6 Registers ................................................................................................................................................................29
7 Data protection ............................................................................................................................49
7.1 Security Regions ...................................................................................................................................................49
7.2 Deep Power Down.................................................................................................................................................49
7.3 Write Enable commands ......................................................................................................................................50
7.4 Write Protect signal...............................................................................................................................................50
7.5 Status Register Protect (SRP1, SRP0) ..................................................................................................................50
7.6 Array protection ....................................................................................................................................................52
7.7 Individual and region protection .........................................................................................................................57
8 Commands ...................................................................................................................................62
8.1 Command set summary .......................................................................................................................................62
8.2 Identification commands .....................................................................................................................................69
Datasheet
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Table of contents
8.3 Register Access commands ..................................................................................................................................73
8.4 Read Memory Array commands ...........................................................................................................................90
8.5 Program Flash Array commands........................................................................................................................100
8.6 Erase Flash Array commands .............................................................................................................................102
8.7 Security Regions Array commands ....................................................................................................................110
8.8 Individual Block Lock commands ......................................................................................................................112
8.9 Pointer Region command...................................................................................................................................117
8.10 Individual and Region Protection (IRP) commands........................................................................................118
8.11 Reset commands ..............................................................................................................................................125
9 Data integrity ............................................................................................................................. 129
9.1 Erase endurance .................................................................................................................................................129
9.2 Data retention .....................................................................................................................................................129
10 Software interface reference ..................................................................................................... 130
10.1 JEDEC JESD216B serial flash discoverable parameters .................................................................................130
10.2 Device ID address map .....................................................................................................................................141
10.3 Initial delivery state ..........................................................................................................................................141
11 Electrical specifications............................................................................................................. 142
11.1 Absolute maximum ratings[59]......................................................................................................................................................... 142
11.2 Latchup characteristics ....................................................................................................................................142
11.3 Thermal resistance ...........................................................................................................................................142
11.4 Operating ranges ..............................................................................................................................................143
11.5 Power-up and power-down..............................................................................................................................144
11.6 DC characteristics .............................................................................................................................................146
12 Timing specifications ................................................................................................................ 150
12.1 Key to switching waveforms.............................................................................................................................150
12.2 AC test conditions .............................................................................................................................................150
12.3 Reset ..................................................................................................................................................................151
12.4 SDR AC characteristics......................................................................................................................................154
12.5 DDR AC characteristics .....................................................................................................................................157
12.6 Embedded algorithm performance tables ......................................................................................................160
13 Ordering information ................................................................................................................ 161
13.1 Ordering part number.......................................................................................................................................161
13.2 Valid combinations — Standard.......................................................................................................................162
13.3 Valid combinations — Automotive grade / AEC-Q100.....................................................................................162
14 Physical diagrams ..................................................................................................................... 163
Revision history ............................................................................................................................ 169
Datasheet
5
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Product overview
1
Product overview
1.1
Migration notes
1.1.1
Features comparison
The FL064L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P
families.
Table 1
SPI families comparison
Parameter
FL-L
FL-L
FL-S
FL1-K
FL-P
65-nm
65-nm
65-nm
90-nm
90-nm
Architecture
Floating gate
Floating gate
MIRRORBIT™
Eclipse
Floating gate
MIRRORBIT™
Release date
In production
In production
In production
In production
In production
64 Mb
256 Mb
128 Mb–1 Gb
16 Mb–64 Mb
32 Mb–256 Mb
x1, x2, x4
x1, x2, x4
x1, x2, x4
x1, x2, x4
x1, x2, x4
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–3.6 V /
1.65 V–3.6 V VIO
2.7 V–3.6 V
2.7 V–3.6 V
6 MBps (50 MHz)
6 MBps
(50 MHz)
5 MBps
(40 MHz)
Technology node
Density
Bus width
Supply voltage
Normal Read
Speed
6 MBps (50 MHz) 6 MBps (50 MHz)
Fast Read Speed
13 MBps
(108 MHz)
16.5 MBps
(133 MHz)
17 MBps (133 MHz)
13 MBps
(108 MHz)
13 MBps
(104 MHz)
Dual Read Speed
26 MBps
(108 MHz)
33 MBps
(133 MHz)
26 MBps (104 MHz)
26 MBps
(108 MHz)
20 MBps
(80 MHz)
Quad Read Speed
52 MBps
(108 MHz)
66 MBps
(133 MHz)
52 MBps (104 MHz)
52 MBps
(108 MHz)
40 MBps
(80 MHz)
Quad Read Speed
(DDR)
54 MBps
(54 MHz)
66 MBps
(66 MHz)
80 MBps (80 MHz)
–
–
Program buffer size
256 B
256B
256 B / 512 B
256 B
256 B
Erase sector/block
size
4 KB / 32 KB /
64 KB
4 KB / 32 KB /
64 KB
64 KB / 256 KB
4 KB / 64 KB
64 KB / 256 KB
Parameter sector
size
–
–
4 KB (option)
–
4 KB
61 KB/s (4 KB) 80 KB/s (4 KB)
Sector / block erase
106 KB/s (32 KB) 168 KB/s (32 KB)
rate (typ.)
142 KB/s (64 KB) 237 KB/s (64 KB)
500 KB/s
80 KB/s (4 KB)
128 KB/s (64 KB)
130 KB/s
Page programming
569 KB/s (256 B) 854 KB/s (256 B)
rate (typ.)
1.2 MBps (256 B)
1.5 MBps (512 B)
365 KB/s
170 KB/s
Security Region /
OTP
1024 B
1024 B
1024 B
768 B (3 × 256 B)
506 B
Individual and
region protection
or advanced sector
protection
Yes
Yes
Yes
Yes
No
Erase
suspend/resume
Yes
Yes
Yes
Yes
No
Note
1. Refer to individual datasheets for further details.
Datasheet
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002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Product overview
Table 1
SPI families comparison (continued)
Parameter
Program
suspend/resume
Operating
temperature
FL-L
FL-L
FL-S
FL1-K
FL-P
Yes
Yes
Yes
Yes
No
–40°C to +85°C –40°C to +85°C
–40°C to +105°C –40°C to +105°C
–40°C to +125°C –40°C to +125°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
–40°C to +125°C
Note
1. Refer to individual datasheets for further details.
1.1.2
Known differences from prior generations
1.1.2.1
Error reporting
FL-K, FL1-K and FL-P memories either do not have error status bits or do not set them if program or erase is
attempted on a protected sector. This product family does have error reporting status bits for program and erase
operations. These can be set when there is an internal failure to program or erase, or when there is an attempt
to program or erase a protected sector. In these cases the program or erase operation did not complete as
requested by the command. The P_ERR or E_ERR bits and the WIP bit will be set to and remain 1 in SR1V. The
Clear Status Register command must be sent to clear the errors and return the device to STANDBY state.
1.1.2.2
Status Register Protect 1 bit
The Configuration Register 1 SRP1 bit CR1V[0], locks the state of the Legacy Block Protection bits (SR1NV[5:2] &
SR1V[5:2]), CMP_NV (CR1NV[6]) and TBPROT_NV bit (SR1NV[6]), as freeze did in prior generations. In the FS-S and
FL-S families the Freeze bit also locks the state of the Configuration Register 1 BPNV_O bit (CR1NV[3]), and the
secure silicon region (OTP) area.
1.1.2.3
WRR Single Register Write
In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status
Register 1 and clear some bits in Configuration Register 1, including the Quad mode bit. This could result in
unintended exit from Quad mode. This product family only updates Status Register 1 when a single data byte is
provided. The Configuration Register 1 is not modified in this case.
1.1.2.4
Other legacy commands not supported
• Autoboot related commands
• Bank Address related commands
• Hold# replaced by the Reset#
1.1.2.5
New features
This product family introduces new features to Infineon SPI category memories:
• Security Regions password protection
• IRP individual region protection
Datasheet
7
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Connection diagrams
2
Connection diagrams
2.1
SOIC 16-lead
IO3 / RESET#
1
16
SCK
VCC
2
15
SI / IO0
RESET#
3
14
RFU
NC
4
13
DNU
NC
5
12
DNU
RFU
6
11
DNU
CS#
7
10
VSS
SO / IO1
8
9
SOIC 16
Figure 1
16-lead SOIC package (SO3016), top view
2.2
8- Connector packages
Figure 2
Figure 3
Datasheet
WP# / IO2
8
VCC
7
IO3 / RESET#
3
6
SCK
4
5
SI / IO0
CS#
1
SO / IO1
2
WP# / IO2
VSS
SOIC 8
8-pin plastic small outline package (SOIC8)
CS#
1
8
VCC
SO / IO1
2
7
IO3 / RESET#
WP# / IO2
3
6
SCK
VSS
4
5
SI / IO0
USON
8-connector package (USON 4 x 4), top view
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002-12878 Rev. *H
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Connection diagrams
CS#
1
8
VCC
SO / IO1
2
7
IO3 / RESET#
WP# / IO2
3
6
SCK
VSS
4
5
SI / IO0
WSON
View
Figure 4
8-connector package (WSON 5 x 6), top view[2]
2.3
BGA ball footprint
1
2
3
4
5
NC
NC
RESET#
NC
DNU
SCK
VSS
VCC
NC
DNU
CS#
RFU
WP#/IO2
NC
DNU
SO/IO1
SI/IO0
NC
NC
NC
A
B
C
D
IO3/ RESET# NC
E
Figure 5
RFU
NC
24-ball BGA, 5 x 5 ball footprint (FAB024), top view[3, 4]
1
2
3
4
NC
NC
NC
RESET#
DNU
SCK
VSS
VCC
DNU
CS#
RFU
WP#/IO2
DNU
SO/IO1
NC
NC
NC
RFU
NC
NC
NC
NC
A
B
C
D
SI/IO0 IO3/RESET#
E
F
Figure 6
24-ball BGA, 4 x 6 ball footprint (FAC024), top view[4]
Notes
2. The RESET# input has an internal pull-up and may be left unconnected in the system if Quad mode and
hardware reset are not in use.
3. Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use
either package.
4. The RESET# input has an internal pull-up and may be left unconnected in the system if Quad mode and
hardware reset are not in use.
Datasheet
9
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal descriptions
3
Signal descriptions
3.1
Serial peripheral interface with multiple input / output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that
require a large number of signal connections and larger package size. The large number of connections increase
power consumption due to so many signals switching and the larger package increases cost.
The S25FL-L family reduces the number of signals for connection to the host system by serially transferring all
control, address, and data information over six signals. This reduces the cost of the memory package, reduces
signal switching power, and either reduces the host connection count or frees host connectors for use in
providing other features.
The S25FL-L family uses the industry standard single bit SPI and also supports optional extension commands for
two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called SPI multi-I/O or
SPI-MIO.
3.2
Input/output summary
Table 2
Signal list
Signal
name
Type
RESET#
Input
Hardware Reset. Low = Device resets and returns to STANDBY state, ready to
receive a command. The signal has an internal pull-up resistor and may be left
unconnected in the host system if not used.
SCK
Input
Serial Clock
CS#
Input
Chip Select
SI / IO0
I/O
Serial Input for Single Bit Data commands or IO0 for Dual or Quad commands.
SO / IO1
I/O
Serial Output for Single Bit Data commands. IO1 for Dual or Quad commands.
WP# / IO2
I/O
Write Protect when not in Quad mode (CR1V[1] = 0 and SR1NV[7] = 1).
IO2 when in Quad mode (CR1V[1] = 1).
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands or write protection. If write protection is
enabled by SR1NV[7] = 1 and CR1V[1] = 0, the host system is required to drive WP#
HIGH or LOW during a WRR or WRAR command.
IO3 /
RESET#
I/O
IO3 in Quad I/O mode, when Configuration Register 1 QUAD bit, CR1V[1] = 1, or in
QPI mode, when Configuration Register 2 QPI bit, CR2V[3] = 1 and CS# is LOW.
RESET# when enabled by CR2V[7] = 1 and not in Quad I/O mode, CR1V[1] = 0, or when
enabled in Quad mode, CR1V[1] = 1 and CS# is HIGH.
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands or RESET#.
VCC
Supply
Power Supply
VSS
Supply
Ground
NC
Unused
Not Connected. No device internal signal is connected to the package connector
nor is there any future plan to use the connector for a signal. The connection may
safely be used for routing space for a signal on a printed circuit board (PCB).
However, any signal connected to an NC must not have voltage levels higher than
VCC.
Description
Note
5. Inputs with internal pull-ups or pull-downs drive less than 2 A. Only during power-up is the current larger
at 150 A for 4 s. Resistance of pull-ups or pull-down resistors with the typical process at Vcc = 3.3 V at –40°C
is ~4.5 M and at 90°C is ~6.6 M.
Datasheet
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002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal descriptions
Table 2
Signal list (continued)
Signal
name
Type
Description
RFU
Reserved
Reserved for Future Use. No device internal signal is currently connected to the
package connector but there is potential future use of the connector for a signal. It
is recommended to not use RFU connectors for PCB routing channels so that the
PCB may take advantage of future enhanced features in compatible footprint
devices.
DNU
Reserved
Do Not Use. A device internal signal may be connected to the package connector.
The connection may be used by Infineon for test or other purposes and is not
intended for connection to any host system signal. Any DNU signal related function
will be inactive when the signal is at VIL. The signal has an internal pull-down resistor
and may be left unconnected in the host system or may be tied to VSS. Do not use
these connections for PCB signal routing channels. Do not connect any host system
signal to this connection.
Note
5. Inputs with internal pull-ups or pull-downs drive less than 2 A. Only during power-up is the current larger
at 150 A for 4 s. Resistance of pull-ups or pull-down resistors with the typical process at Vcc = 3.3 V at –40°C
is ~4.5 M and at 90°C is ~6.6 M.
3.3
Multiple input / output (MIO)
Traditional SPI single bit wide commands (single or SIO) send information from the host to the memory only on
the serial input (SI) signal. Data may be sent back to the host serially on the serial output (SO) signal.
Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal. Address
or data is sent from the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,
and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1,
IO2, and IO3.
QPI mode transfers all instructions, addresses, and data from the host to the memory as four bit (nibble) groups
on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2, and IO3.
3.4
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR
commands.
3.5
Chip Select (CS#)
The Chip Select signal indicates when a command is transferring information to or from the device and the other
signals are relevant for the memory device.
When the CS# signal is at the logic HIGH state, the device is not selected and all input signals are ignored and all
output signals are high impedance. The device will be in the Standby Power mode, unless an internal embedded
operation is in progress. An embedded operation is indicated by the Status Register 1 Write-In-Progress bit
(SR1V[0]) set to 1, until the operation is completed. Some example embedded operations are: program, erase, or
Write Registers (WRR) operations.
Driving the CS# input to the logic LOW state enables the device, placing it in the Active Power mode. After
power-up, a falling edge on CS# is required prior to the start of any command.
3.6
Serial Input (SI) / IO0
This input signals used to transfer data serially into the device. It receives instructions, addresses, and data to be
programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 - an input and
output during dual and quad commands for receiving instructions, addresses, and data to be programmed
(values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK,
in SDR commands, and on every edge of SCK, in DDR commands).
Datasheet
11
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal descriptions
3.7
Serial Output (SO) / IO1
This output signals used to transfer data serially out of the device. Data is shifted out on the falling edge of the
serial SCK clock signal. SO becomes IO1 - an input and output during Dual and Quad commands for receiving
addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting
out data (on the falling edge of SCK in SDR commands, and on every edge of SCK, in DDR commands).
3.8
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), when the Status Register Protect 0 (SRP0_NV) or (SRP0) bit of Status Register 1
(SR1NV[7]) or (SR1V[7]) is set to a 1, it is not possible to write to Status Registers, Configuration Registers or DLR
registers. In this situation, the command selecting SR1NV, SR1V, CR1NV,CR1V, CR2NV, CR2V, CR3NV, DLRNV and
DLRV is ignored, and no error is set.
This prevents any alteration of the legacy block protection settings. As a consequence, all the data bytes in the
memory area that are protected by the legacy block protection feature are also hardware protected against data
modification if WP# is Low during commands changing Status Registers, Configuration Registers or DLR registers,
with SRP0_NV set to 1. Similarly, the Security Region lock bits (LB3–LB0) are protected against programming.
The WP# function is not available when the Quad mode is enabled (CR1V[1] = 1) or QPI mode is enabled
(CR2V[3] = 1). The WP# function is replaced by IO2 for input and output during Quad mode or QPI mode is enabled
(CR2V[3] = 1) for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK
signal) as well as shifting out data on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR
commands).
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host
system if not used for Quad mode or QPI mode or protection.
3.9
IO3 / RESET#
IO3 is used for input and output during Quad mode (CR1V[1] = 1) or QPI mode is enabled (CR2V[3] = 1) for receiving
addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting
out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
The IO3 / RESET# input may also be used to initiate the hardware reset function when the IO3 / RESET# feature
is enabled by writing Configuration Register 2 volatile or non-volatile bit 7 (CR2V[7] = 1)or (CR2NV[7] = 1). The
input is only treated as RESET# when the device is not in Quad modes (114,144,444), CR1V[1] = 0, or when CS# is
HIGH. When Quad modes are in use, CR1V[1] = 1or QPI mode is enabled (CR2V[3] = 1), and the device is selected
with CS# LOW, the IO3 / RESET# is used only as IO3 for information transfer. When CS# is HIGH, the IO3 / RESET#
is not in use for information transfer and is used as the reset input. By conditioning the reset operation on CS#
HIGH during Quad modes (114,144,444), the reset function remains available during Quad modes (114, 144, 444).
When the system enters a reset condition, the CS# signal must be driven HIGH as part of the reset process and
the IO3 / RESET# signal is driven LOW. When CS# goes HIGH, the IO3 / RESET# input transitions from being IO3 to
being the reset input. The reset condition is then detected when CS# remains HIGH and the IO3 / RESET# signal
remains LOW for tRP. If a reset is not intended, the system is required to actively drive IO3 / RESET# to HIGH along
with CS# being driven HIGH at the end of a transfer of data to the memory. Following transfers of data to the host
system, the memory will drive IO3 HIGH during tCS. This will ensure that IO3 / RESET# is not left floating or being
pulled slowly to high by the internal or an external passive pull-up. Thus, an unintended reset is not triggered by
the IO3 / RESET# not being recognized as high before the end of tRP.
The IO3 / RESET# input reset feature is disabled when (CR2V[7] = 0).
The IO3 / RESET# input has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad mode or the reset function. The internal pull-up will hold IO3 / RESET# HIGH after the host system has
actively driven the signal high and then stops driving the signal.
Note that IO3 / RESET# input cannot be shared by more than one SPI-MIO memory if any of them are operating
in Quad I/O mode as IO3 being driven to or from one selected memory may look like a reset signal to a second
non-selected memory sharing the same IO3 / RESET# signal.
Datasheet
12
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal descriptions
3.10
RESET#
The RESET# input provides a hardware method of resetting the device to STANDBY state, ready for receiving a
command. When RESET# is driven to logic LOW (VIL) for at least a period of tRP, the device starts the hardware
reset process.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time.
RESET# may be asserted LOW at any time. To ensure data integrity any operation that was interrupted by a
hardware reset should be reinitiated once the device is ready to accept a command sequence.
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used. The internal
pull-up will hold Reset HIGH after the host system has actively driven the signal HIGH and then stops driving the
signal.
The RESET# input is not available on all packages options. When not available the RESET# input of the device is
tied to the inactive state.
3.11
Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions
including read, program, and erase.
3.12
Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output
drivers.
3.13
Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector
for a signal. The connection may safely be used for routing space for a signal on a printed circuit board (PCB).
3.14
Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but there is potential future use of the
connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take
advantage of future enhanced features in compatible footprint devices.
3.15
Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Infineon
for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related
function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing
channels. Do not connect any host system signal to these connections.
Datasheet
13
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Block diagram
4
Block diagram
X decoders
CS#
SCK
SI/IO0
SO/IO1
Y decoders
I/O
WP#/IO2
Data latch
Control
logic
RESET#/IO3
Data path
RESET#
4.1
System block diagrams
RESET#
WP#
RESET#
WP#
SI
SO
SCK
SI
SO
SCK
CS2#
CS1#
CS#
CS#
SPI
bus master
Figure 7
SPI flash
RESET#
WP#
IO1
IO0
SCK
IO1
IO0
SCK
CS2#
CS1#
SPI
bus master
Datasheet
SPI flash
Bus master and memory devices on the SPI bus - Single bit data path
RESET#
WP#
Figure 8
Memory array
CS#
CS#
SPI flash
SPI flash
Bus master and memory devices on the SPI bus - Dual bit data path
14
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Block diagram
RESET#
IO3
IO2
IO1
IO0
SCK
RESET#
IO3
IO2
IO1
IO0
SCK
CS2#
CS1#
CS#
CS#
SPI
bus master
Figure 9
SPI flash
Bus master and memory devices on the SPI bus - Quad bit data path - separate RESET#
IO3 / RESET#
IO2
IO1
IO0
SCK
CS#
SPI
bus master
Figure 10
Datasheet
SPI flash
IO3 / RESET#
IO2
IO1
IO0
SCK
CS#
SPI flash
Bus master and memory devices on the SPI bus - Quad bit data path - I/O3 / RESET#
15
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
5
Signal protocols
5.1
SPI clock modes
5.1.1
Single data rate (SDR)
The FL-L family can be driven by an embedded micro-controller (bus master) in either of the two following
clocking modes.
• Mode 0 with clock polarity (CPOL) = 0 and, clock phase (CPHA) = 0
• Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the
output data is always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in Standby mode and not
transferring any data.
• SCK will stay at logic LOW state with CPOL = 0, CPHA = 0
• SCK will stay at logic HIGH state with CPOL = 1, CPHA = 1
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
SI_IO0
MSb
SO_IO1
Figure 11
MSb
SPI SDR modes supported
Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by
showing SCK as both HIGH and LOW at the fall of CS#. In some cases, a timing diagram may show only Mode 0
with SCK LOW at the fall of CS#. In such a case, Mode 3 timing simply means clock is HIGH at the fall of CS# so no
SCK rising edge set up or hold time to the falling edge of CS# is needed for Mode 3.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0 the
beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of
SCK because SCK is already LOW at the beginning of a command.
Datasheet
16
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
5.1.2
Double data rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always
latched on the rising edge of clock, the same as in SDR commands. However, the address and input data that
follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is latched on
the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first bit of output
data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the
next falling edge of SCK. In Mode 0 the beginning of the first SCK cycle in a command is measured from the falling
edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a command.
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
Transfer_Phase
IO0
Instruction
Inst. 7
Address
Dummy / DLP
A28 A24
A0 M4 M0
DLP.
DLP.
D0 D1
IO1
A29 A25
A1 M5 M1
DLP.
DLP.
D0 D1
IO2
A30 A26
A2 M6 M2
DLP.
DLP.
D0 D1
IO3
A31 A27
A3 M7 M3
DLP.
DLP.
D0 D1
Figure 12
SPI DDR modes supported
5.2
Command protocol
Inst. 0
Mode
All communication between the host system and FL-L family memory devices is in the form of units called
commands. See “Commands” on page 62 for definition and details for all commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to
be performed. Commands may also have an address, instruction modifier, latency period, data transfer to the
memory, or data transfer from the memory. All instruction, address, and data information is transferred
sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the
transfer width of three command phases:
• instruction;
• address and instruction modifier (Continuous Read mode bits);
• data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI
signal. Data may be sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol
for single bit width instruction, single bit width address and modifier, single bit data.
Dual-output or quad-output commands provide an address sent from the host as serial on SI (IO0) then followed
by dummy cycles. Data is returned to the host as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1,
IO2, and IO3. This is referenced as 1-1-2 for Dual-O and 1-1-4 for Quad-O command protocols.
Dual or quad input / output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or,
four bit (nibble) groups on IO0, IO1, IO2, and IO3 then followed by dummy cycles. Data is returned to the host
similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-2-2
for dual I/O and 1-4-4 for quad I/O command protocols.
The FL-L family also supports a QPI mode in which all information is transferred in 4 bit width, including the
instruction, address, modifier, and data. This is referenced as a 4-4-4 command protocol.
Datasheet
17
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
Commands are structured as follows:
• Each command begins with CS# going LOW and ends with CS# returning HIGH. The memory device is selected
by the host driving the Chip Select (CS#) signal LOW throughout a command.
• The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
• Each command begins with an eight bit (byte) instruction. The instruction selects the type of information
transfer or device operation to be performed. The instruction transfers occur on SCK rising edges. However,
some Read commands are modified by a prior Read command, such that the instruction is implied from the
earlier command. This is called Continuous Read mode. When the device is in Continuous Read mode, the
instruction bits are not transmitted at the beginning of the command because the instruction is the same as
the Read command that initiated the Continuous Read mode. In Continuous Read mode the command will
begin with the read address. Thus, Continuous Read mode removes eight instruction bits from each Read
command in a series of same type Read commands.
• The instruction may be stand alone or may be followed by address bits to select a location within one of several
address spaces in the device. The instruction determines the address space used. The address may be either a
24-bit or a 32-bit, byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands,
or on every SCK edge, in DDR commands.
• In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction sent.
Following transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be
done in two bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per
(quad) transfer on the IO0–IO3 signals. Within the dual or quad groups the least significant bit is on IO0. More
significant bits are placed in significance order on each higher numbered IO signal. Single bits or parallel bit
groups are transferred in most to least significant bit order.
• In QPI mode, the width of all transfers is a 4 bit wide (Quad) transfer on the IO0–IO3 signals.
• Dual and quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following
the address, to indicate whether the next command will be of the same type with an implied, rather than an
explicit, instruction. These mode bits initiate or end the Continuous Read mode. In Continuous Read mode, the
next command thus does not provide an instruction byte, only a new address and mode bits. This reduces the
time needed to send each command when the same command type is repeated in a sequence of commands.
The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency
period before read data is returned to the host.
• Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
• SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles
(also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from
the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits are considered
transferred to the host on the following SCK rising edge. Each following transfer occurs on the next SCK rising
edge, in SDR commands, or on every SCK edge, in DDR commands.
• If the command returns read data to the host, the device continues sending data transfers until the host takes
the CS# signal HIGH. The CS# signal can be driven HIGH after any transfer in the read data sequence. This will
terminate the command.
• At the end of a command that does not return data, the host drives the CS# input HIGH. The CS# signal must go
HIGH after the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is,
the CS# signal must be driven HIGH when the number of bits after the CS# signal was driven LOW is an exact
multiple of eight bits. If the CS# signal does not go HIGH exactly at the eight bit boundary of the instruction or
write data, the command is rejected and not executed.
• All instruction, address, and mode bits are shifted into the device with the most significant bits (MSb) first. The
data bits are shifted in and out of the device MSb first. All data is transferred in byte units with the lowest address
byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address
increments.
• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)
are ignored. The embedded operation will continue to execute without any affect. A very limited set of
commands are accepted during an embedded operation. These are discussed in the individual command
descriptions.
• Depending on the command, the time for execution varies. A command to read status information from an
executing command is available to determine when the command completes execution and whether the
command was successful.
Datasheet
18
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
5.2.1
Command sequence examples
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1-IO3
Phase
Figure 13
Instruction
Standalone Instruction command
CS#
SCLK
SO_IO1-IO3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Figure 14
Instruction
Input Data
Single Bit Wide Input command
CS#
SCLK
SI
7
6
5
4
3
2
1
SO
7
Phase
Figure 15
0
6
5
Instruction
4
3
2
1
0
7
6
5
Data 1
4
3
2
1
0
Data 2
Single Bit Wide Output command without latency
CS#
SCLK
SI
7
6
5
4
3
2
1
0 31
1
0
SO
7
Phase
Figure 16
Instruction
Address
Dummy Cycles
6
5
4
3
2
1
0
Data 1
Single Bit Wide I/O command with latency
CS#
SCK
IO0
7
6
5
4
3
2
1
0
31
1
0
6
IO1
Phase
Figure 17
Datasheet
7
Instruction
Address
Dummy Cycles
4
2
0
6
5
3
1
7
Data 1
4
2
0
5
3
1
Data 2
Dual Output Read command
19
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
CS#
SCK
IO0
7
6
5
4
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
Phase
Figure 18
3
2
1
0
31
1
Instruction
0
Address
Dummy
D1
D2
D3
D4
D5
Quad Output Read command
CS#
SCK
IO0
7
6
5
4
3
2
1
0 30
2
0
6
4
2
0
6
4
2
0
6
4
2
0
31
3
1
7
5
3
1
7
5
3
1
7
5
3
1
IO1
Phase
Figure 19
Instruction
Address
Mode
Dum
Data 1
Data 2
Dual I/O command
CS#
SCLK
IO0
0 28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
7
6
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Figure 20
5
4
3
2
1
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Quad I/O command[6]
CS#
SCLK
IO0
4
0
28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Figure 21
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Quad I/O Read command in QPI mode[6]
Note
6. The gray bits are optional, the host does not have to drive bits during that cycle.
Datasheet
20
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
CS#
SCK
IO0
7
6
5
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
A-1
2
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
A
3
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Figure 22
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
DDR Quad I/O Read command
CS#
SCLK
IO0
4
0
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
A-1
2
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
A
3
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Figure 23
Instruct.
Address
Mode
Dummy
DLP
D1
D2
DDR Quad I/O Read command QPI mode
Additional sequence diagrams, specific to each command, are provided in “Commands” on page 62.
Datasheet
21
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Signal protocols
5.3
Interface states
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3
Interface states summary
IO3 / WP# /
RESET# RESET# IO2
SO /
IO1
SI / IO0
X
Z
X
X
X
Z
X
X
X
X
Z
X
X
HL
HL
X
Z
X
X
HH
HL
HL
X
Z
X
≥VCC (min)
X
HH
HH
HH
X
Z
X
Instruction Cycle (Legacy SPI)
≥VCC (min)
HT
HL
HH
HH
HV
Z
HV
Single Input Cycle
Host to Memory Transfer
≥VCC (min)
HT
HL
HH
HH
X
Z
HV
Single Latency (dummy) cycle
≥VCC (min)
HT
HL
HH
HH
X
Z
X
Single Output Cycle
Memory to Host Transfer
≥VCC (min)
HT
HL
HH
HH
X
MV
X
Dual Input Cycle
Host to Memory Transfer
≥VCC (min)
HT
HL
HH
HH
X
HV
HV
Dual Latency (dummy) Cycle
≥VCC (min)
HT
HL
HH
HH
X
X
X
Dual Output Cycle
Memory to Host Transfer
≥VCC (min)
HT
HL
HH
HH
X
MV
MV
Quad Input Cycle
Host to Memory Transfer
≥VCC (min)
HT
HL
HH
HV
HV
HV
HV
Quad Latency (dummy) cycle
≥VCC (min)
HT
HL
HH
X
X
X
X
Quad Output Cycle
Memory to Host Transfer
≥VCC (min)
HT
HL
HH
MV
MV
MV
MV
DDR Quad Input Cycle
Host to Memory Transfer
≥VCC (min)
HT
HL
HH
HV
HV
HV
HV
DDR Latency (dummy) cycle
≥VCC (min)
HT
HL
HH
X
X
X
X
DDR Quad Output Cycle
Memory to Host Transfer
≥VCC (min)
HT
HL
HH
MV
MV
MV
MV
VCC
SCK
CS#
50 MHz), an LC that provides 1 or more dummy cycles
should be selected to allow additional time for the host to stop driving before the memory starts driving data, to
minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more
dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the
memory starts driving the 4 cycle DLP.
Each Read command ends when CS# is returned High at any point during data return. CS# must not be returned
High during the mode or dummy cycles before data returns as this may cause Mode bits to be captured
incorrectly; making it indeterminate as to whether the device remains in Continuous Read mode.
Datasheet
90
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.4.1
Read (read 03h or 4READ 13h)
The instruction
• 03h (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• 03h (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• 13h is followed by a 4-byte address (A31–A0)
Then the memory contents, at the address given, are shifted out on SO/IO1.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
Phase
Instruction
6
Address
5
4
3
2
1
0
7
6
5
4
Data 1
3
2
1
0
Data N
Figure 65
Read command sequence[29]
8.4.2
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
• 0Bh (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• 0Bh (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• 0Ch is followed by a 4-byte address (A31–A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register
CR3V[3:0]. The dummy cycles allow the device internal circuits additional time for accessing the initial address
location. During the dummy cycles the data value on SO/IO1 is “don’t care” and may be high impedance. Then
the memory contents, at the address given, are shifted out on SO/IO1.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
6
5
4
3
2
1
0
IO2-IO3
Phase
Figure 66
Instruction
Address
Dummy Cycles
Data 1
Fast Read (FAST_READ) command sequence
Note
29.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1 or command 13h.
Datasheet
91
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.4.3
Dual Output Read (DOR 3Bh or 4DOR 3Ch)
The instruction
• 3Bh (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• 3Bh (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• 3Ch is followed by a 4-byte address (A31–A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register
CR3V[3:0]. The dummy cycles allow the device internal circuits additional time for accessing the initial address
location. During the dummy cycles the data value on IO0 (SI) and IO1 (S0) is “don’t care” and may be high
impedance.
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO).
Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
For Dual Output Read commands, there are dummy cycles required after the last address bit is shifted into IO0
(SI) before data begins shifting out of IO0 and IO1.
CS#
SCK
IO0
7
6
5
4
3
2
1
0
A
1
0
IO1
Phase
Figure 67
Instruction
Address
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
Dummy Cycles
Data 1
Data 2
Dual Output Read command sequence[30]
Note
30.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1 or command 3Ch.
Datasheet
92
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.4.4
Quad Output Read (QOR 6Bh or 4QOR 6Ch)
The instruction
• 6Bh (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• 6Bh (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• 6Ch is followed by a 4-byte address (A31–A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register
CR3V[3:0]. The dummy cycles allow the device internal circuits additional time for accessing the initial address
location. During the dummy cycles the data value on IO0–IO3 is “don’t care” and may be high impedance.
Then the memory contents, at the address given, is shifted out four bits at a time through IO0–IO3. Each nibble
(4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
For quad output read commands, there are dummy cycles required after the last address bit is shifted into IO0
before data begins shifting out of IO0–IO3.
CS#
SCK
IO0
7
6
5
4
3
2
1
0
A
1
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
3
7
3
7
3
7
3
7
3
7
IO3
Phase
Figure 68
7
Instruction
Address
Dummy
D1
D2
D3
D4
D5
Output Read command sequence[31]
Note
31.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1 or command 6Ch.
Datasheet
93
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.4.5
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
• BBh (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• BBh (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• BCh is followed by a 4-byte address (A31–A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This command
takes input of the address and returns read data two bits per SCK rising edge. In some applications, the reduced
address input and data output time might allow for code execution in place (XIP) i.e. directly from the memory
device.
The Dual I/O Read command has Continuous Read Mode bits that follow the address so, a series of Dual I/O Read
commands may eliminate the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern
of Axh that indicates the following command will also be a Dual I/O Read command. The first Dual I/O Read
command in a series starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits,
followed by an optional latency period. If the mode bit pattern is Axh the next command is assumed to be an
additional Dual I/O Read command that does not provide instruction bits. That command starts with address,
followed by mode bits, followed by optional latency.
Variable latency may be added after the Mode bits are shifted into SI and SO before data begins shifting out of
IO0 and IO1. This latency period (dummy cycles) allows the device internal circuitry enough time to access data
at the initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high
impedance. The number of dummy cycles is determined by the frequency of SCK. The latency is configured in
CR3V[3:0].
The continuous read feature removes the need for the Instruction bits in a sequence of read accesses and greatly
improves code execution (XIP) performance. The upper nibble (bits 7–4) of the mode bits control the length of
the next Dual I/O Read command through the inclusion or exclusion of the first byte instruction code. The lower
nibble (bits 3-0) of the mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh,
then the device remains in dual I/O Continuous Read mode and the next address can be entered (after CS# is
raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 70; thus, eliminating
eight cycles of the command sequence. The following sequences will release the device from dual I/O Continuous
Read mode; after which, the device can accept standard SPI commands:
• During the dual I/O continuous read command sequence, if the Mode bits are any value other than Axh, then
the next time CS# is raised HIGH the device will be released from dual I/O Continuous Read mode.
• Send the Mode Reset command.
Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial
address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock.
At higher clock speeds the time available to turn off the host outputs before the memory device begins to drive
(bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention, for the host
system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t care” mode
cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time through
IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate.
Datasheet
94
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
Phase
0
A-1
2
0
6
4
2
0
6
4
2
0
6
4
2
0
A
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Instruction
Address
Mode
Dum
Data 1
Data 2
Dual I/O Read command sequence[32, 33]
Figure 69
CS#
SCK
IO0
6
4
2
0
A-1
IO1
7
5
3
1
A
Phase
Figure 70
Data N
2
0
6
4
2
0
3
1
7
5
3
1
Address
Mode
Dum
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
Data 1
Data 2
Dual I/O Continuous Read command sequence[32]
Notes
32.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1 or command BCh.
33.Least significant 4 bits of mode are don’t care and it is optional for the host to drive these bits. The host may
turn off drive during these cycles to increase bus turn around time between mode bits from host and
returning data from the memory.
Datasheet
95
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.4.6
Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction,
• EBh (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• EBh (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• ECh is followed by a 4-byte address (A31–A0)
The Quad I/O Read command improves throughput with four I/O signals IO0–IO3. It allows input of the address
bits four bits per serial SCK clock. In some applications, the reduced instruction overhead might allow for code
execution (XIP) directly from FL-L family devices. The Quad bit of the Configuration Register 1 must be set
(CR1V[1] = 1) or the QPI bit of Configuration Register 2 must be set (CR2V[1] = 1 to enable the quad capability of
FL-L family devices.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data
begins shifting out of IO0–IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry
enough time to access data at the initial address. During latency cycles, the data value on IO0–IO3 are “don’t care”
and may be high impedance. The number of dummy cycles is determined by the frequency of SCK. The latency
is configured in CR3V[3:0].
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through
IO0–IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through
the setting of the Mode bits (after the address sequence, as shown in Figure 71. This added feature removes the
need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7–4) of the
Mode bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the first byte
instruction code. The lower nibble (bits 3–0) of the mode bits are “don’t care” (“x”). If the mode bits equal Axh,
then the device remains in Quad I/O High Performance Read mode and the next address can be entered (after
CS# is raised HIGH and then asserted LOW) without requiring the EBh or ECh instruction, as shown in Figure 73;
thus, eliminating eight cycles for the command sequence. The following sequences will release the device from
Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:
• During the Quad I/O Read command sequence, if the Mode bits are any value other than Axh, then the next time
CS# is raised HIGH, the device will be released from quad I/O high Performance Read mode.
• Send the mode Reset command.
Note that the two Mode bit clock cycles and additional WAIT states (i.e., dummy cycles) allow the device’s internal
circuitry latency time to access the initial address after the last address cycle that is clocked into IO0–IO3.
It is important that the IO0–IO3 signals be set to high-impedance at or before the falling edge of the first data out
clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins to
drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0–IO3 signal contention,
for the host system to turn off the IO0–IO3 signal outputs (make them high impedance) during the last “don’t
care” mode cycle or during any dummy cycles.
CS# should not be driven HIGH during mode or dummy bits as this may make the Mode bits indeterminate.
In QPI mode, (CR2V[3] = 1) the quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the
command protocol is identical to the Quad I/O commands.
Datasheet
96
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
CS#
SCLK
IO0
7
6
5
0 A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Figure 71
4
3
2
1
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Quad I/O Read Initial Access command sequence[34]
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Figure 72
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Quad I/O Read Initial Access command sequence QPI mode[34]
CS#
SCK
IO0
4
0
4
0
A-3
4
0
4
0
4
0
4
0
6
4
2
0
IO1
5
1
5
1
A-2
5
1
5
1
5
1
5
1
7
5
3
1
IO2
6
2
6
2
A-1
6
2
6
2
6
2
6
1
7
5
3
1
IO3
7
3
7
3
A
7
3
7
3
3
7
1
7
5
3
Phase
Figure 73
DN-1
DN
Address
Mode
7
Dummy
D1
D2
D3
1
D4
Continuous Quad I/O Read command sequence[34, 35]
Notes
34.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1 or command ECh.
35.The same sequence is used in QPI mode.
Datasheet
97
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.4.7
DDR Quad I/O Read (EDh, EEh)
The DDR Quad I/O Read command improves throughput with four I/O signals IO0–IO3. It is similar to the Quad
I/O Read command but allows input of the address four bits on every edge of the clock. In some applications, the
reduced instruction overhead might allow for code execution (XIP) directly from FL-L Family devices. The Quad
bit of the Configuration Register 1 must be set (CR1V[1] = 1) or the QPI bit of Configuration Register 2 must be set
(CR2V[1] = 1 to enable the Quad capability of FL-L family devices.
The instruction
• EDh (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• EDh (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• EEh is followed by a 4-byte address (A31–A0)
The address is followed by Mode bits. Then the memory contents, at the address given, is shifted out, in a DDR
fashion, with four bits at a time on each clock edge through IO0–IO3.
The maximum operating clock frequency for DDR quad I/O read command is 54 MHz.
For DDR Quad I/O Read, there is a latency required after the last address and Mode bits are shifted into the
IO0–IO3 signals before data begins shifting out of IO0–IO3. This latency period (dummy cycles) allows the device’s
internal circuitry enough time to access the initial address. During these latency cycles, the data value on
IO0–IO3 are “don’t care” and may be high impedance. When the data learning pattern (DLP) is enabled the host
system must not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the
host so that the memory device can drive the DLP during the dummy cycles.
The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR3V[3:0].
Mode bits allow a series of Quad I/O DDR commands to eliminate the 8-bit instruction after the first command
sends a complementary mode bit pattern. This feature removes the need for the eight bit SDR instruction
sequence and dramatically reduces initial access times (improves XIP performance). The mode bits control the
length of the next DDR Quad I/O Read operation through the inclusion or exclusion of the first byte instruction
code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah)
the device transitions to Continuous DDR Quad I/O Read mode and the next address can be entered (after CS# is
raised HIGH and then asserted low) without requiring the EDh or EEh instruction, thus eliminating eight cycles
from the command sequence. The following sequences will release the device from Continuous DDR Quad I/O
Read mode; after which, the device can accept standard SPI commands:
• During the DDR Quad I/O Read command sequence, if the mode bits are not complementary the next time CS#
is raised HIGH and then asserted low the device will be released from DDR Quad I/O Read mode.
• Send the Mode Reset command.
The address can start at any byte location of the memory array. The address is automatically incremented to the
next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore
be read out with one single read instruction and address 000000h provided. When the highest address is reached,
the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued
indefinitely.
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate. Note
that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is a data
learning pattern (DLP) that is used by the host controller to optimize data capture at higher frequencies. The
preamble drives the IO bus for the four clock cycles immediately before data is output. The host must be sure to
stop driving the IO bus prior to the time that the memory starts outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host
drives a clock edge to when the corresponding data value returns from the memory device. The host controller
will skew the data capture point during the preamble period to optimize timing margins and then use the same
skew time to capture the data during the rest of the read operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization strategy is intended to compensate
for both the PVT (process, voltage, temperature) of both the memory device and the host controller as well as
any system level delays caused by flight time on the PCB.
Datasheet
98
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of
34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four IOs). This pattern was
chosen to cover both “DC” and “AC” data transition scenarios. The two DC transition scenarios include data low
for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low
going transition (110). The two AC transition scenarios include data low for a short period of time (one half clock)
followed by a high going transition (101) and the complementary low going transition (010). The DC transitions
will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow the
host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See “DDR Data Learning Registers” on page 48 for
more details.
In QPI mode, (CR2V[3] = 1) the DDR quad I/O instructions are sent 4 bits at SCK rising edge. The remainder of the
command protocol is identical to the DDR Quad I/O commands.
CS#
SCK
IO0
7
6
5
4
3
2
1
0
A-3
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
A-1
10 6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
11 7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
IO3
A
Phase
Figure 74
8
Instruction
Address
Mode
Dummy
DLP
D1
D2
DDR Quad I/O Read initial access[36, 37]
CS#
SCLK
IO0
4
0
A-3
IO1
5
1
IO2
6
2
IO3
7
3
A
Phase
Figure 75
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
A-1
10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
Instruct.
Address
Mode
Dummy
DLP
D1
3
D2
DDR Quad I/O Read initial access QPI mode[36, 37]
CS#
SCK
IO0
A-3
IO1
IO2
IO3
A
Phase
Figure 76
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
A-1
10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
Address
Mode
Dummy
DLP
D1
3
D2
Continuous DDR Quad I/O Read subsequent access[36, 37, 38]
Notes
36.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1 or command EEh.
37.Example DLP of 34h (or 00110100).
38.The same sequence is used in QPI mode.
Datasheet
99
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.5
Program Flash Array commands
8.5.1
Program Granularity
8.5.1.1
Page Programming
Page Programming is done by loading a page buffer with data to be programmed and issuing a Programming
command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that
can be programmed with a single Programming command. Page Programming allows up to a page size 256 bytes
to be programmed in one operation. The page is aligned on the page size address boundary. It is possible to
program from one bit up to a page size in each page programming operation. For the very best performance,
programming should be done in full pages of 256 bytes aligned on 256 byte boundaries with each page being
programmed only once.
8.5.1.2
Single byte programming
Single byte Programming allows full backward compatibility to the legacy standard SPI page programming (PP)
command by allowing a single byte to be programmed anywhere in the memory array.
8.5.2
Page Program (PP 02h or 4PP 12H)
The Page Program (PP) command allows bytes to be programmed in the memory (changing bits from 1 to 0).
Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must
be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully,
the device sets the write enable latch (WEL) in the Status Register to enable any write operations.
The instruction
• 02h (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• 02h (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• 12h is followed by a 4-byte address (A31–A0)
and at least one data byte on SI/IO0. Up to a page can be provided on SI/IO0 after the 3-byte address with
instruction 02h or 4-byte address with instruction 12h has been provided. As with the Write and Erase commands,
the CS# pin must be driven HIGH after the eighth bit of the last byte has been latched. If this is not done the Page
Program command will not be executed. After CS# is driven HIGH, the self-timed Page Program command will
commence for a time duration of tPP.
Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall
programming time versus loading less than a page into the program buffer.
The programming process is managed by the Flash memory device internal control logic. After a Programming
command is issued, the programming operation status can be checked using the Read Status Register 1
command. The WIP bit (SR1V[0]) will indicate when the programming operation is completed. The P_ERR bit
(SR2V[5]) will indicate if an error occurs in the programming operation that prevents successful completion of
programming. This includes attempted programming of a protected area.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 77
Instruction
Address
Input Data 1
Input Data 2
Page Program (PP 02h or 4PP 12h) command sequence[39]
Note
39.A = MSb of address = A23 for PP 02h with CR2V[0] = 0, or A31 for PP 02h with CR2V[0] = 1, or for 4PP 12h.
Datasheet
100
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
This command is also supported in QPI mode. In QPI mode, the instruction address and data is shifted in on
IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Input D1
Input D2
Input D3
Figure 78
Page Program (PP 02h or 4PP 12h) QPI mode command sequence[40]
8.5.3
Quad Page Program (QPP 32h or 4QPP 34h)
Input D4
The Quad-Input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits
from 1 to 0). The Quad-Input Page Program (QPP) command allows up to a page of data to be loaded into the
page buffer using four signals: IO0–IO3. QPP can improve performance for PROM programmer and applications
that have slower clock speeds (< 12 MHz) by loading 4 bits of data per clock cycle. Systems with faster clock
speeds do not realize as much benefit for the QPP command since the inherent page program time becomes
greater than the time it takes to clock-in the data. The maximum frequency for the QPP command is 108MHz.
To use Quad Page Program the Quad Enable bit in the Configuration Register must be set (QUAD = 1). A Write
Enable command must be executed before the device will accept the QPP command (Status Register 1, WEL = 1).
The instruction
• 32h (CR2V[0] = 0) is followed by a 3-byte address (A23–A0) or
• 32h (CR2V[0] = 1) is followed by a 4-byte address (A31–A0) or
• 34h is followed by a 4-byte address (A31–A0)
and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory
locations.
All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the figure
below.
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
Phase
Figure 79
7
6
5
4
3
Instruction
2
1
0
A
1
0
Address
Data 1
Data 2
Data 3
Data 4
Data 5
...
Quad Page Program command sequence[40]
Note
40.A = MSb of address = A23 for QPP 32h with CR2V[0] = 0, or A31 for QPP 32h with CR2V[0] = 1, or for 4QPP 34h.
Datasheet
101
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.6
Erase Flash Array commands
8.6.0.1
Sector Erase (SE 20h or 4SE 21h)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the Sector
Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the write enable latch (WEL) in the Status Register to enable any write
operations.
The instruction
• 20h [CR2V[0] = 0] is followed by a 3-byte address (A23–A0), or
• 20h [CR2V[0] = 1] is followed by a 4-byte address (A31–A0), or
• 21h is followed by a 4-byte address (A31–A0)
CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of the address has been
latched in on SI/IO0. This will initiate the beginning of internal erase cycle, which involves the pre-programming
and erase of the chosen sector of the flash memory array. If CS# is not driven HIGH after the last bit of address,
the sector erase operation will not be executed.
As soon as CS# is driven HIGH, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write in Progress (WIP) bit to determine when the operation has been
completed. The WIP bit will indicate a ‘1’. when the erase cycle is in progress and a ‘0’ when the erase cycle has
been completed.
A SE or 4SE command applied to a sector that has been write protected through the legacy block protection,
Individual block lock or pointer region protection will not be executed and will set the E_ERR status.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Figure 80
Instruction
Address
Sector Erase (SE 20h or 4SE 21h) command sequence[41]
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Figure 81
Instructtion
Address
Sector Erase (SE 20h or 4SE 21h) QPI mode command sequence[41]
Note
41.A = MSb of address = A23 for SE 20h with CR2V[0] = 0, or A31 for SE 20h with CR2V[0] = 1 or for 4SE 21h.
Datasheet
102
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.6.1
Half Block Erase (HBE 52h or 4HBE 53h)
The Half Block Erase (HBE) command sets all bits in the addressed half block to 1 (all bytes are FFh). Before the
Half Block Erase (HBE) command can be accepted by the device, a Write Enable (WREN) command must be issued
and decoded by the device, which sets the write enable latch (WEL) in the Status Register to enable any write
operations.
The instruction
• 52h [CR2V[0] = 0] is followed by a 3-byte address (A23–A0), or
• 52h [CR2V[0] = 1] is followed by a 4-byte address (A31–A0), or
• 53h is followed by a 4-byte address (A31–A0)
CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of address has been
latched in on SI/IO0. This will initiate the erase cycle, which involves the pre-programming and erase of each
sector of the chose block. If CS# is not driven HIGH after the last bit of address, the half block erase operation will
not be executed.
As soon as CS# is driven into the logic HIGH state, the internal erase cycle will be initiated. With the internal erase
cycle in progress, the user can read the value of the Write-in Progress (WIP) bit to check if the operation has been
completed. The WIP bit will indicate a ‘1’ when the erase cycle is in progress and a ‘0’ when the erase cycle has
been completed.
A Half Block Erase (HBE) command applied to a block that has been write protected through the legacy block
protection, individual block lock or pointer region protection will not be executed and will set the E_ERR status.
If a Half Block Erase command is applied and if any region, sector or block in the half block erase area is protected
the erase will not be executed on the 32 KB range and will set the E_ERR status.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Figure 82
Instruction
Address
Half Block Erase (HBE 52h or 4HBE 53h) command sequence[42, 43]
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Figure 83
Instructtion
Address
Half Block Erase (HBE 52h or 4HBE 53h) QPI mode command sequence[42, 43]
Notes
42.A = MSb of address = A23 for HBE 52h with CR2V[0] = 0, or A31 for HBE 52h with CR2V[0] = 1 or 4HBE 53h.
43.When A[15] = 0 the sectors 0–7 of block are erased and A[15] = 1 then sectors 8–15 of Block are erased.
Datasheet
103
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.6.2
Block Erase (BE D8h or 4BE DCh)
The Block Erase (BE) command sets all bits in the addressed block to 1 (all bytes are FFh). Before the Block Erase
(BE) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by
the device, which sets the write enable latch (WEL) in the Status Register to enable any write operations.
The instruction
• D8h [CR2V[0] = 0] is followed by a 3-byte address (A23–A0), or
• D8h [CR2V[0] = 1] is followed by a 4-byte address (A31–A0), or
• DCh is followed by a 4-byte address (A31–A0)
CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of address has been
latched in on SI/IO0. This will initiate the erase cycle, which involves the pre-programming and erase of each
sector of the chosen block. If CS# is not driven HIGH after the last bit of address, the block erase operation will
not be executed.
As soon as CS# is driven into the logic HIGH state, the internal erase cycle will be initiated. With the internal erase
cycle in progress, the user can read the value of the Write-in Progress (WIP) bit to check if the operation has been
completed. The WIP bit will indicate a ‘1’ when the erase cycle is in progress and a ‘0’ when the erase cycle has
been completed.
A Block Erase (BE) command applied to a block that has been write protected through the legacy block
protection, individual block lock or pointer region protection will not be executed and will set the E_ERR status.
If a Block Erase command is applied and if any region or sector area is protected the erase will not be executed
on the 64 KB range and will set the E_ERR status.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Figure 84
Instruction
Address
Block Erase (BE D8h or 4BE DCh) command sequence[44]
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Figure 85
Instructtion
Address
Block Erase (BE D8h or 4BE DCh) QPI mode command sequence[44]
Note
44.A = MSb of address = A23 for BE D8h with CR2V[0] = 0, or A31 for BE D8h with CR2V[0] = 1 or 4BE DCh.
Datasheet
104
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.6.3
Chip Erase (CE 60h or C7h)
The Chip Erase (CE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the
CE command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by
the device, which sets the write enable latch (WEL) in the Status Register to enable any write operations.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on
SI/IO0. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory
array. If CS# is not driven HIGH after the last bit of instruction, the CE operation will not be executed.
As soon as CS# is driven into the logic HIGH state, the erase cycle will be initiated. With the erase cycle in progress,
the user can read the value of the Write-in Progress (WIP) bit to determine when the operation has been
completed. The WIP bit will indicate a ‘1’ when the erase cycle is in progress and a ‘0’ when the erase cycle has
been completed.
A CE command will not be executed when the legacy block protection, individual block lock or pointer region
protection set to protect any sector or block and this will set the E_ERR status bit.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 86
Instruction
Chip Erase command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 87
Datasheet
Instruction
Chip Erase command sequence QPI mode
105
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.6.4
Program or Erase Suspend (PES 75h)
The PES command allows the system to interrupt a programming or erase operation and then read from any
other non-erase-suspended sector or non-program-suspended-page. Program or Erase Suspend is valid only
during a programming or sector erase, half block erase or block erase operation. A chip erase operation cannot
be suspended.
The Write-in Progress (WIP) bit in Status Register 1 (SR1V[0]) must be checked to know when the programming
or erase operation has stopped. The program suspend status bit in the Status Register 1 (SR2[0]) can be used to
determine if a programming operation has been suspended or was completed at the time WIP changes to 0. The
Erase Suspend Status bit in the Status Register 1 (SR2[1]) can be used to determine if an erase operation has been
suspended or was completed at the time WIP changes to 0. The time required for the suspend operation to
complete is tSL, see Table 57.
An erase can be suspended to allow a program operation or a read operation. During an erase suspend, the IBL
array may be read to examine sector protection and written to remove or restore protection on a sector to be
programmed. The Protection bits will not be rechecked when the operation is resumed so any changes made will
not impact current in progress operation.
A program operation may be suspended to allow a read operation.
A new suspend operation is not allowed with-in an already suspended erase or program operation. The suspend
command is ignored in this situation.
Table 36
Commands allowed during Program or Erase Suspend
Instruction Instruction
name
code (hex)
Allowed Allowed
during
during
Erase Program
Suspend Suspend
Comment
READ
03
X
X
All array reads allowed in suspend
RDSR1
05
X
X
Needed to read WIP to determine end of suspend process
RDAR
65
X
X
Alternate way to read WIP to determine end of suspend
process
RDSR2
07
X
X
Needed to read suspend status to determine whether the
operation is suspended or complete.
RDCR1
35
X
X
Needed to read Configuration Register 1
RDCR2
15
X
X
Needed to read Configuration Register 2
RDCR3
33
X
X
Needed to read Configuration Register 3
RUID
4B
X
X
Needed to read Unique Id
RDID
9F
X
X
Needed to read Device Id
RDQID
AF
X
X
Needed to read Quad Device Id
RSFDP
5A
X
X
Needed to read SFDP
SBL
77
X
X
Needed to set burst length
WREN
06
X
X
Required for program command within Erase Suspend
WRDI
04
X
X
Required for program command within Erase Suspend
PP
02
X
–
Required for array program during Erase Suspend. Only
allowed if there is no other program suspended program
operation (SR2V[0] = 0). A program command will be ignored
while there is a suspended program. If a program command is
sent for a location within an erase suspended sector the
program operation will fail with the P_ERR bit set.
Note
45.For all Quad commands the Quad Enable CR1V[1] bit (See Table 11) needs to be set to ‘1’ before initial
program or erase, since the WRR/WRAR commands are not allowed inside of the suspend state.
Datasheet
106
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
Table 36
Commands allowed during Program or Erase Suspend (continued)
Instruction Instruction
name
code (hex)
Allowed Allowed
during
during
Erase Program
Suspend Suspend
Comment
QPP
32
X
–
Required for array program during erase suspend. Only
allowed if there is no other program suspended program
operation (SR2V[0] = 0). A program command will be ignored
while there is a suspended program. If a program command is
sent for a location within an erase suspended sector the
program operation will fail with the P_ERR bit set.
CLSR
30
X
X
Clear status may be used if a program operation fails during
erase suspend.
EPR
7A
X
X
Required to resume from erase or program suspend
RSTEN
66
X
X
Reset allowed anytime
RST
99
X
X
Reset allowed anytime
FAST_READ
0B
X
X
All array reads allowed in suspend
DOR
3B
X
X
All array reads allowed in suspend
DIOR
BB
X
X
All array reads allowed in suspend
IBLRD
3D
X
X
It may be necessary to remove and restore individual block
lock during erase suspend to allow programming during erase
suspend.
IBL
36
X
X
It may be necessary to restore individual block lock during
erase suspend to allow programming during erase suspend.
IBUL
39
X
X
It may be necessary to remove individual block lock during
erase suspend to allow programming during erase suspend.
QOR
6B
X
X
Read Quad output (3-byte Address)[45]
QIOR
EB
X
X
All array reads allowed in suspend[45]
MBR
FF
X
X
May need to reset a read operation during suspend
SECRP
42
X
–
All Security Regions program allowed in erase suspend
SECRR
48
X
X
All Security Regions reads allowed in suspend
Note
45.For all Quad commands the Quad Enable CR1V[1] bit (See Table 11) needs to be set to ‘1’ before initial
program or erase, since the WRR/WRAR commands are not allowed inside of the suspend state.
All command not included in Table 36 are not allowed during erase or program suspend. The WRR, WRAR, or
SPRP commands are not allowed during erase or program suspend, it is therefore not possible to alter the legacy
block protection bits or pointer region protection during erase suspend.
Reading at any address within an erase-suspended sector or program-suspended page produces undetermined
data.
After an erase-suspended program operation is complete, the device returns to the Erase-Suspend mode. The
system can determine the status of the program operation by reading the WIP bit in the Status Register, just as
in the standard program operation.
Datasheet
107
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 88
Instruction
Program or Erase Suspend command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 89
Instruction
Program or Erase Suspend command sequence QPI mode
tSL
CS#
SCK
SI_IO0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SO
Phase
Phase
Figure 90
Datasheet
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Suspend Instruction
Read Status Instruction
Status
Instr. During Suspend
Repeat Status Read Until Suspended
Program or Erase Suspend command with continuing instruction commands sequence
108
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.6.5
Erase or Program Resume (EPR 7Ah)
After program or read operations are completed during a Program or Erase Suspend the erase or Program
Resume command is sent to continue the suspended operation.
After an Erase or Program Resume command is issued, the WIP bit in the Status Register 1 will be set to a 1 and
the suspended operation will resume if one is suspended. If there is no suspended program or erase operation
the Resume command is ignored.
Program or erase operations may be interrupted as often as necessary e.g. a Program Suspend command could
immediately follow a Program Resume command but, but in order for a program or erase operation to progress
to completion there must be some periods of time between resume and the next suspend command greater than
or equal to tRNS. See Table 57.
The Program Suspend Status bit in the Status Register 1 (SR2[0]) can be used to determine if a programming
operation has been suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in
the Status Register 1 (SR2[1]) can be used to determine if an erase operation has been suspended or was
completed at the time WIP changes to 0. See “Status Register 2 Volatile (SR2V)” on page 32.
An erase or program resume command must be written to resume a suspended operation.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 91
Instruction
Erase or Program Resume command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 92
Datasheet
Instruction
Erase or Program Resume command sequence QPI mode
109
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.7
Security Regions Array commands
The Security Regions commands select which region to use by address A15 to A8 as shown below.
• Security Region 0: A23–16 = 00h; A15–8 = 00h; A7–0 = Byte address
• Security Region 1: A23–16 = 00h; A15–8 = 01h; A7–0 = Byte address
• Security Region 2: A23–16 = 00h; A15–8 = 02h; A7–0 = Byte address
• Security Region 3: A23–16 = 00h; A15–8 = 03h; A7–0 = Byte address
8.7.1
Security Region Erase (SECRE 44h)
The Security Region Erase command erases data in the Security Region, which is in a different address space from
the main array data. The Security Region is 1024 bytes so, the address bits for S25FL064L (A22 to A10) must be
zero for this command. Each region can be individually erased. Refer to “Security Regions address space” on
page 28 for details on the Security Region.
Before the Security Region Erase command can be accepted by the device, a Write Enable (WREN) command
must be issued and decoded by the device, which sets the write enable latch (WEL) in the Status Register to
enable any write operations. The WIP bit in SR1V may be checked to determine when the operation is completed.
The E_ERR bit in SR2V may be checked to determine if an error occurred during the operation.
The Security Region Lock bits (CR1NV[2-5]) in the Configuration Register 1 can be used to protect the Security
Region for erase. Once a Lock bit is set to 1, the corresponding Security Regions will be permanently locked,
Attempting to erase a region that is locked will fail with the E_ERR bit in SR2V[6] set to ‘1’.
When the Protection Register NVLOCK bit = ‘0’, Security Region 2 and 3 are protected from program or erase.
Attempting to erase in a region that locked will fail with the E_ERR bits in SR2V[6] set to ‘1’. See “NVLOCK bit
(PR[0])” on page 60.
The Password Protection Mode Lock bit (IRP[2]) allows regions 2 and 3 to be protected from erase operations
until the correct password is provided to enable erasing of these Security Regions. Attempting to erase in a region
that is password locked will fail with the E_ERR bit in SR2V[6] set to ‘1’.
The protocol of the Security Region erase command is the same as the Sector Erase command. See “Sector Erase
(SE 20h or 4SE 21h)” on page 102 for the command sequence. QPI mode is supported.
8.7.2
Security Region Program (SECRP 42h)
The Security Region Program command programs data in the Security Region, which is in a different address
space from the main array data. The Security Region is 1024 bytes so, the Address bits for S25FL064L (A22 to A10)
must be zero for this command. Refer to “Security Regions address space” on page 28 for details on the
Security Region.
Before the Security Region Program command can be accepted by the device, a Write Enable (WREN) command
must be issued and decoded by the device, which sets the write enable latch (WEL) in the Status Register to
enable any write operations. The WIP bit in SR1V may be checked to determine when the operation is completed.
The P_ERR bit in SR2V may be checked to determine if any error occurred during the operation.
To program the Security Region array in bit granularity, the rest of the bits within a data byte can be set to ‘1’.
Each region in the Security Region memory space can be programmed one or more times, provided that the
region is not locked. However, for the best data integrity, it is recommended that one or more 16-byte length and
aligned groups of bytes be programed together and programmed only once between erase operations within
each region.
The Security Region Lock bits (CR1NV[2-5]) in the Configuration Register 1 can be used to protect the Security
Regions for programming. Once a Lock bit is set to 1, the corresponding Security Region will be permanently
locked. Attempting to program zeros or ones in a region that is locked (protected) will fail with the P_ERR bit in
SR2V[5] set to ‘1’. Programming ones in a un-protected area does not cause an error and does not set P_ERR (see
“Configuration Register 1” on page 34 for detail descriptions).
Datasheet
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2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
When the Protection Register NVLOCK bit = ‘0’, Security Regions 2 and 3 are protected from program or erase.
Attempting to program in a region that locked will fail with the P_ERR bit in SR2V[5] set to ‘1’. See “NVLOCK bit
(PR[0])” on page 60.
The Password Protection Mode Lock bit (IRP[2]) allows regions 2 and 3 to be protected from programming
operations until the correct password is provided to enable programming of these Security Regions 2 and 3.
Attempting to program in a region that is password locked will fail with the P_ERR bit in SR2V[5] set to ‘1’. See
“Password Protection mode” on page 60.
The protocol of the Security Region program command is the same as the Page Program command. See “Page
Programming” on page 100 for the command sequence. QPI mode is supported.
8.7.3
Security Regions Read (SECRR 48h)
The Security Region Read (SECRR) command provides a way to read data from the Security Regions. The Security
Region is 1024 bytes so, the address bits for S25FL064L (A22 to A10) must be zero for this command. Refer to
“Security Regions address space” on page 28 for details on the Security Regions.
The instruction is followed by a 3 or 4 byte address (depending on the address length configuration CR2V[0],
followed by a number of latency (dummy) cycles set by CR3V[3:0]. Then the selected register data are returned.
The protocol of the Security Region read command will not wrap to the starting address after the Security Region
address is at its maximum; instead, the data beyond the maximum address will be undefined. The Security
Region read command read latency is set by the latency value in CR3V[3:0].
The Security Region Read Password Mode Enable bit (IRP[6]) allows regions 3 to be protected from read
operations until the correct password is provided to enable reading of this Security Region. Attempting to read
in region 3 that is password locked will return invalid and undefined data. See “Security Region read password
protection” on page 61.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
Phase
Instruction
Address
6
5
4
Dummy Cycles
3
2
1
0
Data 1
Security Regions Read command sequence[46]
Figure 93
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in and returning
data out on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Figure 94
Instruct.
Address
Dummy
D1
D2
D3
D4
Security Regions Read command sequence QPI mode[47]
Notes
46.A = MSb of address = 23 for address length CR2V[0] = 0, or 31 for CR2V[0] = 1.
47.A = MSb of address = 23 for CR2V[0] = 0, or 31 for CR2V[0] = 1.
Datasheet
111
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.8
Individual Block Lock commands
In order to use Individual Block Lock, the IBL protection scheme must be selected by the WPS bit in Configuration
Register 2 CR2V[2] = 1. If if IBL protection scheme is not selected CR2V[2] = 0 the IBL commands are ignored.
individual block Lock bits (IBL) are volatile, with one for each sector / block, and can be individually modified. By
issuing the IBL or GBL commands, a IBL bit is set to ‘0’ protecting each related sector / block. By issuing the IBUL
or GUL commands, a IBL bit is cleared to ‘1’ unprotecting each related sector or block. By issuing the IBLRD
command the state of each IBL bit protection can be read.
8.8.1
IBL Read (IBLRD 3Dh or 4IBLRD E0h)
The IBLRD/4IBLRD command allows reading the state of each IBL bit protection.
The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the
24- or 32- bit address, depending on the address length configuration CR2V[0], selecting location zero within the
desired sector.
Then the 8-bit IBL access register contents are shifted out on the serial output SO/IO1. Each bit is shifted out at
the SCK frequency by the falling edge of the SCK signal. It is possible to read the same IBL access register
continuously by providing multiples of eight clock cycles. The address of the IBL register does not increment so
this is not a means to read the entire IBL array. Each location must be read with a separate IBL read command.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
Phase
Figure 95
Instruction
Address
6
5
Dummy Cycles
4
3
2
1 0
Output IBL
IBLRD command sequence[48, 49]
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in and returning
data out on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
Phase
Figure 96
Instruct.
Address
Dummy
IBL
Repeat IBL
IBLRD command sequence QPI[48, 49]
Notes
48.A = MSb of address = 23 for Address length CR2V[0] = 0, or 31 for CR2V[0] = 1 with command 3Dh.
49.A = MSb of address = 31 with command E0h.
Datasheet
112
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.8.2
IBL Lock (IBL 36h or 4IBL E1h)
The IBL/4IBL commands sets the selected IBL bit to ‘0’ protecting each related sector / block.
The IBL command is entered by driving CS# to the logic LOW state, followed by the instruction, followed by the
24- or 32-bit address, depending on the address length configuration CR2V[0]. The IBL command affects the WIP
bits of the Status and Configuration Registers in the same manner as any other programming operation.
CS# must be driven to the logic HIGH state after the 24- or 32-bit address (depending on the address length
configuration CR2V[0]) has been latched in. As soon as CS# is driven to the logic HIGH state, the self-timed IBL
operation is initiated. While the IBL operation is in progress, the Status Register may be read to check the value
of the Write-in Progress (WIP) bit. The Write-in Progress (WIP) bit is a ‘1’ during the self-timed IBL operation, and
is a ‘0’ when it is completed.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Figure 97
Instruction
Address
IBL command sequence[50, 51]
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Figure 98
Instructtion
Address
IBL command sequence QPI mode[50, 51]
Notes
50.A = MSb of address = 23 for Address length CR2V[0] = 0, or 31 for CR2V[0] = 1 with command 36h.
51.A = MSb of address = 31 with command E1h.
Datasheet
113
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.8.3
IBL Unlock (IBUL 39h or 4IBUL E2h)
The IBUL/4IBULcommands clears the selected IBL bit to ‘1’ unprotecting each related sector / block.
The IBUL command is entered by driving CS# to the logic LOW state, followed by the instruction, followed by the
24- or 32- bit address, depending on the address length configuration CR2V[0]. The IBUL command affects the
WIP bits of the Status and Configuration Registers in the same manner as any other programming operation.
CS# must be driven to the logic HIGH state after the 24- or 32-bit address (depending on the address length
configuration CR2V[0]) has been latched in. As soon as CS# is driven to the logic HIGH state, the self-timed IBL
operation is initiated. While the IBUL operation is in progress, the Status Register may be read to check the value
of the Write-in Progress (WIP) bit. The Write-in Progress (WIP) bit is a ‘1’ during the self-timed IBUL operation, and
is a ‘0’ when it is completed.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Figure 99
Instruction
Address
IBUL command sequence[51, 52]
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Figure 100
Instructtion
Address
IBUL command sequence QPI mode[52, 53]
Notes
52.A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0] = 1 with command 39h.
53.A = MSb of address = 31 with command E2h.
Datasheet
114
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.8.4
Global IBL Lock (GBL 7Eh)
The GBL commands sets all the IBL bits to ‘0’ protecting all sectors / blocks.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.
This will initiate the GBL. If CS# is not driven HIGH after the last bit of instruction, the GBL operation will not be
executed.
As soon as CS# is driven into the logic HIGH state, the GBL will be initiated. With the GBL in progress, the user can
read the value of the Write-in Progress (WIP) bit to determine when the operation has been completed. The WIP
bit will indicate a ‘1’ when the GBL is in progress and a ‘0’ when the GBL has been completed.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 101
Instruction
Global IBL lock (GBL) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 102
Datasheet
Instruction
Global IBL lock (GBL) command sequence QPI mode
115
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.8.5
Global IBL Unlock (GBUL 98h)
The GBUL commands clears all the IBL bits to ‘1’ unprotecting all sectors / blocks.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.
This will initiate the GBUL If CS# is not driven HIGH after the last bit of instruction, the GBUL operation will not be
executed.
As soon as CS# is driven into the logic HIGH state, the GBL will be initiated. With the GBL in progress, the user can
read the value of the Write-in Progress (WIP) bit to determine when the operation has been completed. The WIP
bit will indicate a ‘1’ when the GBUL is in progress and a ‘0’ when the GBUL has been completed.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 103
Instruction
Global IBL Unlock (GBUL) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 104
Datasheet
Instruction
Global IBL Unlock (GBUL) command sequence QPI mode
116
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.9
Pointer Region command
8.9.1
Set Pointer Region Protection (SPRP FBh or 4SPRP E3h)
The SPRP or 4SPRP command is ignored during a suspend operation because the pointer value cannot be erased
and re-programmed during a suspend.
The SPRP or 4SPRP command is ignored if default power supply lock-down protection NVLOCK PR[0] = 0 or power
supply lock-down protection enabled IRP[1] = 0 or password protection enabled IRP[2] = 0 and NVLOCK PR[0] = 0.
Before the SPRP or 4SPRP command can be accepted by the device, a Write Enable (WREN) command must be
issued. After the Write Enable (WREN) command has been decoded, the device will set the write enable latch
(WEL) in the Status Register to enable any write operations.
The SPRP or 4SPRP command is entered by driving CS# to the logic LOW state, followed by the instruction,
followed by the 24- or 32-bit address, depending on the address length configuration CR2V[0], see “Pointer
region protection (PRP)” on page 56 for details on address values to select protection options.
CS# must be driven to the logic HIGH state after the last bit of address has been latched in. If not, the SPRP
command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed SPRP operation is
initiated. While the SPRP operation is in progress, the Status Register may be read to check the value of the
Write-in Progress (WIP) bit. The WIP bit is a ‘1’ during the self-timed SPRP operation, and is a ‘0’ when it is
completed. When the SPRP operation is completed, the write enable latch (WEL) is set to a ‘0’. The SPRP or 4SPRP
command will set the P_ERR or E_ERR bits if there is a failure in the set pointer region protection operation.
For details on the address pointer defining a sector boundary between protected and unprotected regions in the
memory, see “Pointer region protection (PRP)” on page 56.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
SPRP command sequence[54, 55]
Figure 105
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Figure 106
Instructtion
Address
SPRP command sequence QPI mode[54, 55]
Notes
54.A = MSb of address = 23 for address length (CR2V[0] = 0, or 31 for CR2V[0] = 1 with command FDh.
55.A = MSb of address = 31 with command E3h.
Datasheet
117
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.10
Individual and Region Protection (IRP) commands
8.10.1
IRP Register Read (IRPRD 2Bh)
The IRP Register Read instruction 2Bh is shifted into SI/IO0 by the rising edge of the SCK signal followed by one
dummy cycle. This latency period allows the device’s internal circuitry enough time to access data at the initial
address. During latency cycles, the data value on IO0–IO3 are “don’t care” and may be high impedance.
Then the 16-bit IRP Register contents are shifted out on the serial output S0/IO1,least significant byte first. Each
bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the IRP register
continuously by providing multiples of 16 clock cycles.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 107
7
Instruction
6
DY
5
4
3
2
1
0
7
Output IRP Low Byte
6
5
4
3
2
1
0
Output IRP High Byte
IRPRD command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in and returning data out on
IO0–IO3.
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
Figure 108
Datasheet
Instruct.
Dummy
IRP Low Byte
IRP High Byte
IRPRD command sequence – QPI mode
118
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.10.2
IRP Program (IRPP 2Fh)
Before the IRP program (IRPP) command can be accepted by the device, a Write Enable (WREN) command must
be issued. After the Write Enable (WREN) command has been decoded, the device will set the write enable latch
(WEL) in the Status Register to enable any write operations.
The IRPP command is entered by driving CS# to the logic LOW state, followed by the instruction and two data
bytes on SI, least significant byte first. The IRP Register is two data bytes in length.
The IRPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner
as any other programming operation.
CS# input must be driven to the logic HIGH state after the sixteenth bit of data has been latched in. If not, the IRPP
command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed IRPP operation is
initiated. While the IRPP operation is in progress, the Status Register may be read to check the value of the
Write-in Progress (WIP) bit. The Write-in Progress (WIP) bit is a ‘1’ during the self-timed IRPP operation, and is a
‘0’ when it is completed. When the IRPP operation is completed, the write enable latch (WEL) is set to a ‘0’.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 109
Instruction
Input IRP Low Byte
Input IRP High Byte
IRP Program (IRPP) command
This command is also supported in QPI mode. In QPI mode, the instruction and data is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
4
0
C
8
IO1
5
1
5
1
D
9
IO2
6
2
6
2
E
A
IO3
7
3
7
3
F
B
Phase
Figure 110
Datasheet
Instruct.
IRP Low Byte
IRP High Byte
IRP Program (IRPP) command QPI
119
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.10.3
Protection Register Read (PRRD A7h)
The Protection Register Read (PRRD) command allows the Protection Register contents to be read out of SO/IO1.
The read instruction A7h is shifted into SI by the rising edge of the SCK signal followed by one dummy cycle. This
latency period allows the device’s internal circuitry enough time to access data at the initial address. During
latency cycles, the data value on IO0–IO3 are “don’t care” and may be high impedance.
Then the 8-bit Protection Register contents are shifted out on the serial output SO/IO1. Each bit is shifted out at
the SCK frequency by the falling edge of the SCK signal. It is possible to read the Protection register continuously
by providing multiples of eight clock cycles.
The Protection Register contents may only be read when the device is in STANDBY state with no other operation
in progress.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 111
7
Instruction
6
DY
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
Protection Register Read (PRRD) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in and returning data out on
IO0–IO3.
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
Figure 112
Datasheet
Instruct.
Dummy
Register Read
Register Read
Protection Register Read (PRRD) command sequence – QPI mode
120
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.10.4
Protection Register Lock (PRL A6h)
The Protection Register Lock (PRL) command clears the NVLOCK bit (PR[0]) to zero and loads the IRP[6] value in
to SECRRP (PR[6]). See “Protection Register (PR)” on page 46. Before the PRL command can be accepted by the
device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the write enable
latch (WEL) in the Status Register to enable any write operations.
The PRL command is entered by driving CS# to the logic LOW state, followed by the instruction.
CS# must be driven to the logic HIGH state after the eighth bit of instruction has been latched in. If not, the PRL
command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PRL operation is
initiated. While the PRL operation is in progress, the Status Register may still be read to check the value of the
Write-in Progress (WIP) bit. The WIP bit is a ‘1’ during the self-timed PRL operation, and is a ‘0’ when it is
completed. When the PRL operation is completed, the write enable latch (WEL) is set to a ‘0’.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 113
Instruction
Protection Register Lock (PRL) command sequence
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 114
Datasheet
Instruction
Protection Register Lock (PRL) command sequence – QPI mode
121
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Commands
8.10.5
Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password mode has been
selected by programming the Password Protection Mode bit to 0 in the IRP Register (IRP[2]). After the Password
Protection mode is selected the password is no longer readable, the PASSRD command will output undefined
data.
The PASSRD command is shifted into SI followed by one dummy cycle. This latency period allows the device’s
internal circuitry enough time to access data at the initial address. During latency cycles, the data value on are
“don’t care” and may be high impedance.
Then the 64-bit password is shifted out on the serial output, least significant byte first, most significant bit of each
byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read
the password continuously by providing multiples of 64 clock cycles.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IO2-IO3
Phase
Figure 115
Instruction
DY
Data 1
Data 8
Password Read (PASSRD) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in and returning data out on
IO0–IO3.
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
Figure 116
Datasheet
Instruct.
Dummy
Data 1
Data 8
Password Read (PASSRD) command sequence – QPI mode
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Commands
8.10.6
Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded, the device sets the write enable latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password mode is selected by programming the Password
Protection Mode bit to 0 in the IRP Register (IRP[2]). After the Password Protection mode is selected the PASSP
command is ignored.
The PASSP command is entered by driving CS# to the logic LOW state, followed by the instruction and the
password data bytes on SI/IO0, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic HIGH state after the sixty-fourth (64th) bit of data has been latched. If not, the
PASSP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSP operation
is initiated. While the PASSP operation is in progress, the Status Register may be read to check the value of the
Write-in Progress (WIP) bit. The Write-in Progress (WIP) bit is a ‘1’ during the self-timed PASSP cycle, and is a ‘0’
when it is completed. The PASSP command can report a program error in the P_ERR bit of the status register.
When the PASSP operation is completed, the write enable latch (WEL) is set to a ‘0’.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 117
Instruction
Password Byte 1
Password Byte 8
Password Program (PASSP) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction and data is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
Figure 118
Datasheet
Instruct.
Password Byte 1
Password Byte 8
Password Program (PASSP) command sequence QPI mode
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SPI multi-I/O, 3.0 V
Commands
8.10.7
Password Unlock (PASSU EAh)
The PASSU command is entered by driving CS# to the logic LOW state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic HIGH state after the sixty-fourth (64th) bit of data has been latched. If not, the
PASSU command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSU operation
is initiated. While the PASSU operation is in progress, the Status Register may be read to check the value of the
Write-in Progress (WIP) bit. The Write-in Progress (WIP) bit is a ‘1’ during the self-timed PASSU cycle, and is a ‘0’
when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register, an
error is reported by setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is necessary
to use the CLSR command to clear the Status Register, the Software Reset command (RSTEN 66h followed by RST
99h) to reset the device, or drive the RESET# and IO3 / RESET# input to initiate a hardware reset, in order to return
the P_ERR and WIP bits to 0. This returns the device to standby STANDBY, ready for new commands such as a
retry of the PASSU command.
If the password does match, the NVLOCK bit is set to ‘1’.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 119
Instruction
Password Byte 1
Password Byte 8
Password Unlock (PASSU) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction and data is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
Figure 120
Datasheet
Instruct.
Password Byte 1
Password Byte 8
Password Unlock (PASSU) command sequence QPI mode
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Commands
8.11
Reset commands
Software controlled Reset commands restore the device to its initial power up state, by reloading volatile
registers from non-volatile default values. If a software reset is initiated during a erase, program or writing of a
register operation the data in that sector, page or Register is not stable, the operation that was interrupted needs
to be initiated again.
However, the volatile SRP1 bit in the Configuration Register CR1V[0] and the volatile NVLOCK bit in the Protection
Register are not changed by a software reset. The software reset cannot be used to circumvent the SRP1 or
NVLOCK bit protection mechanisms for the other security configuration bits.
The SRP1 bit and the NVLOCK bit will remain set at their last value prior to the software reset. To clear the SRP1
bit and set the NVLOCK bit to its Protection mode selected power on state, a full power-on-reset sequence or
hardware reset must be done.
A Software Reset command (RSTEN 66h followed by RST 99h) is executed when CS# is brought HIGH at the end
of the instruction and requires tRPH time to execute.
In the case of a previous power-up reset (POR) failure to complete, a Reset command triggers a full power up
sequence requiring tPU to complete.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 121
Instruction
Software Reset / Mode Bit Reset command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Instruction
Figure 122
Software Reset / Mode Bit command sequence – QPI mode
8.11.1
Software Reset Enable (RSTEN 66h)
The Reset Enable (RSTEN) command is required immediately before a Software Reset command (RST 99h) such
that a Software Reset is a sequence of the two commands. Any command other than RST following the RSTEN
command, will clear the reset enable condition and prevent a later RST command from being recognized.
8.11.2
Software Reset (RST 99h)
The Reset (RST) command immediately following a RSTEN command, initiates the Software Reset process. Any
command other than RST following the RSTEN command, will clear the reset enable condition and prevent a later
RST command from being recognized.
Datasheet
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SPI multi-I/O, 3.0 V
Commands
8.11.3
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command is used to return the device from Continuous High Performance Read mode
back to normal Standby awaiting any new command. Because the hardware RESET# input may be disabled and
a device that is in a Continuous High Performance Read mode may not recognize any normal SPI command, a
System Hardware Reset or Software Reset command may not be recognized by the device. It is recommended to
use the MBR command after a system reset when the RESET# signal is not available or, before sending a Software
Reset, to ensure the device is released from Continuous High Performance Read mode.
The MBR command sends ones on SI/IO0 for eight SCK cycles. IO1–IO3 are “don’t care” during these cycles.
8.11.4
Deep Power Down commands
8.11.5
Deep Power Down (DPD B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced
with the Deep Power Down command. The lower power consumption makes the Deep Power Down (DPD)
command especially useful for battery powered applications (see ICC1 and ICC2 in (“DC characteristics” on
page 146). The command is initiated by driving the CS# pin LOW and shifting the instruction code “B9h”.
The CS# pin must be driven HIGH after the eighth bit has been latched. If this is not done the Deep Power Down
command will not be executed. After CS# is driven HIGH, the power-down state will be entered within the time
duration of tDP (Table 54). While in the power-down state only the release from Deep Power Down / Device ID
command, which restores the device to normal operation, will be recognized. All other commands are ignored.
This includes the Read Status Register command, which is always available during normal operation. Ignoring all
but one command also makes the power down state a useful condition for securing maximum write protection.
While in the Deep Power Down mode the device will only accept a hardware reset which will initiate a power on
reset that will restore the device to normal operation. The device always powers-up in the normal operation with
the standby current of ICC1.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 123
Instruction
Deep Power Down (DPD) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 124
Datasheet
Instruction
Deep Power Down (DPD) command sequence – QPI mode
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Commands
8.11.6
Release from Deep Power Down / Device ID (RES ABh)
The release from Deep Power Down / Device ID command is a multi-purpose command. It can be used to release
the device from the deep power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the deep power-down state, the command is issued by driving the CS# pin LOW,
shifting the instruction code “ABh” and driving CS# HIGH. Release from deep power-down will take the time
duration of tRES (Table 54) before the device will resume normal operation and other commands are accepted.
The CS# pin must remain HIGH during the tRES time duration.
When used only to obtain the Device ID while not in the deep power-down state, the command is initiated by
driving the CS# pin LOW and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits
are then shifted out on the falling edge of CLK with most significant bit (MSb) first. The Device ID values for the
S25FL-L family is listed in and Table 43. Continued shifting of output beyond the end of the defined ID address
space will provide undefined data. The command is completed by driving CS# HIGH.
When used to release the device from the deep power-down state and obtain the device ID, the command is the
same as previously described, and shown in Figure 127 and Figure 128, except that after CS# is driven HIGH it
must remain HIGH for a time duration of tRES. After this time duration the device will resume normal operation
and other commands will be accepted. If the release from Deep Power-down / Device ID command is issued while
an erase, program or write cycle is in process (when BUSY equals 1) the command is ignored and will not have
any effects on the current cycle.
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Figure 125
Instruction
Release from Deep Power Down (RES) command sequence
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Figure 126
Instruction
Release from Deep Power Down (RES) command sequence – QPI mode
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0 23
1
SO_IO1
Phase
Figure 127
Datasheet
0
7
Instruction
Dummy
6
5
4
3
Dev ID
2
1
0
7
1
0
Dev ID
Read Identification (RES) command sequence
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SPI multi-I/O, 3.0 V
Commands
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3 and the
returning data is shifted out on IO0–IO3.
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
IO3
7
Phase
Figure 128
Datasheet
4
0
4
0
4
5
5
1
5
1
5
2
6
6
2
6
2
6
3
7
7
3
7
3
7
Instruction
23
22
4
0
Dummy
Dev ID
Dev ID
Read Identification (RES) QPI mode command
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Data integrity
9
Data integrity
9.1
Erase endurance
Table 37
Erase endurance
Parameter
Program/erase cycles per main flash array sectors
Program/erase cycles Security Region or Non-volatile Register
Array[56]
Minimum
Unit
100 K
PE cycle
1K
PE cycle
Note
56.Each write command to a Non-volatile Register causes a PE cycle on the entire Non-volatile Register Array.
9.2
Data retention
Table 38
Data retention
Parameter
Data retention time
Test conditions
Minimum time
Unit
10 K program/erase cycles
20
Years
100 K program/erase cycles
2
Years
Contact Infineon and FAE for further information on the data integrity. An application note is available at:
www.infineon.com/support.
Datasheet
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Software interface reference
10
Software interface reference
10.1
JEDEC JESD216B serial flash discoverable parameters
This document defines the serial flash discoverable parameters (SFDP) revision B data structure used in the
following Infineon serial flash devices:
• S25FL-L family
These data structure values are an update to the earlier revision SFDP data structure currently existing in the
above devices.
The Read SFDP (RSFDP) command (5Ah) reads information from a separate flash memory address space for
device identification, feature, and configuration information, in accord with the JEDEC JESD216B standard for
serial flash discoverable parameters.
The SFDP data structure consists of a header table that identifies the revision of the JESD216 header format that
is supported and provides a revision number and pointer for each of the SFDP parameter tables that are provided.
The parameter tables follow the SFDP header. However, the parameter tables may be placed in any physical
location and order within the SFDP address space. The tables are not necessarily adjacent nor in the same order
as their header table entries.
The SFDP header points to the following parameter tables:
• Basic flash
- This is the original SFDP table. It has a few modified fields and new additional field added at the end of the table.
• 4-byte address instruction
- This is the original SFDP table. It has a few modified fields and new additional field added at the end of the table.
The physical order of the tables in the SFDP address space is: SFDP header, Basic flash sector map, 4-byte
Instruction.
The SFDP address space is programmed by Infineon and read-only for the host system.
10.1.1
Serial flash discoverable parameters (SFDP) address map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides
a pointer to each parameter. One basic flash parameter is mandated by the JEDEC JESD216B standard. Optional
parameter tables for 4-byte address instructions follow the basic flash table.
Table 39
SFDP overview map
Byte
address
0000h
...
0300h
...
Datasheet
Description
Location zero within JEDEC JESD216B SFDP space - start of SFDP header
Remainder of SFDP header followed by undefined space
Start of SFDP parameter
Remainder of SFDP JEDEC parameter followed by undefined space
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Software interface reference
10.1.2
SFDP header field definitions
Table 40
SFDP header
SFDP byte
address
SFDP Dword
name
Data
Description
53h
This is the entry point for read SFDP (5Ah) command i.e. location zero
within SFDP space
ASCII “S”
46h
ASCII “F”
02h
44h
ASCII “D”
03h
50h
ASCII “P”
06h
SFDP minor revision (06h = JEDEC JESD216 Revision B)
- This revision is backward compatible with all prior minor revisions.
SFDP reading and parsing software will work with higher minor
revision numbers than the software was designed to handle.
Software designed for a higher revisions must know how to handle
earlier revisions. Example: SFDP reading and parsing software for
minor revision 0 will still work with minor revision 6. SFDP reading
and parsing software for minor revision 6 must be designed to also
read minor revision 0 or 5. Do not do a simple compare on the minor
revision number, looking only for a match with the revision number
that the software is designed to handle. There is no problem with
using a higher number minor revision.
01h
SFDP major revision
This is the original major revision. This major revision is compatible
with all SFDP reading and parsing software.
06h
01h
Number of parameter headers (zero based, 01h = 2 parameters)
07h
FFh
Unused
08h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI flash parameter)
06h
Parameter minor revision (06h = JESD216 revision B)
01h
Parameter major revision (01h = The original major revision - all
SFDP software is compatible with this major revision.
10h
Parameter table length (in double words = Dwords = 4-byte units)
10h = 16 Dwords
00h
Parameter table pointer byte 0 (Dword = 4-byte aligned)
JEDEC Basic SPI flash parameter byte offset = 0300h address
03h
Parameter table pointer byte 1
00h
Parameter table pointer byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined parameter)
84h
Parameter ID LSB (84h = SFDP 4-byte address instructions
parameter)
00h
Parameter minor revision (00h = Initial version as defined in JESD216
Revision B)
01h
Parameter major revision (01h = The original major revision - all
SFDP software that recognizes this parameter’s ID is compatible with
this major revision.
02h
Parameter table length (in double words = Dwords = 4-byte units) (2h
= 2 Dwords)
00h
01h
SFDP header
1st DWORD
04h
SFDP header
2nd DWORD
05h
09h
0Ah
0Bh
Parameter
header 0
1st DWORD
0Ch
0Dh
0Eh
Parameter
header 0
2nd DWORD
0Fh
10h
11h
12h
13h
Datasheet
Parameter
header 1
1st DWORD
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Software interface reference
Table 40
SFDP byte
address
SFDP header (continued)
SFDP Dword
name
14h
15h
16h
17h
Datasheet
Parameter
header 1
2nd DWORD
Data
Description
40h
Parameter table pointer byte 0 (Dword = 4-byte aligned)
JEDEC parameter byte offset = 0340h
03h
Parameter table pointer byte 1
00h
Parameter table pointer byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
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Software interface reference
10.1.3
JEDEC SFDP basic SPI flash parameter
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
E5h
Start of SFDP JEDEC parameter
Bits 7:5 = unused = 111b
Bit 4:3 = 05h is volatile status register write instruction and status
register is default non-volatile = 00b
Bit 2 = Program buffer > 64 bytes = 1
Bits 1:0 = Uniform 4 KB erase is supported through out the device
= 01b
20h
Bits 15:8 = Uniform 4 KB erase instruction = 20h
FBh
Bit 23 = Unused = 1b
Bit 22 = Supports QOR (1-1-4)read, Yes = 1b
Bit 21 = Supports QIO (1-4-4) read, Yes = 1b
Bit 20 = Supports DIO (1-2-2) read, Yes = 1b
Bit19 = Supports DDR, Yes = 1b
Bit 18:17 = Number of address bytes, 3 or 4 = 01b
Bit 16 = Supports fast read SIO and DIO Yes = 1b
FFh
Bits 31:24 = Unused = FFh
FFh
Density in bits, zero based,
64 Mb = 03FFFFFFh
00h
01h
02h
JEDEC basic
flash
parameter
Dword-1
03h
04h
05h
06h
07h
JEDEC basic
flash
parameter
Dword-2
08h
09h
0Ah
JEDEC basic
flash
parameter
Dword-3
0Bh
0Ch
0Dh
0Eh
0Fh
Datasheet
JEDEC basic
flash
parameter
Dword-4
FFh
FFh
03h
64Mb
48h
Bits 7:5 = number of QIO mode cycles = 010b
Bits 4:0 = number of fast read QIO Dummy cycles = 01000b for
default latency code
EBh
Fast Read QIO instruction code
08h
Bits 23:21 = number of quad out mode cycles = 000b
Bits 20:16 = number of quad out dummy cycles = 01000b for
default latency code
6Bh
Quad out instruction code
08h
Bits 7:5 = number of dual out mode cycles = 000b
Bits 4:0 = number of dual out dummy cycles = 01000b for default
latency code
3Bh
Dual out instruction code
88h
Bits 23:21 = number of dual I/O mode cycles = 100b
Bits 20:16 = number of dual I/O dummy cycles = 01000b for
default latency code
BBh
Dual I/O instruction code
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Software interface reference
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B (continued)
SFDP parameter
relative byte
address
SFDP Dword
name
Data
10h
11h
12h
JEDEC basic
flash
parameter
Dword-5
13h
14h
15h
16h
17h
JEDEC basic
flash
parameter
Dword-6
18h
19h
1Ah
JEDEC basic
flash
parameter
Dword-7
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
Datasheet
JEDEC basic
flash
parameter
Dword-8
JEDEC basic
flash
parameter
Dword-9
Description
FEh
Bits 7:5 RFU = 111b
Bit 4 = QPI supported = 1b
Bits 3:1 RFU = 111b
Bit 0 = Dual all not supported = 0b
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:16 = RFU = FFh
FFh
Bits 31:24 = RFU = FFh
FFh
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of dual all mode cycles = 111b
Bits 20:16 = number of dual all dummy cycles = 11111b
FFh
Dual all instruction code
FFh
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
48h
Bits 23:21 = number of QPI mode cycles = 010b
Bits 20:16 = number of QPI dummy cycles = 01000b for default
latency code
EBh
QPI fast read instruction code (Same as QIO when QPI is enabled)
0Ch
Sector type 1 size 2^N bytes = 4 KB = 0Ch (for uniform 4KB)
20h
Sector type 1 instruction
0Fh
Sector type 2 size 2^N bytes = 32 KB = 0Fh (for uniform 32KB)
52h
Sector type 2 instruction
10h
Sector type 3 size 2^N bytes = 64 KB = 10h (for uniform 64KB)
D8h
Sector type 3 instruction
00h
Sector type 4 size 2^N bytes = not supported = 00h
FFh
Sector type 4 instruction = not supported = FFh
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SPI multi-I/O, 3.0 V
Software interface reference
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B (continued)
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
24h
31h
25h
92h
26h
0Dh
Bits 31:30 = Sector type 4 erase, typical time units (00b: 1 ms, 01b:
16 ms, 10b: 128 ms, 11b: 1 s) = RFU = 11b
Bits 29:25 = Sector type 4 erase, typical time count = RFU =
1_1111b (typ erase time = count + 1 * units = RFU = 11111)
Bits 24:23 = Sector type 3 erase, typical time units (00b: 1 ms, 01b:
16 ms, 10b: 128 ms, 11b: 1 s) = 16 ms = 10b
Bits 22:18 = Sector type 3 erase, typical time count = 0_0011b (typ
erase time = count + 1 * units = 4 * 128 ms = 512 ms)
Bits 17:16 = Sector type 2 erase, typical time units (00b: 1 ms, 01b:
16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b
Bits 15:11 = Sector type 2 erase, typical time count = 1_0010b
(typ erase time = count + 1 * units = 19 * 16 ms = 304 ms)
Bits 10:9 = Sector type 1 erase, typical time units (00b: 1 ms, 01b:
16 ms, 10b: 128 ms, 11b: 1 s) = 16 ms = 01b
Bits 8:4 = Sector type 1 erase, typical time count = 0_0011b
(typ erase time = count + 1 * units = 4 * 16 ms = 64 ms)
Bits 3:0 = Count = (max erase time / (2 * typical erase time)) – 1 =
0001b
Multiplier from typical erase time to maximum erase time = 4x
multiplier
Max erase time = 2 * (Count + 1) * typ erase time
27h
JEDEC basic
flash
parameter
Dword-10
FFh
Binary fields: 11-11111-10-00011-01-10010-01-00011-0001
Nibble format: 1111_1111_0000_1101_1001_0010_0011_0001
Hex format: FF_0D_92_31
Datasheet
135
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Software interface reference
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B (continued)
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
28h
81h
29h
66h
Bits 23 = Byte program typical time, additional byte units
(0b:1 µs, 1b:8 µs) = 1 µs = 0b
Bits 22:19 = Byte program typical time, additional byte count,
(count + 1) * units, count = 1001b, (typ Program time = count + 1
* units = 10 * 1 µs = 10 µs
Bits 18 = Byte program typical time, first byte units
(0b:1 µs, 1b:8 µs) = 1 µs = 1b
Bits 17:14 = Byte program typical time, first byte count,
(count + 1) * units, count = 1001b, (typ program time =
count + 1 * units = 10 * 8 µs = 80 µs
Bits 13 = Page program typical time units (0b:8 µs, 1b:64 µs) =
64 µs = 1b
Bits 12:8 = Page program typical time count, (count + 1) * units,
count = 00110b, (typ Program time = count + 1 * units = 7 * 64 µs
= 450 µs)
Bits 7:4 = N = 1000b, page size= 2^N = 256B page
Bits 3:0 = Count = 0001b = (max page program time / (2 * typ page
program time)) – 1
Multiplier from typical page program time to maximum page
program time = 4x multiplier
Max page program time = 2 * (count + 1) * typ page program time
2Ah
JEDEC basic
flash
parameter
Dword-11
4Eh
Binary fields: 0-1001-1-1001-1-00110-1000-0001
Nibble format: 0100_1110_0110_0110_1000_0001
Hex format: 4E_66_81
2Bh
CDh
64Mb
Datasheet
64 Mb = 1100_1101 = CD
Bit 31 Reserved = 1b
Bits 30:29 = Chip erase, typical time units
(00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b
Bits 28:24 = Chip erase, typical time count, (count + 1) * units,
count = 01100b, (typ program time = count + 1 * units = 14 * 4 s =
56 s
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Software interface reference
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B (continued)
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
2Ch
CCh
2Dh
83h
2Eh
18h
Bit 31 = Suspend and resume supported = 0b
Bits 30:29 = Suspend in-progress erase max latency units
(00b: 128 ns, 01b: 1 µs, 10b: 8 µs, 11b: 64 µs) = 8 µs = 10b
Bits 28:24 = Suspend in-progress erase max latency count =
00100b, max erase suspend latency = count + 1 * units = 5 * 8 µs
= 40 µs
Bits 23:20 = Erase resume to suspend interval count = 0001b,
interval = count + 1 * 64 µs = 2 * 64 µs = 128 µs
Bits 19:18 = Suspend in-progress program max latency units
(00b: 128 ns, 01b: 1 µs, 10b: 8 µs, 11b: 64 µs) = 8 µs = 10b
Bits 17:13 = Suspend in-progress program max latency count =
00100b, max erase suspend latency = count + 1 * units = 5 * 8 µs
= 40 µs
Bits 12:9 = Program resume to suspend interval count = 0001b,
interval = count + 1 * 64 µs = 2 * 64 µs = 128 µs
Bit 8 = RFU = 1b
Bits 7:4 = Prohibited operations during erase suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not
permitted)
+ xx0xb: May not initiate a page program anywhere
+ x1xxb: May not initiate a read in the erase suspended sector size
+ 1xxxb: The erase and program restrictions in bits 5:4 are
sufficient
= 1100b
Bits 3:0 = Prohibited operations during program suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not
permitted)
+ xx0xb: May not initiate a new page program anywhere (program
nesting not permitted)
+ x1xxb: May not initiate a read in the program suspended page
size
+ 1xxxb: The erase and program restrictions in bits 1:0 are
sufficient
= 1100b
2Fh
JEDEC Basic
Flash
Parameter
Dword-12
44h
Binary fields: 0-10-00100-0001-10-00100-0001-1-1100-1100
Nibble format: 0100_0100_0001_1000_1000_0011_1100_1100
Hex format: 44_18_83_CC
30h
31h
32h
33h
Datasheet
JEDEC basic
flash
parameter
Dword-13
7Ah
75h
7Ah
75h
Bits 31:24 = Erase suspend instruction = 75h
Bits 23:16 = Erase resume instruction = 7Ah
Bits 15:8 = Program suspend instruction = 75h
Bits 7:0 = Program resume instruction = 7Ah
137
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Software interface reference
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B (continued)
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
34h
F7h
35h
A2h
36h
D5h
Bit 31 = Deep power down supported = supported = 0
Bits 30:23 = Enter deep power down instruction = B9h =
1011_1001b
Bits 22:15 = Exit deep power down instruction = ABh =
1010_1011b
Bits 14:13 = Exit deep power down to next operation delay units
= (00b: 128 ns, 01b: 1 µs, 10b: 8 µs, 11b: 64 µs) = 1 µs = 01b
Bits 12:8 = Exit deep power down to next operation delay count
= 00010b, Exit deep power down to next operation delay =
(count + 1) * units = 3 * 1 µs = 3 µs
Bits 7:4 = RFU = Fh
Bit 3:2 = Status Register polling device busy = 01b: Legacy status
polling supported = Use legacy polling by reading the Status
Register with 05h instruction and checking WIP bit[0] (0 = ready;
1 = busy).
Bits 1:0 = RFU = 11b
37h
JEDEC basic
flash
parameter
Dword-14
5Ch
Binary fields: 0-10111001-10101011-01-00010-1111-01-11
Nibble format: 0101_1100_1101_0101_1010_0010_1111_0111
Hex format: 5C_D5_A2_F7
38h
22h
39h
F6h
3Ah
5Dh
3Bh
JEDEC basic
flash
parameter
Dword-15
FFh
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP disable = not supported = 0b
Bits 22:20 = quad enable requirements
= 101b: QE is bit 1 of the status register 2. Status register 1 is read
using Read Status instruction 05h. Status register 2 is read using
instruction 35h. QE is set via Write Status instruction 01h with two
data bytes where bit 1 of the second byte is one. It is cleared via
write status with two data bytes where bit 1 of the second byte is
zero.
Bits 19:16 0-4-4 mode entry method
= xxx1b: mode bits[7:0] = A5h Note: QE must be set prior to using
this mode + x1xxb: mode bits[7:0] = Axh + 1xxxb: RFU = 1101b
Bits 15:10 0-4-4 mode exit method = xx_xxx1b: mode bits[7:0] =
00h will terminate this mode at the end of the current read
operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0–DQ3 for 8 clocks.
This will terminate the mode prior to the next read operation.
+ 11_x1xx: RFU= 111101
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences
= 0_0010b: issue instruction 38h
Bits 3:0 = 4-4-4 mode disable sequences
= 0010b: 4-4-4 issues F5h instruction
Binary fields: 11111111-0-101-1101-111101-1-00010-0010
Nibble format: 1111_1111_0101_1101_1111_0110_0010_0010
Hex format: FF_5D_F6_22
Datasheet
138
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Software interface reference
Table 41
Basic SPI flash parameter, JEDEC SFDP Rev B (continued)
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
3Ch
E8h
3Dh
50h
3Eh
F8h
Bits 31:24 = Enter 4-byte addressing
= xxxx_xxx1b: issue instruction B7 (preceding write enable not
required
= xxxx_1xxxb: 8-bit Volatile Bank Register used to define A[30:24]
bits. MSb (bit[7]) is used to enable/disable 4-byte Address mode.
When MSb is set to ‘1’, 4-byte Address mode is active and A[30:24]
bits are don’t care. Read with instruction 16h. Write instruction is
17h with 1 byte of data. When MSb is cleared to ‘0’, select the
active 128 Mb segment by setting the appropriate A[30:24] bits
and use 3-byte addressing.
+ xx1x_xxxxb: Supports dedicated 4-byte address instruction set.
Consult vendor data sheet for the instruction set definition or
look for 4-byte address parameter table.
+ 1xxx_xxxxb: Reserved = 10100001b
Bits 23:14 = Exit 4-byte addressing
= xx_xxxx_xxx1b:issue instruction E9h to exit 4-byte Address
mode (write enable instruction 06h is not required)
= xx_xxxx_1xxxb: 8-bit Volatile Bank Register used to define
A[30:24] bits. MSb (bit[7]) is used to enable/disable 4-byte
Address mode. When MSb is cleared to ‘0’, 3-byte Address mode
is active and A30:A24 are used to select the active 128 Mb memory
segment. Read with instruction 16h. Write instruction is 17h, data
length is 1 byte.
+ xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved
= 1111100001b
Bits 13:8 = Soft reset and rescue sequence support
= x1_xxxxb: issue reset enable instruction 66h, then issue reset
instruction 99h. The reset enable, reset sequence may be issued
on 1,2, or 4 wires depending on the device operating mode =
010000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-volatile Register and write enable
instruction for Status Register 1 = xxx_1xxxb:
Non-volatile/Volatile Status register 1 powers-up to last written
value in the Non-volatile Status register, use instruction 06h to
enable write to Non-volatile Status register. Volatile Status
register may be activated after power-up to override the
Non-volatile Status register, use instruction 50h to enable write
and activate the volatile status register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1101000b
3Fh
JEDEC basic
flash
parameter
Dword-16
A1h
Binary fields: 10100001-1111100001-010000-1-1101000
Nibble format: 1010_0001_1111_1000_0101_0000_1110_1000
Hex format: A1_F8_60_E8
Datasheet
139
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2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Software interface reference
10.1.4
JEDEC SFDP 4-byte address instruction table
Table 42
4-byte address instruction, JEDEC SFDP Rev B
SFDP parameter
relative byte
address
SFDP Dword
name
Data
Description
40h
FBh
41h
8Eh
42h
F3h
Supported = 1, not supported = 0
Bits 31:20 = RFU = FFFh
Bit 19 = Support for Non-volatile Individual Sector Lock Write
command, Instruction = E3h = 0
Bit 18 = Support for Non-volatile Individual Sector Lock Read
command, Instruction = E2h = 0
Bit 17 = Support for Volatile Individual Sector Lock Write
command, Instruction = E1h = 1
Bit 16 = Support for Volatile Individual Sector lock Read
command, Instruction = E0h = 1
Bit 15 = Support for (1-4-4) DTR_Read command, instruction =
EEh = 1
Bit 14 = Support for (1-2-2) DTR_Read command, instruction =
BEh = 0
Bit 13 = Support for (1-1-1) DTR_Read command, instruction =
0Eh = 0
Bit 12 = Support for Erase command – Type 4 = 0
Bit 11 = Support for Erase command – Type 3 = 1
Bit 10 = Support for Erase command – Type 2 = 1
Bit 9 = Support for Erase command – Type 1 = 1
Bit 8 = Support for (1-4-4) Page Program command,
instruction = 3Eh = 0
Bit 7 = Support for (1-1-4) Page Program command,
instruction = 34h = 1
Bit 6 = Support for (1-1-1) Page Program command,
instruction = 12h = 1
Bit 5 = Support for (1-4-4) FAST_READ command, instruction =
ECh = 1
Bit 4 = Support for (1-1-4) FAST_READ command, instruction =
6Ch = 1
Bit 3 = Support for (1-2-2) FAST_READ command, instruction =
BCh = 1
Bit 2 = Support for (1-1-2) FAST_READ command, instruction =
3Ch = 0
Bit 1 = Support for (1-1-1) FAST_READ command, instruction =
0Ch = 1
Bit 0 = Support for (1-1-1) READ command, Instruction = 13h = 1
43h
JEDEC 4-byte
address
instructions
parameter
Dword-1h
FFh
Nibble format: 1111_1111_1111_0011_1000_1110_1111_1011
Hex format: FF_F3_8E_FB
44h
45h
46h
47h
Datasheet
JEDEC4-byte
address
instructions
parameter
Dword-2h
21h
52h
DCh
FFh
Bits 31:24 = FFh = Instruction for erase type 4: RFU
Bits 23:16 = DCh = Instruction for erase type 3 block
Bits 15:8 = 52h = Instruction for erase type 2 half block
Bits 7:0 = 21h = Instruction for erase type 1 sector
140
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Software interface reference
10.2
Device ID address map
10.2.1
Field definitions
Table 43
Manufacturer device type
Byte address
Data
00h
01h
Manufacturer ID for Infineon
01h
60h
Device ID most significant byte - Memory interface type
02h
17h (64 Mb)
Device ID least significant byte - Density and features
03h
Undefined
Reserved for future use
Table 44
Unique device ID
Byte address
Data
00h to 07
8-byte unique Device ID
10.3
Description
Description
64-bit unique ID number.
See section “Device Unique ID” on page 28.
Initial delivery state
The device is shipped from Infineon with non-volatile bits set as follows:
• The entire memory array is erased: all bits are set to 1 (each byte contains FFh).
• The Security Region address space has all bytes erased to FFh.
• The SFDP address space contains the values as defined in the description of the SFDP address space.
• The ID address space contains the values as defined in the description of the ID address space.
• The Status Register 1 non-volatile contains 00h (all SR1NV bits are cleared to 0’s).
• The Configuration Register 1 non-volatile contains 00h.
• The Configuration Register 2 non-volatile contains 60h.
• The Configuration Register 3 non-volatile contains 78h.
• The Password Register contains FFFFFFFF–FFFFFFFFh
• The IRP Register bits are FFFDh for standard part and FFFFh for high security part.
• The PRPR Register bits are FFFFFFh
Datasheet
141
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2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
11
Electrical specifications
11.1
Absolute maximum ratings[59]
Storage temperature plastic packages............................................................................................–65°C to +150°C
Ambient temperature with power applied......................................................................................–65°C to +125°C
VCC......................................................................................................................................................–0.5 V to +4.0 V
Input voltage with respect to ground (VSS)[58]................................................................................–0.5 V to VCC + 0.5 V
Output short circuit current[57]........................................................................................................100 mA
11.2
Latchup characteristics
Table 45
Latchup specification[60]
Description
Min
Max
Unit
Input voltage with respect to VSS on all input only connections
–1.0
VCC + 1.0
V
Input voltage with respect to VSS on all I/O connections
–1.0
VCC + 1.0
V
VCC current
–100
+100
mA
11.3
Thermal resistance
Table 46
Thermal resistance
Parameter Description Test condition SL3016 SOC008 FAB024 FAC024 WND008 UNF008 Unit
Theta JA
Theta JB
Theta JC
Thermal
resistance
(junction to
ambient)
Test conditions
follow
standard test
methods and
Thermal procedures for
resistance measuring
(junction to thermal
impedance in
board)
accordance
Thermal with
resistance EIA/JESD51.
(junction to with still air
case)
(0 m/s).
45.7
65.8
46.9
46.9
32.9
34.0
°C/W
26.6
39.6
30.4
30.4
9.1
8.0
°C/W
13.1
33.8
20.9
20.9
25.2
28.0
°C/W
Notes
57.See “Input signal overshoot” on page 143 for allowed maximums during signal transition.
58.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.
59.Stresses above those listed under “Absolute maximum ratings[59]” on page 142 may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.
60.Excludes power supply VCC. Test conditions: VCC = 3.0 V, one connection at a time tested, connections not
being tested are at VSS.
Datasheet
142
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
11.4
Operating ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
11.4.1
Power supply voltages
VCC ……................................................................................................................................................. 2.7 V to 3.6 V
11.4.2
Temperature ranges
Parameter
Symbol
Ambient temperature
TA
11.4.3
Spec
Devices
Unit
Min
Max
Industrial (I)
–40
+85
°C
Industrial Plus (V)
–40
+105
°C
Automotive, AEC-Q100 grade 3 (A)
–40
+85
°C
Automotive, AEC-Q100 grade 2 (B)
–40
+105
°C
Automotive, AEC-Q100 grade 1 (M)
–40
+125
°C
Input signal overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage
transitions, inputs or I/Os may overshoot VSS to –1.0 V or overshoot to VCC + 1.0 V, for periods up to 20 ns.
VSS to VCC
–1.0
V
< = 20 ns
Figure 129
Maximum negative overshoot waveform
< = 20 ns
VCC + 1.0 V
VSS to VCC
Figure 130
Datasheet
Maximum positive overshoot waveform
143
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
11.5
Power-up and power-down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC)
until VCC reaches the correct value as follows:
• VCC (min) at power-up, and then for a further delay of tPU
• VSS at power-down
User is not allowed to enter any command until a valid delay of tPU has elapsed after the moment that VCC rises
above the minimum VCC threshold. See Figure 131. However, correct operation of the device is not guaranteed
if VCC returns below VCC (min) during tPU. No command should be sent to the device until the end of tPU.
The device draws IPOR during tPU. After power-up (tPU), the device is in Standby mode, draws CMOS standby
current (ISB), and the WEL bit is reset.
During power-down or if supply voltage drops below VCC(cut-off), the supply voltage must stay below VCC(low)
for a period of tPD for the part to initialize correctly on power-up. See Figure 132. If during a voltage drop the VCC
stays above VCC(cut-off) the part will stay initialized and will work correctly when VCC is again above VCC(min). In
the event power-on reset (POR) did not complete correctly after power up, the assertion of the RESET# signal or
receiving a Software Reset command (RSTEN 66h followed by RST 99h) will restart the POR process.
If VCC drops below the VCC (Cut-off) during an embedded program or erase operation the embedded operation may
be aborted and the data in that memory area may be incorrect.
Normal precautions must be taken for supply rail decoupling to stabilize the VCC supply at the device. Each device
in a system should have the VCC rail decoupled by a suitable capacitor close to the package supply connection
(this capacitor is generally of the order of 0.1 µF).
Table 47
Power-up / power-down voltage and timing
Symbol
VCC (min)
VCC (cut-off)
VCC (low)
Parameter
VCC (minimum operation voltage)
Min
Max
Unit
2.7
–
V
[61]
VCC (cut off where re-initialization is needed)
2.4
VCC (low voltage for initialization to occur)
1.0
tPU
VCC(min) to read operation
tPD
VCC(low) time
[62]
–
–
–
300
10.0
–
µs
Notes
61.Re-initialization is needed if VCC drops below 2.4 V.
62.VCC need to go below 1.0 V for initialization to occur.
Datasheet
144
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
VCC (max)
VCC (min)
tPU
Full device access
Time
Figure 131
Power-up[63, 64]
VCC (max)
No device access allowed
VCC (min)
tPU
VCC (cut-off)
VCC (low)
tPD
Time
Figure 132
Power-down and voltage drop
Notes
63.Re-initialization is needed if VCC drops below 2.4 V.
64.VCC need to go below 1.0 V for initialization to occur.
Datasheet
145
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
11.6
DC characteristics
Table 48
DC characteristics — Operating temperature range –40°C to +85°C
Symbol
Parameter
Test conditions
Min
Typ[65]
Max
Unit
VIL
Input low voltage
–0.5
–
0.3 × VCC
V
VIH
Input high voltage
0.7 × VCC
–
VCC + 0.4
V
VOL
Output low voltage
IOL = 0.1 mA, VCC = VCC min
–
0.2
V
VOH
Output high voltage
IOH = –0.1 mA
ILI
Input leakage current
VCC – 0.2
–
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
ILO
Output leakage current VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
ICC1
Active power supply
current (READ)[66]
–
10
10
10
15
20
20
15
17
15
15
15
20
25
30
20
25
ICC2
Active power supply
CS# = VCC
current (page program)
–
17
25
ICC3
Active power supply
CS# = VCC
current (WRR or WRAR)
–
11
20
ICC4
Active power supply
current (SE)
CS# = VCC
–
17
25
ICC5
Active power supply
current (HBE, BE)
CS# = VCC
–
15
25
ISB
Standby current
RESET#, CS# = VCC;
SI, SCK = VCC or VSS: SPI, dual I/O
and Quad I/O modes
–
20
30
RESET#, CS# = VCC;
SI, SCK = VCC or VSS: QPI mode
–
35
55
Serial SDR @ 5 MHz
Serial SDR @ 10 MHz
Serial SDR @ 20 MHz
Serial SDR @ 50 MHz
Serial SDR @ 108 MHz
QIO/QPI SDR @ 108 MHz
QIO/QPI DDR @ 30 MHz
QIO/QPI DDR @ 54 MHz
V
±2
±2
IDPD
Deep power down
current
–
2
20
IPOR[67]
RESET#, CS# = VCC,
VIN = GND or VCC
Power on reset current
RESET#, CS# = VCC;
SI, SCK = VCC or VSS
–
3
5
µA
µA
mA
mA
mA
mA
mA
µA
µA
µA
mA
Notes
65.Typical values are at TAI = 25°C and VCC = 3.0 V.
66.Outputs unconnected during read data return. Output switching current is not included.
67.In-rush/peak current up to 25 mA during POR with current specified represent time average for tPU duration.
Datasheet
146
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
Table 49
Symbol
DC characteristics — Operating temperature range –40°C to +105°C
Parameter
Test conditions
Min
Typ[68]
Max
Unit
VIL
Input low voltage
–
–0.5
–
0.3 VCC
V
VIH
Input high voltage
–
0.7 VCC
–
VCC+0.4
V
VOL
Output low voltage
IOL = 0.1 mA, VCC = VCC min
–
0.2
V
VOH
Output high voltage
IOH = –0.1 mA
ILI
Input leakage current
VCC - 0.2
–
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
ILO
Output leakage current VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
ICC1
Active power supply
current (READ)[69]
–
10
10
10
15
20
20
15
17
15
15
20
25
30
30
15
25
ICC2
Active power supply
CS# = VCC
current (page program)
–
17
25
ICC3
Active power supply
CS# = VCC
current (WRR or WRAR)
–
11
20
ICC4
Active power supply
current (SE)
CS# = VCC
–
17
25
ICC5
Active power supply
current (HBE, BE)
CS# = VCC
–
15
25
ISB
Standby current
RESET#, CS# = VCC;
SI, SCK = VCC or VSS: SPI, dual I/O
and Quad I/O modes
–
20
40
RESET#, CS# = VCC;
SI, SCK = VCC or VSS: QPI mode
–
35
70
Deep power down
current
RESET#, CS# = VCC, VIN = GND or
VCC
–
2
30
Power on reset current
RESET#, CS# = VCC;
SI, SCK = VCC or VSS
–
3
7
IDPD
IPOR[70]
Serial SDR @ 5 MHz
Serial SDR @ 10 MHz
Serial SDR @ 20 MHz
Serial SDR @ 50 MHz
Serial SDR @ 108 MHz
QIO/QPI SDR @ 108 MHz
QIO/QPI DDR @ 30 MHz
QIO/QPI DDR @ 54 MHz
V
µA
µA
mA
mA
mA
mA
mA
µA
µA
µA
mA
Notes
68.Typical values are at TAI = 25°C and VCC = 3.0 V.
69.Outputs unconnected during read data return. Output switching current is not included.
70.In-rush/peak current up to 25 mA during POR with current specified represent time average for tPU duration.
Datasheet
147
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
Table 50
DC Characteristics — Operating temperature range –40°C to +125°C
Min
Typ[71]
Max
Unit
–
–0.5
–
0.3 ×
VCC
V
VIH
Input high voltage –
0.7 ×
VCC
–
VCC +
0.4
V
VOL
Output low
voltage
IOL = 0.1 mA, VCC = VCC min
–
0.2
V
VOH
Output high
voltage
IOH = –0.1 mA
ILI
Input leakage
current
ILO
Symbol
Parameter
VIL
Input low voltage
Test conditions
VCC –
0.2
–
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
Output leakage
current
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
ICC1
Active power
supply current
(READ)[72]
Serial SDR @ 5 MHz
Serial SDR @ 10 MHz
Serial SDR @ 20 MHz
Serial SDR @ 50 MHz
Serial SDR @ 108 MHz
QIO/QPI SDR @ 108 MHz
QIO/QPI DDR @ 30 MHz
QIO/QPI DDR @ 54 MHz
–
10
10
10
15
20
20
15
17
15
15
20
25
30
30
15
25
mA
ICC2
Active power
supply current
(Page Program)
CS# = VCC
–
17
25
mA
ICC3
Active power
supply current
(WRR or WRAR)
CS# = VCC
–
11
20
mA
ICC4
Active power
supply current
(SE)
CS# = VCC
–
17
25
mA
ICC5
Active power
supply current
(HBE, BE)
CS# = VCC
–
15
25
mA
ISB
Standby current
RESET#, CS# = VCC;
SI, SCK = VCC or VSS: SPI, dual I/O and
Quad I/O modes
–
20
60
µA
RESET#, CS# = VCC;
SI, SCK = VCC or VSS: QPI mode
–
35
70
µA
Deep power down RESET#, CS# = VCC, VIN = GND or VCC
current
–
2
40
µA
Power on reset
current
–
3
9
mA
IDPD
IPOR[73]
RESET#, CS# = VCC;
SI, SCK = VCC or VSS
V
µA
µA
Notes
71.Typical values are at TAI = 25°C and VCC = 3.0 V.
72.Outputs unconnected during read data return. Output switching current is not included.
73.In-rush/peak current up to 25 mA during POR with current specified represent time average for tPU duration.
Datasheet
148
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Electrical specifications
11.6.1
Active Power and Standby Power modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is HIGH, the device
is disabled, but may still be in an Active Power mode until all program, erase, and write operations have
completed. The device then goes into the Standby Power mode, and power consumption drops to ISB.
11.6.2
Deep Power Down Power mode (DPD)
The Deep Power Down mode is enabled by inputing the command instruction code “B9h” and the power
consumption drops to IDPD. In DPD mode the device responds only to the resume from DPD command (RES ABh)
or Hardware reset (RESET# and IO3 / RESET#). All other commands are ignored during DPD mode.
Datasheet
149
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12
Timing specifications
12.1
Key to switching waveforms
Input
Valid at logic high or low
High Impedance
Any change permitted
Logic high
Logic low
Valid at logic high or low
High Impedance
Changing, state unknown
Logic high
Logic low
Symbol
Output
Figure 133
Waveform element meanings
12.2
AC test conditions
Device
under
test
CL
Figure 134
Test setup
Table 51
AC measurement conditions
Symbol
Parameter
CL
Load capacitance
–
–
–
Input pulse voltage
Min
Max
–
15 / 30
0.2 × VCC
Unit
[74]
pF
0.8 × VCC
Input timing ref Voltage
0.5 × VCC
Output timing ref voltage
0.5 × VCC
V
Notes
74.Load capacitance depends on the operation frequency or mode of operation.
75.AC characteristics tables assume clock and data signals have the same slew rate (slope). See “SDR AC
characteristics[79]” on page 154 note 84 for slew Rates at operating frequency’s.
Input levels
Output levels
VCC + 0.4 V
0.8 x VCC
0.5 x VCC
VCC - 0.2 V
Timing reference level
0.2 x VCC
0.2 V
- 0.5 V
Figure 135
Datasheet
Input, output, and timing reference levels
150
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12.2.1
Capacitance characteristics
Table 52
Capacitance
Symbol
Parameter
Test conditions
Min
Max
Unit
CIN
Input capacitance (applies to SCK, CS#,
RESET#, IO3 / RESET#)
1 MHz
–
8
pF
COUT
Output capacitance (applies to All I/O)
1 MHz
–
8
pF
12.3
Reset
If a hardware reset is initiated during a erase, program or writing of a register operation the data in that sector,
page or register is not stable, the operation that was interrupted needs to be initiated again. If a hardware reset
is initiated during a software reset operation, the hardware reset might be ignored.
12.3.1
Power-on (cold) reset
The device executes a power-on reset (POR) process until a time delay of tPU has elapsed after the moment that
VCC rises above the minimum VCC threshold. See Figure 131 and Table 47. The device must not be selected (CS#
to go HIGH with VCC) during power-up (tPU), i.e. no commands may be sent to the device until the end of tPU.
RESET# and IO3 / RESET# reset function is ignored during POR. If RESET# or IO3 / RESET# is LOW during POR and
remains low through and beyond the end of tPU, CS# must remain HIGH until tRH after RESET# and IO3 / RESET#
returns HIGH. RESET# and IO3 / RESET# must return HIGH for greater than tRS before returning low to initiate a
hardware reset.
The IO3 / RESET# input functions as the RESET# signal when CS# is HIGH for more than tCS time or when Quad or
QPI mode is not enabled CR1V[1] = 0 or CR2V[3] = 0.
VCC
tPU
RESET#
If RESET# is low at tPU end
tRH
CS#
Figure 136
CS# must be high at tPU end
Reset LOW at the end of POR
VCC
tPU
RESET#
If RESET# is high at tPU end
tPU
CS#
Figure 137
Datasheet
CS# may stay high or go low at tPU end
Reset HIGH at the end of POR
151
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
VCC
tPU
tRS
RESET#
tPU
CS#
Figure 138
POR followed by hardware reset
12.3.2
RESET # and IO3 / RESET# input initiated hardware (warm) reset
The RESET# and IO3 / RESET# inputs can function as the RESET# signal. Both inputs can initiate the reset
operation under conditions.
The RESET# input initiates the reset operation when transitions from VIH to VIL for > tRP, the device will reset
register states in the same manner as power-on reset but, does not go through the full reset process that is
performed during POR. The hardware reset process requires a period of tRPH to complete. The RESET# input is
available only on the SOIC 16 lead and BGA ball packages.
The IO3 / RESET# input initiates the reset operation under the following when CS# is HIGH for more than tCS time
or when quad or QPI mode is not enabled CR1V[1] = 0 or CR2V[3] = 0. The IO3 / RESET# input has an internal pull-up
to VCC and may be left unconnected if quad or QPI mode is not used. The tCS delay after CS# goes HIGH gives the
memory or host system time to drive IO3 HIGH after its use as a quad or QPI mode I/O signal while CS# was LOW.
The internal pull-up to VCC will then hold IO3 / RESET# HIGH until the host system begins driving IO3 / RESET#.
The IO3 / RESET# input is ignored while CS# remains HIGH during tCS, to avoid an unintended reset operation. If
CS# is driven LOW to start a new command, IO3 / RESET# is used as IO3.
When the device is not in quad or QPI mode or, when CS# is HIGH, and IO3 / RESET# transitions from VIH to VIL for
> tRP, following tCS, the device will reset register states in the same manner as POR but, does not go through the
full reset process that is performed during POR.
The hardware reset process requires a period of tRPH to complete. If the POR process did not complete correctly
for any reason during power-up (tPU), RESET# going LOW will initiate the full POR process instead of the hardware
reset process and will require tPU to complete the POR process.
The Software Reset command (RSTEN 66h followed by RST 99h) is independent of the state of RESET # and IO3 /
RESET#. If RESET# and IO3 / RESET# is HIGH or unconnected, and the software reset instructions are issued, the
device will perform software reset.
Additional notes:
• If both RESET# and IO3 / RESET# input options are available use only one reset option in your system. IO3 /
RESET# input reset operation can be disable by setting CR2NV[7] = 0 (See Table 12) setting the IO3_RESET to
only operate as IO3. The RESET# input can be disable by not connecting or tying the RESET# input to VIH. RESET#
and IO3 / RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
• When IO3 / RESET# is driven LOW for at least a minimum period of time (tRP), following tCS, the device terminates
any operation in progress, makes all outputs high impedance, and ignores all read/write commands for the
duration of tRPH. The device resets the interface to STANDBY state.
• If Quad or QPI mode and the IO3 / RESET# feature are enabled, the host system should not drive IO3 low during
tCS, to avoid driver contention on IO3. Immediately following commands that transfer data to the host in quad
or QPI mode, e.g. Quad I/O read, the memory drives IO3 / RESET# HIGH during tCS, to avoid an unintended reset
operation. Immediately following commands that transfer data to the memory in Quad mode, e.g. page
program, the host system should drive IO3 / RESET# HIGH during tCS, to avoid an unintended reset operation.
• If Quad or QPI mode is not enabled, and if CS# is LOW at the time IO3 / RESET# is asserted LOW, CS# must return
HIGH during tRPH before it can be asserted low again after tRH.
Datasheet
152
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
Hardware reset parameters[76, 77, 78]
Table 53
Parameter
Description
Limit
Time
Unit
tRS
Reset setup - prior reset end and RESET# HIGH
before RESET# LOW
Min
50
ns
tRPH
Reset pulse hold - RESET# LOW to CS# LOW
Min
100
µs
tRP
RESET# pulse width
Min
200
ns
tRH
Reset hold - RESET# HIGH before CS# LOW
Min
150
ns
Notes
76.RESET# and IO3 / RESET# Low is ignored during power-up (tPU). If RESET# is asserted during the end of tPU,
the device will remain in the reset state and tRH will determine when CS# may go LOW.
77.If quad or QPI mode is enabled, IO3 / RESET# Low is ignored during tCS.
78.Sum of tRP and tRH must be equal to or greater than tRPH.
tRP
RESET#
Any prior reset
tRH
tRH
tRPH
tRS
tRPH
CS#
Figure 139
Hardware reset using RESET# input
tRP
IO3_RESET#
Any prior reset
tRH
tRPH
tRH
tRS
tRPH
CS#
Figure 140
Hardware reset when Quad or QPI mode is not enabled and IO3 / RESET# is enabled
tDIS
IO3_RESET#
tRP
Reset Pulse
tRH
tCS
CS#
Figure 141
Datasheet
tRPH
Prior access using IO3 for data
Hardware reset when Quad or QPI mode and IO3 / RESET# are enabled
153
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12.4
SDR AC characteristics
Table 54
SDR AC characteristics[79]
Symbol
Parameter
Min
Max
Unit
FSCK, R
SCK clock frequency for READ and 4READ instructions
DC
50
MHz
FSCK, C
SCK Clock frequency for the following dual and quad
commands: QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR
DC
108
MHz
PSCK
SCK clock period
1/ FSCK
–
MHz
tWH, tCH
Clock high time
50% PSCK – 5%
–
ns
tWL, tCL
Clock Low time
50% PSCK – 5%
–
ns
tCRT, tCLCH Clock rise time (slew rate)
0.1
–
V/ns
tCFT, tCHCL Clock fall time (slew rate)
0.1
–
V/ns
CS# high time (any read instructions)
20
–
ns
CS# high time (All other non-read instructions)
50
–
ns
tCSS
CS# active setup time (relative to SCK)
3
–
ns
tCSH
CS# active hold time (relative to SCK)
5
–
ns
tSU
Data in setup time
3
–
ns
tHD
Data in hold time
2
–
ns
8[80]
[81]
ns
[80]
[80]
tCS
tV
Clock low to output valid
6
tHO
Output hold time
tDIS
Output disable time
Output disable time (when reset feature and Quad
mode are both enabled)
–
8
20[83]
ns
tWPS
WP# setup time[84]
20
–
ns
tWPH
WP# hold time
100
–
ns
TDP
CS# High to Deep Power Down mode
–
3
µs
TRES
CS# High to release from Deep Power Down mode
–
5
µs
tQEN
QIO or QPI Enter mode, time needed to issue next
command
–
1.5
tQEXN
QIO or QPI Exit mode, time needed to issue next
command
–
1
1
[82]
[84]
ns
µs
µs
Notes
79.tCRT, tCLCH clock rise and fall slew rate for fast clock (108 MHz) min is 1.5 V/ns and for slow clock (50 MHz)
min is 1.0 V/ns.
80.Full VCC range and CL = 30 pF.
81.Full VCC range and CL = 15 pF.
82.Output HI-Z is defined as the point where data is no longer driven.
83.tDIS require additional time when the reset feature and Quad mode are enabled (CR2V[7] = 1 and CR1V[1] = 1).
84.Only applicable as a constraint for WRR or WRAR instruction when SRP0 is set to a 1.
Datasheet
154
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12.4.1
Clock timing
PSCK
tCL
tCH
VIH min
VCC / 2
VIL max
tCFT
tCRT
Figure 142
Clock timing
12.4.2
Input / output timing
tCS
CS#
tCSH
tCSS
SCK
tSU
tHD
SI_IO0
MSb IN
LSb IN
SO
Figure 143
SPI single bit input timing
tCS
CS#
SCK
SI
tV
SO
Figure 144
Datasheet
tHO
tDIS
MSb OUT
LSb OUT
SPI single bit output timing
155
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
tCS
CS#
tCSH
tCSS
SCLK
tSU
tHD
IO
Figure 145
MSB IN
tV
LSB IN
tHO
MSB O.
tV
tDIS
LSB OUT
SDR MIO timing
CS#
tWPS
tWPH
WP#
SCLK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Figure 146
Datasheet
WRR or WRAR Instruction
Input Data
WP# input timing
156
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12.5
DDR AC characteristics
Table 55
DDR AC characteristics 54 MHz operation
Symbol
Parameter
Min
Max
Unit
DC
54
MHz
1/ FSCK
–
ns
FSCK, R
SCK clock frequency for DDR READ instruction
PSCK, R
SCK clock period for DDR READ instruction
tcrt
Clock rise time (slew rate)
1.5
–
V/ns
tcft
Clock fall time (slew rate)
1.5
–
V/ns
tWH, tCH
Clock high time
50% PSCK – 5%
–
ns
tWL, tCL
Clock low time
50% PSCK – 5%
–
ns
tCS
CS# HIGH time (read instructions)
CS# HIGH time (read instructions when reset feature
is enabled)
20
50
–
ns
tCSS
CS# active setup time (relative to SCK)
3
–
ns
tSU
IO in setup time
3
–
ns
tHD
IO in hold time
2
–
ns
tV
Clock low to output valid
–
8[85]
[86]
ns
tHO
Output hold time
1
–
ns
tDIS
Output disable time
Output disable time (when reset feature is enabled)
–
8
20
ns
tO_skew
First IO to last IO data valid time
–
600[87]
ps
6
Notes
85.Full VCC range and CL = 30 pF.
86.Full VCC range and CL = 15 pF.
87.Not tested.
12.5.1
DDR input timing
tCS
CS#
tCSS
SCK
tHD
tSU
tHD
tSU
IO's
Figure 147
Datasheet
Inst. MSb
MSb IN
LSb IN
SPI DDR input timing
157
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12.5.2
DDR output timing
tCS
CS#
SCK
tHO
IO's
tV
tV
tDIS
MSB
LSB
Figure 148
SPI DDR output timing
12.5.3
DDR data valid timing using DLP
pSCK
t CL
t CH
SCK
tIO_SKEW
tV
t OTT
IO Slow
Slow D1
Slow D2
tV
IO Fast
Fast D1
Fast D2
t V_min
t HO
t DV
IO_valid
Figure 149
Datasheet
D1
D2
SPI DDR data valid window
158
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
The minimum data valid window (tDV) and tV minimum can be calculated as follows:
tDV = minimum half clock cycle time (tCLH[88]) - tOTT[90] - tIO_SKEW[89]
tV _min = tHO + tIO_SKEW + tOTT
Example:
• 66 MHz clock frequency = 15 ns clock period, DDR operations and duty cycle of 45% or higher
- tCLH = 0.45 × PSCK = 0.45 × 15 ns = 6.75 ns
• tOTT calculation[91] is bus impedance of 45 ohm and capacitance of 37 pf, with timing reference of 0.75 VCC, the
rise time from 0 to 1 or fall time 1 to 0 is 1.4[94] × RC time constant (Tau)[93] = 1.4 × 1.67 ns = 2.34 ns
- tOTT = rise time or fall time = 2.34 ns.
• Data valid window
- tDV = tCLH – tIO_SKEW – tOTT = 6.75 ns – 600 ps – 2.34ns = 3.81ns
• tV minimum
- tV _min = tHO + tIO_SKEW + tOTT = 1.0 ns + 600 ps + 2.34 ns = 3.94 ns
Notes
88.tCLH is the shorter duration of tCL or tCH.
89.tIO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all
IO signals.
90.tOTT is the maximum output transition time from one valid data value to the next valid data value on each IO.
91.tOTT is dependent on system level considerations including:
a. Memory device output impedance (drive strength).
b. System level parasitics on the IOs (primarily bus capacitance).
c. Host memory controller input VIH and VIL levels at which 0 to 1 and 1 to 0 transitions are recognized.
d. tOTT is not a specification tested by Infineon, it is system dependent and must be derived by the system designer
based on the above considerations.
92.tDV is the data valid window.
93.Tau = R (output impedance) x C (load capacitance).
94.Multiplier of Tau time for voltage to rise to 75% of VCC.
Datasheet
159
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Timing specifications
12.6
Embedded algorithm performance tables
Table 56
Program and erase performance
Symbol
Parameter
Min
Typ[95]
Max
Unit
tW
Non-volatile Register write time
–
220
1200
ms
tPP
Page programming (256 bytes)
–
450
1350
µs
tBP1
Byte programming (first byte)
–
75
90
µs
tBP2
Additional byte programming (after first byte)
–
10
30
µs
tSE
Sector erase time (4 KB physical sectors)
–
65
320
ms
tHBE
Half block erase time (32 KB physical sectors)
–
300
600
ms
tBE
Block erase time (64 KB physical sectors)
–
450
1150
ms
tCE
Chip erase time (S25FL064L)
–
55
150
sec
Notes
95.Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V; checkerboard data
pattern.
96.The programming time for any OTP programming command is the same as tPP. This includes IRPP 2Fh,
PASSP E8h and PDLRNV 43h.
Table 57
Program or erase suspend AC parameters
Parameter
Suspend latency (tSL)
Resume to next suspend (tRNS)
Datasheet
Typical
Max
Unit
Comments
–
40
µs
The time from suspend command until
the WIP bit is 0.
100
–
µs
160
Is the time needed to issue the next
suspend command.
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Ordering information
13
Ordering information
13.1
Ordering part number
The ordering part number is formed by a valid combination of the following:
S25FL 064
L
AB
M
F
I
00 1
Packing type
0 = Tray
1 = Tube
3 = 13” Tape and reel
Model number (additional ordering options)
00 = SOIC16 (300 mil)
01 = SOIC8 (208 mil) / 8-contact WSON footprint
02 = 5x5 ball BGA footprint
03 = 4x6 ball BGA footprint
04 = USON (4 x 4mm)
Temperature range
I = Industrial (–40°C to +85°C)
V = Industrial Plus (–40°C to +105°C)
A = Automotive, AEC-Q100 grade 3 (–40°C to +85°C)
B = Automotive, AEC-Q100 grade 2 (–40°C to +105°C)
M = Automotive, AEC-Q100 grade 1 (–40°C to +125°C)
Package materials[97]
F = Halogen free, lead (Pb)-free
H = Halogen free, lead (Pb)-free
Package type
M = 8-lead SOIC / 16-lead SOIC
N = USON 4 x 4 mm / WSON 5 x 6 mm
B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AB =108 MHz SDR and 54 MHz DDR
Device technology
L = Floating gate process technology
Density
064 = 64 Mb
Device family
S25FL memory 3.0 V-only, SPI flash memory
Note
97.Halogen free definition is in accordance with IEC 61249-2-21 specification.
Datasheet
161
002-12878 Rev. *H
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Ordering information
13.2
Valid combinations — Standard
Valid combinations list configurations planned to be supported in volume for this device. Contact your local sales
office to confirm availability of specific valid combinations and to check on newly released combinations.
Table 58
Valid Combinations — Standard
Base ordering Speed Package and
part number option temperature
S25FL064L
13.3
Model
number
Packing
type
Package marking
AB
MFI, MFV
00, 01
0, 1, 3
FL064L + (temp) + F + (model number)
AB
NFI, NFV
01, 04
0, 1, 3
FL064L + (temp) + F + (model number)
AB
BHI, BHV
02, 03
0, 3
FL064L + (temp) + H + (model number)
Valid combinations — Automotive grade / AEC-Q100
The Table 59 lists configurations that are automotive grade / AEC-Q100 qualified and are planned to be available
in volume. The table will be updated as new combinations are released. Consult your local sales representative
to confirm availability of specific combinations and to check on newly released combinations.
Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade
products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full
compliance with ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require
ISO/TS-16949 compliance.
Table 59
Valid combinations — Automotive grade / AEC-Q100
Base ordering Speed Package and
part number option temperature
S25FL064L
Datasheet
Model number
Packing
type
Package marking
AB
MFA, MFB,
MFM
00, 01
0, 1, 3
FL064L + (temp) + F + (model
number)
AB
NFA, NFB,
NFM
01, 04
0, 1, 3
FL064L + (temp) + F + (model
number)
AB
BHA, BHB,
BHM
02, 03
0, 3
FL064L + (temp) + H + (model
number)
162
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SPI multi-I/O, 3.0 V
Physical diagrams
14
Physical diagrams
NOTES:
DIMENSIONS
SYMBOL
NOM.
MAX.
A
MIN.
1.75
-
2.16
A1
0.05
-
0.25
A2
1.70
-
1.90
b
0.36
-
0.48
b1
0.33
-
0.46
c
0.19
-
0.24
c1
0.15
-
0.20
D
5.28 BSC
E
8.00 BSC
E1
5.28 BSC
e
1.27 BSC
L
L1
1.36 REF
L2
0.25 BSC
0
0°
-
8°
01
5°
-
15°
02
Datasheet
0.76
8
N
Figure 150
-
0.51
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
002-15548 Rev. **
0-8° REF
8-lead SOIC (5.28 × 5.28 × 2.16 mm) SOC008 package outline, 002-15548
163
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Physical diagrams
0.20 C A-B
0.10 C D
2X
0.33 C
0.25 M
C A-B D
0.10 C
0.10 C
DIMENSIONS
SYMBOL
A
Datasheet
MAX.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.35
-
2.65
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
A1
0.10
-
0.30
A2
2.05
-
2.55
b
0.31
-
b1
c
0.27
-
0.48
0.20
-
0.33
c1
0.20
-
0.30
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
Figure 151
NOTES:
NOM.
MIN.
0.40
-
L1
1.40 REF
L2
0.25 BSC
N
16
0.51
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
1.27
h
0.25
-
0.75
0
0°
-
8°
01
5°
-
15°
02
0°
-
-
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
002-15547 Rev. *A
16-lead SOIC (10.30 × 7.50 × 2.65 mm) SO3016/SL3016/SS3016 package outline, 002-15547
164
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Physical diagrams
NOTES:
DIMENSIONS
SYMBOL
MIN.
e
NOM.
MAX.
0.80 BSC.
8
N
ND
N IS THE TOTAL NUMBER OF TERMINALS.
0.40
0.45
b
0.25
0.30
0.35
D2
2.20
2.30
2.40
E2
2.90
3.00
3.10
D
4.00 BSC
E
4.00 BSC
0.55
0.035
0.50
0.00
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
0.35
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
4.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
5.
6.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
7.
JEDEC SPECIFICATION NO. REF: N/A
COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
0.60
0.05
0.152 REF
A3
K
ALL DIMENSIONS ARE IN MILLIMETERS.
2.
3.
4
L
A
A1
1.
0.20
-
-
002-16243 Rev. *A
Figure 152
Datasheet
8-lead DFN ((4.0 × 4.0 × 0.6 mm) UNF008, 2.3 × 3.0 mm E-Pad (Sawn)) package outline,
002-16243
165
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Physical diagrams
NOTES:
DIMENSIONS
SYMBOL
MIN.
e
MAX.
1.27 BSC.
8
N
ND
L
NOM.
4
0.55
0.60
1.
DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
N IS THE TOTAL NUMBER OF TERMINALS.
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
0.65
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
b
0.35
0.40
0.45
D2
3.90
4.00
4.10
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
3.30
3.40
3.50
MAX. PACKAGE WARPAGE IS 0.05mm.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
D
5.00 BSC
6.
7.
E
6.00 BSC
0.75
0.02
8
9
A
A1
0.70
0.00
A3
0.20 REF
K
0.20 MIN.
Figure 153
Datasheet
0.80
0.05
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
10
A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
002-18755 Rev. **
8-lead DFN ((5.0 × 6.0 × 0.8 mm) WND008, 4.0 × 3.4 mm E-Pad (Sawn)) package outline,
002-18755
166
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Physical diagrams
NOTES:
DIMENSIONS
SYMBOL
MIN.
A
-
A1
0.20
NOM.
MAX.
-
1.20
-
-
8.00 BSC
D
1.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
E
6.00 BSC
4.
D1
4.00 BSC
5.
E1
4.00 BSC
MD
5
ME
5
N
24
b
0.35
0.40
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
PARALLEL TO DATUM C.
0.45
7
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
eE
1.00 BSC
eD
1.00 BSC
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
SD
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
SE
0.00 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
"SE" = eE/2.
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
002-15534 Rev. **
Figure 154
Datasheet
24-ball FBGA (8.0 × 6.0 × 1.2 mm) FAB024 package outline, 002-15534
167
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Physical diagrams
NOTES:
DIMENSIONS
SYMBOL
MIN.
A
-
A1
0.25
NOM.
MAX.
1.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
-
1.20
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
-
-
3.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
4.
e
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
8.00 BSC
E
6.00 BSC
D1
5.00 BSC
E1
3.00 BSC
MD
6
ME
4
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
24
b
0.35
0.40
REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
PARALLEL TO DATUM C.
0.45
7
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
eE
1.00 BSC
eD
1.00 BSC
SD
0.50 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
SE
0.50 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
"SE" = eE/2.
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
002-15535 Rev. *A
Figure 155
Datasheet
24-ball FBGA (8.0 × 6.0 × 1.2 mm) FAC024 package outline, 002-15535
168
002-12878 Rev. *H
2023-04-17
64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Revision history
Revision histor y
Document
version
Date
Description of changes
**
2016-07-27
Initial release.
2016-09-26
Changed status from Advance to Preliminary.
Updated Features:
Added Automotive Grade related information.
Updated Data integrity:
Updated Data retention:
Updated Table 38.
Updated Ordering information:
Updated Ordering part number:
Updated details corresponding to “01” under “Model Number (Additional
Ordering Options)”.
Added Automotive Grade related information.
Removed “Valid Combinations”.
Added Valid combinations — Standard.
Added Valid combinations — Automotive grade / AEC-Q100.
Updated Physical diagrams:
Updated SOIC 8-Lead, 208 mil Body Width (SOC008):
Replaced existing spec with 002-15548 **.
Updated USON 4 x 4 mm (UNF008):
Replaced existing spec with 002-16243 **.
Updated Ball Grid Array, 24-ball 6 x 8 mm (FAB024):
Replaced existing spec with 002-15534 **.
Updated Ball Grid Array, 24-ball 6 x 8 mm (FAC024):
Replaced existing spec with 002-15535 **.
Updated Other Resources:
Updated Link to Application Notes:
Updated hyperlinks.
2017-01-13
Changed status from Preliminary to Final.
Updated Commands:
Updated Command set summary:
Updated Command summary by function:
Updated Table 33.
Updated Register Access commands:
Updated Read Any Register (RDAR 65h):
Updated Table 34.
Updated Data integrity:
Updated Data retention:
Updated description below table.
Updated Electrical specifications:
Updated Power-up and power-down:
Updated Table 47.
Updated DC characteristics:
Updated Table 48.
Updated Table 49.
Updated Table 50.
Updated Ordering information:
Updated Ordering part number:
Added “04” under “Model Number”.
Completing Sunset Review.
*A
*B
Datasheet
169
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Revision history
Document
version
*C
*D
Datasheet
Date
Description of changes
2017-05-15
Removed Extended Temperature Range Options (–40°C to +125°C) from
datasheet.
Updated Product overview:
Updated Migration notes:
Updated Features comparison:
Updated Table 1.
Updated Connection diagrams:
Added SOIC 16-lead.
Updated Commands:
Updated Command set summary:
Updated Command summary by function:
Updated Table 33.
Updated Register Access commands:
Updated Read Status Register 2 (RDSR2 07h):
Replaced “Status Register 1” with “Status Register 2” in all instances.
Updated Software interface reference:
Updated JEDEC JESD216B serial flash discoverable parameters:
Updated JEDEC SFDP basic SPI flash parameter:
Updated Table 41.
Updated Ordering information:
Updated Ordering part number:
Added WSON 5 × 6 mm option to “N” under “Package Type”.
Added 16-lead SOIC option to “M” under “Package Type”.
Updated Valid combinations — Standard:
Updated Table 58.
Updated Valid combinations — Automotive grade / AEC-Q100:
Updated Table 59.
Updated Physical diagrams:
Added “SOIC 16-Lead, 300 mil Body Width (SO3016)”.
Added “WSON 5x 6mm (WND008)”.
Updated Other Resources:
Updated Link to Cypress Flash Roadmap:
Updated hyperlinks.
Updated Link to Software:
Updated hyperlinks.
Updated Link to Application Notes:
Updated hyperlinks.
Updated to new template.
Completing Sunset Review.
2018-04-04
Updated Signal protocols:
Updated Command protocol:
Updated Command sequence examples:
Updated Figure 22.
Updated Figure 23.
Updated Commands:
Updated Read Memory Array commands:
Updated DDR Quad I/O Read (EDh, EEh):
Updated Figure 74.
Updated Figure 75.
Updated Figure 76.
Updated Software interface reference:
Updated Device ID address map:
Updated Field definitions:
Updated Table 44.
170
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64 Mb (8 MB) FL-L flash
SPI multi-I/O, 3.0 V
Revision history
Document
version
*D (cont.)
*E
*F
*G
*H
Datasheet
Date
Description of changes
2018-04-04
Updated Electrical specifications:
Updated Latchup characteristics:
Updated Table 45.
Updated DC characteristics:
Updated Table 48.
Updated Table 49.
Updated Table 50.
Updated Timing specifications:
Updated DDR AC characteristics:
Removed “DDR Minimum Data Valid Window”.
Added DDR data valid timing using DLP.
2018-07-11
Updated Timing specifications:
Updated DDR AC characteristics:
Updated the DDR data valid timing using DLP:
Updated description.
Updated Ordering information:
Updated Ordering part number:
Changed Low-halogen to Halogen free under “Package Materials”.
Added Note 97 and referred the same note in “Package Materials”.
Updated Other Resources:
Updated Glossary:
Updated Definition of MSb and LSb.
Completing Sunset Review.
2019-01-29
Updated Performance summary:
Updated “Typical Current Consumption” table.
Updated Software interface reference:
Updated JEDEC JESD216B serial flash discoverable parameters:
Updated JEDEC SFDP basic SPI flash parameter:
Updated Table 41.
Updated Electrical specifications:
Updated Power-up and power-down:
Updated Table 47.
Updated to new template.
2022-07-21
Updated Document Title to read as “S25FL064L, 64 Mb (8 MB) FL-L flash SPI
multi-I/O, 3.0 V”.
Updated Electrical specifications:
Updated Thermal resistance:
Updated Table 46.
Removed “Other resources”.
Migrated to Infineon template.
2023-04-17
Updated Connection diagrams:
Updated SOIC 16-lead:
Updated Figure 1.
Updated BGA ball footprint:
Updated Figure 5.
Updated Physical diagrams:
spec 002-15535 – Changed revision from ** to *A.
Updated to new template.
171
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Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2023-04-17
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2023 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email:
erratum@infineon.com
Document reference
002-12878 Rev. *H
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
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