S72XS256RE0AHBH10

S72XS-R MCP 256 Mb (16M x 16 bit), 1.8V MirrorBit® Flash and DDR DRAM Features General Description ■ Power supply voltage ❐ 1.7V to 1.95V ■ Burst speed ❐ Flash = 83 MHz, 104 MHz or 108 MHz ❐ DDR DRAM = 166 MHz This datasheet contains information on the S72XS-R Multi-Chip Product (MCP) stacked products. Refer to the S29VS256R, S29VS128R, S29XS256R, S29XS128R datasheet (002-00833) for full electrical specifications of the Flash memory component. ■ Packages ❐ 8.0  8.0 mm, 133-ball MCP ■ Temperature range ❐ Wireless: –25 °C to +85 °C ❐ Industrial: –40 °C to +85 °C The S72XS series is a product line of stacked products (MCPs), and consists of: ■ S29XS family Address-High, Address-Low, Data Multiplexed Flash memory die ■ DDR DRAM Table 1 and Table 2 lists the products covered in this datasheet. Table 1. Memory Density Flash Density DRAM Density 256 Mb S72XS256RE0 Table 2. DDR DRAM Specification Reference Density Reference Name Document Identification Number 256 Mb 256 Mb (16M  16-bit) DDR DRAM SDM256D166D1R/D3R Block Diagram F -RS T# RST# A DQ15-A DQ0 A DQ 15-A D Q 0 A max -A 16 (No Connec t) F -V P P V PP F -CE # F -O E # F -W E # F -A V D # CE# OE# W E# A V D# CLK NOR FLASH X S -R (A A D M ) RDY V CC V CCQ V SS F -CLK F -RD Y F -V C C F -V C CQ VSS V SSQ D -R A S # D -C A S # D -B A 0 D -B A 1 D -C K E D -W E # D -C E # D -A m ax - D -A 0 D -V C C D -V C C Q RA S# CK CA S# CK# BA 0 BA 1 CKE W E# CS# LDQS DDR DRAM M EM ORY A max -A 0 UDQS LDM UDM DQ15-DQ0 V DD V SS V DDQ D -C LK D -C LK # D-LDQ S D-UDQ S D-LDQ M D-UDQ M D-DQ 15 - D-DQ 0 VSS V SSQ Notes 1. Amax indicates highest address bit for memory component: Amax = A12 for 256 Mb DDR DRAM. 2. For Flash, A15 - A0 is tied to DQ15 - DQ0. Cypress Semiconductor Corporation Document Number: 002-00772 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 18, 2016 S72XS-R MCP Pin Diagram Figure 1. 133-Ball Fine-Pitch Ball Grid Array MCP 1 2 3 DNU DNU VSS DNU VSS 4 5 6 7 8 9 10 11 12 13 14 Legend VSS DNU DNU Index Location DNU Do Not Use A D-VCCQ D-DQ9 D-DQ8 VSS D-VCC D-VCC D-DQ5 D-DQ3 B D-DQ13 D-UDQS D-DQ10 VSS D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ C D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM VSS D-VCC VSS D-DQ7 D-LDQS D-DQ2 D-DQ0 VSS No Connect D RFU NC NC INDEX F-OE# ADQ8 D-VCC DRAM Only E RFU RFU RFU ADQ9 ADQ1 ADQ0 RFU RFU RFU VSS ADQ3 ADQ2 F-CE# RFU F-WE# F-VCCQ ADQ11 ADQ10 F-VPP F-VCC F-CLK ADQ13 ADQ12 RFU VSS NC VSS VSS ADQ5 RFU F-AVD# NC NC ADQ7 ADQ6 RFU F-RST# D-CE# Code Flash Only F Reserved for Future Use G VSS H ADQ4 J K L F-VCCQ ADQ15 ADQ14 M NC RFU D-A3 D-A6 D-A9 D-CKE VSS D-WE# D-A10 D-A1 RFU RFU F-RDY VSS DNU VSS D-VCC D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 D-A12 RFU F-VCC DNU DNU DNU NC D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC VSS DNU DNU N P Table 3. DRAM Address Maximum MCP Device ID DDR DRAM Density D-Amax S72XS256RE0 256 Mb D-A12 Document Number: 002-00772 Rev. *J Page 2 of 7 S72XS-R MCP Signal Description Table 4. Input/Output Description Symbol Description Flash RAM Flash multiplexed Address and Data X  F-CE# Flash Chip-enable input X  F-OE# Flash Output Enable input. Asynchronous relative to CLK for Burst mode. X  F-WE# Flash Write Enable input X  F-VCC Flash device power supply (1.7 V to 1.95 V) X  F-VCCQ Flash Input/Output Buffer power supply X  VSS Ground X X F-RDY Flash ready output. Indicates the status of the Burst read. VOL = Data invalid, VOH = Data valid. X  F-CLK Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. X  F-AVD# Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = For asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH = Device ignores address inputs. X  F-RST# Flash hardware reset input. VIL= device resets and returns to reading array data. X  F-VPP Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X  D-Amax – D-A0 DRAM Address input  X D-DQ15 – D-DQ0 DRAM Data input/output  X D-CLK DRAM System Clock  X D-CE# DRAM Chip Select  X D-CKE DRAM Clock Enable  X D-BA1 – BA0 DRAM Bank Select  X D-RAS# DRAM Row Address Strobe  X D-CAS# DRAM Column Address Strobe  X  X ADQ15 – ADQ0 D-UDQM – D-LDQM DRAM Data Input Mask D-WE# DRAM Write Enable input  X D-VCCQ DRAM Input/Output Buffer power supply  X D-VCC DRAM device power supply  X D-UDQS DRAM Upper Data Strobe, output with read data and input with write data  X D-LDQS DRAM Lower Data Strobe, output with read data and input with write data  X D-CLK# DDR Clock for negative edge of CLK  X RFU Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use for the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.   NC Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).   DNU Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.   Document Number: 002-00772 Rev. *J Page 3 of 7 S72XS-R MCP Ordering Information The order number (Valid Combination) is formed by the following: S72XS 256 R E0 AH B HE 3 Packing Type 0 = Tray 3 = 13-inch Tape and Reel Model Number See Valid Combinations (Table 5) Package Modifier B = 133-ball, 8x8 mm, FBGA MCP Package and Material Type AH = Thin profile Fine-pitch BGA Pb-free Low-Halogen MCP (0.5 mm pitch) DDR DRAM and Data Flash Density E0 = 256 Mb DDR, No Data Flash Process Technology R = 65 nm, MirrorBit Technology Code Flash Density 256 = 256 Mb Product Family S72XS Multi-Chip Product (MCP) 1.8V Address-High, Address-Low, Data Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus Valid Combinations Valid combinations in Table 5 list the configurations planned to be supported in volume for this device. Contact your local sales office to confirm the availability of specific valid combinations and to check on newly released combinations. Table 5. Valid Combinations Base OPN [4] Package Model Number Packing [3, 4] Type H1 Flash Boot Temperature Range Top Electronic Serial Number Flash Density DDR DRAM Density Flash Speed (MHz) DRAM Speed (MHz) S72XS256RE0 AHB J1 Bottom Top 0, 3 JH No 256 Mb Bottom Industrial H2 Top J2 Bottom Package SDM256D166 D1R Yes Wireless HH DRAM Specification Yes 256 Mb 108 166 SDM256D166 D3R 8.0  8.0 mm 133-ball MCP (RSC133) Electronic Serial Number For applicable devices, the Factory Secured Silicon Area contains a random, 128-bit ESN, stored in the address range 000000h-000007h. Notes 3. Packing Type 0 is standard. Specify other options as required. 4. BGA package marking omits leading “S” and packing type designator from ordering part number. Document Number: 002-00772 Rev. *J Page 4 of 7 S72XS-R MCP Package Diagram Figure 2. RSC133 133-Ball Fine-Pitch Ball Grid Array (FBGA) 8.0  8.0 mm Document Number: 002-00772 Rev. *J Page 5 of 7 S72XS-R MCP Document History Page Document Title: S72XS-R MCP, 256 Mb (16M x 16 bit), 1.8V MirrorBit® Flash and DDR DRAM Document Number: 002-00772 Revision ECN Orig. of Change Submission Date BWHA 10/07/2008 Initial release BWHA 01/13/2009 Global: Added section Electronic Serial Number Description of Change *A   *B  BWHA 12/18/2009 *C  Global: Added SDM128D166D1K OPN Product Block Diagram: Figure: Updated D-VSS and D-VSSQ connections. Removed D-TEST signal Physical Dimensions: Updated with RSC133 BWHA 02/01/2010 Connection Diagrams: Updated figure: changed Ball A2 with DNU ** *D  BWHA 08/19/2010 *E  Global: Updated references for Low Power DDR SDRAM to SDM128D166D1R DDR Specification Reference: Added reference for 256 Mb DDR DRAM Product Selector Guide: Added “not recommended for new designs” note to OPN S72XS128RD0AHBH60 Added OPN S72XS256RE0AHBH1 Removed OPN S72XS256RD0AHBHE Product Block Diagram: Updated block diagram to show common Ground. Updated Note 1b. Connection Diagrams: Updated connection diagram to show common Ground Updated to show D-A12 Added table to show D-Amax value for related MCP Balls F1, M2 and M12 changed from NC to RFU Input/Output Descriptions: Replaced F-VSS, D-VSS, D-VSSQ with VSS Corrected F-ACC to F-VPP Refreshed descriptions for DNU, NC, RFU Ordering Information/Valid Combinations: Updated for new OPN S72XS256RE0AHBH1 BWHA 12/10/2010 Global: Updated 256 Mb DRAM specification reference *F  BWHA 03/17/2011 Global: Removed SDM128D166D1K references Removed OPN S72XS128RD0AHBH60, Added OPN S72XS256RE0AHBJ1 *G  BWHA 10/05/2011 Ordering Information: Replaced Product Selector Guide section Valid Combinations: Made a separate section Added OPNs: S72XS128RD0AHBHD, S72XS256RE0AHBHH/JH *H  BWHA 04/17/2012 Ordering Information: Added ESN support for S72XS256RE0AHBH1 *I 4960467 BWHA 10/13/2015 Updated to new template. *J 5181007 NFB 03/18/2016 Removed S72XS128RD0 as it is EOL’d. Document Number: 002-00772 Rev. *J Page 6 of 7 S72XS-R MCP Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/clocks cypress.com/interface cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/memory cypress.com/psoc Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation 2008-2016. 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