D at a S h e e t , V 1 . 0, J a n . 20 0 5
XC164N
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er
w i t h C 1 6 6 S V 2 C or e
M i c r o c o n t r o l l er s
N e v e r
s t o p
t h i n k i n g .
Edition 2005-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D at a S h e e t , V 1 . 0, J a n . 20 0 5
XC164N
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er
w i t h C 1 6 6 S V 2 C or e
M i c r o c o n t r o l l er s
N e v e r
s t o p
t h i n k i n g .
XC164N
Revision History:
2005-01
Previous Version:
None
Page
V1.0
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15
XC164-32
Derivatives
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . .
High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
17
18
20
25
26
29
30
33
35
36
36
37
37
40
41
4
4.1
4.2
4.3
4.4
4.5
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
43
44
45
46
5
5.1
5.2
5.3
5.4
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
55
56
57
6
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Data Sheet
1
V1.0, 2005-01
XC164N
Derivatives
Summary of Features
1
•
•
•
•
•
•
•
•
•
•
•
Summary of Features
High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
16-Priority-Level Interrupt System with up to 65 Sources, Sample-Rate down to 50 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)
On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 2 Kbytes On-Chip Data SRAM (DSRAM)
– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
– up to 128 Kbytes On-Chip Program Memory (Flash Memory)
On-Chip Peripheral Modules
– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)
(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip Real Time Clock
Idle, Sleep, and Power Down Modes with Flexible Power Management
Programmable Watchdog Timer and Oscillator Watchdog
Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Four Programmable Chip-Select Signals
Up to 79 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
On-Chip Bootstrap Loader
Data Sheet
1
V1.0, 2005-01
XC164N
Derivatives
Summary of Features
•
•
•
Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
On-Chip Debug Support via JTAG Interface
100-Pin TQFP Package, 0.5 mm (19.7 mil) pitch
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
the derivative itself, i.e. its function set, the temperature range, and the supply voltage
the package and the type of delivery.
For the available ordering codes for the XC164N please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes several derivatives of the XC164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC164N throughout this document.
Data Sheet
2
V1.0, 2005-01
XC164N
Derivatives
Summary of Features
Table 1
XC164N Derivative Synopsis
Derivative1)
Program Memory
On-Chip RAM
Interfaces
Clock
SAF-XC164N-16F40F
128 Kbytes Flash
2Kbytes DPRAM,
2Kbytes DSRAM,
2Kbytes PSRAM
ASC0,
ASC1,
SSC0,
SSC1
40
MHz
SAF-XC164N-16F20F
128 Kbytes Flash
2Kbytes DPRAM,
2Kbytes DSRAM,
2Kbytes PSRAM
ASC0,
ASC1,
SSC0,
SSC1
20
MHz
SAF-XC164N-8F40F
64 Kbytes Flash
2Kbytes DPRAM,
2Kbytes DSRAM,
2Kbytes PSRAM
ASC0,
ASC1,
SSC0,
SSC1
40
MHz
SAF-XC164N-8F20F
64 Kbytes Flash
2Kbytes DPRAM,
2Kbytes DSRAM,
2Kbytes PSRAM
ASC0,
ASC1,
SSC0,
SSC1
20
MHz
1) This Data Sheet is valid for devices starting with and including design step BA.
Data Sheet
3
V1.0, 2005-01
XC164N
Derivatives
General Device Information
2
General Device Information
2.1
Introduction
The XC164N derivatives are high-performance members of the Infineon XC166 Family
of full featured single-chip CMOS microcontrollers. These devices extend the
functionality and performance of the C166 Family in terms of instructions (MAC unit),
peripherals, and speed. They combine high CPU performance (up to 40 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities.
They also provide clock generation via PLL and various on-chip memory modules such
as program Flash, program RAM, and data RAM.
VDDP
VSSP
VDDI/P
VSSI/P
XTAL1
XTAL2
PORT0
16 bit
PORT1
16 bit
NMI
RSTIN
RSTOUT
EA
Port 20
5 bit
XC164N
Port 3
14 bit
Port 4
8 bit
ALE
RD
WR/WRL
Port 9
6 bit
Port 5
14 bit
TRST JTAG Debug Via Port 3
Figure 1
Data Sheet
Logic Symbol
4
V1.0, 2005-01
XC164N
Derivatives
General Device Information
2.2
Pin Configuration and Definition
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
XTAL1
XTAL2
VSSI
VDDI
P1H.7/A15/CC27/EX7IN
P1H.6/A14/CC26/EX6IN
P1H.5/A13/CC25/EX5IN
P1H.4/A12/CC24/EX4IN
P1H.3/A11/T7IN/SCLK1/EX3IN/E*)
P1H.2/A10/C6P2/MTSR1/EX2IN
P1H.1/A9/C6P1/MRST1/EX1IN
P1H.0/A8/C6P0/CC23/EX0IN
VSSP
VDDP
P1L.7/A7/CTRAP/CC22
P1L.6/A6/COUT63
P1L.5/A5/COUT62
P1L.4/A4/CC62
P1L.3/A3/COUT61
P1L.2/A2/CC61
P1L.1/A1/COUT60
P1L.0/A0/CC60
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
The pins of the XC164N are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) marks pins to be used as alternate external interrupt
inputs.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
XC164N
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P0H.4/AD12
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
P20.5/EA
P20.4/ALE
P20.1/WR/WRL
P20.0/RD
VSSP
VDDP
P4.7/A23/C*)
P4.6/A22/C*)
P4.5/A21/C*)
P4.4/A20/C*)
P4.3/A19/CS0
P4.2/A18/CS1
P4.1/A17/CS2
P4.0/A16/CS3
P3.15/CLKOUT/FO
P3.13/SCLK0/E*)
P5.6
P5.7
VDDP
VSSP
P5.12/T6IN
P5.13/T5IN
P5.14/T4EUD
P5.15/T2EUD
VSSI
VDDI
TRST
VSSP
VDDP
P3.1/T6OUT/RxD1/TCK/E*)
P3.2/CAPIN/TDI
P3.3/T3OUT/TDO
P3.4/T3EUD/TMS
P3.5/T4IN/TxD1/BRKOUT
P3.6/T3IN
P3.7/T2IN/BRKIN
P3.8/MRST0
P3.9/MTSR0
P3.10/TxD0/E*)
P3.11/RxD0/E*)
P3.12/BHE/WRH/E*)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RSTIN
P20.12/RSTOUT
NMI
P0H.0/AD8
P0H.1/AD9
P0H.2/AD10
P0H.3/AD11
VSSP
VDDP
P9.0/CC16IO
P9.1/CC17IO
P9.2/CC18IO
P9.3/CC19IO
P9.4/CC20IO
P9.5/CC21IO
VSSP
VDDP
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10/T6EUD
P5.11/T5EUD
Figure 2
Data Sheet
Pin Configuration (top view)
5
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions
Symbo Pin
l
Num.
RSTIN
1
Input
Outp.
Function
I
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC164N.
A spike filter suppresses input pulses 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
P20.12 2
IO
For details, please refer to the description of P20.
NMI
3
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164N into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P0H.0P0H.3
4…7
IO
For details, please refer to the description of PORT0.
Data Sheet
6
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
P9
IO
10
I/O
Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 9 is selectable (standard
or special).
The following Port 9 pins also serve for alternate functions:
CC16IO
CAPCOM2: CC16 Capture Inp./Compare Outp.,
11
I
I/O
EX7IN
CC17IO
Fast External Interrupt 7 Input (alternate pin B)
CAPCOM2: CC17 Capture Inp./Compare Outp.,
P9.2
12
I
I/O
EX6IN
CC18IO
Fast External Interrupt 6 Input (alternate pin B)
CAPCOM2: CC18 Capture Inp./Compare Outp.,
P9.3
13
I
I/O
EX7IN
CC19IO
Fast External Interrupt 7 Input (alternate pin A)
CAPCOM2: CC19 Capture Inp./Compare Outp.,
14
15
I
I/O
I/O
EX6IN
CC20IO
CC21IO
Fast External Interrupt 6 Input (alternate pin A)
CAPCOM2: CC20 Capture Inp./Compare Outp.
CAPCOM2: CC21 Capture Inp./Compare Outp.
I
Port 5 is a 14-bit input-only port.
Some pins of Port 5 serve as timer inputs:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
T6EUD
GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
T5EUD
GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
P9.0
P9.1
P9.4
P9.5
P5
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15
18
19
20
21
22
23
24
25
26
27
30
31
32
33
Data Sheet
T6IN
T5IN
T4EUD
T2EUD
GPT2 Timer T6 Count/Gate Input
GPT2 Timer T5 Count/Gate Input
GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
7
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
TRST
I
Test-System Reset Input. A high level at this pin activates
the XC164N’s debug system. For normal system operation,
pin TRST should be held low.
IO
Port 3 is a 14-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:
T6OUT
GPT2 Timer T6 Toggle Latch Output,
RxD1
ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN
Fast External Interrupt 1 Input (alternate pin A),
TCK
Debug System: JTAG Clock Input
CAPIN
GPT2 Register CAPREL Capture Input,
TDI
Debug System: JTAG Data In
T3OUT
GPT1 Timer T3 Toggle Latch Output,
TDO
Debug System: JTAG Data Out
T3EUD
GPT1 Timer T3 External Up/Down Control Input,
TMS
Debug System: JTAG Test Mode Selection
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
TxD1
ASC0 Clock/Data Output (Async./Sync.),
BRKOUT Debug System: Break Out
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
BRKIN
Debug System: Break In
MRST0
SSC0 Master-Receive/Slave-Transmit In/Out.
MTSR0
SSC0 Master-Transmit/Slave-Receive Out/In.
TxD0
ASC0 Clock/Data Output (Async./Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin B)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin A)
BHE
External Memory High Byte Enable Signal,
WRH
External Memory High Byte Write Strobe,
EX3IN
Fast External Interrupt 3 Input (alternate pin B)
SCLK0
SSC0 Master Clock Output / Slave Clock Input.,
EX3IN
Fast External Interrupt 3 Input (alternate pin A)
CLKOUT System Clock Output (=CPU Clock),
FOUT
Programmable Frequency Output
36
P3
P3.1
39
P3.2
40
P3.3
41
P3.4
42
P3.5
43
P3.6
P3.7
44
45
P3.8
P3.9
P3.10
46
47
48
P3.11
49
P3.12
50
P3.13
51
P3.15
52
Data Sheet
O
I/O
I
I
I
I
O
O
I
I
I
O
O
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O
8
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
P4
IO
Port 4 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 4 is selectable (standard
or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:
A16
Least Significant Segment Address Line,
CS3
Chip Select 3 Output
A17
Segment Address Line,
CS2
Chip Select 2 Output
A18
Segment Address Line,
CS1
Chip Select 1 Output
A19
Segment Address Line,
CS0
Chip Select 0 Output
A20
Segment Address Line,
P4.0
53
P4.1
54
P4.2
55
P4.3
56
P4.4
57
O
O
O
O
O
O
O
O
O
P4.5
58
I
O
EX5IN
A21
Fast External Interrupt 5 Input (alternate pin B)
Segment Address Line,
P4.6
59
I
O
EX4IN
A22
Fast External Interrupt 4 Input (alternate pin B)
Segment Address Line,
60
I
O
EX5IN
A23
Fast External Interrupt 5 Input (alternate pin A)
Most Significant Segment Address Line,
I
EX4IN
Fast External Interrupt 4 Input (alternate pin A)
P4.7
Data Sheet
9
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
P20
IO
Port 20 is a 5-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD
External Memory Read Strobe, activated for
every external instruction or data read access.
WR/WRL External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
ALE
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
EA
External Access Enable pin.
A low level at this pin during and after Reset
forces the XC164N to latch the configuration
from PORT0 and pin RD, and to begin
instruction execution out of external memory.
A high level forces the XC164N to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. "ROMless" versions must
have this pin tied to ‘0’.
RSTOUT Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
P20.0
63
O
P20.1
64
O
P20.4
65
O
P20.5
66
I
P20.12 2
O
Note: Port 20 pins may input configuration values (see EA).
Data Sheet
10
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
PORT0
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7:
A8 - A15
AD8 - AD15
P0L.0 - 67 P0L.7
74
P0H.0 - 4 P0L.3
7
P0H.4 - 75 P0L.7
78
Note: At the end of an external reset (EA = 0) PORT0 also
may input configuration values
IO
PORT1
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
79
80
81
82
83
84
85
86
P1H
…
I/O
O
I/O
O
I/O
O
O
I
I/O
Data Sheet
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes (also after switching from a
demultiplexed to a multiplexed bus mode).
The following PORT1 pins also serve for alt. functions:
CC60
CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61
CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62
CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
CTRAP
CAPCOM6: Trap Input
CTRAP is an input pin with an internal pullup resistor. A low
level on this pin switches the CAPCOM6 compare outputs to
the logic level defined by software (if enabled).
CC22IO
CAPCOM2: CC22 Capture Inp./Compare Outp.
…continued…
11
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
PORT1
(cont’d)
P1H.0 89
IO
…continued…
I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I
I
I/O
I
I/O
I
I/O
I
I/O
I
CC6POS0
EX0IN
CC23IO
CC6POS1
EX1IN
MRST1
CC6POS2
EX2IN
MTSR1
T7IN
SCLK1
EX3IN
EX0IN
CC24IO
EX4IN
CC25IO
EX5IN
CC26IO
EX6IN
CC27IO
EX7IN
CAPCOM6: Position 0 Input,
Fast External Interrupt 0 Input (default pin),
CAPCOM2: CC23 Capture Inp./Compare Outp.
CAPCOM6: Position 1 Input,
Fast External Interrupt 1 Input (default pin),
SSC1 Master-Receive/Slave-Transmit In/Out.
CAPCOM6: Position 2 Input,
Fast External Interrupt 2 Input (default pin),
SSC1 Master-Transmit/Slave-Receive Out/Inp.
CAPCOM2: Timer T7 Count Input,
SSC1 Master Clock Output / Slave Clock Input,
Fast External Interrupt 3 Input (default pin),
Fast External Interrupt 0 Input (alternate pin A)
CAPCOM2: CC24 Capture Inp./Compare Outp.,
Fast External Interrupt 4 Input (default pin)
CAPCOM2: CC25 Capture Inp./Compare Outp.,
Fast External Interrupt 5 Input (default pin)
CAPCOM2: CC26 Capture Inp./Compare Outp.,
Fast External Interrupt 6 Input (default pin)
CAPCOM2: CC27 Capture Inp./Compare Outp.,
Fast External Interrupt 7 Input (default pin)
P1H.1
90
P1H.2
91
P1H.3
92
P1H.4
93
P1H.5
94
P1H.6
95
P1H.7
96
XTAL2
XTAL1
99
100
O
I
XTAL2:
XTAL1:
res
res
VDDI
28
-
pin is reserved and connected to VDDP
29
-
pin is reserved and connected to VSSP
35, 97
-
Digital Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the Operating Conditions
Data Sheet
Output of the oscillator amplifier circuit
Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
12
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
l
Num.
Input
Outp.
Function
VDDP
9, 17, 38, 61,
87
Digital Pad Supply Voltage (Pin Output Drivers):
+5 V during normal operation and idle mode.
Please refer to the Operating Conditions
VSSI
VSSP
34, 98
Digital Ground.
Connect decoupling capacitors to adjacent VDD/VSS pin pairs
as close as possible to the pins.
All VSS pins must be connected to the ground-line or groundplane.
-
8, 16, 37, 62,
88
Data Sheet
13
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3
Functional Description
The architecture of the XC164N combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resoures as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164N.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164N.
PSRAM
DPRAM
DSRAM
ProgMem
Flash
128 KBytes
DMU
PMU
EBC
CPU
XBUS Control
External Bus
Control
C166SV2-Core
OCDS
Debug Support
XTAL
Osc / PLL
RTC
WDT
Interrupt & PEC
Clock Generation
Interrupt Bus
Peripheral Data Bus
GPT
T2
ASC0 ASC1 SSC0
(USART)
(USART)
SSC1
(SPI)
(SPI)
T3
CC1
CC2
CC6
T0
T7
T12
T1
T8
T13
T4
T5
T6
P 20 Port 9
5
BRGen
BRGen
Port 5
6
14
BRGen
BRGen
Port 4
Port 3
PORT1
PORT0
8
14
16
16
SAF-XC164N-16FxxF AC
Figure 3
Data Sheet
Block Diagram
14
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC164N is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the onchip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXbus. The system bus allows
concurrent two-way communication for maximum transfer performance.
128 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and one 64-Kbyte
sectors. Each sector can be separately write protected1), erased and programmed (in
blocks of 128 Bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector
typically takes 200 ms (500 ms max.).
2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
2 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data.The DSRAM is accessed via the DMU and is therefore optimized for data accesses.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, general purpose register banks. A register bank
can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7)
1) Each two 8-Kbyte sectors are combined for write-protection purposes.
Data Sheet
15
V1.0, 2005-01
XC164N
Derivatives
Functional Description
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC164N Memory Map1)
Address Area
Start Loc.
End Loc.
Area Size2)
Flash register space
FF’F000H
FF’FFFFH
4 Kbytes
Reserved (Acc. trap)
F8’0000H
FF’EFFFH
0
IOV < 0
IOV > 0
IOV < 0
Overload current coupling KOVD
factor for digital I/O pins7)
–
5.0 × 10-3 –
–
1.0 × 10-2 –
Absolute sum of overload
currents
Σ|IOV|
–
50
mA
6)
External Load
Capacitance
CL
–
50
pF
Pin drivers in
default mode8)
Ambient temperature
TA
0
70
°C
SAB-XC164N …
-40
85
°C
SAF-XC164N …
-40
125
°C
SAK-XC164N …
1) fCPUmax = 40 MHz for devices marked …40F, fCPUmax = 20 MHz for devices marked …20F.
2) External circuitry must guarantee low level at the RSTIN pin at least until both power supply voltages have
reached the operating level.
3) The specified voltage range is allowed for operation. The range limits may be reached under extreme
operating conditions. However, specified parameters, such as leakage currents, refer to the standard
operating voltage range of VDDP = 4.75 V to 5.25 V.
4) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down,
and power-save modes.
Data Sheet
44
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
5) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum of
input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the
specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
6) Not subject to production test - verified by design/characterization.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
8) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
4.4
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the XC164N
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the XC164N will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC164N.
Data Sheet
45
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
4.5
DC Parameters
DC Characteristics
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
Input low voltage TTL
(all except XTAL1)
VIL
SR -0.5
0.2×VDDP V
- 0.1
–
Input low voltage XTAL1
VILC SR -0.5
VILS SR -0.5
0.3 ×VDDI V
–
0.45
× VDDP
V
2)
Input low voltage
(Special Threshold)
Input high voltage TTL
(all except XTAL1)
VIH
SR 0.2×VDDP VDDP
+ 0.5
+ 0.9
V
–
Input high voltage XTAL1
VIHC SR 0.7
VDDI
× VDDI
+ 0.5
VIHS SR 0.8×VDDP VDDP
V
–
V
2)
V
VDDP in [V],
Input high voltage
(Special Threshold)
- 0.2
+ 0.5
0.04
× VDDP
–
Input Hysteresis
(Special Threshold)
HYS
Output low voltage
VOL CC –
–
Output high voltage5)
VOH CC VDDP
Series resistance = 0 Ω2)
1.0
V
0.45
V
–
V
IOL ≤ IOLmax3)
IOL ≤ IOLnom3) 4)
IOH ≥ IOHmax3)
–
V
IOH ≥ IOHnom3) 4)
±300
nA
0 V < VIN < VDDP,
TA ≤ 125 °C
±200
nA
0 V < VIN < VDDP,
TA ≤ 85 °C12)
±500
nA
0.45 V < VIN <
VDDP
VIN = VIHmin
VIN = VILmax
- 1.0
VDDP
- 0.45
Input leakage current
(Port 5)6)
Input leakage current
(all other)6)
IOZ1 CC –
IOZ2 CC –
Configuration pull-up current7) ICPUH8)
ICPUL9)
Data Sheet
–
-10
µA
-100
–
µA
46
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
DC Characteristics (cont’d)
(Operating Conditions apply)1)
Parameter
Configuration pull-down
current10)
Level inactive hold current11)
Level active hold current11)
XTAL1 input current
Pin capacitance12)
(digital inputs/outputs)
Symbol
8)
ICPDL
ICPDH9)
ILHI8)
Limit Values
Unit Test Condition
min.
max.
–
10
µA
120
–
µA
–
-10
µA
–
µA
±20
µA
10
pF
ILHA9)
-100
IIL CC –
CIO CC –
VIN = VILmax
VIN = VIHmin
VOUT =
0.5 × VDDP
VOUT = 0.45 V
0 V < VIN < VDDI
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV.
2) This parameter is tested for P2, P3, P4, P9.
3) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
4) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are guaranteed.
5) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
6) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV.
7) This specification is valid during Reset for configuration on RD, WR, EA, PORT0.
8) The maximum current may be drawn while the respective signal line remains inactive.
9) The minimum current must be drawn to drive the respective signal line active.
10) This specification is valid during Reset for configuration on ALE.
11) This specification is valid during Reset for pins P4.3-0, which can act as CS outputs.
12) Not subject to production test - verified by design/characterization.
Data Sheet
47
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
Table 12
Current Limits for Port Output Drivers
Port Output Driver
Mode
Maximum Output Current
(IOLmax, -IOHmax)1)
Nominal Output Current
(IOLnom, -IOHnom)
Strong driver
10 mA
2.5 mA
Medium driver
4.0 mA
1.0 mA
Weak driver
0.5 mA
0.1 mA
1) An output current above |IOXnom| may be drawn from up to three pins at the same time.
For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH) must
remain below 50 mA.
Power Consumption XC164N
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
15 +
2.6 × fCPU
mA
Power supply current (active)
with all peripherals active
IDDI
–
Pad supply current
IDDP
IIDX
–
5
mA
–
15 +
1.2 × fCPU
mA
Sleep and Power-down mode
supply current caused by
leakage4)
IPDL5)
–
128,000
× e-α
mA
Sleep and Power-down mode
supply current caused by
leakage and the RTC running,
clocked by the main oscillator4)
IPDM7)
0.6 +
0.02×fOSC
+ IPDL
mA
Idle mode supply current
with all peripherals active
–
1)
fCPU in [MHz]2)
3)
fCPU in [MHz]2)
VDDI=VDDImax6)
TJ in [°C]
α=
4670/(273+TJ)
VDDI=VDDImax
fOSC in [MHz]
1) During Flash programming or erase operations the supply current is increased by max. 5 mA.
2) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.
These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected and
all inputs at VIL or VIH.
3) The pad supply voltage pins (VDDP) mainly provides the current consumed by the pin output drivers. A small
amount of current is consumed even though no outputs are driven, because the drivers’ input stages are
switched and also the Flash module draws some power from the VDDP supply.
4) The total supply current in Sleep and Power-down mode is the sum of the temperature dependent leakage
current and the frequency dependent current for RTC and main oscillator (if active).
Data Sheet
48
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the
junction temperature (see Figure 12). The junction temperature TJ is the same as the ambient temperature TA
if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be
taken into account.
6) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including
pins configured as outputs) disconnected. This parameter is tested at 25 °C and is valid for TJ ≥ 25 °C.
7) This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see
Figure 11). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The
given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
Data Sheet
49
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
I [mA]
IDDImax
140
120
IDDItyp
100
80
IIDXmax
60
IIDXtyp
40
20
10
Figure 10
Data Sheet
20
30
40
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
50
V1.0, 2005-01
XC164N
Derivatives
Electrical Parameters
I [mA]
3.0
2.0
IPDMmax
IPDMtyp
1.0
IPDAmax
0.1
32 kHz
Figure 11
4
8
12
16
fOSC [MHz]
Sleep and Power Down Supply Current due to RTC and Oscillator
running, as a Function of Oscillator Frequency
IPDO
[mA]
1.5
1.0
0.5
-50
Figure 12
Data Sheet
0
50
100
150
TJ [°C]
Sleep and Power Down Leakage Supply Current as a Function of
Temperature
51
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
5
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC164N is controlled by the internal master clock fMC.
The master clock signal fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate fMC.
This influence must be regarded when calculating the timings for the XC164N.
Phase Locked Loop Operation (1:N)
fOSC
fMC
TCM
Direct Clock Drive (1:1)
fOSC
fMC
TCM
Prescaler Operation (N:1)
fOSC
fMC
TCM
Figure 13
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 13 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have the
same frequency as the master clock (fCPU = fMC) or can be the master clock divided by
two: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal fSYS which has the same
frequency as the CPU clock signal fCPU.
Data Sheet
52
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and outputprescalers:
fMC = fOSC / ((PLLIDIV+1)×(PLLODIV+1)).
If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of fMC
directly follows the frequency of fOSC so the high and low time of fMC is defined by the duty
cycle of the input clock fOSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
fMC = fOSC / ((3+1)×(14+1)) = fOSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor, and
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it
is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 14).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore,
the number of VCO cycles can be represented as K × N, where N is the number of
consecutive fMC cycles (TCM).
Data Sheet
53
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
For a period of N × TCM the accumulated PLL jitter is defined by the deviation DN:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K×N=95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
A cc. jitter D N
ns
K =1 5 K =12 K =10 K =8
K =6
K =5
±8
±7
±6
M
Hz
±5
10
±4
±3
±2
z
MH
0
2
Hz
40 M
±1
0
1
5
15
10
20
25
N
m c b 04 41 3 _x c .vs d
Figure 14
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Table 13
VCO Bands for PLL Operation1)
PLLCON.PLLVB VCO Frequency Range
Base Frequency Range
00
100 … 150 MHz
20 … 80 MHz
01
150 … 200 MHz
40 … 130 MHz
10
200 … 250 MHz
60 … 180 MHz
11
Reserved
1) Not subject to production test - verified by design/characterization.
Data Sheet
54
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
5.2
Table 14
External Clock Drive XTAL1
External Clock Drive Characteristics
(Operating Conditions apply)
Parameter
Symbol
tOSC
t1
t2
t3
t4
Oscillator period
High time2)
Low time2)
Rise time2)
Fall time2)
Limit Values
Unit
min.
max.
SR
20
2501)
ns
SR
6
–
ns
SR
6
–
ns
SR
–
8
ns
SR
–
8
ns
1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
2) The clock input signal must reach the defined levels VILC and VIHC.
t1
t3
t4
VIHC
0.5 VDDI
VILC
t2
t OSC
MCT05138
Figure 15
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not subject to production test).
Data Sheet
55
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
5.3
Testing Waveforms
Input signal
(driven by tester)
Output signal
(measured)
2.0 V
0.8 V
0.45 V
Figure 16
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 17
Data Sheet
Float Waveforms
56
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
5.4
AC Characteristics
Table 15
CLKOUT Reference Signal
Parameter
Symbol
Limits
min.
tc5
tc6
tc7
tc8
tc9
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CC
Unit
max.
50/251)
ns
CC 8
–
ns
CC 6
–
ns
CC –
4
ns
CC –
4
ns
1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 20/40 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
tc7
tc5
tc6
tc9
tc8
CLKOUT
MCT04415
Figure 18
Data Sheet
CLKOUT Signal Timing
57
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
Variable Memory Cycles
External bus cycles of the XC164N are executed in five subsequent cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
This table provides a summary of the phases and the respective choices for their
duration. The specification of the external timing depends on the period of the CPU
clock, which is called “TCP” and is used in Table 16
Table 16
Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter
Address setup phase, the standard duration of this tpAB
phase (1 … 2 TCP) can be extended by 0 … 3 TCP
if the address window is changed
tpC
tpD
tpE
tpF
Command delay phase
Write Data setup / MUX Tristate phase
Access phase
Address / Write Data hold phase
Valid Values Unit
1 … 2 (5)
TCP
0…3
TCP
0…1
TCP
1 … 32
TCP
0…3
TCP
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Data Sheet
58
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
Table 17
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
min.
Unit
max.
Output valid delay for:
RD, WR(L/H)
tc10
CC 1
15
ns
Output valid delay for:
BHE, ALE
tc11
CC -1
8
ns
Output valid delay for:
A23…A16, A15…A0 (on PORT1)
tc12
CC 3
18
ns
Output valid delay for:
A15…A0 (on PORT0)
tc13
CC 3
18
ns
Output valid delay for:
CS
tc14
CC 3
16
ns
Output valid delay for:
D15…D0 (write data, mux-mode)
tc15
CC 3
19
ns
Output valid delay for:
D15…D0 (write data, demux-mode)
tc16
CC 2
16
ns
Output hold time for:
RD, WR(L/H)
tc20
CC -3
4
ns
Output hold time for:
BHE, ALE
tc21
CC 0
11
ns
Output hold time for:
A23…A16, A15…A0 (on PORT0)
tc23
CC 1
13
ns
Output hold time for:
CS
tc24
CC -2
4
ns
Output hold time for:
D15…D0 (write data)
tc25
CC 1
13
ns
Input setup time for:
D15…D0 (read data)
tc30
SR 29
–
ns
Input hold time
D15…D0 (read data)1)
tc31
SR -5
–
ns
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD
Note: The shaded parameters have been verified by characterization.
They are not subject to production test.
Data Sheet
59
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
tpAB
tpC
tc11
tc21
tpD
tpE
tpF
CLKOUT
ALE
tc11|tc14
A23-A16,
BHE, CSx
High Address
tc10
tc20
RD
WR(L/H)
tc13
AD15-AD0
(read)
tc23
Low Address
tc13
AD15-AD0
(write)
Figure 19
Data Sheet
tc30
tc31
Data In
tc15
Low Address
tc25
Data Out
Multiplexed Bus Cycle
60
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
tpAB
tpC
tc11
tc21
tpD
tpE
tpF
CLKOUT
ALE
tc11|tc14
A23-A0,
BHE, CSx
Address
tc10
tc20
RD
WR(L/H)
tc30
D15-D0
(read)
Data In
tc16
D15-D0
(write)
Figure 20
Data Sheet
tc31
tc25
Data Out
Demultiplexed Bus Cycle
61
V1.0, 2005-01
XC164N
Derivatives
Packaging
6
Figure 21
Packaging
Package Outlines P-TQFP-100-16 (Plastic Thin Quad Flat Package)
Dimensions in mm.
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products
Data Sheet
62
V1.0, 2005-01
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
工商网监
湘ICP备2023018690号
