TC1728N192F133HRACKXUMA2

32-Bit Microcontroller TC1728 32-Bit Single-Chip Microcontroller Data Sheet V1.2 2014-06 Microcontrollers Edition 2014-06 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 32-Bit Microcontroller TC1728 32-Bit Single-Chip Microcontroller Data Sheet V1.2 2014-06 Microcontrollers TC1728 Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 2.1 System Overview of the TC1728 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.5.1 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.11.1 5.3.11.2 5.3.11.3 5.3.11.4 5.4 5.4.1 5.4.2 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-33 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-42 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 Power Sequencing 5V Supply Only . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 Power Sequencing 3.3V Supply Only . . . . . . . . . . . . . . . . . . . . . . . . 5-46 Power Sequencing all Voltages supplied from External . . . . . . . . . . 5-48 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 EVR Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-57 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-64 SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 Data Sheet I-1 V1.2, 2014-06 TC1728 Table of Contents 5.4.3 5.4.4 6 Data Sheet Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 I-2 V1.2, 2014-06 TC1728 Summary of Features 1 Summary of Features The SAK-TC1728N-192F133HL / SAK-TC1728N-192F133HR has the following features: • • • • • • • High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 24 Kbyte Code Memory (CMEM) – 133 MHz operation at full temperature range Multiple on-chip memories – 1.5 Mbyte Program Flash Memory (PFLASH) with ECC – 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 120 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 8Kbyte (ICACHE, configurable) – 24 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyte (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM) 16-Channel DMA Controller Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer Data Sheet 1-1 V1.2, 2014-06 TC1728 Summary of Features • • • • • • • • – One General Purpose Timer Array Module (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – Two Capture/Compare Unit 6 (CAPCOM6) kernels – Two General Purpose Timer (GPT12) modules 36 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply) – Broken wire detection 2 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 127 digital general purpose I/O lines (GPIO), 3 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1728ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL The SAK-TC1728F-192F133HL / SAK-TC1728F-192F133HR features: • • • has the following High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 24 Kbyte Code Memory (CMEM) – 133 MHz operation at full temperature range Multiple on-chip memories – 1.5 Mbyte Program Flash Memory (PFLASH) with ECC – 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 120 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 8Kbyte (ICACHE, configurable) – 24 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyte (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) Data Sheet 1-2 V1.2, 2014-06 TC1728 Summary of Features • • • • • • • • • • • • – 16 Kbyte BootROM (BROM) 16-Channel DMA Controller Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – One FlexRayTM module with 2 channels (E-Ray). – One General Purpose Timer Array Module (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – Two Capture/Compare Unit 6 (CAPCOM6) kernels – Two General Purpose Timer (GPT12) modules 36 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply) – Broken wire detection 2 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 127 digital general purpose I/O lines (GPIO), 3 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1728ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL Data Sheet 1-3 V1.2, 2014-06 TC1728 Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • • The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery. For the available ordering codes for the TC1728 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 TC1728 Derivative Synopsis Derivative SAK-TC1728N-192F133HL SAK-TC1728N-192F133HR SAK-TC1728F-192F133HR SAK-TC1728F-192F133HL 1) 2) Ambient Temperature Range ERAY Wire Bond Material TA = -40oC to +125oC No Gold TA = -40oC to +125oC No Copper o o Yes Copper o o Yes Gold TA = -40 C to +125 C TA = -40 C to +125 C 1) This derivative has the same features as the SAK-TC1728N-192F133HL, except the wire-bonding material. 2) This derivative has the same features as the SAK-TC1728F-192F133HL, except the wire-bonding material. Data Sheet 1-4 V1.2, 2014-06 TC1728 System Overview of the TC1728 2 System Overview of the TC1728 The TC1728 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: • • • Reduced Instruction Set Computing (RISC) processor architecture Digital Signal Processing (DSP) operations and addressing modes On-chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features of the TC1728 include: • • • • • • • • • Efficient memory organization: instruction and data scratch memories, caches Serial communication interfaces – flexible synchronous and asynchronous modes Peripheral Control Processor – standalone data operations and interrupt servicing DMA Controller – DMA operations and interrupt servicing General-purpose timers High-performance on-chip buses On-chip debugging and emulation facilities Flexible interconnections to external components Flexible power-management The TC1728 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor and a DMA controller and several on-chip peripherals. The TC1728 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. The TC1728 offers several versatile on-chip peripheral units such as serial controllers, timer units, CAPCOM6 and Analog-to-Digital converters. Within the TC1728, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1728 ports are reserved for these peripheral units to communicate with the external world. Data Sheet 2-1 V1.2, 2014-06 TC1728 System Overview of the TC1728 2.1 Block Diagrams Figure 1 shows the block diagram of the SAK-TC1728N-192F133HL./ SAK-TC1728N192F133HR. Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP CMEM: Code RAM in PCP FPU PMI DMI TriCore CPU 16 KB SPRAM 8 KB ICACHE (Configurable) 116 KB LDRAM 4 KB DCACHE (Configurable) TC1.3.1 133MHz CPS Local Memory Bus LBCU (LMB) 1.3V, 3.3V Int. Supply DMA LFI Bridge 16 channels SMIF M PMU 1,5 MB PFlash 64 KB Dflash 16 KB BROM 8 KB OVRAM Optional Ext. Supply EVR 5V, 3.3V Single-source Ext. Supply Embedded Voltage Regulator M/S OCDS L1 Debug Interface ASC0 ASC1 JTAG/DAP Interrupt System MLI0 Interrupts FPI-Bus Interface 8 KB PRAM System Peripheral Bus (SPB) PCP2 Core STM MemCheck 24 KB CMEM CAPCOM (CCU60, CCU61) GPT12 (GPT 120) System Peripheral Bus SCU FCE Ports 5V Ext. ADC Supply BMU ADC0 GPT12 (GPT 121) SSC0 SBCU PLL fCPU 16 (5V max, 24 channels ) 4 FADC SSC2 Ext. Request Unit MultiCAN (3 Nodes, 64 MO) MSC0 SSC3 LVDS Data Sheet 16 ADC1 SSC1 GPTA 0 Figure 1 (5V max, 16 channels ) (3.3V max, 2 differential channels ) BlockDiagram TC1728N V0.8 SAK-TC1728N-192F133HL / SAK-TC1728N-192F133HR Block Diagram 2-2 V1.2, 2014-06 TC1728 System Overview of the TC1728 Figure 2 shows the block diagram of the SAK-TC1728F-192F133HL / SAK-TC1728F192F133HR. Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP CMEM: Code RAM in PCP FPU PMI DMI TriCore CPU 16 KB SPRAM 8 KB ICACHE (Configurable) 116 KB LDRAM 4 KB DCACHE (Configurable) TC1.3.1 133MHz CPS Local Memory Bus LBCU (LMB) 1.3V, 3.3V Int. Supply DMA LFI Bridge 16 channels SMIF M PMU 1,5 MB PFlash 64 KB Dflash 16 KB BROM 8 KB OVRAM Optional Ext. Supply EVR 5V, 3.3V Single-source Ext. Supply Embedded Voltage Regulator M/S OCDS L1 Debug Interface ASC0 ASC1 System Peripheral Bus (SPB) JTAG/DAP Interrupt System MLI0 Interrupts FPI-Bus Interface 8 KB PRAM PCP2 Core STM MemCheck 24 KB CMEM SCU CAPCOM (CCU60, CCU61) GPT12 (GPT 120) System Peripheral Bus E-Ray (2 channels) FCE Ports 5V Ext. ADC Supply BMU ADC0 GPT12 (GPT 121) SBCU PLL E-RAY PLL f E-Ray SSC0 fCPU (5V max, 16 channels ) 16 ADC1 16 (5V max, 24 channels ) 4 SSC1 GPTA 0 FADC SSC2 Ext. Request Unit MultiCAN (3 Nodes, 64 MO) MSC0 SSC3 (3.3V max, 2 differential channels ) BlockDiagram TC1728F LVDS Figure 2 Data Sheet SAK-TC1728F-192F133HR Block Diagram 2-3 V1.2, 2014-06 TC1728 Pinning 3 Pinning Figure 3-1 shows the TC1728 Logic Symbol. Alternate Functions General Control 16 PORST TESTMODE ESR0 ESR1 16 14 16 TRST OCDS / JTAG Control Analog Inputs Analog Power Supply TCK / DAP0 4 TMS / DAP1 16 AN[35:0] VD D M VSSM V AR EF0 VAGN D 0 V5 Digital Circuitry Power Supply VD D VD D P V SS EVR Pass Device Gate V PD G TC1728 4 14 7 4 4 5 16 4 2 1 Port 0 Port 1 Port 2 Port 3 GPTA, SCU, ERAY 1 ), MSC0, CCU6, GPT12, MultiCAN SCU, GPTA, SSC1, ADC0, OCDS, CCU6, GPT12 GPTA, SSC0/1, MLI0, MSC0, CCU6, GPT12 GPTA, ASC0/1, SSC0/1, SCU, CAN, MSC0 Port 4 GPTA, SCU, CAN, CCU6, GPT12 Port 5 GPTA, ERAY 1 ), SSC0/2, CAN, CCU6, GPT12, SCU, ADC1 Port 6 GPTA, MSC0 Port 8 CCU6, GPT12, SSC3, GPTA Port 9 GPTA, CCU6, OCDS/JTAG Port 10 SSC2 Port 11 Overlaid digital /analog inputs XTAL1 XTAL2 Oscillator 1) On ly a va ila b le fo r SAK- TC1 7 2 8F-1 9 2F1 3 3H R TC1728_LogSym_176 Figure 3-1 Data Sheet TC1728 Logic Symbol 3-1 V1.2, 2014-06 TC1728 REQ7/CC 62/ CC62INA /B/CAPINA/B/SLSO20 /OUT 40 /IN40 /P5 .0 SLSO21 /OUT 41 /IN41 /P5 .1 COUT 62 /SLSO22 /OUT 42 /IN42 /P5 .2 SLSO23 /OUT 43 /IN43 /P5 .3 SLSI2 A/SLSO24 /OUT 44 /IN44 /P5 .4 M RST2A/OUT 45 /IN45 /P5 .5 M T SR2A/OUT 46 /IN46 /P5 .6 SCLK2A/OUT 47 /IN47 /P5 .7 1) T XDCAN0/OUT 37 /RXDB1 /P5. 15 VDD CC60 IN C/CC 60/ OU T87/P 9.7 COU T60/ OU T88/P 9.8 CC61 /CC61 INA/B/T XDA11 )/OUT 6/P5 .8 1) OUT 7/RXDCAN0 /T XDB1 /P5 .9 1) COUT 61/ OUT 8/T XENA1 )/P5.10 COUT 63/ OUT 9/T XENB /P5.11 CCPOS0 A/ T12 HRB/T 3INA/B/ AD1 EM UX0 /SLSO07 /OUT 19 /P5.12 1) TC1728 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 P3 .4/OUT 88 /M T SR0 P3 .7/SLSI 0/OUT 89 /SLSO02 /SLSO 12 P3 .3/OUT 87 /M RST0 P3 .2/OUT 86 /SCLK0 P3 .8/SLSO 06/ OUT 90/ T XD1/ REQ14 P3 .6/SLSO 01/ SLSO11 /SLSO01 &SLSO11 P3 .5/SLSO 00/ SLSO10 /SLSO00 &SLSO10 P 8.13/ OU T4 /COU T60 P 8.3/ SLSI3 /CC 61IN C/ CC61/ OU T51/ SLSO30 P 8.4/ OU T99 /COU T62/ SLSO31 ESR0 PORST ESR1 P1. 1/IN17 /OUT 17 /OUT 73 /T 13 HRE/CT RAPB T EST M ODE P1.15 /BRKIN/ BRKOUT P1.0 /REQ15 /IN16 /OUT 16 /OUT 72 /T 3OUT /BRKIN /BRKOUT T CK/DAP0 T RST P9 .6/T DO/ BRKIN/BRKOUT T M S/ DAP1 P9 .5/T DI/BRKIN/ BRKOUT P1 .7/IN 23/ OUT 23/OUT 79 P1 .6/IN 22/ OUT 22/OUT 78 P1 .5/IN 21/ OUT 21/OUT 77 V5 V DDP V DD V SS XT AL2 XT AL1 V SS P 8.12/ OU T107 P1 .4/IN 20/ EM GST OP/OUT 20 /OUT 76 /COUT 61 P1 .3/IN 19/ OUT 19/ OUT 75/COUT 63 P1 .11 /IN27 /IN51 /SCLK1 B/ OUT 27/ OUT 51/ CCPOS0C/T 2INA/ B P1 .10 /IN26 /IN50 /OUT 26 /OUT 50 /SLSO17 P1 .9/IN 25/ IN49 /M RST1B/OUT 25 /OUT 49 /CCPOS1 C/T 2EUDA/B P1 .8/IN 24/ IN48 /M T SR1B/OUT 24 /OUT 48 /CCPOS2 C/T 4EUDA/B P1 .2/IN 18/ OUT 18/OUT 74 P8.11 /OUT 106 P8.10 /OUT 105 P4 .3/IN 31/ IN55 /OUT 31/ OUT 55/ EXT CLK0 /T12 HRE/CT RAPA P8.9 /OUT 57 /SLSO34 AN1 9/DIG 3/P1 1.3 AN1 8/DIG 2/P1 1.2 AN1 7/DIG 1/P1 1.1 AN1 6/DIG 0/P1 1.0 AN15 AN14 VAGND0 V AREF0 VSSM VDDM AN13 AN12 AN11 AN10 AN9 AN8 AN6 AN5 AN4 AN3 AN2 AN1 AN0 V DD V DDP V5 AD0EM UX2/P1 .14 AD0EM UX1/P1 .13 AD0EM UX0/P1 .12 CC62 /CC62 INA/B/T CLK0/ OUT 32/ IN32 /P2.0 CCPOS0A/T 12 HRB/T 2INA/B/SLSO 13/ SL SO03 /OUT 33 /TR EADY0A/ IN33 /P2.1 CC61 /CC6 1INA/B/T VALID0 A/ OUT 34/ IN34 /P2.2 T1 2HRC/ T1 3HRC/C CPO S2A/T 4EUDA/B/T DATA0/ OUT 35/ IN35 /P2.3 COUT 63 /OUT 36 /RCLK0A/ IN36 /P2.4 CC6 0/CC6 0INA/B/RR EADY0 A/ OUT 37/ IN37 /P2.5 COUT 62 /OUT 38 /RVAL ID0A/ IN38 /P2.6 COUT 60 /OUT 39/ RDATA0A/ IN39 /P2.7 SLSO 32 /O U T100/ CC6 0/C C60IN C/ P8.5 C OU T61/ O U T101/ P8.6 CC 62IN C/ CC62/ O U T102/ P8.7 SLSO33 /O U T56/ P8.8 RXDCAN2/O UT5 2/O UT2 8/I N52/ IN28 /P4.0 T XDCAN2/O UT5 3/O UT2 9/I N53/ IN29 /P4.1 T 13H RB/ CCPOS1A/T 2EUDA/B/EXT CLK1/O UT5 4/O UT3 0/I N54/ IN30 /P4.2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 CCPOS2A/T 12HRC /T13 HRC/ T4 INA/B/OUT 36 /AD1EM UX2/RXDA1 /P5.14 V DDP V DD(SB) V5 M RST2B /P 10.0 M TSR2B /P 10.1 SCLK2B /P 10.2 SLSI 2B/SLSO20 /P 10.3 VPDG AN35 AN34 AN33 AN32 AN31 /DIG 15/ P11 .15 AN30 /DIG 14/ P11 .14 AN29 /DIG 13/ P11 .13 AN28 /DIG 12/ P11 .12 AN7 AN27 /DIG 11/ P11 .11 AN26 /DIG 10/ P11 .10 AN25 /DIG9 /P11 .9 AN24 /DIG8 /P11 .8 AN23 /DIG7 /P11 .7 AN22 /DIG6 /P11 .6 AN21 /DIG5 /P11 .5 AN20 /DIG4 /P11 .4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 17 6 17 5 17 4 17 3 17 2 17 1 17 0 16 9 16 8 167 16 6 16 5 16 4 16 3 16 2 16 1 16 0 15 9 15 8 1 57 15 6 15 5 15 4 15 3 15 2 15 1 15 0 14 9 14 8 147 14 6 14 5 14 4 14 3 14 2 14 1 14 0 13 9 13 8 137 13 6 13 5 13 4 13 3 P0.1 5/IN 15/ REQ 5/O UT1 5/O UT7 1/CO UT6 1 P0.1 4/IN 14/ REQ 4/O UT1 4/O UT7 0/CC 61IN C/ CC61 P0.7 /IN7 /HWCF G7/R EQ 3/O UT7 /OUT 63 /EVT O3 P0.6 /IN6 /HWCF G6/R EQ 2/O UT6 /OUT 62 /EVT O2 P9.2 /CO UT6 3/O U T82 P9.3 /O U T83/ CO U T62 P9.4 /CC 62IN C/ CC62 /O U T84 1) P0.1 3/IN 13/ OUT 13/T XE NB 1)/O UT6 9 P0.1 2/IN 12/ OUT 12/T XE NA /O UT6 8/CT RAPB/T1 3HRE P0.5 /IN5 /HWCF G5/O UT5 /OUT 61 /EVTO 1 P0.4 /IN4 /HWCF G4/O UT4 /OUT 60 /EVTO 0 P2.1 3/SL SI 11/SDI 0/CT RAPA/ T1 2HRE/SLSO 16/ T6O UT P2.8 /SLSO0 4/SLSO 14/ EN0 0 P2.1 2/M TSR1 A/SOP0B P2.1 1/SCL K1 A/FC LP0B P2.1 0/M RST1 A P2.9 /SLSO0 5/SLSO 15/ EN0 1 P6.3 /OUT 83 /SOP0A P6.2 /OUT 82 /SON0 P6.1 /OUT 81 /FC LP0A P6.0 /OUT 80 /FC LN0 V5 VDDP VDD P0.1 1/IN 11/ OUT 11/O UT6 7/REQ 9 P0.1 0/IN 10/ OUT 10/O UT6 6 P0.9 /IN9 /OUT 9/O UT6 5/T 6O UT P0.8 /IN8 /OUT 8/O UT6 4/T 3O UT P0.3 /IN3 /HWCF G3/O UT3 /OUT 59 P0.2 /IN2 /HWCF G2/O UT2 /OUT 58 P0.1 /IN1 /HWCF G1/O UT1 /OUT 57 /SDI1/ COUT 60 P0.0 /IN0 /HWCF G0/O UT0 /OUT 56 /CC60 /CC6 0INA/B P3.1 1/O UT9 3//R EQ 1 P3.1 2/O UT9 4//R XDC AN0 /RXD0B P3.1 3/O UT9 5//T XDCAN0/ TXD0 P8.0 /SCLK3 /CC PO S0C/ T3IN A/ B/ O UT4 8 P8.1 /M RST3/ CCP OS1 C/T 3EU DA /B /O U T49 P8.2 /M TSR3/ CCP OS2 C/T 4IN A/ B/ OU T50 P3.9 /OUT 91 /RXD1A P3.1 0/O UT9 2/REQ0 P3.0 /OUT 84 /RXD0A/RE Q 6 P3.1 /OUT 85 /TXD0 P3.1 4/O UT9 6RXDCAN1/ RXD1B/SDI2 P3.1 5/O UT9 7/T XDCAN1/T XD1 Pinning 1) Only available for SAK -T C1728 F- 192 F133 HR TC1728_QFP176 Figure 3-2 SAK-TC1728N-192F133HL / SAK-TC1728N-192F133HR / SAKTC1728F-192F133HR Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) Pin Symbol Ctrl. Type Function Port 0 Data Sheet 3-2 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 145 P0.0 I/O0 A1/ PU 146 147 148 Port 0 General Purpose I/O Line 0 IN0 I CCU60 I CC60INA CCU61 I CC60INB HWCFG0 I Hardware Configuration Input 0 OUT0 O1 GPTA0 Output 0 OUT56 O2 GPTA0 Output 56 GPTA0 Input 0 CCU60 O3 P0.1 I/O0 IN1 I SDI1 I MSC0 Serial Data Input 1 HWCFG1 I Hardware Configuration Input 1 OUT1 O1 GPTA0 Output 1 OUT57 O2 GPTA0 Output 57 CCU60 O3 COUT60 P0.2 I/O0 IN2 I CC60 A1/ PU A1/ PU Port 0 General Purpose I/O Line 1 GPTA0 Input 1 Port 0 General Purpose I/O Line 2 GPTA0 Input 2 HWCFG2 I Hardware Configuration Input 2 OUT2 O1 GPTA0 Output 2 OUT58 O2 GPTA0 Output 58 Reserved O3 P0.3 I/O0 IN3 I A1+/ Port 0 General Purpose I/O Line 3 PU GPTA0 Input 3 HWCFG3 I Hardware Configuration Input 3 OUT3 O1 GPTA0 Output 3 OUT59 O2 GPTA0 Output 59 Reserved O3 - Data Sheet 3-3 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 166 P0.4 I/O0 IN4 I A1/ PD HWCFG4 I Hardware Configuration Input 4 OUT4 O1 GPTA0 Output 4 OUT60 O2 GPTA0 Output 60 EVTO0 O3 MCDS event output 0 P0.5 I/O0 IN5 I HWCFG5 I Hardware Configuration Input 5 OUT5 O1 GPTA0 Output 5 OUT61 O2 GPTA0 Output 61 EVTO1 O3 MCDS event output 1 167 173 174 P0.6 I/O0 IN6 I HWCFG6 I A1/ PD A1/ PU Port 0 General Purpose I/O Line 4 GPTA0 Input 4 Port 0 General Purpose I/O Line 5 GPTA0 Input 5 Port 0 General Purpose I/O Line 6 GPTA0 Input 6 Hardware Configuration Input 6 REQ2 I External Request Input 2 OUT6 O1 GPTA0 Output 6 OUT62 O2 GPTA0 Output 62 EVTO2 O3 MCDS event output 2 P0.7 I/O0 IN7 I HWCFG7 I Hardware Configuration Input 7 REQ3 I External Request Input 3 OUT7 O1 GPTA0 Output 7 OUT63 O2 GPTA0 Output 63 EVTO3 O3 MCDS event output 3 Data Sheet A1/ PU Port 0 General Purpose I/O Line 7 GPTA0 Input 7 3-4 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 149 P0.8 I/O0 IN8 I A1/ PU OUT8 O1 GPTA0 Output 8 OUT64 O2 GPTA0 Output 64 150 151 152 168 Port 0 General Purpose I/O Line 8 GPTA0 Input 8 GPT121 O3 P0.9 I/O0 IN9 I GPTA0 Input 9 OUT9 O1 GPTA0 Output 9 OUT65 O2 GPTA0 Output 65 T3OUT A1/ PU Port 0 General Purpose I/O Line 9 GPT121 O3 P0.10 I/O0 IN10 I OUT10 O1 GPTA0 Output 10 OUT66 O2 GPTA0 Output 66 T6OUT A2/ PU Port 0 General Purpose I/O Line 10 GPTA0 Input 10 Reserved O3 P0.11 I/O0 IN11 I GPTA0 Input 11 REQ9 I External Request Input 9 OUT11 O1 GPTA0 Output 11 OUT67 O2 GPTA0 Output 67 Reserved O3 - A2/ PU P0.12 I/O0 IN12 I CCU60 I CTRAPB CCU61 I T13HRE OUT12 O1 GPTA0 Output 12 OUT68 O2 GPTA0 Output 68 TXENA O3 E-Ray Channel A transmit Data Output enable1) Data Sheet A2/ PU Port 0 General Purpose I/O Line 11 Port 0 General Purpose I/O Line 12 GPTA0 Input 12 3-5 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 169 P0.13 I/O0 IN13 I A2/ PU OUT13 O1 GPTA0 Output 13 OUT69 O2 GPTA0 Output 69 TXENB O3 E-Ray Channel B transmit Data Output enable1) P0.14 I/O0 IN14 I REQ4 I External Request Input 4 CCU61 I CC61INC OUT14 O1 GPTA0 Output 14 OUT70 O2 GPTA0 Output 70 CCU60 O3 P0.15 I/O0 IN15 I 175 176 Port 0 General Purpose I/O Line 13 GPTA0 Input 13 A1+/ Port 0 General Purpose I/O Line 14 PU GPTA0 Input 14 CC61 A1+/ Port 0 General Purpose I/O Line 15 PU GPTA0 Input 15 REQ5 I External Request Input 5 OUT15 O1 GPTA0 Output 15 OUT71 O2 GPTA0 Output 71 CCU60 O3 COUT61 Port 1 116 P1.0 I/O0 REQ15 I IN16 I GPTA0 Input 16 BRKIN I Break Input OUT16 O1 GPTA0 Output 16 OUT72 O2 GPTA0 Output 72 GPT120 O3 T3OUT BRKOUT O Break Output (controlled by OCDS module) Data Sheet A2/ PU Port 1 General Purpose I/O Line 0 External Request Input 15 3-6 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 119 P1.1 I/O0 IN17 I A1/ PU CCU60 I T13HRE CCU61 I CTRAPB OUT17 O1 GPTA0 Output 17 OUT73 O2 GPTA0 Output 73 Reserved O3 - 93 98 99 108 A1/ PU Port 1 General Purpose I/O Line 1 GPTA0 Input 17 P1.2 I/O0 IN18 I OUT18 O1 GPTA0 Output 18 OUT74 O2 GPTA0 Output 74 Reserved O3 A1/ PU Port 1 General Purpose I/O Line 2 GPTA0 Input 18 P1.3 I/O0 IN19 I OUT19 O1 GPTA0 Output 19 OUT75 O2 GPTA0 Output 75 CCU61 O3 COUT63 A1/ PU Port 1 General Purpose I/O Line 3 GPTA0 Input 19 P1.4 I/O0 IN20 I EMGSTOP I Emergency Stop Input OUT20 O1 GPTA0 Output 20 OUT76 O2 GPTA0 Output 76 CCU61 O3 COUT61 GPTA0 Input 20 P1.5 I/O0 IN21 I OUT21 O1 GPTA0 Output 21 OUT77 O2 GPTA0 Output 77 Reserved O3 - Data Sheet A1/ PU Port 1 General Purpose I/O Line 4 Port 1 General Purpose I/O Line 35 GPTA0 Input 21 3-7 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 109 P1.6 I/O0 IN22 I A1/ PU OUT22 O1 GPTA0 Output 22 OUT78 O2 GPTA0 Output 78 110 94 95 Port 1 General Purpose I/O Line 6 GPTA0 Input 22 Reserved O3 P1.7 I/O0 IN23 I OUT23 O1 GPTA0 Output 23 OUT79 O2 GPTA0 Output 79 A1/ PU Port 1 General Purpose I/O Line 7 GPTA0 Input 23 Reserved O3 P1.8 I/O0 IN24 I IN48 I GPTA0 Input 48 MTSR1B I SSC1 Slave Receive Input B (Slave Mode) CCU61 I CCPOS2C GPT120 I T4EUDB GPT121 I T4EUDA OUT24 O1 GPTA0 Output 24 OUT48 O2 GPTA0 Output 48 MTSR1B O3 SSC1 Master Transmit Output B (Master Mode) A1+/ Port 1 General Purpose I/O Line 8 PU GPTA0 Input 24 P1.9 I/O0 IN25 I IN49 I GPTA0 Input 49 MRST1B I SSC1 Master Receive Input B (Master Mode) CCU61 I CCPOS1C GPT120 I T2EUDB GPT121 I T2EUDA OUT25 O1 GPTA0 Output 25 OUT49 O2 GPTA0 Output 49 MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode) Data Sheet A1+/ Port 1 General Purpose I/O Line 9 PU GPTA0 Input 25 3-8 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 96 P1.10 I/O0 IN26 I A1+/ Port 1 General Purpose I/O Line 10 PU GPTA0 Input 26 IN50 I GPTA0 Input 50 OUT26 O1 GPTA0 Output 26 OUT50 O2 GPTA0 Output 50 SLSO17 O3 SSC1 Slave Select Output 7 P1.11 I/O0 IN27 I A1+/ Port 1 General Purpose I/O Line 11 PU GPTA0 Input 27 IN51 I GPTA0 Input 51 SCLK1B I SSC1 Clock Input B CCU61 I CCPOS0C GPT120 I T2INB GPT121 I T2INA OUT27 O1 GPTA0 Output 27 OUT51 O2 GPTA0 Output 51 97 73 72 71 SCLK1B O3 P1.12 I/O0 AD0EMUX0 O1 Reserved O2 - Reserved O3 - P1.13 I/O0 AD0EMUX1 O1 Reserved O2 SSC1 Clock Output B A1/ PU A1/ PU Port 1 General Purpose I/O Line 12 ADC0 External Multiplexer Control Output 0 Port 1 General Purpose I/O Line 13 ADC0 External Multiplexer Control Output 1 - Reserved O3 P1.14 I/O0 AD0EMUX2 O1 Reserved O2 - Reserved O3 - Data Sheet A1/ PU Port 1 General Purpose I/O Line 14 ADC0 External Multiplexer Control Output 2 3-9 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 117 P1.15 I/O0 BRKIN I A2/ PU Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O Break Output (controlled by OCDS module) Port 1 General Purpose I/O Line 15 Break Input Port 2 74 75 P2.0 I/O0 IN32 I CCU60 I CC62INB CCU61 I CC62INA OUT32 O1 GPTA0 Output 32 TCLK0 O2 MLI0 Transmitter Clock Output 0 CCU61 O3 CC62 P2.1 I/O0 IN33 I TREADY0A I MLI0 Transmitter Ready Input A CCU61 I CCPOS0A CCU60 I T12HRB GPT120 I T2INA GPT121 I T2INB OUT33 O1 GPTA0 Output 33 SLSO03 O2 SSC0 Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 Data Sheet A2/ PU A2/ PU Port 2 General Purpose I/O Line 0 GPTA0 Input 32 Port 2 General Purpose I/O Line 1 GPTA0 Input 33 3-10 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 76 P2.2 I/O0 IN34 I A2/ PU CCU60 I CC61INB CCU61 I CC61INA OUT34 O1 GPTA0 Output 34 TVALID0A O2 MLI0 Transmitter Valid Output CCU61 O3 CC61 77 78 79 A2/ PU Port 2 General Purpose I/O Line 2 GPTA0 Input 34 P2.3 I/O0 IN35 I CCU60 I T12HRC CCU60 I T13HRC CCU61 I CCPOS2A GPT120 I T4EUDA GPT121 I T4EUDB OUT35 O1 GPTA0 Output 35 TDATA0 O2 MLI0 Transmitter Data Output Reserved O3 A2/ PU Port 2 General Purpose I/O Line 3 GPTA0 Input 35 P2.4 I/O0 IN36 I RCLK0A I MLI Receiver Clock Input A OUT36 O1 GPTA0 Output 36 CCU61 O2 COUT63 Reserved O3 - GPTA0 Input 36 P2.5 I/O0 IN37 I CCU60 I CC60INB CCU61 I CC60INA OUT37 O1 GPTA0 Output 37 RREADY0A O2 MLI0 Receiver Ready Output A CCU61 O3 CC60 Data Sheet A2/ PU Port 2 General Purpose I/O Line 4 Port 2 General Purpose I/O Line 5 GPTA0 Input 37 3-11 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 80 P2.6 I/O0 A2/ PU 81 164 160 161 162 Port 2 General Purpose I/O Line 6 IN38 I RVALID0A I MLI Receiver Valid Input A OUT38 O1 GPTA0 Output 38 CCU61 O2 COUT62 Reserved O3 - P2.7 I/O0 RDATA0A I IN39 I GPTA0 Input 39 OUT39 O1 GPTA0 Output 39 CCU61 O2 COUT60 Reserved O3 - P2.8 I/O0 SLSO04 O1 SLSO14 O2 A2/ PU A2/ PU GPTA0 Input 38 Port 2 General Purpose I/O Line 7 MLI Receiver Data Input A Port 2 General Purpose I/O Line 8 SSC0 Slave Select Output 4 SSC1 Slave Select Output 4 EN00 O3 P2.9 I/O0 SLSO05 O1 SLSO15 O2 SSC1 Slave Select Output 5 EN01 O3 MSC0 Enable Output 1 MSC0 Enable Output 0 A2/ PU Port 2 General Purpose I/O Line 9 SSC0 Slave Select Output 5 P2.10 I/O0 MRST1A I A1+/ Port 2 General Purpose I/O Line 10 PU SSC1 Master Receive Input A MRST1A O1 SSC1 Slave Transmit Output Reserved O2 - Reserved O3 - P2.11 I/O0 SCLK1A I SCLK1A O1 SSC1 Clock Output A Reserved O2 - FCLP0B O3 MSC0 Clock Output Positive B Data Sheet A1+/ Port 2 General Purpose I/O Line 11 PU SSC1 Clock Input A 3-12 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 163 P2.12 I/O0 MTSR1A I A1+/ Port 2 General Purpose I/O Line 12 PU SSC1 Slave Receive Input A MTSR1A O1 SSC1 Master Transmit Output A Reserved O2 - 165 SOP0B O3 P2.13 I/O0 SLSI11 I MSC0 Serial Data Output Positive B A1+/ Port 2 General Purpose I/O Line 13 PU SSC1 Slave Select Input 1 SDI0 I MSC0 Serial Data Input 0 CCU60 I CTRAPA CCU61 I T12HRE Reserved O1 - SLSO16 O2 SSC1 Slave Select Output 6 GPT120 O3 T6OUT P3.0 I/O0 RXD0A I REQ6 I External Request Input 6 RXD0A O1 ASC0 Output (Sync. Mode) Reserved O2 - OUT84 O3 GPTA0 Output 84 Port 3 136 135 129 P3.1 I/O0 TXD0 O1 Reserved O2 A1+/ Port 3 General Purpose I/O Line 0 PU ASC0 Receiver Input A (Async. & Sync. Mode) A1+/ Port 3 General Purpose I/O Line 1 PU ASC0 Output - OUT85 O3 P3.2 I/O0 SCLK0 I SCLK0 O1 SSC0 Clock Output (Master Mode) Reserved O2 - OUT86 O3 GPTA0 Output 86 Data Sheet GPTA0 Output 85 A1+/ Port 3 General Purpose I/O Line 2 PU SSC0 Clock Input (Slave Mode) 3-13 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 130 P3.3 I/O0 MRST0 I A1+/ Port 3 General Purpose I/O Line 3 PU SSC0 Master Receive Input (Master Mode) MRST0 O1 SSC0 Slave Transmit Output (Slave Mode) Reserved O2 - 132 126 OUT87 O3 P3.4 I/O0 MTSR0 I MTSR0 O1 SSC0 Master Transmit Output (Master Mode) Reserved O2 - GPTA0 Output 87 A2/ PU O3 P3.5 I/O0 SLSO00 O1 A1+/ Port 3 General Purpose I/O Line 5 PU SSC0 Slave Select Output 0 SLSO10 O2 SSC1 Slave Select Output 0 GPTA0 Output 88 SSC0 AND SSC1 Slave Select Output 0 P3.6 I/O0 SLSO01 O1 A1+/ Port 3 General Purpose I/O Line 6 PU SSC0 Slave Select Output 1 SLSO11 O2 SSC1 Slave Select Output 1 SLSOANDO1 O3 131 128 SSC0 Slave Receive Input (Slave Mode) OUT88 SLSOANDO0 O3 127 Port 3 General Purpose I/O Line 4 SSC0 AND SSC1 Slave Select Output 1 P3.7 I/O0 A2/ PU SLSI0 I SLSO02 O1 SSC0 Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTA0 Output 89 P3.8 I/O0 REQ14 I A2/ PU Port 3 General Purpose I/O Line 7 SSC0 Slave Select Input 1 Port 3 General Purpose I/O Line 8 External Request Input 14 SLSO06 O1 SSC0 Slave Select Output 6 TXD1 O2 ASC1 Transmit Output OUT90 O3 GPTA0 Output 90 Data Sheet 3-14 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 138 P3.9 I/O0 RXD1A I A1/ PU RXD1A O1 ASC1 Receiver Output A (Synchronous Mode) Reserved O2 - 137 144 143 142 Port 3 General Purpose I/O Line 9 ASC1 Receiver Input A OUT91 O3 P3.10 I/O0 REQ0 I Reserved O1 - Reserved O2 - GPTA0 Output 91 A1/ PU Port 3 General Purpose I/O Line 10 External Request Input 0 OUT92 O3 P3.11 I/O0 REQ1 I Reserved O1 - Reserved O2 - OUT93 O3 GPTA0 Output 93 GPTA0 Output 92 A1/ PU A1/ PU Port 3 General Purpose I/O Line 11 External Request Input 1 P3.12 I/O0 RXDCAN0 I RXD0B I ASC0 Receiver Input B RXD0B O1 ASC0 Receiver Output B (Synchronous Mode) Reserved O2 - Port 3 General Purpose I/O Line 12 CAN Node 0 Receiver Input OUT94 O3 P3.13 I/O0 TXDCAN0 O1 TXD0 O2 ASC0 Transmit Output OUT95 O3 GPTA0 Output 95 Data Sheet GPTA0 Output 94 A2/ PU Port 3 General Purpose I/O Line 13 CAN Node 0 Transmitter Output 3-15 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 134 P3.14 I/O0 RXDCAN1 I A1/ PU RXD1B I ASC1 Receiver Input B SDI2 I MSC0 Serial Data Input 2 RXD1B O1 ASC1 Receiver Output B (Synchronous Mode) Reserved O2 - OUT96 O3 GPTA0 Output 96 133 A2/ PU Port 3 General Purpose I/O Line 14 CAN Node 1 Receiver Input P3.15 I/O0 TXDCAN1 O1 TXD1 O2 ASC1 Transmit Output OUT97 O3 GPTA0 Output 97 Port 3 General Purpose I/O Line 15 CAN Node 1 Transmitter Output Port 4 86 87 P4.0 I/O0 IN28 I IN52 I GPTA0 Input 52 RXDCAN2 I CAN Node 2 Receiver Input OUT28 O1 GPTA0 Output 28 OUT52 O2 GPTA0 Output 52 Reserved O3 - P4.1 I/O0 IN29 I IN53 I GPTA0 Input 53 OUT29 O1 GPTA0 Output 29 OUT53 O2 GPTA0 Output 53 TXDCAN2 O3 CAN Node 2 Transmitter Output Data Sheet A1+/ Port 4 General Purpose I/O Line 0 PU GPTA0 Input 28 A1+/ Port 4 General Purpose I/O Line 1 PU GPTA0 Input 29 3-16 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 88 P4.2 I/O0 IN30 I A2/ PU IN54 I GPTA0 Input 54 CCU60 I T13HRB CCU61 I CCPOS1A GPT120 I T2EUDA GPT121 I T2EUDB OUT30 O1 GPTA0 Output 30 OUT54 O2 GPTA0 Output 54 90 Port 4 General Purpose I/O Line 2 GPTA0 Input 30 EXTCLK1 O3 P4.3 I/O0 IN31 I IN55 I GPTA0 Input 55 CCU60 I T12HRE CCU61 I CTRAPA OUT31 O1 GPTA0 Output 31 OUT55 O2 GPTA0 Output 55 EXTCLK0 O3 External Clock 0 Output P5.0 I/O0 External Clock 1 Output A2/ PU Port 4 General Purpose I/O Line 3 GPTA0 Input 31 Port 5 1 A1+/ Port 5 General Purpose I/O Line 0 PU External Request Input 7 REQ7 I IN40 I GPTA0 Input 40 CCU60 I CC62INA CCU61 I CC62INB GPT120 I CAPINB GPT121 I CAPINA OUT40 O1 GPTA0 Output 40 CCU60 O2 CC62 SLSO20 O3 SSC2 Slave Select Output 0 Data Sheet 3-17 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 2 P5.1 I/O0 IN41 I A1+/ Port 5 General Purpose I/O Line 1 PU GPTA0 Input 41 OUT41 O1 GPTA0 Output 41 Reserved O2 - 3 4 5 6 SLSO21 O3 SSC2 Slave Select Output 1 P5.2 I/O0 IN42 I A1+/ Port 5 General Purpose I/O Line 2 PU GPTA0 Input 42 OUT42 O1 GPTA0 Output 42 CCU60 O2 COUT62 SLSO22 O3 SSC2 Slave Select Output 2 P5.3 I/O0 IN43 I A1+/ Port 5 General Purpose I/O Line 3 PU GPTA0 Input 43 OUT43 O1 GPTA0 Output 43 Reserved O2 - SLSO23 O3 SSC2 Slave Select Output 3 P5.4 I/O0 IN44 I A1+/ Port 5 General Purpose I/O Line 4 PU GPTA0 Input 44 SLSI2A I SSC2 Slave Select Input A OUT44 O1 GPTA0 Output 44 Reserved O2 - SLSO24 O3 SSC2 Slave Select Output 4 P5.5 I/O0 IN45 I A1+/ Port 5 General Purpose I/O Line 5 PU GPTA0 Input 45 MRST2A I SSC2 Master Receive Input A (Master Mode) OUT45 O1 GPTA0 Output 45 Reserved O2 - MRST2 O3 SSC2 Slave Transmit Output (Slave Mode) Data Sheet 3-18 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 7 P5.6 I/O0 IN46 I A1+/ Port 5 General Purpose I/O Line 6 PU GPTA0 Input 46 MTSR2A I SSC2 Slave Receive Input (Slave Mode) OUT46 O1 GPTA0 Output 46 Reserved O2 - MTSR2 O3 SSC2 Master Transmit Output (Master Mode) P5.7 I/O0 IN47 I A1+/ Port 5 General Purpose I/O Line 7 PU GPTA0 Input 47 SCLK2A I SSC2 Clock Input A (Slave Mode) OUT47 O1 GPTA0 Output 47 Reserved O2 - SCLK2 O3 SSC2 Clock Output (Master Mode) 8 13 14 15 P5.8 I/O0 CCU60 I A2/ PU CCU61 I CC61INB OUT6 O1 GPTA0 Output 6 TXDA1 O2 E-Ray Channel A transmit Data Output1) CCU60 O3 P5.9 I/O0 RXDCAN0 I Port 5 General Purpose I/O Line 8 CC61INA CC61 A2/ PU Port 5 General Purpose I/O Line 9 CAN Node 0 Receiver Input OUT7 O1 GPTA0 Output 7 TXDB1 O2 E-Ray Channel B transmit Data Output1) Reserved O3 - P5.10 I/O0 OUT8 O1 TXENA O2 E-Ray Channel A transmit Data Output enable1) CCU60 O3 COUT61 Data Sheet A2/ PU Port 5 General Purpose I/O Line 10 GPTA0 Output 8 3-19 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 16 P5.11 I/O0 A2/ PU 17 18 19 Port 5 General Purpose I/O Line 11 OUT9 O1 TXENB O2 CCU60 O3 P5.12 I/O0 CCU60 I CCU61 I T12HRB GPT120 I T3INA GPT121 I T3INB OUT19 O1 GPTA0 Output 19 SLSO07 O2 SSC0 Slave Select Output 7 AD1EMUX0 O3 P5.13 I/O0 CCU60 I CCU61 I T13HRB GPT120 I T3EUDA GPT121 I T3EUDB OUT20 O1 GPTA0 Output 20 Reserved O2 - AD1EMUX1 O3 P5.14 I/O0 RXDA1 I CCU60 I CCPOS2A CCU61 I T12HRC CCU61 I T13HRC GPT120 I T4INA GPT121 I T4INB OUT36 O1 GPTA0 Output 36 Reserved O2 - AD1EMUX2 O3 ADC1 External Multiplexer Control Output 2 Data Sheet GPTA0 Output 9 E-Ray Channel B transmit Data Output enable1) COUT63 A1+/ Port 5 General Purpose I/O Line 12 PU CCPOS0A ADC1 External Multiplexer Control Output 0 A1+/ Port 5 General Purpose I/O Line 13 PU CCPOS1A ADC1 External Multiplexer Control Output 1 A1+/ Port 5 General Purpose I/O Line 14 PU E-Ray Channel A Receive Data Input 11) 3-20 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 9 P5.15 I/O0 A1+/ Port 5 General Purpose I/O Line 15 PU E-Ray Channel B Receive Data Input 11) RXDB1 I OUT37 O1 GPTA0 Output 37 Reserved O2 - TXDCAN0 O3 CAN Node 0 Transmitter Output P6.0 I/O0 FCLN0 O1 OUT80 O2 Port 6 156 157 158 159 F/ PU Port 6 General Purpose I/O Line 0 MSC0 Clock Output Negative GPTA0 Output 80 Reserved O3 P6.1 I/O0 FCLP0A O1 OUT81 O2 GPTA0 Output 81 Reserved O3 - P6.2 I/O0 SON0 O1 OUT82 O2 F/ PU F/ PU Port 6 General Purpose I/O Line 1 MSC0 Clock Output Positive A Port 6 General Purpose I/O Line 2 MSC0 Serial Data Output Negative GPTA0 Output 82 Reserved O3 P6.3 I/O0 SOP0A O1 OUT83 O2 GPTA0 Output 83 Reserved O3 - F/ PU Port 6 General Purpose I/O Line 3 MSC0 Serial Data Output Positive A Port 8 Data Sheet 3-21 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 141 P8.0 I/O0 A2/ PU 140 139 124 Port 8 General Purpose I/O Line 0 SCLK3 I CCU60 I CCPOS0C GPT120 I T3INB GPT121 I T3INA Reserved O1 - OUT48 O2 GPTA0 Output 48 SCLK3 O3 P8.1 I/O0 SSC3 Clock Input (Slave Mode) SSC3 Clock Output (Master Mode) A2/ PU Port 8 General Purpose I/O Line 1 MRST3 I CCU60 I CCPOS1C GPT120 I T3EUDB GPT121 I T3EUDA Reserved O1 - OUT49 O2 GPTA0 Output 49 MRST3 O3 P8.2 I/O0 SSC3 Master Receive Input (Master Mode) SSC3 Slave Transmit Output (Slave Mode) A2/ PU Port 8 General Purpose I/O Line 2 MTSR3 I CCU60 I CCPOS2C GPT120 I T4INB GPT121 I T4INA Reserved O1 - OUT50 O2 GPTA0 Output 50 MTSR3 O3 P8.3 I/O0 SSC3 Slave Receive Input (Slave Mode) SSC3 Master Transmit Output (Master Mode) A2/ PU Port 8 General Purpose I/O Line 3 SLSI3 I CCU60 I CC61INC CCU61 O1 CC61 OUT51 O2 GPTA0 Output 51 SLSO30 O3 SSC3 Slave Select Output 0 Data Sheet SSC3 Slave Select Input B 3-22 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 123 P8.4 I/O0 A2/ PU 82 83 84 85 89 91 Port 8 General Purpose I/O Line 4 OUT99 O1 CCU61 O2 COUT62 SLSO31 O3 SSC3 Slave Select Output 1 A2/ PU GPTA0 Output 99 P8.5 I/O0 CCU60 I OUT100 O1 GPTA0 Output 100 CCU61 O2 CC60 SLSO32 O3 SSC3 Slave Select Output 2 CC60INC P8.6 I/O0 OUT101 O1 Reserved O2 CCU61 O3 P8.7 I/O0 CCU60 I OUT102 O1 GPTA0 Output 102 Reserved O2 - CCU61 O3 P8.8 I/O0 Reserved O1 OUT56 O2 GPTA0 Output 56 SLSO33 O3 SSC3 Slave Select Output 3 P8.9 I/O0 Reserved O1 OUT57 O2 A2/ PU Port 8 General Purpose I/O Line 5 Port 8 General Purpose I/O Line 6 GPTA0 Output 101 COUT61 A2/ PU Port 8 General Purpose I/O Line 7 CC62INC CC62 A2/ PU A2/ PU Port 8 General Purpose I/O Line 8 - Port 8 General Purpose I/O Line 9 GPTA0 Output 57 SLSO34 O3 P8.10 I/O0 OUT105 O1 Reserved O2 - Reserved O3 - Data Sheet SSC3 Slave Select Output 4 A2/ PU Port 8 General Purpose I/O Line 10 GPTA0 Output 105 3-23 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 92 P8.11 I/O0 OUT106 O1 A2/ PU Reserved O2 - Reserved O3 - 100 125 P8.12 I/O0 OUT107 O1 Reserved O2 A2/ PU Port 8 General Purpose I/O Line 11 GPTA0 Output 106 Port 8 General Purpose I/O Line 12 GPTA0 Output 107 - Reserved O3 P8.13 I/O0 OUT4 O1 Reserved O2 - CCU61 O3 COUT60 P9.2 I/O0 Reserved O1 A2/ PU Port 8 General Purpose I/O Line 13 GPTA0 Output 4 Port 9 172 171 170 A1/ PU Port 9 General Purpose I/O Line 2 - OUT82 O2 GPTA0 Output 82 CCU60 O3 COUT63 P9.3 I/O0 Reserved O1 OUT83 O2 CCU60 O3 P9.4 I/O0 CCU61 I A1/ PU Port 9 General Purpose I/O Line 3 GPTA0 Output 83 COUT62 A1/ PU Port 9 General Purpose I/O Line 4 CC62INC Reserved O1 - OUT84 O2 GPTA0 Output 84 CCU60 O3 CC62 Data Sheet 3-24 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 111 P9.5 I/O0 A2/ PU 113 11 12 Port 9 General Purpose I/O Line 5 TDI I BRKIN I OCDS Break Input Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O OCDS Break Output (controlled by OCDS module) P9.6 I/O0 TDO I BRKIN I OCDS Break Input Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O OCDS Break Output (controlled by OCDS module) TDO O JTAG Serial Data Output (controlled by OCDS module) A2/ PU A1/ PU JTAG Serial Data Input Port 9 General Purpose I/O Line 6 JTAG Serial Data Output P9.7 I/O0 CCU61 I Reserved O1 - OUT87 O2 GPTA0 Output 87 CCU60 O3 CC60 P9.8 I/O0 A1/ PU Port 9 General Purpose I/O Line 7 CC60INC Port 9 General Purpose I/O Line 7 Reserved O1 OUT88 O2 GPTA0 Output 88 CCU60 O3 COUT60 - Port 10 Data Sheet 3-25 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 23 P10.0 I/O0 A2/ PU 24 25 26 Port 10 General Purpose I/O Line 0 MRST2B I MRST2 O1 SSC2 Slave Transmit Output (Slave Mode) Reserved O2 - SSC2 Master Receive Input B (Master Mode) Reserved O3 P10.1 I/O0 MTSR2B I MTSR2 O1 SSC2 Master Transmit Output (Master Mode) Reserved O2 - A2/ PU Port 10 General Purpose I/O Line 1 SSC2 Slave Receive Input B (Slave Mode) Reserved O3 P10.2 I/O0 SCLK2B I SCLK2 O1 SSC2 Clock Output (Master Mode) Reserved O2 - Reserved O3 - A2/ PU A2/ PU Port 10 General Purpose I/O Line 2 SSC2 Clock Input B (Slave Mode) P10.3 I/O0 SLSI2B I SLSO20 O1 SSC2 Slave Select Output 0 Reserved O2 - Reserved O3 - Port 10 General Purpose I/O Line 3 SSC2 Slave Select Input B Port 11 48 47 46 P11.0 I D / S Port 11 General Purpose I/O Line 02) Dig0 I Digital Input 0 AN16 I Analog Input : ADC1.CH0 3) P11.1 I D / S Port 11 General Purpose I/O Line 12) Dig1 I Digital Input 1 AN17 I Analog Input : ADC1.CH1 3) P11.2 I D / S Port 11 General Purpose I/O Line 22) Dig2 I Digital Input 2 AN18 I Analog Input : ADC1.CH2 3) Data Sheet 3-26 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 45 P11.3 I D / S Port 11 General Purpose I/O Line 32) 44 43 42 41 40 39 38 37 35 Dig3 I Digital Input 3 AN19 I Analog Input : ADC1.CH3 3) P11.4 I D / S Port 11 General Purpose I/O Line 42) Dig4 I Digital Input 4 AN20 I Analog Input : ADC1.CH4 3) P11.5 I D / S Port 11 General Purpose I/O Line 52) Dig5 I Digital Input 5 AN21 I Analog Input : ADC1.CH5 3) P11.6 I Dig6 I Digital Input 6 AN22 I Analog Input : ADC1.CH6 3) P11.7 I Dig7 I Digital Input 7 AN23 I Analog Input : ADC1.CH7 3) P11.8 I Dig8 I Digital Input 8 AN24 I Analog Input : ADC1.CH8 3) P11.9 I Dig9 I Digital Input 9 AN25 I Analog Input : ADC1.CH9 3) P11.10 I Dig10 I Digital Input 10 AN26 I Analog Input : ADC1.CH10 3) P11.11 I D / S Port 11 General Purpose I/O Line 62) D / S Port 11 General Purpose I/O Line 72) D / S Port 11 General Purpose I/O Line 82) D / S Port 11 General Purpose I/O Line 92) D / S Port 11 General Purpose I/O Line 102) D / S Port 11 General Purpose I/O Line 112) Dig11 I Digital Input 11 AN27 I Analog Input : ADC1.CH11 3) P11.12 I D / S Port 11 General Purpose I/O Line 122) Dig12 I Digital Input 12 AN28 I Analog Input : ADC1.CH12 3) Data Sheet 3-27 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 34 P11.13 I D / S Port 11 General Purpose I/O Line 132) 33 32 Dig13 I Digital Input 13 AN29 I Analog Input : ADC1.CH13 3) P11.14 I D / S Port 11 General Purpose I/O Line 142) Dig14 I Digital Input 14 AN30 I Analog Input : ADC1.CH14 3) P11.15 I D / S Port 11 General Purpose I/O Line 152) Dig15 I Digital Input 15 AN31 I Analog Input : ADC1.CH15 3) Analog Input Port 67 AN0 I D Analog Input 0: ADC0.CH0 3) 66 AN1 I D Analog Input 1: ADC0.CH1 3) 65 AN2 I D Analog Input 2: ADC0.CH2 3) 64 AN3 I D Analog Input 3: ADC0.CH3 3) 63 AN4 I D Analog Input 4: ADC0.CH4 3) 62 AN5 I D Analog Input 5: ADC0.CH5 3) 61 AN6 I D Analog Input 6: ADC0.CH6 3) 36 AN7 I D Analog Input 7: ADC0.CH7 3) 60 AN8 I D Analog Input 8: ADC0.CH8 3) 59 AN9 I D Analog Input 9: ADC0.CH9 3) 58 AN10 I D Analog Input 10: ADC0.CH10 3) 57 AN11 I D Analog Input 11: ADC0.CH11 3) 56 AN12 I D Analog Input 12: ADC0.CH12 3) 55 AN13 I D Analog Input 13: ADC0.CH13 3) 50 AN14 I D Analog Input 14: ADC0.CH14 3) 49 AN15 I D Analog Input 15: ADC0.CH15 3) 48 AN16 I D / S Analog Input 16: ADC1.CH0, Dig0 3) 47 AN17 I D / S Analog Input 17: ADC1.CH1, Dig1 3) 46 AN18 I D / S Analog Input 18: ADC1.CH2, Dig2 3) 45 AN19 I D / S Analog Input 19: ADC1.CH3, Dig3 3) Data Sheet 3-28 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 44 AN20 I D / S Analog Input 20: ADC1.CH4, Dig4 3) 43 AN21 I D / S Analog Input 21: ADC1.CH5, Dig5 3) 42 AN22 I D / S Analog Input 22: ADC1.CH6, Dig6 3) 41 AN23 I D / S Analog Input 23: ADC1.CH7, Dig7 3) 40 AN24 I D / S Analog Input 24: ADC1.CH8, Dig8 3) 39 AN25 I D / S Analog Input 25: ADC1.CH9, Dig9 3) 38 AN26 I D / S Analog Input 26: ADC1.CH10, Dig10 3) 37 AN27 I D / S Analog Input 27: ADC1.CH11, Dig11 3) 35 AN28 I D / S Analog Input 28: ADC1.CH12, Dig12 3) 34 AN29 I D / S Analog Input 29: ADC1.CH13, Dig13 3) 33 AN30 I D / S Analog Input 30: ADC1.CH14, Dig14 3) 32 AN31 I D / S Analog Input 31: ADC1.CH15, Dig15 3) 31 AN32 I D Analog Input 32: FADC_FADIN0P 4) 30 AN33 I D Analog Input 33: FADC_FADIN0N 4) 29 AN34 I D Analog Input 34: FADC_FADIN1P 4) 28 AN35 I D Analog Input 35: FADC_FADIN1N 4) 54 VDDM VSSM VAREF0 VAGND0 VDD - - ADC Analog Part Power Supply (3.3V - 5V) - - ADC Analog Part Ground - - ADC0 and ADC1 Reference Voltage - - ADC Reference Ground - - Digital Core Power Supply (1.3V) VDDP - - Port Power Supply (3.3V) 53 52 51 10, 215), 68, 105, 153 20, 69, 106, 154 Data Sheet 3-29 V1.2, 2014-06 TC1728 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-176-6 Package) (cont’d) Pin Symbol Ctrl. Type Function 22, 70, 107, 155 V5 - - EVR Power Supply (5V) 27 VPDG - - EVR Pass Device Gate If this pin is connected to ground, the internal pass devices are used and the external pass device bypassed. 101, 104 VSS - - Digital Ground 102 XTAL1 I Main Oscillator Input 103 XTAL2 O Main Oscillator Output 112 TMS I A2/ PD JTAG State Machine Control Input DAP1 I/O 114 TRST I A1/ PD JTAG Reset Input 115 TCK I I A1/ PD JTAG Clock Input DAP0 118 TESTMODE I I/PU Test Mode Select Input 120 ESR1 I/O A2/ PD External System Request Reset Input 1 121 PORST I I/PU Power On Reset 122 ESR0 I/O A2 External System Request Reset Input 0 Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. Device Access Port Line 1 Device Access Port Line 0 1) Only applicable for SAK-TC1728F-192F133HR. 2) Analog input overlayed with digital input functionality. The related port logic is used to configure the input as either analog input (default after reset) or digital input. The related port logic supports only the port input features as the connected pads are input only pads. 3) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table. 4) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table. 5) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the production devide device, this pin is bonded to a VDD pad. Data Sheet 3-30 V1.2, 2014-06 TC1728 Pinning Legend for Table 3-1 Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X00B O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2) O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column “Type”: A1 = Pad class A1 (LVTTL) A1+ = Pad class A1+ (LVTTL) A2 = Pad class A2 (LVTTL) F = Pad class F (LVDS/CMOS) D = Pad class D (ADC) I = Pad class I (LVTTL) S = Pad class S (CMOS) PU = with pull-up device connected during reset (PORST = 0) PD = with pull-down device connected during reset (PORST = 0) TR = tri-state during reset (PORST = 0) Data Sheet 3-31 V1.2, 2014-06 TC1728 Pinning Data Sheet 3-32 V1.2, 2014-06 TC1728 Identification Registers 4 Identification Registers The Identification Registers uniquely identify the device. Table 2 SAK-TC1728N-192F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H AB CBS_JTAGID 101D 0083H F000 0464H AB SCU_CHIPID 0300 9C01H F000 0640H AB SCU_MANID 0000 1820H F000 0644H AB SCU_RTID 0000 0001H F000 0648H AB Table 3 SAK-TC1728N-192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H AC CBS_JTAGID 101D 0083H F000 0464H AC SCU_CHIPID 8300 9C01H F000 0640H AC SCU_MANID 0000 1820H F000 0644H AC SCU_RTID 0000 0002H F000 0648H AC Table 4 SAK-TC1728F-192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H AC CBS_JTAGID 101D 0083H F000 0464H AC SCU_CHIPID 8300 AD01H F000 0640H AC SCU_MANID 0000 1820H F000 0644H AC SCU_RTID 0000 0002H F000 0648H AC Table 5 SAK-TC1728F-192F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H AB CBS_JTAGID 101D 0083H F000 0464H AB SCU_CHIPID 0300 AD01H F000 0640H AB Data Sheet 4-1 V1.2, 2014-06 TC1728 Identification Registers Table 5 SAK-TC1728F-192F133HL Identification Registers (cont’d) Short Name Value Address Stepping SCU_MANID 0000 1820H F000 0644H AB SCU_RTID 0000 0001H F000 0648H AB Data Sheet 4-2 V1.2, 2014-06 TC1728 Electrical Parameters 5 Electrical Parameters This specification provides all electrical parameters of the TC1728. 5.1 General Parameters 5.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1728 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”: • • CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1728 and must be regarded for a system design. SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1728 designed in. Data Sheet 5-1 V1.2, 2014-06 TC1728 Electrical Parameters 5.1.2 Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1. Table 6 Pad Driver and Pad Classes Overview Class Power Type Supply A F 3.3 V 3.3 V LVTTL I/O, LVTTL outputs Sub Class Speed Load Grade A1 6 MHz (e.g. GPIO) Leakage1) 150°C 100 pF 500 nA Termination No A1+ (e.g. serial I/Os) 25 MHz 50 pF 1 μA Series termination recommended A2 (e.g. serial I/Os) 40 MHz 50 pF 3 μA Series termination recommended LVDS – 50 MHz – – 2) CMOS – 50 MHz – – Parallel termination, 100 Ω ± 10% DE 5V ADC – – – – I 3.3 V LVTTL (input only) – – – – 1) Two values are given: for TJ = 150 °C and a 50% higher value for TJ = 160 °C. 2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 Ω ± 10%. Data Sheet 5-2 V1.2, 2014-06 TC1728 Electrical Parameters 5.1.3 Absolute Maximum Ratings Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 7 Absolute Maximum Rating Parameters Parameter Symbol Values Min. Typ. Max. Storage temperature TST Voltage at 1.3 V power supply VDD pins with respect to VSS Voltage at 3.3 V power supply VDDP SR pins with respect to VSS Voltage at 5 V power supply VDDM pins with respect to VSS Voltage on any Class A input VIN Unit Note / Test Con dition SR -65 – 160 °C – SR – – 2.0 V – – – 4.33 V – SR – – 7.0 V – SR -0.6 – VDDP + 0.5 V or max. 4.33 Whatever is lower -0.6 – 7.0 V – Voltage on any shared Class VAINF -0.6 – D analog input pin with respect to VSSAF, if the FADC SR is switched through to the pin. 7.0 V – Input current on any pin during overload condition pin and dedicated input pins with respect to VSS Voltage on any Class D analog input pin with respect to VAGND VAIN VAREFx SR IIN -10 – +10 mA Absolute maximum sum of all IIN input circuit currents for one port group during overload condition1) -75 – +75 mA Absolute maximum sum of all ΣIIN input circuit currents during overload condition – – |200| mA Data Sheet 5-3 V1.2, 2014-06 TC1728 Electrical Parameters 1) The port groups are defined in Table 12. Data Sheet 5-4 V1.2, 2014-06 TC1728 Electrical Parameters 5.1.4 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 8 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: • • full operation life-time (24000 h) is not exceeded Operating Conditions are met for – pad supply levels (VDDP or VDDM) – temperature If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Table 8 Overload Parameters Parameter Min. Typ. Max. Unit Note / Test Con dition Input current on any digital pin IIN during overload condition except LVDS pins -5 mA Input current on LVDS pins IINLVDS IING -3 – +3 mA -70 – +70 mA IINANA IINSAS -3 – +3 mA -15 – +15 mA ΣIINS -100 – 100 mA Absolute sum of all input circuit currents for one port group during overload condition1) Input current on analog pins Absolute sum of all analog input currents for analog inputs of a single ADC during overload condition Absolute sum of all input circuit currents during overload condition Symbol Values – +5 1) The port groups are defined in Table 12. Note: FADC input pins count as analog pin as they are overlayed with an ADC pins. Data Sheet 5-5 V1.2, 2014-06 TC1728 Electrical Parameters Table 9 Pad Type A1 / A1+ / F A2 LVDS D/S Table 10 Pad Type A1 / A1+ / F A2 LVDS D/S PN-Junction Characterisitics for positive Overload IIN = 3 mA UIN = VDDP + 0.6 V UIN = VDDP + 0.5 V UIN = VDDP + 0.7 V UIN = VDDM + 0.6 V IIN = 5 mA UIN = VDDP + 0.7 V UIN = VDDP + 0.6 V - PN-Junction Characterisitics for negative Overload IIN = -3 mA UIN = VSS - 0.6 V UIN = VSS - 0.5 V UIN = VSS - 0.7 V UIN = VSSM - 0.6 V IIN = -5 mA UIN = VSS - 0.7 V UIN = VSS - 0.6 V - Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life-time. Data Sheet 5-6 V1.2, 2014-06 TC1728 Electrical Parameters 5.1.5 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC1728. All parameters specified in the following tables refer to these operating conditions, unless otherwise noticed. Digital supply voltages applied to the TC1728 from external must be static regulated voltages which allow a typical voltage swing of ± 5 %. All parameters specified in the following tables refer to these operating conditions (Table 11), unless otherwise noticed in the Note / Test Condition column. Table 11 Operating Conditions Parameters Parameter Symbol Values Min. Overload coupling factor for analog inputs, negative KOVAN Overload coupling factor for analog inputs, positive KOVAP CPU Frequency fCPU fFPI fLMB fPCP IID CC − Unit Typ Max. . − IOV≥ -2 mA; IOV≤ 0 mA; analog 0.0001 pad= 5.0 V CC − − IOV≥ 0 mA; IOV≤ 3 mA; analog 0.00001 pad= 5.0 V SR − − 133 MHz − − 110 MHz SR − − 133 MHz SR − − 133 MHz SR -1 − 1 mA SR -5 − 5 mA Absolute sum of ΣISC_D CC − short circuit currents of the device − 100 mA Absolute sum of ΣISC_PG CC − short circuit currents per pin group − 70 mA Ambient Temperature − 125 °C FPI Frequency LMB Frequency PCP Frequency Inactive device pin current Short circuit current of digital outputs1) Data Sheet Note / Test Condition ISC TA SR SR -40 5-7 All power supply voltages VDDx = 0 V1.2, 2014-06 TC1728 Electrical Parameters Table 11 Operating Conditions Parameters Parameter Symbol Values Min. Unit Typ Max. . Note / Test Condition SR -40 − 160 °C Core Supply Voltage VDD SR 1.17 1.3 1.432) V ADC analog supply voltage VDDM SR 2.97 5.0 5.53) V EVR supply voltage V5 4.00 5.0 5.5 V 5.0V single supply 2.97 3.3 3.63 V 3.3V single supply Only required if externally supplied5) Junction temperature TJ Digital supply voltage VDDP for IO pads SR SR 2.97 4) 3.3 3.63 V − − V VDDP voltage to ensure defined pad states6) VDDPPA CC 0.65 Digital ground voltage VSS SR 0 − − V Analog ground voltage for VDDM VSSM SR -0.1 0 0.1 V Only required if externally supplied5) 1) Applicable for digital outputs. 2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 5) No external inductive load permissable if EVR is used. 6) This parameter is valid under the assumption the PORST signal is constantly at low level during the powerup/power-down of VDDP. Table 12 Pin Groups for Overload / Short-Circuit Current Sum Parameter Group Pins 1 P0.15, P5.[7:0], P5.[15:8], P9.[8:7], P10.[3:0] 2 P0.[14:0], P2.[13:8], P3.[1:0], P3.[4:3], P3.7, P3.[15:9], P6.[3:0], P8.[2:0], P9.[4:2] Data Sheet 5-8 V1.2, 2014-06 TC1728 Electrical Parameters Table 12 Pin Groups for Overload / Short-Circuit Current Sum Parameter (cont’d) Group Pins 3 P1.[1:0], P1.[7:5], P1.15, P3.2, P3.[6:5], P3.8, P8.[4:3], P8.13, P9.[6:5] 4 P1.[4:2], P1.[14:8], P2.[7:0], P4.[3:0], P8.[12:5] Data Sheet 5-9 V1.2, 2014-06 TC1728 Electrical Parameters 5.2 DC Parameters 5.2.1 Input/Output Pins Table 13 Standard_Pads Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition TA= 25 °C; f= 1 MHz Vi≥ 0.6 x VDDP V Vi≥ 0.36 x VDDP V Vi≤ 0.6 x VDDP V Vi≤ 0.36 x VDDP V Pin capacitance (digital inputs/outputs) CIO CC − − 10 pF Pull-down current |IPDL| CC − − 150 μA 10 − − μA 10 − − μA − − 100 μA − − 10 ns only PORST pin 120 − − ns only PORST pin Pull-Up current Spike filter always blocked pulse duration |IPUH| CC tSF1 CC Spike filter pass-through tSF2 CC pulse duration Table 14 Standard_Pads Class_A1 Parameter Symbol Values Min. Typ. Unit Max. HYSA CC 0.1 x − VDDP Input Leakage Current IOZA1 CC -500 − − V 500 nA -750 − 750 nA Input Hysteresis for pads of all A classes1) Class A1 Ratio Vil/Vih, A1 pads Data Sheet 0.6 VILA1 / VIHA1 CC − 5-10 Note / Test Condition Vi≤ VDDP V; Vi≥ 0 V; -40°C ≤ TJ ≤ 150°C Vi≤ VDDP V; Vi≥ 0 V; 150°C < TJ ≤ 160°C − V1.2, 2014-06 TC1728 Electrical Parameters Table 14 Standard_Pads Class_A1 Parameter On-Resistance of the class A1 pad, weak driver Symbol Values − 450 600 Ohm IOH> -0.5 mA; P_MOS − 210 340 Ohm IOL< 0.5 mA; N_MOS − − 155 Ohm IOH> -2 mA; P_MOS − − 110 Ohm IOL< 2 mA; N_MOS CC − − 150 ns CC CC Fall time,pad type A1 tFA1 Note / Test Condition Max. RDSONW On-Resistance of the class A1 pad, medium driver Unit Min. Typ. RDSONM CL= 20 pF; pin out driver= weak − − 50 ns CL= 50 pF; pin out driver= medium − − 140 ns CL= 150 pF; pin out − − 550 ns CL= 150 pF; pin out driver= medium driver= weak − − 18000 ns CL= 20000 pF; pin − − 65000 ns CL= 20000 pF; pin out driver= medium out driver= weak Rise time, pad type A1 tRA1 CC − − 150 ns CL= 20 pF; pin out driver= weak − − 50 ns CL= 50 pF; pin out − − 140 ns CL= 150 pF; pin out driver= medium driver= medium − − 550 ns CL= 150 pF; pin out driver= weak − − 18000 ns CL= 20000 pF; pin − − 65000 ns CL= 20000 pF; pin out driver= medium out driver= weak Data Sheet 5-11 V1.2, 2014-06 TC1728 Electrical Parameters Table 14 Standard_Pads Class_A1 Parameter Symbol Input high voltage, class A1 pads VIHA1 SR Unit Max. 0.6 x − min(VD V + 0.3, 3.6) VDDP Input low voltage, class VILA1 SR A1 pads Output voltage high, class A1 pads Values Min. Typ. Note / Test Condition DP − -0.3 0.36 x V VDDP VOHA1 CC VDDP − − V IOH≥ -1.4 mA; pin out − − V IOH≥ -2 mA; pin out - 0.4 2.4 driver= medium driver= medium VDDP − − V IOH≥ -400 μA; pin out driver= weak 2.4 − − V IOH≥ -500 μA; pin out driver= weak − − 0.4 V IOL≤ 2 mA; pin out - 0.4 Output voltage low, class A1 pads VOLA1 CC driver= medium − − 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 15 Standard_Pads Class_A1+ Parameter Symbo l Min. Values Input Hysteresis for HYSA1 0.1 x VDDP − + CC A1+ pads 1) Input Leakage Current Class A1+ Data Sheet IOZA1+ -1000 Unit Typ Max. . − − V 1000 nA Note / Test Condition CC 5-12 V1.2, 2014-06 TC1728 Electrical Parameters Table 15 Standard_Pads Class_A1+ Parameter Symbo l Min. Values Unit Typ Max. . Note / Test Condition On-Resistance of the class A1+ pad, weak driver RDSONW − 450 600 Ohm IOH> -0.5 mA; P_MOS − 210 340 Ohm IOL< 0.5 mA; N_MOS On-Resistance of the class A1+ pad, medium driver RDSONM − − 155 Ohm IOH> -2 mA; P_MOS − − 110 Ohm IOL< 2 mA; N_MOS RDSON1+ − − 110 Ohm IOH> -2 mA; P_MOS − − 80 Ohm IOL< 2 mA; N_MOS − − 150 ns CL= 20 pF; pin out driver= weak − − 28 ns CL= 50 pF; edge= slow; pin out driver= strong − − 16 ns CL= 50 pF; edge= soft ; pin out driver= strong − − 50 ns CL= 50 pF; pin out driver= medium − − 140 ns CL= 150 pF; pin out driver= medium − − 550 ns CL= 150 pF; pin out driver= weak − − 18000 ns CL= 20000 pF; pin out driver= medium − − 65000 ns CL= 20000 pF; pin out driver= weak CC CC On-Resistance of the class A1+ pad, strong driver CC Fall time, pad type A1+ tFA1+ C Data Sheet C 5-13 V1.2, 2014-06 TC1728 Electrical Parameters Table 15 Standard_Pads Class_A1+ Parameter Rise time, pad type A1+ Symbo l Min. tRA1+ Values Unit Note / Test Condition Typ Max. . − − 150 ns CL= 20 pF; pin out driver= weak − − 28 ns CL= 50 pF; edge= slow ; pin out driver= strong − − 16 ns CL= 50 pF; edge= soft ; pin out driver= strong − − 50 ns CL= 50 pF; pin out driver= medium − − 140 ns CL= 150 pF; pin out driver= medium − − 550 ns CL= 150 pF; pin out driver= weak − − 18000 ns CL= 20000 pF; pin out driver= medium − − 65000 ns CL= 20000 pF; pin out driver= weak C C Input high voltage, Class A1+ pads VIHA1+ 0.6 x VDDP − Input low voltage, Class A1+ pads VILA1+ -0.3 Ratio Vil/Vih, A1+ pads VILA1+ / VIHA1+ SR − SR min(VD V DP + 0.3, 3.6) 0.36 x V VDDP 0.6 − − CC Data Sheet 5-14 V1.2, 2014-06 TC1728 Electrical Parameters Table 15 Standard_Pads Class_A1+ Parameter Symbo l Min. Output voltage high, VOHA1+ class A1+ pads CC Output voltage low, class A1+ pads VOLA1+ Values Unit Note / Test Condition Typ Max. . VDDP - 0.4 − − V IOH≥ -1.4 mA; pin out driver= medium VDDP - 0.4 − − V IOH≥ -1.4 mA; pin out driver= strong 2.4 − − V IOH≥ -2 mA; pin out driver= medium 2.4 − − V IOH≥ -2 mA; pin out driver= strong VDDP - 0.4 − − V IOH≥ -400 μA; pin out driver= weak 2.4 − − V IOH≥ -500 μA; pin out driver= weak − − 0.4 V IOL≤ 2 mA; pin out − − 0.4 V IOL≤ 2 mA; pin out CC driver= medium driver= strong − − 0.4 IOL≤ 500 μA; pin out V driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 16 Standard_Pads Class_A2 Parameter Symbol Input Hysteresis for A2 pads 1) HYSA2 Values Min. Data Sheet CC Unit Typ. Max. 0.1 x VDDP − 5-15 − Note / Test Condition V V1.2, 2014-06 TC1728 Electrical Parameters Table 16 Standard_Pads Class_A2 Parameter Symbol Unit Note / Test Condition 6000 nA − 3000 nA Vi< VDDP / 2 - 1 V; Vi> VDDP / 2 + 1 V; Vi≥ 0 V; Vi≤ VDDP V Vi> VDDP / 2 - 1 V; Vi< VDDP / 2 + 1 V 0.6 − − − 450 600 Ohm IOH> -0.5 mA; P_MOS − 210 340 Ohm IOL< 0.5 mA; N_MOS − − 155 Ohm IOH> -2 mA; P_MOS − − 110 Ohm IOL< 2 mA; N_MOS On-Resistance RDSON2 CC − of the class A2 pad, strong driver − − 42 Ohm IOH> -2 mA; P_MOS − 22 Ohm IOL< 2 mA; N_MOS Input Leakage IOZA2 CC current Class A2 Ratio Vil/Vih, A2 pads VILA2 / VIHA2 CC RDSONW On-Resistance of the class A2 CC pad, weak driver On-Resistance of the class A2 pad, medium driver Data Sheet RDSONM Values Min. Typ. Max. -6000 − -3000 CC 5-16 V1.2, 2014-06 TC1728 Electrical Parameters Table 16 Parameter Fall time, pad type A2 Standard_Pads Class_A2 Symbol tFA2 CC Values Min. Typ. Max. − − 150 Unit Note / Test Condition ns CL= 20 pF; pin out driver= weak − − 7 ns CL= 50 pF; edge= medium ; pin out driver= strong − − 10 ns CL= 50 pF; edge= mediumminus ; pin out driver= strong − − 3.7 ns CL= 50 pF; edge= sharp ; pin out driver= strong − − 5 ns CL= 50 pF; edge= sharpminus ; pin out driver= strong − − 16 ns CL= 50 pF; edge= soft ; pin out driver= strong − − 50 ns CL= 50 pF; pin out − − 7.5 ns CL= 100 pF; driver= medium edge= sharp ; pin out driver= strong − − 140 ns CL= 150 pF; pin out driver= medium Data Sheet 5-17 V1.2, 2014-06 TC1728 Electrical Parameters Table 16 Standard_Pads Class_A2 Parameter Symbol Values Unit Note / Test Condition 550 ns CL= 150 pF; pin 18000 ns CL= 20000 pF; Min. Typ. Max. − − − − out driver= weak pin out driver= medium − − 65000 ns CL= 20000 pF; pin out driver= weak Rise time, pad type A2 tRA2 CC − − 150 ns CL= 20 pF; pin out driver= weak − − 7.0 ns CL= 50 pF; edge= medium ; pin out driver= strong − − 10 ns CL= 50 pF; edge= mediumminus ; pin out driver= strong − − 3.7 ns CL= 50 pF; edge= sharp ; pin out driver= strong − − 5 ns CL= 50 pF; edge= sharpminus ; pin out driver= strong − − 16 ns CL= 50 pF; edge= soft ; pin out driver= strong − − 50 ns CL= 50 pF; pin out − − 7.5 ns CL= 100 pF; driver= medium edge= sharp ; pin out driver= strong − − 140 ns CL= 150 pF; pin out driver= medium Data Sheet 5-18 V1.2, 2014-06 TC1728 Electrical Parameters Table 16 Standard_Pads Class_A2 Parameter Symbol Values Unit Note / Test Condition 550 ns CL= 150 pF; pin 18000 ns CL= 20000 pF; Min. Typ. Max. − − − − out driver= weak pin out driver= medium − − 65000 ns CL= 20000 pF; pin out driver= weak VIHA2 SR Input high voltage, class A2 pads 0.6 x VDDP − Input low voltage, VILA2 SR Class A2 pads -0.3 Output voltage high, class A2 pads VDDP - 0.4 − VDDP - 0.4 − 2.4 − VOHA2 CC − min(VDDP V + 0.3, 3.6) 0.36 x V VDDP − V IOH≥ -1.4 mA; pin out driver= medium − V IOH≥ -1.4 mA; pin out driver= strong − V IOH≥ -2 mA; pin out driver= medium 2.4 − − V IOH≥ -2 mA; pin out VDDP - 0.4 − − V IOH≥ -400 μA; pin 2.4 − − V IOH≥ -500 μA; pin out driver= weak − − 0.4 V IOL≤ 2 mA; pin out driver= strong Output voltage low, class A2 pads VOLA2 CC out driver= weak driver= medium − − 0.4 V IOL≤ 2 mA; pin out driver= strong − − 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Data Sheet 5-19 V1.2, 2014-06 TC1728 Electrical Parameters Table 17 Standard_Pads Class_F Parameter Input Hysteresis F Symbol 1) HYSF CC Values Unit Min. Typ. Max. 0.05 x − − V − 6000 nA Note / Test Condition VDDP Input Leakage Current Class F IOZF CC -6000 Vi≤ VDDP V; Vi≥ 0 V; Vi< VDDP / 2 1 V; Vi> VDDP / 2 +1V -3000 Ratio Vil/ Vih, F pads On-Resistance of the class F pad, medium driver − 3000 nA Vi< VDDP / 2 + 1 V; Vi> VDDP / 2 -1V − − − 175 Ohm IOH> -2 mA; P_MOS − − 160 Ohm IOL< 2 mA; N_MOS VILF / VIHF CC 0.6 RDSONM CC − Fall time, pad type F, CMOS mode tFF CC − − 60 ns CL= 50 pF Rise time, pad type F, CMOS mode tRF CC − − 60 ns CL= 50 pF Input high voltage, pad class F, CMOS mode VIHF SR 0.6 x − VDDP Input low voltage, Class VILF SR F pads, CMOS mode Output high voltage, class F pads, CMOS mode VOHF CC Output low voltage, class F pads, CMOS mode VOLF CC -0.3 min(V V + 0.3, 3.6) DDP − 0.36 x V VDDP VDDP - − − V IOH≥ -1.4 mA 2.4 − − V − − 0.4 V IOH≥ -2 mA IOL≤ 2 mA 0.4 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Data Sheet 5-20 V1.2, 2014-06 TC1728 Electrical Parameters Table 18 Standard_Pads Class_I Parameter Symbol Values Unit Note / Test Condit ion Min. Typ. Max. 0.1 x − − V CC -1000 − 1000 nA -40°C ≤ TJ ≤ 150°C -1500 − 1500 nA 150°C < TJ ≤ 160°C − − − min(VD V DP + 0.3, 3.6) − 0.36 x Input Hysteresis Class I1) HYSI CC VDDP Input Leakage Current Ratio between low and high input threshold IOZI VILI / VIHI CC 0.6 Input high voltage, class I VIHI pins SR 0.6 x Input low voltage, Class I VILI pads SR -0.3 VDDP V VDDP 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. LVDS parameter are valid for VDD = 1.235 V to 1.365 V; VDDP = 3.135 V to 3.465 V. Table 19 LVDS_Pads Parameters Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Output impedance, pad class F, LVDS mode RO CC 40 − 140 Ohm Fall time, pad type LVDS tFL CC − − 2 ns termination 100 Ω ± 1 %; Rise time, pad type LVDS tRL CC − − 2 ns termination 100 Ω ± 1 %; tSET_LVD − − 13 μs termination 100 Ω ± 1 % − 400 mV termination 100 Ω ± 1 % Pad set-up time S CC Output Differential Voltage VOD CC 150 Data Sheet 5-21 V1.2, 2014-06 TC1728 Electrical Parameters Table 19 LVDS_Pads Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Output voltage high, pad class F, LVDS mode VOH CC − − 1525 mV termination 100 Ω ± 1 % Output voltage low, pad class F, LVDS mode VOL CC − − mV termination 100 Ω ± 1 % Output Offset Voltage VOS CC 1075 − 1325 mV termination 100 Ω ± 1 % 875 Class S pad parameters are only valid for VDDM = 4.75 V to 5.25 V. Table 20 Standard_Pads Class_S Parameter Symbol Values Min. Input Hysteresis for class S pads1) HYSS CC 0.3 Input leakage current IOZS CC VIHS CC VILS CC VILSD CC Input voltage high Input voltage low VILS Delta 2) −300 Unit Typ. Max. − − V − 300 nA − − 3.6 V 1.9 − − V -50 − 50 mV Note / Test Condition Maximum input low state treshold variation over 1ms (VDDP = consta nt) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. 2) VILSD is implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to external noise. Data Sheet 5-22 V1.2, 2014-06 TC1728 Electrical Parameters 5.2.2 Analog to Digital Converters (ADCx) ADC parameter in Table 21 are valid for VDD = 1.235 V to 1.365 V; VDDM = 4.75 V to 5.25 V; TJ = 150°C. Table 21 5V ADC Parameters Parameter Symbol Values Unit Min. Typ. Max. Switched capacitance at the analog voltage inputs1) CAINSW − 9 20 pF Total capacitance of an analog input CAINTOT − 20 30 pF Switched capacitance at the positive reference voltage input2)3) CAREFSW − 15 30 pF Total capacitance of the CAREFTOT − voltage reference inputs2) CC 20 40 pF Differential Non-Linearity EADNL Error4)5)6)7) CC − 3 LSB Note / Test Condition CC CC CC -3 ADC resolution= 12bit 8) 9) Gain Error4)5)6)7) EAGAIN -3.5 − 3.5 LSB ADC resolution= 12bit 8) 9) EAINL -3 − 3 LSB ADC resolution= 12bit8) 9) EAOFF -4 − 4 LSB ADC resolution= 12bit 8) 9) fADC 4 − 110 MHz fADC= fFPI − 20 MHz 10) pC charge needs to be provided via CC Integral NonLinearity4)5)6)7) Offset Error4)5)6)7) CC CC Converter clock SR Internal ADC clock fADCI CC 1 Charge consumption per QCONV 70 conversion 8511) 100 CC VAREF0 Data Sheet 5-23 V1.2, 2014-06 TC1728 Electrical Parameters Table 21 5V ADC Parameters Parameter Input leakage at analog inputs12) Symbol IOZ1 Values Min. Typ. Max. -100 − 500 Unit Note / Test Condition nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; CC overlayed= No -100 − 600 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= Yes -500 − 100 nA -600 − 100 nA Vi≥ 0 V; Vi≤ 0.03 x VDDM V; overlayed= No Vi≤ 0.03 x VDDM V; Vi≥ 0 V; overlayed= Yes -100 − 200 nA -100 − 300 nA Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= No Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= Yes Input leakage current at Varef0 IOZ2 CC -2 − 2 μA Input leakage current at Vagnd0 IOZ3 CC -2 − 2 μA 900 1500 Ohm ON resistance of the RAIN − transmission gates in the CC analog voltage path Data Sheet 5-24 VAREF0≥ 0V; VAREF0≤ VDDM V VAGND0≥ 0V; VAGND0≤ VDDM V V1.2, 2014-06 TC1728 Electrical Parameters Table 21 5V ADC Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition ON resistance for the ADC test (pull down for AIN7) RAIN7T 180 550 900 Ohm Test feature available only for odd AINx pins Resistance of the reference voltage input path RAREF − 500 1000 Ohm 500 Ohm increased if AIN[1:0] used as reference input Broken wire detection delay against VAGND tBWG CC − − 50 13) Broken wire detection delay against VAREF tBWR CC − − 50 14) Sample time tS CC tCAL CC 2 − 257 TADCI − − 4352 cycles − 416) LSB Calibration time after bit ADC_GLOBCFG.SUCAL is set Total Unadjusted Error5)6)15) CC CC TUE CC -4 Wakeup time from analog tAWAF powerdown, fast mode CC − − 5 μs Wakeup time from analog tAWAS powerdown, slow mode CC − − 10 μs VSSM - − VAREF0 V − VDDM/2 VAREF0 V VDDM + V Analog reference ground2) Analog input voltage Analog reference voltage2) VAGND0 SR VAIN SR VAREF0 SR Analog reference voltage VAREF0 range5)6)2) VAGND0 SR Data Sheet 0.05 VAGND0 VAGND0 - − + VDDM/2 VDDM/2 5-25 ADC resolution= 12bit 0.0517) 18) − VDDM + V 0.05 V1.2, 2014-06 TC1728 Electrical Parameters 1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2. 2) Applies to AINx, when used as auxiliary reference input. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage. 4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error. 5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k VDDM, then the ADC converter errors increase. 8) For 10-bit conversions the error value must be multiplied with a factor 0.25. 9) For 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) If the alternate reference is used or fADCI is more than 16 MHz, the accuracy of the ADC may decrease. 11) For a conversion time of 1 µs a rms value of 85µA result for IAREF0. 12) The leakage current definition is a continous function,as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given countinuous linear approximation they do not define step function. 13) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 250μs. Results below 10% (199H). 14) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10μs. This function is influenced by leakage current, in particular at high temperature.Results above 60% (999H). 15) Measured without noise. 16) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB 17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 18) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decrease by 4LSB12. ADC parameter in Table 22 are valid for VDD = 1.235 V to 1.365 V; VDDM = 3.135 V to 3.465 V; TJ = 150°C. Table 22 3.3V ADC Parameters Parameter Symbo l Min. Switched capacitance at the analog voltage inputs1) CAINSW Total capacitance of an analog input CAINTOT − Data Sheet Values Unit Typ. Max. − 9 20 pF 20 30 pF Note / Test Condition CC CC 5-26 V1.2, 2014-06 TC1728 Electrical Parameters Table 22 3.3V ADC Parameters Parameter Symbo l Min. Values Unit Typ. Max. − 15 30 pF Total capacitance of the CAREFTO − voltage reference inputs2) T CC 20 40 pF Differential Non-Linearity EADNL Error4)5)6)7) CC − 4 LSB Switched capacitance at the positive reference voltage input2)3) CAREFS W Note / Test Condition CC -4 ADC resolution= 12bit 8) 9) 4)5)6)7) EAGAIN -3.5 − 3.5 LSB ADC resolution= 12bit 8) 9) EAINL -4 − 4 LSB ADC resolution= 12bit8) 9) EAOFF -4 − 4 LSB ADC resolution= 12bit 8) 9) fADC 4 − 110 MHz fADC= fFPI Internal ADC clock fADCI 1 − 20 MHz 10) Charge consumption per conversion11) QCONV − − 70 pC charge needs to be provided via Gain Error CC Integral NonLinearity4)5)6)7) Offset Error4)5)6)7) CC CC Converter clock SR CC CC VAREF0 Data Sheet 5-27 V1.2, 2014-06 TC1728 Electrical Parameters Table 22 3.3V ADC Parameters Parameter Input leakage at analog inputs12) Symbo l Min. IOZ1 Values Unit Note / Test Condition nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; Typ. Max. − -100 500 C C overlayed= No − -100 600 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= Yes -500 − 100 nA -600 − 100 nA Vi≥ 0 V; Vi≤ 0.03 x VDDM V; overlayed= No Vi≤ 0.03 x VDDM V; Vi≥ 0 V; overlayed= Yes -100 − 200 nA -100 − 300 nA Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= No Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= Yes Input leakage current at Varef IOZ2 CC -2 − 2 μA VAREF0≤ VDDM V Input leakage current at Vagnd IOZ3 CC -2 − 2 μA VAGND0≤ VDDM V ON resistance of the RAIN transmission gates in the C analog voltage path C − 3500 9000 Ohm ON resistance for the ADC test (pull down for AIN7) 180 800 Ohm Data Sheet RAIN7T CC 5-28 1800 Test feature available only for odd AINx pins V1.2, 2014-06 TC1728 Electrical Parameters Table 22 3.3V ADC Parameters Parameter Symbo l Min. Values Unit Note / Test Condition 500 Ohm increased if AIN[1:0] used as reference input Typ. Max. Resistance of the reference voltage input path RAREF − 1700 3000 Ohm Broken wire detection delay against VAGND tBWG − − 50 13) Broken wire detection delay against VAREF tBWR CC − − 50 14) Sample time tS CC 2 tCAL CC − − 257 TADCI − 4352 cycles -4.5 − 4.516) LSB Calibration time after bit ADC_GLOBCFG.SUCAL is set CC CC Total Unadjusted Error5)6)15) TUE Analog reference ground2) VAGND0 VSSM - − Analog input voltage VAIN SR VAGND0 VAREF0 VAGND0 − Analog reference voltage2) CC SR SR 0.05 VAREF0 V - − + VDDM/2 Analog reference voltage VAREF0 - VDDM/2 range5)6)2) VAGND0 ADC resolution= 12bit VDDM/2 VAREF0 V VDDM + V 0.0517) 18) − VDDM + V 0.05 SR 1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2. 2) Applies to AINx, when used as auxiliary reference input. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage. 4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error. 5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k VDDM, then the ADC converter errors increase. 8) For 10-bit conversions the error value must be multiplied with a factor 0.25. 9) For 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) If the alternate reference is used, or fADCI is more than 16 MHz, or STC is lower than 8, the accuracy of the ADC may decrease. 11) QCONV is calculated as QCONV = CAREF*VAREF. 12) The leakage current definition is a continous function,as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given countinuous linear approximation they do not define step function. 13) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 250μs. Results below 10% (199H). 14) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10μs. This function is influenced by leakage current, in particular at high temperature.Results above 60% (999H). 15) Measured without noise. 16) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB 17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 18) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decrease by 4LSB12. Table 23 Conversion Time (Operating Conditions apply) Parameter Symbol Values tC Conversion time with post-calibration Conversion time without post-calibration Data Sheet Unit Note CC 2 × TADC + (4 + STC + n) × TADCI μs 2 × TADC + (2 + STC + n) × TADCI 5-30 n = 8, 10, 12 for n - bit conversion TADC = 1 / fFPI TADCI = 1 / fADCI V1.2, 2014-06 TC1728 Electrical Parameters REXT VAIN = Analog Input Circuitry RAIN, On ANx CEXT CAINTOT - CAINSW VAGNDx CAINSW RAIN7T Reference Voltage Input Circuitry RAREF, On VAREFx VAREF CAREFTOT - CAREFSW CAREFSW VAGNDx Analog_InpRefDiag Figure 3 Data Sheet ADCx Input Circuits 5-31 V1.2, 2014-06 TC1728 Electrical Parameters Ioz1 Single ADC Input 500nA 200nA 100nA -100nA VIN[VDDM%] 3% 97% 100% -500nA Ioz1 Overlayed ADC/FADC Input 600nA 300nA 100nA -100nA VIN[VDDM%] 3% 97% 100% -600nA Figure 4 Data Sheet ADCx Analog Inputs Leakage 5-32 V1.2, 2014-06 TC1728 Electrical Parameters 5.2.3 Fast Analog to Digital Converter (FADC) FADC parameter are valid for VDDM = 4.75 V to 5.25 V;TJ = 150°C. Table 24 Parameter FADC Parameters with VDDM = 5V Symbol Values Min. DNL error Typ. Max. EFDNL CC -1 − 1 -1 − Unit Note / Test Condition LSB VIN mode= differential Gain = 1, 2 1 LSB VIN mode= single ended Gain = 1, 2 − -2 2 LSB VIN mode= differential Gain = 4, 8 TJ = 150°C 1) -2.5 − 2.5 LSB VIN mode= differential Gain = 4, 8 TJ = 160°C 1) − -2 2 LSB VIN mode= single ended Gain = 4, 8 TJ = 150°C 1) -2.5 − 2.5 LSB VIN mode= single ended Gain = 4, 8 TJ = 160°C 1) Data Sheet 5-33 V1.2, 2014-06 TC1728 Electrical Parameters Table 24 FADC Parameters with VDDM = 5V Parameter GRADient error Symbol EFGRAD Values Min. Typ. Max. -5 − 5 Unit Note / Test Condition % VIN mode= CC differential ; Gain< 4 − -5 5 % VIN mode= single ended ; Gain< 4 -5.5 − 5 % VIN mode= differential ; Gain= 4 -5.5 − 5 % VIN mode= single ended ; Gain= 4 − -6 6 % VIN mode= differential ; Gain= 8 − -6 6 % VIN mode= single ended ; Gain= 8 INL error EFINL CC -4 − -4 − 4 LSB VIN mode= differential 4 LSB VIN mode= single ended Data Sheet 5-34 V1.2, 2014-06 TC1728 Electrical Parameters Table 24 FADC Parameters with VDDM = 5V Parameter Symbol Values Min. Offset error Typ. Max. EFOFF CC -90 − 90 -90 − Unit Note / Test Condition mV VIN mode= differential ; Calibration= No 90 mV VIN mode= single ended ; Calibration= No -20 − 20 mV VIN mode= differential ; Calibration= Yes 2)3) -20 − 20 mV VIN mode= single ended ; Calibration= Yes 2)3) EFREFI -80 − 80 mV Channel amplifier cutoff frequency fCOFF CC 2 − − MHz Converter clock fFADC 4 − 110 MHz fFADC= fFPI tC CC − − 21 1/ Error of common mode voltage VFAREFI/2 CC SR Conversion time Input resistance of the analog voltage path (Rn, Rp) RFAIN CC 100 − 200 kOh m μs Settling time of a channel tSET CC amplifier after changing ENN or ENP − − 5 Analog input voltage range4) VSSM − VDDP V Wakeup time from analog tFWAF CC powerdown, fast mode − − 5 μs Wakeup time from analog tFWAS CC powerdown, slow mode − − 10 μs Data Sheet VAINF SR For 10-bit fFADC conversion 5-35 V1.2, 2014-06 TC1728 Electrical Parameters Table 24 FADC Parameters with VDDM = 5V Parameter Symbol Values Unit Note / Test Condition − V Internally generated −5)6) V Internally generated Min. Typ. Max. Analog reference ground VFAGNDI CC − 0 Analog reference voltage VFAREFI CC − 3.3 1) No missing codes. 2) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed minimium once per week. 3) The offser error voltage drifts over the whole temperature range maximum +-3LSB. 4) The accuracy values is valid between 5% and 90%of VAINF 5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots). The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. Data Sheet 5-36 V1.2, 2014-06 TC1728 Electrical Parameters FADC Analog Input Stage RN FAINxN - VFAREF/2 VSSM + + RP FAINxP VFAREF - FADC Reference Voltage Input Circuitry (from IVR) IFAREF VFAREF VFAGND FADC _InpRefDiag Figure 5 Data Sheet FADC Input Circuits 5-37 V1.2, 2014-06 TC1728 Electrical Parameters 5.2.4 Table 25 Oscillator Pins OSC_XTAL Parameters Parameter Symbol Values Min. Unit Note / Test Condition VIN> 0 V; VIN