TC377TX96F300SABKXUMA1

32-Bit Microcontroller TC37xEXT 32-Bit Single-Chip Microcontroller AB-Step 32-Bit Single-Chip Microcontroller Data Sheet V 1.0, 2019-10 Microcontroller OPEN MARKET VERSION Edition 2019-10 Published by Infineon Technologies AG 81726 Munich, Germany © 2019 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com) Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. OPEN MARKET VERSION TC37xEXT AB-Step Revision History Page or Item Subjects (major changes since previous revision) V 0.6, 2018-10 The history is documented in the last chapter V 0.6.1, 2019-01 The history is documented in the last chapter V 0.7, 2019-05 The history is documented in the last chapter V 1.0, 2019-10 The history is documented in the last chapter Data Sheet 3 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Data Sheet 4 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 2.1 2.2 2.3 2.4 2.5 2.6 TC37xEXT Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LFBGA-292 Package Pinning of TC37xEXT TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LFBGA-292 Package Pinning of TC37xEXT TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LQFP-176 Package Pinning of TC37xEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 LQFP-144 Package Pinning of TC37xEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Pad Position Configuration of TC37xEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.12.1 3.13 3.13.1 3.13.1.1 3.13.1.2 3.13.1.3 3.13.1.4 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.24.1 3.24.2 3.24.3 3.24.4 3.24.5 3.25 3.26 3.27 3.28 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance LVDS Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculating the 1.25 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Infrastructure and Supply Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Ramp-up and Ramp-down Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Supply mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Supply mode (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Supply mode (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Supply mode (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Phase Locked Loop (SYS_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Phase Locked Loop (PER_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH RGMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 5 OPEN MARKET VERSION 388 388 389 390 393 397 417 420 424 427 429 430 431 437 438 438 438 441 443 445 447 450 460 461 462 463 465 467 469 473 475 475 476 477 478 479 480 482 483 487 V 1.0, 2019-10 TC37xEXT AB-Step 3.29 3.30 3.31 3.32 3.32.1 Camera Interface Timing (CIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 489 494 495 496 4 4.1 4.2 4.3 4.4 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes from Version 0.4 to Version 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes from Version 0.6 to Version 0.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes from Version 0.61 to Version 0.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes from Version 0.7 to Version 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 498 507 510 512 Data Sheet 6 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Summary of Features 1 Summary of Features The TC37xEXT product family has the following features: • High Performance Microcontroller with three CPU cores • Three 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate unit able to sustain 2 MAC operations per cycle – Fully pipelined Floating point unit (FPU) – up to 300 MHz operation at full temperature range – up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR) – up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR) – 32 Kbyte Instruction Cache (ICACHE) – 16 Kbyte Data Cache (DCACHE) • Lockstepped shadow cores for up to three TC1.6.2P • Multiple on-chip memories – All embedded NVM and SRAM are ECC protected – up to 6 Mbyte Program Flash Memory (PFLASH) – up to 384 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – BootROM (BROM) • 128-Channel DMA Controller with safe data transfer • Sophisticated interrupt system (ECC protected) • High performance on-chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – SRI to SPB bus bridges (SFI Bridge) • Optional Hardware Security Module (HSM) on some variants • Safety Management Unit (SMU) handling safety monitor alarms • Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) • Hardware I/O Monitor (IOM) for checking of digital I/O • Versatile On-chip Peripheral Units – 12 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – 5 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s – 1 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s – 2 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices – 3 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering – 15 Single Edge Nibble Transmission (SENT) channels for connection to sensors – 1 FlexRayTM module with 2 channels (E-Ray) supporting V2.1 – One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) Data Sheet 7 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Summary of Features • • – One General Purpose 12 Timer Unit (GPT120) – 2 channel Peripheral Sensor Interface conforming to V1.3 (PSI5) – 1 Peripheral Sensor Interface with Serial PHY (PSI5-S) – 1 Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1 – 2 IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH) Versatile Successive Approximation ADC (VADC) – Cluster of 12 independent ADC kernels – Input voltage range from 0 V to 5.5V (ADC supply) Delta-Sigma ADC (DSADC) – 6 channels • Digital programmable I/O ports • On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses) • multi-core debugging, real time tracing, and calibration • four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface • Power Management System and on-chip regulators • Clock Generation Unit with System PLL and Peripheral PLL • Embedded Voltage Regulator Data Sheet 8 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • The package and the type of delivery Table 1-1 Platform Feature Overview Feature CPUs TC37xEXT Type TC1.6.2 Cores / Checker Cores 3/3 Max. Freq. 300 MHz Program 32 KB Data 16 KB PSPR 64 KB DSPR 240 KB for CPU0,1/ 96 KB else DLMU 64 KB SRAM global DAM 32 KB Extension Memory TCM 2 MB XCM 1 MB XTM 16 KB Size 6 MB Banks 2 x 3 MB Data Flash Size (single-ended) 256 KB + 128 KB DMA Channels 128 CONVCTRL Modules 1 EVADC Primary Groups/Channels 4 / 32 Secondary Groups/Channels 4 / 64 Fast Compare Channels 4 Channels 6 Cache per CPU SRAM per CPU Program Flash EDSADC Data Sheet 9 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Summary of Features Table 1-1 Platform Feature Overview (cont’d) Feature GTM TC37xEXT Clusters 5 @ 200 MHz, 1 @ 100 MHz TIM (8 ch) 6 TOM (16 ch) 3 ATOM (8 ch) 6 MCS (8 ch) 5 CMU / ICM 1/1 PSM 1 TBU channels 1) 4 (TBU0-3) SPE 2 CMP / MON 1/1 BRC / DPLL 1/1 CDTM modules 5 DTM modules 16 (6 on TOM, 10 on ATOM) GPT12 1 CCU6 1 STM Modules 3 FlexRay Modules 1 Channels 2 Modules 3 Nodes 3x4 of which support TT-CAN 1 Modules 5 HSCI Channels 0 ASCLIN Modules 12 I2C Interfaces 1 SENT Channels 15 PSI5 Modules 2 PSI5-S Modules 1 HSSL Channels 1 MSC Channels 2 SDMMC eMMC/SD Interface 1 CIF Camera Interface 1 Ethernet (10/100Mbit/1Gbit) Modules 2 FCE Modules Safety Support SMU yes IOM yes Timer CAN QSPI Security Data Sheet 1 HSM+ 1 10 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Summary of Features Table 1-1 Platform Feature Overview (cont’d) Feature Debug TC37xEXT OCDS yes MCDS yes miniMCDS - miniMCDS TRAM - AGBT yes Standby RAM 2 SCR yes Packages Type Pad Position Configuration / LFBGA-292 / LQFP-176 / LFQP144 I/O Type 5 V CMOS / 3.3 V CMOS / LVDS Tambient Range Low Power Features −40 … +150°C 1) TBU3 has special purpose as angle clock. Data Sheet 11 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions 2 TC37xEXT Pin Definition and Functions The following figures show the TC37xEXT package variants: • LFBGA-292 for feature package TE (Figure 2-1) • LFBGA-292 for feature package TX (Figure 2-2) • LQFP-176 for feature package (Figure 2-3) • LQFP-144 for feature package (Figure 2-4) • Pad Position Configuration of TC37xEXT (Chapter 2.5) Data Sheet 12 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of 2.1 LFBGA-292 Package Pinning of TC37xEXT TE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A NC1 VEXT P10.7 P10.6 P10.2 P10.3 P10.0 P11.11 P11.9 P11.2 P13.3 P13.1 P14.8 P14.5 P14.1 P15.6 P15.4 P15.1 VDDP3 VSS A B P02.0 VSS VEXT P10.8 P10.5 P10.4 P10.1 P11.12 P11.10 P11.3 P13.2 P13.0 P14.6 P14.3 P14.4 P14.0 P15.3 VDDP3 VSS P15.0 B C P02.2 P02.1 P15.2 P20.14 C D P02.4 P02.3 VSS VFLEX P11.15 P11.14 P11.5 P11.6 P11.4 P14.10 P14.9 P14.7 P15.8 P15.7 VDD VSS P20.12 P20.13 D E P02.6 P02.5 P02.9 VSS P11.13 P11.8 P11.7 P11.1 P11.0 P12.1 P12.0 P14.2 P15.5 VDD VSS P20.9 P20.10 P20.11 E F P02.8 P02.7 P02.11 P02.10 ESR0 P20.6 P20.7 P20.8 F G P00.0 P00.1 P01.4 P01.3 ESR1 PORST P20.1 P20.3 G H P00.2 P00.3 P01.6 P01.5 VDDSB (VDD) VDD P21.7 / TDO P21.6 / TDI P20.2 P20.0 H J P00.4 P00.5 P00.6 P01.7 VSS VSS VSS VSS TCK P21.1 P21.3 P21.5 J K P00.7 P00.9 P00.8 P00.10 AGBTC LKP (VSS) VSS L P00.11 P00.12 AN43 AN42 AGBTC LKN (VSS) VSS M AN46 AN47 AN41 AN40 VSS VSS N AN44 AN45 AN36 / P40.6 AN38 / P40.8 VDD P AN39 / P40.9 AN37 / P40.7 AN32 / P40.4 AN34 R AN33 / P40.5 AN35 AN31 AN23 T VAREF 2 VAGND 2 AN30 AN22 AN15 AN12 AN6 AN4 AN0 VEVRS B P34.2 P34.4 P33.14 U AN29 / P40.14 AN28 / P40.13 NC1 AN17 / P40.10 AN14 AN9 AN7 AN3 AN1 P34.1 P34.3 P34.5 P33.15 V AN27 / P40.3 AN26 / P40.2 W AN25 / P40.1 AN24 / P40.0 AN19 / P40.12 AN18 / P40.11 AN16 AN13 AN11 AN8 AN2 P33.0 P33.2 P33.4 P33.6 P33.8 P33.10 P33.12 P32.1 / VGATE 1P Y NC1 AN21 AN20 VSSM VDDM VAREF 1 VAGND 1 AN10 AN5 P33.1 P33.3 P33.5 P33.7 P33.9 P33.11 P33.13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDDSB (VDD) VDD VSS DAPE2 DAPE1 VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DAPE0 TMS P21.0 P21.2 P21.4 K VSS VSS VSS VSS VSS AGBTE RR (VSS) P22.10 P22.11 TRST VSS L VSS VSS VSS VSS P22.8 P22.9 XTAL2 XTAL1 M VSS VSS VSS VSS VDD P22.6 P22.7 VDD VEXT N VSS AGBTT XN (VSS) AGBTT XP (VSS) VSS P22.4 P22.5 P22.1 P22.0 P P23.7 P23.6 P22.3 P22.2 R P32.5 VSS P23.5 P23.3 P23.4 T P32.6 P32.7 VSS P23.1 P23.2 U VEXT P23.0 V P32.4 VSS VEXT W P32.0 / VGATE 1N P32.2 P32.3 VSS Y 17 18 19 20 VDD TC37xed - (top view) Figure 2-1 TC37xEXT TE package variant LFBGA-292 Data Sheet 13 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions Ball Symbol Ctrl. Buffer Type Function G1 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_10 GTM_TIM3_IN0_1 GTM_TIM2_IN0_1 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port CIF_D9 sensor pixel data input GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O4 Reserved CAN10_TXD O5 CAN transmit output node 0 — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO Data Sheet O MDIO Output 14 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function G2 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_11 GTM_TIM3_IN1_1 GTM_TIM2_IN1_1 Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input EDSADC_DSCIN5A Modulator clock input, channel 5 CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CIF_D10 sensor pixel data input CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI EDSADC_EDS5NA Analog input channel 11, group 9 Negative analog input channel 5, pin A P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 ASCLIN3_ATX Reference input 0 O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 15 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H1 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN6_11 GTM_TIM3_IN1_2 GTM_TIM2_IN1_2 Mux input channel 6 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 EDSADC_DSDIN5A Digital datastream input, channel 5 SENT_SENT1B Receive input channel 1 CIF_D11 sensor pixel data input EVADC_G9CH10 AI EDSADC_EDS5PA Analog input channel 10, group 9 Positive analog input channel 5, pin A P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output CAN21_TXD O3 CAN transmit output node 1 PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 16 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H2 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN7_10 GTM_TIM3_IN2_1 GTM_TIM2_IN2_1 Mux input channel 7 of TIM module 5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 EDSADC_ITR5F Trigger/Gate input, channel 5 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 CAN21_RXDA CAN receive input node 1 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CIF_D12 sensor pixel data input CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI EDSADC_EDS5NB Analog input channel 9, group 9 Negative analog input channel 5, pin B P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output — O5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 17 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J1 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN3_1 GTM_TIM2_IN3_1 SCU_E_REQ2_2 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input CIF_D13 sensor pixel data input EVADC_G9CH8 AI EDSADC_EDS5PB Analog input channel 8, group 9 Positive analog input channel 5, pin B P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 — O5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Data Sheet 18 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J2 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN4_1 GTM_TIM3_IN0_11 GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CIF_D14 sensor pixel data input CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 19 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J4 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN5_1 GTM_TIM3_IN1_14 GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 3 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 2 EDSADC_ITR4F Trigger/Gate input, channel 4 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 CIF_D15 sensor pixel data input ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output — O3 Reserved — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Data Sheet 20 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K1 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN6_1 GTM_TIM3_IN2_11 GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 3 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 EDSADC_DSCIN4A Modulator clock input, channel 4 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 CIF_PCLK Sensor Pixel Clock input GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI EDSADC_EDS4NA Analog input channel 5, group 9 Negative analog input channel 4, pin A P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output EVADC_FC2BFLOUT O3 Boundary flag output, FC channel 2 EDSADC_DSCOUT4 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 21 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K4 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN7_1 GTM_TIM3_IN3_11 GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 3 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 EDSADC_DSDIN4A Digital datastream input, channel 4 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CIF_VSYNC vertical synchronization signal input CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI EDSADC_EDS4PA Analog input channel 4, group 9 Positive analog input channel 4, pin A P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output — O4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 22 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K2 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN0_7 GTM_TIM1_IN0_1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CIF_HSYNC horizontal synchronization signal input CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI EDSADC_EDS4NB Analog input channel 3, group 9 Negative analog input channel 4, pin B P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 23 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K5 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN1_11 GTM_TIM1_IN1_1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 EDSADC_EDS4PB L1 Mux input channel 1 of TIM module 4 Positive analog input channel 4, pin B P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 P00.11 I GTM_TIM4_IN2_11 GTM_TIM1_IN2_1 GTM_TIM0_IN2_1 SLOW / PU1 / VEXT / ES1 General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 SENT_SENT10B Receive input channel 10 EVADC_G9CH1 AI EVADC_FC3CH0 Analog input channel 1, group 9 Analog input FC channel 3 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT0 O4 Modulator clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 24 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function L2 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN3_11 GTM_TIM1_IN3_1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input SENT_SENT11B Receive input channel 11 EVADC_G9CH0 AI EVADC_FC2CH0 Analog input channel 0, group 9 Analog input FC channel 2 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Data Sheet 25 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-2 Port 01 Functions Ball Symbol Ctrl. Buffer Type Function G5 P01.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_2 GTM_TIM2_IN0_14 GTM_TIM0_IN5_8 Mux input channel 0 of TIM module 2 Mux input channel 5 of TIM module 0 QSPI3_SLSIB G4 Mux input channel 5 of TIM module 4 Slave select input EVADC_G9CH14 AI Analog input channel 14, group 9 P01.3 O0 General-purpose output GTM_TOUT111 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI3_SLSO9 O4 Master slave select output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 — O6 Reserved — O7 Reserved P01.4 I GTM_TIM4_IN6_2 GTM_TIM2_IN1_14 GTM_TIM0_IN6_8 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 4 Mux input channel 1 of TIM module 2 Mux input channel 6 of TIM module 0 CAN01_RXDC CAN receive input node 1 EVADC_G9CH13 AI Analog input channel 13, group 9 P01.4 O0 General-purpose output GTM_TOUT112 O1 GTM muxed output — O2 Reserved ASCLIN9_ASLSO O3 Slave select signal output QSPI3_SLSO10 O4 Master slave select output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 26 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H5 P01.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_2 GTM_TIM2_IN3_7 GTM_TIM2_IN2_7 H4 Mux input channel 3 of TIM module 5 Mux input channel 3 of TIM module 2 Mux input channel 2 of TIM module 2 QSPI3_MRSTC Master SPI data input ASCLIN9_ARXA Receive input EVADC_G9CH12 AI Analog input channel 12, group 9 P01.5 O0 General-purpose output GTM_TOUT113 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI3_MRST O4 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 — O5 Reserved — O6 Reserved — O7 Reserved P01.6 I GTM_TIM5_IN6_2 GTM_TIM5_IN5_3 GTM_TIM2_IN5_7 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 5 of TIM module 5 Mux input channel 5 of TIM module 2 QSPI3_MTSRC Slave SPI data input P01.6 O0 General-purpose output GTM_TOUT114 O1 GTM muxed output — O2 Reserved ASCLIN9_ASCLK O3 Shift clock output QSPI3_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 27 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J5 P01.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_2 GTM_TIM2_IN7_7 QSPI3_SCLKC Mux input channel 7 of TIM module 5 Mux input channel 7 of TIM module 2 Slave SPI clock inputs ASCLIN9_ARXB Receive input P01.7 O0 General-purpose output GTM_TOUT115 O1 GTM muxed output — O2 Reserved ASCLIN9_ATX O3 Transmit output QSPI3_SCLK O4 Master SPI clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 28 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions Ball Symbol Ctrl. Buffer Type Function B1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 GTM_TIM0_IN0_2 CCU61_CC60INB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D0 sensor pixel data input GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 ASCLIN2_ATX Reference input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 29 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function C2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 GTM_TIM0_IN1_2 ERAY0_RXDA2 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D1 sensor pixel data input P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 QSPI4_SLSO7 O2 Master slave select output QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 30 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function C1 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 GTM_TIM0_IN2_2 CCU61_CC61INB Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 T12 capture input 61 CCU60_CC61INA T12 capture input 61 CIF_D2 sensor pixel data input SENT_SENT14B Receive input channel 14 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 ASCLIN1_ATX Reference input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 31 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D2 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 GTM_TIM0_IN3_2 EDSADC_DSCIN5B Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Modulator clock input, channel 5 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input MSC1_SDI1 Upstream assynchronous input signal PSI5_RX0B RXD inputs (receive data) channel 0 CIF_D3 sensor pixel data input SENT_SENT13B Receive input channel 13 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved — O6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 32 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D1 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 GTM_TIM0_IN4_1 CCU61_CC62INB Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 T12 capture input 62 EDSADC_DSDIN5B Digital datastream input, channel 5 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input CIF_D4 sensor pixel data input SENT_SENT12B Receive input channel 12 P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 33 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E2 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 GTM_TIM0_IN5_1 EDSADC_DSCIN4B Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Modulator clock input, channel 4 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input CIF_D5 sensor pixel data input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 EDSADC_DSCOUT4 O4 Modulator clock output I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 34 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E1 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_10 GTM_TIM1_IN6_1 GTM_TIM0_IN6_1 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 EDSADC_DSDIN4B Digital datastream input, channel 4 EDSADC_ITR5E Trigger/Gate input, channel 5 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input CIF_D6 sensor pixel data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 35 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F2 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_10 GTM_TIM1_IN7_1 GTM_TIM0_IN7_1 Mux input channel 1 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 EDSADC_ITR4E Trigger/Gate input, channel 4 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 CIF_D7 sensor pixel data input QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 — O2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 36 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F1 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_10 GTM_TIM3_IN0_2 GTM_TIM2_IN0_2 Mux input channel 2 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CIF_D8 sensor pixel data input CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output — O4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 37 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E4 P02.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN2_2 GTM_TIM3_IN3_10 GTM_TIM0_IN2_10 Mux input channel 3 of TIM module 3 Mux input channel 2 of TIM module 0 ASCLIN8_ARXA F5 Mux input channel 2 of TIM module 4 Receive input P02.9 O0 General-purpose output GTM_TOUT116 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 ASCLIN8_ATX O3 Transmit output — O4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 — O6 Reserved — O7 Reserved P02.10 I GTM_TIM4_IN3_2 GTM_TIM3_IN4_11 GTM_TIM0_IN3_10 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 3 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 3 of TIM module 0 ASCLIN2_ARXC Receive input CAN01_RXDE CAN receive input node 1 ASCLIN8_ARXB Receive input P02.10 O0 General-purpose output GTM_TOUT117 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 38 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F4 P02.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_3 GTM_TIM3_IN5_12 GTM_TIM0_IN7_7 Mux input channel 4 of TIM module 4 Mux input channel 5 of TIM module 3 Mux input channel 7 of TIM module 0 EVADC_G9CH15 AI Analog input channel 15, group 9 P02.11 O0 General-purpose output GTM_TOUT118 O1 GTM muxed output — O2 Reserved ASCLIN8_ASLSO O3 Slave select signal output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-4 Port 10 Functions Ball Symbol Ctrl. Buffer Type Function A7 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_12 GTM_TIM1_IN4_2 GTM_TIM0_IN4_2 Mux input channel 0 of TIM module 4 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 39 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B7 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_12 GTM_TIM1_IN1_3 GTM_TIM0_IN1_3 A5 Mux input channel 4 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 — O6 Reserved — O7 Reserved P10.2 I GTM_TIM4_IN5_12 GTM_TIM1_IN2_3 GTM_TIM0_IN2_3 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMT2_2 CDTM2_DTM0 P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 — O2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select EVADC_FC3BFLOUT O5 Boundary flag output, FC channel 3 — O6 Reserved — O7 Reserved Data Sheet 40 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A6 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_10 GTM_TIM1_IN3_3 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 B6 Mux input channel 6 of TIM module 4 Monitor input 2 — O2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select — O5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 — O7 P10.4 I GTM_TIM4_IN7_3 GTM_TIM1_IN6_2 GTM_TIM0_IN6_2 Reserved FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 4 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 — O2 Reserved QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select — O6 Reserved — O7 Reserved Data Sheet 41 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B5 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN3_13 GTM_TIM1_IN2_4 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input CAN20_RXDA CAN receive input node 0 MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 ASCLIN2_ATX A4 Mux input channel 3 of TIM module 4 Reference input 2 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output — O7 Reserved P10.6 I GTM_TIM4_IN2_13 GTM_TIM1_IN3_4 GTM_TIM0_IN3_4 SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 CAN20_TXD O5 CAN transmit output node 0 QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 — Data Sheet O7 Reserved 42 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A3 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 GTM_TIM0_IN0_3 GPT120_T3EUDB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 — O2 Reserved QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 — O4 Reserved CAN20_TXD O5 CAN transmit output node 0 CAN12_TXD O6 CAN transmit output node 2 — O7 Reserved Data Sheet 43 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B4 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_13 GTM_TIM1_IN5_2 GTM_TIM0_IN5_2 Mux input channel 0 of TIM module 4 Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 CAN20_RXDB CAN receive input node 0 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-5 Port 11 Functions Ball Symbol Ctrl. Buffer Type Function E10 P11.0 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_4 GTM_TIM2_IN0_7 ASCLIN3_ARXB Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 2 Receive input GTM_DTMA2_1 CDTM2_DTM4 P11.0 O0 General-purpose output GTM_TOUT119 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved — O4 Reserved CAN11_TXD O5 CAN transmit output node 1 GETH_TXD3 O6 Transmit Data — O7 Reserved Data Sheet 44 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E9 P11.1 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_5 GTM_TIM2_IN1_6 A10 Mux input channel 1 of TIM module 4 Mux input channel 1 of TIM module 2 P11.1 O0 GTM_TOUT120 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output General-purpose output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O4 Reserved CAN12_TXD O5 CAN transmit output node 2 GETH_TXD2 O6 Transmit Data — O7 Reserved P11.2 I GTM_TIM3_IN1_3 GTM_TIM2_IN1_3 RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 P11.2 O0 GTM_TOUT95 O1 GTM muxed output — O2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 General-purpose output IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Data Sheet 45 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B10 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN2_2 GTM_TIM2_IN2_2 MSC0_SDI3 Mux input channel 2 of TIM module 2 Upstream assynchronous input signal QSPI1_MRSTB D10 Mux input channel 2 of TIM module 3 Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output — O2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A — O5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 P11.4 I GTM_TIM4_IN2_5 GTM_TIM2_IN2_6 GETH_RXCLKB RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 2 Receive Clock MII P11.4 O0 General-purpose output GTM_TOUT121 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved CAN13_TXD O5 CAN transmit output node 3 GETH_TXER O6 Transmit Error MII GETH_TXCLK O7 Transmit Clock Output for RGMII Data Sheet 46 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D8 P11.5 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN3_5 GTM_TIM2_IN3_8 GETH_TXCLKA GETH_GREFCLK D9 Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 2 Transmit Clock Input for MII Gigabit Reference Clock input for RGMII (125 MHz high precission) P11.5 O0 General-purpose output GTM_TOUT122 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved CAN20_TXD O5 CAN transmit output node 0 — O6 Reserved — O7 Reserved P11.6 I GTM_TIM3_IN3_2 GTM_TIM2_IN3_2 QSPI1_SCLKB RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL CCU60_COUT61 Transmit Control for RGMII O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 47 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E8 P11.7 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN4_5 GTM_TIM2_IN4_7 GETH_RXD3A CAN11_RXDD E7 Mux input channel 4 of TIM module 4 Mux input channel 4 of TIM module 2 Receive Data 3 MII and RGMII (RGMII can use RXD3A only) CAN receive input node 1 P11.7 O0 General-purpose output GTM_TOUT123 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P11.8 I GTM_TIM4_IN5_5 GTM_TIM2_IN5_8 GETH_RXD2A CAN12_RXDD SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 5 of TIM module 2 Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 48 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A9 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN4_2 GTM_TIM2_IN4_2 QSPI1_MTSRB Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output — O2 Reserved QSPI1_MTSR O3 Master SPI data output — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 49 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B9 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN5_2 GTM_TIM2_IN5_2 GTM_TIM2_IN0_9 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output — O2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output — O5 Reserved — O6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 50 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A8 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN6_2 GTM_TIM3_IN0_14 GTM_TIM2_IN6_2 B8 Mux input channel 6 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output — O2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P11.12 I GTM_TIM3_IN7_2 GTM_TIM2_IN7_2 GETH_REFCLKA FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 51 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E6 P11.13 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN6_5 GTM_TIM2_IN6_7 GETH_RXERA Mux input channel 6 of TIM module 2 Receive Error MII CAN13_RXDD D7 Mux input channel 6 of TIM module 4 CAN receive input node 3 P11.13 O0 General-purpose output GTM_TOUT125 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P11.14 I GTM_TIM4_IN7_4 GTM_TIM2_IN7_8 GETH_CRSDVB SLOW / PU1 / VFLEX / ES General-purpose input Mux input channel 7 of TIM module 4 Mux input channel 7 of TIM module 2 Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVB Receive Data Valid MII GETH_CRSA Carrier Sense MII CAN20_RXDF CAN receive input node 0 P11.14 O0 General-purpose output GTM_TOUT126 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 52 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D6 P11.15 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN7_5 GTM_TIM0_IN7_8 GETH_COLA Mux input channel 7 of TIM module 4 Mux input channel 7 of TIM module 0 Collision MII P11.15 O0 General-purpose output GTM_TOUT127 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-6 Port 12 Functions Ball Symbol Ctrl. Buffer Type Function E12 P12.0 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_5 GTM_TIM3_IN0_7 CAN00_RXDC Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 3 CAN receive input node 0 GETH_RXCLKC Receive Clock MII GTM_DTMA4_0 CDTM4_DTM4 P12.0 O0 General-purpose output GTM_TOUT128 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH_MDC O6 MDIO clock — O7 Reserved Data Sheet 53 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-6 Port 12 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E11 P12.1 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_6 GTM_TIM3_IN1_6 GETH_MDIOC Mux input channel 1 of TIM module 4 Mux input channel 1 of TIM module 3 MDIO Input P12.1 O0 General-purpose output GTM_TOUT129 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved — O7 Reserved GETH_MDIO O MDIO Output Table 2-7 Port 13 Functions Ball Symbol Ctrl. Buffer Type Function B12 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN5_3 GTM_TIM2_IN5_3 ASCLIN10_ARXC Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved CAN10_TXD O7 CAN transmit output node 0 Data Sheet 54 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A12 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN6_3 GTM_TIM2_IN6_3 I2C0_SCLB B11 Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output — O2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) — O4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output — O7 Reserved P13.2 I GTM_TIM3_IN7_3 GTM_TIM2_IN7_3 GPT120_CAPINA I2C0_SDAB LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Trigger input to capture value of timer T5 into CAPREL register Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output — O7 Reserved Data Sheet 55 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A11 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN0_3 GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 P13.3 O0 GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Table 2-8 General-purpose output Port 14 Functions Ball Symbol Ctrl. Buffer Type Function B16 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 P14.0 O0 GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output General-purpose output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 56 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A15 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 GTM_TIM0_IN4_3 ERAY0_RXDA3 E13 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 P14.2 I GTM_TIM1_IN5_3 GTM_TIM0_IN5_3 PMS_HWCFG2IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output — O4 Reserved — O5 Reserved ASCLIN2_ASCLK O6 Shift clock output — O7 Reserved Data Sheet 57 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B14 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 GTM_TIM0_IN6_3 PMS_HWCFG3IN B15 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output — O6 Reserved — O7 Reserved P14.4 I GTM_TIM1_IN7_2 GTM_TIM0_IN7_2 PMS_HWCFG6IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH_PPS O6 Pulse Per Second — O7 Reserved Data Sheet 58 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A14 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 GTM_TIM0_IN0_4 PMS_HWCFG1IN Mux input channel 0 of TIM module 0 HWCFG1 pin input GTM_DTMA2_0 B13 Mux input channel 0 of TIM module 1 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved ERAY0_TXDB O6 Transmit Channel B — O7 Reserved P14.6 I GTM_TIM1_IN1_4 GTM_TIM0_IN1_4 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 P14.6 O0 GTM_TOUT86 O1 GTM muxed output — O2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 — O5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B — O7 Reserved Data Sheet General-purpose output 59 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D13 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_10 GTM_TIM1_IN0_5 GTM_TIM0_IN0_5 A13 Mux input channel 7 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output — O5 Reserved — O6 Reserved — O7 Reserved P14.8 I GTM_TIM3_IN2_3 GTM_TIM2_IN2_3 ERAY0_RXDA0 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 60 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D12 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_3 GTM_TIM2_IN3_3 ASCLIN0_ACTSA D11 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output CAN23_TXD O2 CAN transmit output node 3 MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A — O7 Reserved P14.10 I GTM_TIM3_IN4_3 GTM_TIM2_IN4_3 CAN23_RXDA QSPI2_MRSTFP LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 3 Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output — O2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A — O7 Reserved Data Sheet 61 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-9 Port 15 Functions Ball Symbol Ctrl. Buffer Type Function B20 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_4 GTM_TIM2_IN3_4 SDMMC0_DAT7_IN A18 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 read data in P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output — O4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output — O7 Reserved SDMMC0_DAT7 O write data out P15.1 I GTM_TIM3_IN4_4 GTM_TIM2_IN4_4 CAN02_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved SDMMC0_CLK O7 card clock Data Sheet 62 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function C19 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_4 GTM_TIM2_IN5_4 QSPI2_SLSIA B17 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Slave select input SENT_SENT10D Receive input channel 10 QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output — O4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output — O7 Reserved P15.3 I GTM_TIM3_IN6_4 GTM_TIM2_IN6_4 CAN01_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs SDMMC0_CMD_IN command in P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output — O4 Reserved MSC0_EN1 O5 Chip Select — O6 Reserved — O7 Reserved SDMMC0_CMD O command out Data Sheet 63 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A17 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_4 GTM_TIM2_IN7_4 I2C0_SCLC Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT11D Receive input channel 11 P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 64 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E14 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_4 GTM_TIM2_IN0_4 ASCLIN1_ARXB A16 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P15.6 I GTM_TIM2_IN2_14 GTM_TIM1_IN0_6 GTM_TIM0_IN0_6 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 2 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 65 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D15 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 GTM_TIM0_IN1_5 ASCLIN3_ARXA Mux input channel 1 of TIM module 0 Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST D14 Mux input channel 1 of TIM module 1 O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 P15.8 I GTM_TIM1_IN2_5 GTM_TIM0_IN2_5 QSPI2_SCLKB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output — O2 Reserved QSPI2_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 66 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-10 Port 20 Functions Ball Symbol Ctrl. Buffer Type Function H20 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 GTM_TIM1_IN4_9 GTM_TIM0_IN6_7 G19 Mux input channel 6 of TIM module 1 Mux input channel 4 of TIM module 1 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CAN21_RXDC CAN receive input node 1 CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output — O6 Reserved — O7 Reserved CBS_TGO0 O Trigger output P20.1 I GTM_TIM4_IN4_11 GTM_TIM3_IN3_5 GTM_TIM2_IN3_5 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 4 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved CBS_TGO1 O Trigger output Data Sheet 67 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H19 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE G20 P20.3 Testmode Enable Input I GTM_TIM4_IN5_11 GTM_TIM3_IN4_5 GTM_TIM2_IN4_5 F17 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P20.6 I GTM_TIM3_IN6_5 GTM_TIM2_IN6_5 CAN12_RXDA SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 68 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F19 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_5 GTM_TIM2_IN7_5 GTM_TIM1_IN5_8 F20 Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input SDMMC0_DAT0_IN read data in P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output — O3 Reserved — O4 Reserved CAN12_TXD O5 CAN transmit output node 2 — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 SDMMC0_DAT0 O P20.8 I GTM_TIM1_IN7_3 GTM_TIM0_IN7_3 SDMMC0_DAT1_IN write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 read data in P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 SDMMC0_DAT1 Data Sheet O write data out 69 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E17 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_5 GTM_TIM2_IN5_5 CAN03_RXDE E19 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output — O2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output — O5 Reserved — O6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 P20.10 I GTM_TIM3_IN6_6 GTM_TIM2_IN6_6 SDMMC0_DAT2_IN FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 read data in P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 SDMMC0_DAT2 Data Sheet O write data out 70 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E20 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_6 GTM_TIM2_IN7_6 QSPI0_SCLKA Mux input channel 7 of TIM module 2 Slave SPI clock inputs SDMMC0_DAT3_IN D19 Mux input channel 7 of TIM module 3 read data in P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output — O2 Reserved QSPI0_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 SDMMC0_DAT3 O P20.12 I GTM_TIM3_IN0_5 GTM_TIM2_IN0_5 QSPI0_MRSTA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Master SPI data input SDMMC0_DAT4_IN read data in IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 — O2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SDMMC0_DAT4 Data Sheet O write data out 71 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D20 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_4 GTM_TIM2_IN1_4 QSPI0_SLSIA Mux input channel 1 of TIM module 2 Slave select input SDMMC0_DAT5_IN read data in IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 C20 Mux input channel 1 of TIM module 3 Monitor input 0 — O2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SDMMC0_DAT5 O P20.14 I GTM_TIM3_IN2_4 GTM_TIM2_IN2_4 QSPI0_MTSRA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Slave SPI data input SDMMC0_DAT6_IN read data in IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 — O2 Reserved QSPI0_MTSR O3 Master SPI data output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved SDMMC0_DAT6 O write data out Data Sheet 72 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-11 Port 21 Functions Ball Symbol Ctrl. Buffer Type Function K17 P21.0 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_11 GTM_TIM3_IN4_6 GTM_TIM2_IN4_6 J17 Mux input channel 0 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 QSPI4_MRSTDN Master SPI data input (LVDS N line) ASCLIN11_ARXC Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved GETH1_PPS O6 Pulse Per Second — O7 Reserved HSM_HSM1 O Pin Output Value P21.1 I GTM_TIM4_IN1_13 GTM_TIM3_IN5_6 GTM_TIM2_IN5_6 LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 4 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 QSPI4_MRSTDP Master SPI data input (LVDS P line) ASCLIN11_ARXD Receive input GTM_DTMA4_1 CDTM4_DTM4 P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSM_HSM2 O Pin Output Value Data Sheet 73 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K19 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_11 GTM_TIM1_IN0_7 GTM_TIM0_IN0_7 J19 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data QSPI4_MRSTCN Master SPI data input (LVDS N line) ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved GETH_MDC O5 MDIO clock — O6 Reserved — O7 Reserved P21.3 I GTM_TIM5_IN5_12 GTM_TIM1_IN1_6 GTM_TIM0_IN1_6 LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data QSPI4_MRSTCP Master SPI data input (LVDS P line) P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved GETH_MDIO O MDIO Output Data Sheet 74 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K20 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN6_12 GTM_TIM1_IN2_6 GTM_TIM0_IN2_6 J20 Mux input channel 6 of TIM module 5 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDN O Tx data P21.5 I GTM_TIM5_IN7_11 GTM_TIM1_IN3_6 GTM_TIM0_IN3_6 ASCLIN11_ARXF LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 7 of TIM module 5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDP O Tx data Data Sheet 75 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H17 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O. GTM_TIM4_IN2_12 Mux input channel 2 of TIM module 4 GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O DAPE1 I/O DAPE: DAPE1 Data I/O Data Sheet 76 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H16 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O. GTM_TIM4_IN3_12 GTM_TIM1_IN5_7 Mux input channel 3 of TIM module 4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O DAPE2 I/O DAPE: DAPE2 Data I/O TDO O JTAG Module Data Output Data Sheet 77 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-12 Port 22 Functions Ball Symbol Ctrl. Buffer Type Function P20 P22.0 I LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input GTM_TIM1_IN1_7 GTM_TIM0_IN1_7 QSPI4_MTSRB P19 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Slave SPI data input ASCLIN6_ARXE Receive input GETH1_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH1_RXDVB Receive Data Valid MII GETH1_CRSA Carrier Sense MII P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATXN O2 Differential Transmit output (low active) QSPI4_MTSR O3 Master SPI data output QSPI4_SCLKN O4 Master SPI clock output (LVDS N line) MSC1_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved ASCLIN6_ATX O7 Transmit output P22.1 I GTM_TIM1_IN0_8 GTM_TIM0_IN0_8 QSPI4_MRSTB LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Master SPI data input ASCLIN7_ARXE Receive input GETH1_RXERA Receive Error MII P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATXP O2 Differential Transmit output (high active) QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI4_SCLKP O4 Master SPI clock output (LVDS P line) MSC1_FCLP O5 Shift-clock direct part of the differential signal — O6 Reserved ASCLIN7_ATX O7 Transmit output Data Sheet 78 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function R20 P22.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 GTM_TIM0_IN3_7 QSPI4_SLSIB GETH1_COLA R19 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Slave select input Collision MII P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI4_SLSO3 O3 Master slave select output QSPI4_MTSRN O4 Master SPI data output (LVDS N line) MSC1_SON O5 Data output - inverted part of the differential signal — O6 Reserved — O7 Reserved P22.3 I GTM_TIM1_IN4_4 GTM_TIM0_IN4_4 QSPI4_SCLKB ASCLIN5_ARXC LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Slave SPI clock inputs Receive input P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output — O2 Reserved QSPI4_SCLK O3 Master SPI clock output QSPI4_MTSRP O4 Master SPI data output (LVDS P line) MSC1_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Data Sheet 79 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function P16 P22.4 I SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM3_IN0_8 ASCLIN7_ARXF GETH1_RXD0A GTM_DTMA3_0 P17 Mux input channel 0 of TIM module 3 Receive input Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) CDTM3_DTM4 P22.4 O0 General-purpose output GTM_TOUT130 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved QSPI0_SLSO12 O4 Master slave select output — O5 Reserved CAN13_TXD O6 CAN transmit output node 3 — O7 Reserved P22.5 I GTM_TIM3_IN1_7 QSPI0_MTSRC CAN13_RXDC SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input Mux input channel 1 of TIM module 3 Slave SPI data input CAN receive input node 3 GETH1_REFCLKA Reference Clock input for RMII (50 MHz) GETH1_TXCLKB Transmit Clock Input for MII GETH1_RXCLKA Receive Clock MII P22.5 O0 General-purpose output GTM_TOUT131 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output — O3 Reserved QSPI0_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 80 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function N16 P22.6 I SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM3_IN2_6 GTM_TIM2_IN6_14 QSPI0_MRSTC N17 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 2 Master SPI data input ASCLIN4_ARXC Receive input GETH1_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH1_RXDVA Receive Data Valid MII GETH1_CRSB Carrier Sense MII GETH1_RCTLA Receive Control for RGMII P22.6 O0 General-purpose output GTM_TOUT132 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 CAN21_TXD O5 CAN transmit output node 1 — O6 Reserved — O7 Reserved P22.7 I GTM_TIM3_IN3_7 QSPI0_SCLKC CAN21_RXDF SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input Mux input channel 3 of TIM module 3 Slave SPI clock inputs CAN receive input node 1 GETH1_TXCLKA Transmit Clock Input for MII GETH1_GREFCLK Gigabit Reference Clock input for RGMII (125 MHz high precission) P22.7 O0 General-purpose output GTM_TOUT133 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved QSPI0_SCLK O4 Master SPI clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 81 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type M16 P22.8 I General-purpose input SLOW / PU1 / Mux input channel 0 of TIM module 5 VFLEX2 / Mux input channel 4 of TIM module 3 ES Slave SPI clock inputs GTM_TIM5_IN0_4 GTM_TIM3_IN4_7 QSPI0_SCLKB GETH1_RXCLKC M17 Function Receive Clock MII P22.8 O0 General-purpose output GTM_TOUT134 O1 GTM muxed output ASCLIN5_ASCLK O2 Shift clock output — O3 Reserved QSPI0_SCLK O4 Master SPI clock output CAN22_TXD O5 CAN transmit output node 2 GETH1_MDC O6 MDIO clock — O7 Reserved P22.9 I GTM_TIM5_IN1_10 GTM_TIM3_IN5_7 QSPI0_MRSTB General-purpose input SLOW / PU1 / Mux input channel 1 of TIM module 5 VFLEX2 / Mux input channel 5 of TIM module 3 ES Master SPI data input ASCLIN4_ARXD Receive input CAN22_RXDE CAN receive input node 2 GETH1_MDIOC MDIO Input GTM_DTMA3_1 CDTM3_DTM4 P22.9 O0 General-purpose output GTM_TOUT135 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 — O5 Reserved — O6 Reserved — O7 Reserved GETH1_MDIO O MDIO Output Data Sheet 82 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type L16 P22.10 I RFAST / General-purpose input PU1 / Mux input channel 2 of TIM module 5 VFLEX2 / Mux input channel 6 of TIM module 3 ES Slave SPI data input GTM_TIM5_IN2_8 GTM_TIM3_IN6_7 QSPI0_MTSRB L17 Function P22.10 O0 General-purpose output GTM_TOUT136 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output — O3 Reserved QSPI0_MTSR O4 Master SPI data output CAN23_TXD O5 CAN transmit output node 3 GETH1_TXD0 O6 Transmit Data — O7 Reserved P22.11 I GTM_TIM5_IN3_10 GTM_TIM3_IN7_7 CAN23_RXDE RFAST / General-purpose input PU1 / Mux input channel 3 of TIM module 5 VFLEX2 / Mux input channel 7 of TIM module 3 ES CAN receive input node 3 P22.11 O0 General-purpose output GTM_TOUT137 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved QSPI0_SLSO10 O4 Master slave select output — O5 Reserved GETH1_TXEN O6 Transmit Enable MII and RMII GETH1_TCTL — Data Sheet Transmit Control for RGMII O7 Reserved 83 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-13 Port 23 Functions Ball Symbol Ctrl. Buffer Type Function V20 P23.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_4 GTM_TIM0_IN5_4 CAN10_RXDC U19 Mux input channel 5 of TIM module 0 CAN receive input node 0 P23.0 O0 General-purpose output GTM_TOUT41 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P23.1 I GTM_TIM1_IN6_4 GTM_TIM0_IN6_4 MSC1_SDI0 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 Upstream assynchronous input signal ASCLIN6_ARXF U20 Mux input channel 5 of TIM module 1 Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI4_SLSO6 O3 Master slave select output GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output P23.2 I GTM_TIM1_IN6_5 GTM_TIM0_IN6_5 ASCLIN7_ARXC RFAST / General-purpose input PU1 / Mux input channel 6 of TIM module 1 VFLEX2 / Mux input channel 6 of TIM module 0 ES Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output — O2 Reserved — O3 Reserved CAN23_TXD O4 CAN transmit output node 3 CAN12_TXD O5 CAN transmit output node 2 GETH1_TXD3 O6 Transmit Data — O7 Reserved Data Sheet 84 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-13 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type T19 P23.3 I RFAST / General-purpose input PU1 / Mux input channel 7 of TIM module 1 VFLEX2 / Mux input channel 7 of TIM module 0 ES Injection signal from port GTM_TIM1_IN7_4 GTM_TIM0_IN7_4 MSC1_INJ0 T20 Function ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 CAN23_RXDB CAN receive input node 3 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved GETH1_TXD2 O6 Transmit Data — O7 Reserved P23.4 I GTM_TIM1_IN7_5 GTM_TIM0_IN7_5 RFAST / General-purpose input PU1 / Mux input channel 7 of TIM module 1 VFLEX2 / Mux input channel 7 of TIM module 0 ES General-purpose output P23.4 O0 GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output QSPI4_SLSO5 O3 Master slave select output — O4 Reserved MSC1_EN0 O5 Chip Select GETH1_TXD1 O6 Transmit Data — O7 Reserved Data Sheet 85 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-13 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function T17 P23.5 I FAST / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM1_IN2_7 GTM_TIM0_IN2_7 GETH1_RXD3A R17 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Receive Data 3 MII and RGMII (RGMII can use RXD3A only) P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output QSPI4_SLSO4 O3 Master slave select output — O4 Reserved MSC1_EN1 O5 Chip Select CAN22_TXD O6 CAN transmit output node 2 — O7 Reserved P23.6 I GTM_TIM4_IN2_7 GTM_TIM1_IN2_10 CAN22_RXDC GETH1_RXD2A SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 1 CAN receive input node 2 Receive Data 2 MII and RGMII (RGMII can use RXD2A only) P23.6 O0 General-purpose output GTM_TOUT138 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI0_SLSO11 O4 Master slave select output CAN11_TXD O5 CAN transmit output node 1 — O6 Reserved — O7 Reserved Data Sheet 86 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-13 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function R16 P23.7 I SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM4_IN3_7 GTM_TIM1_IN3_10 CAN11_RXDC GETH1_RXD1A Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 1 CAN receive input node 1 Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P23.7 O0 General-purpose output GTM_TOUT139 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-14 Port 32 Functions Ball Symbol Ctrl. Buffer Type Function Y17 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM3_IN2_5 GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 87 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-14 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W17 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC GTM_TIM3_IN3_15 Y18 Mux input channel 3 of TIM module 3 P32.1 O0 GTM_TOUT37 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P32.2 I GTM_TIM1_IN3_8 GTM_TIM0_IN3_8 CAN03_RXDB SLOW / PU1 / VEXT / ES General-purpose output General-purpose input Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 3 ASCLIN3_ARXD Receive input CAN21_RXDD CAN receive input node 1 P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output — O7 Reserved Data Sheet 88 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-14 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y19 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 GTM_TIM0_IN4_5 W18 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 P32.3 O0 GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output General-purpose output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P32.4 I GTM_TIM1_IN5_5 GTM_TIM0_IN5_5 ASCLIN1_ACTSB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Clear to send input MSC1_SDI2 Upstream assynchronous input signal P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output — O2 Reserved — O3 Reserved GTM_CLK1 O4 CGM generated clock MSC1_EN0 O5 Chip Select CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO Data Sheet O DC-DC synchronization output 89 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-14 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function T15 P32.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_9 GTM_TIM4_IN1_14 GTM_TIM3_IN5_8 Mux input channel 1 of TIM module 4 Mux input channel 5 of TIM module 3 SENT_SENT10C U15 Mux input channel 5 of TIM module 5 Receive input channel 10 P32.5 O0 General-purpose output GTM_TOUT140 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 — O7 P32.6 I GTM_TIM5_IN6_9 GTM_TIM4_IN4_15 GTM_TIM3_IN6_8 Reserved SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 4 of TIM module 4 Mux input channel 6 of TIM module 3 CAN02_RXDC CAN receive input node 2 CBS_TGI4 Trigger input ASCLIN2_ARXF Receive input ASCLIN6_ARXC Receive input SENT_SENT11C Receive input channel 11 P32.6 O0 General-purpose output GTM_TOUT141 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI2_SLSO12 O4 Master slave select output CAN22_TXD O5 CAN transmit output node 2 — O6 Reserved — O7 Reserved CBS_TGO4 O Trigger output Data Sheet 90 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-14 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function U16 P32.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_8 GTM_TIM4_IN0_15 GTM_TIM3_IN7_8 Mux input channel 7 of TIM module 5 Mux input channel 0 of TIM module 4 Mux input channel 7 of TIM module 3 CBS_TGI5 Trigger input CAN22_RXDB CAN receive input node 2 SENT_SENT12C Receive input channel 12 P32.7 O0 General-purpose output GTM_TOUT142 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved CBS_TGO5 O Trigger output Data Sheet 91 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions Ball Symbol Ctrl. Buffer Type Function W10 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_13 GTM_TIM1_IN4_6 GTM_TIM0_IN4_6 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 SENT_SENT13C Receive input channel 13 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 EVADC_G10CH7 AI Analog input channel 7, group 10 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 — O7 Reserved Data Sheet 92 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y10 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_15 GTM_TIM1_IN5_6 GTM_TIM0_IN5_6 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC EVADC_G10CH6 AI Analog input channel 6, group 10 P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 — O6 Reserved — O7 Reserved Data Sheet 93 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W11 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN2_14 GTM_TIM1_IN6_6 GTM_TIM0_IN6_6 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC EVADC_G10CH5 AI Analog input channel 5, group 10 P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 94 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y11 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN3_12 GTM_TIM1_IN7_6 GTM_TIM0_IN7_6 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC EVADC_G10CH4 AI Analog input channel 4, group 10 P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output QSPI4_SLSO2 O3 Master slave select output EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved — O7 Reserved Data Sheet 95 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W12 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_10 GTM_TIM1_IN0_10 GTM_TIM0_IN0_10 Mux input channel 4 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC GTM_DTMT2_0 CDTM2_DTM0 EVADC_G10CH3 AI Analog input channel 3, group 10 P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Data Sheet 96 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y12 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN5_10 GTM_TIM1_IN1_8 GTM_TIM0_IN1_8 Mux input channel 5 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC EVADC_G10CH2 AI Analog input channel 2, group 10 P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 ASCLIN5_ASLSO O7 Slave select signal output Data Sheet 97 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W13 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 GTM_TIM0_IN2_9 EDSADC_ITR2F Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC GTM_DTMT2_1 CDTM2_DTM0 EVADC_G10CH1 AI Analog input channel 1, group 10 P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Data Sheet 98 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y13 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 GTM_TIM0_IN3_9 CAN00_RXDE Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT14C Receive input channel 14 IOM_PIN_7 GPIO pad input to FPC EVADC_G10CH0 AI Analog input channel 0, group 10 P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output QSPI4_SLSO7 O3 Master slave select output ASCLIN8_ATX O4 Transmit output — O5 Reserved EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 99 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W14 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO2 O3 Master slave select output — O4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 Data Sheet O FSP[1..0] Output Signals - Generated by SMU_core 100 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y14 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 GTM_TIM0_IN1_9 IOM_PIN_9 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO1 O3 Master slave select output ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 101 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W15 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 GTM_TIM1_IN0_9 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Y15 Mux input channel 4 of TIM module 4 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O P33.11 I GTM_TIM1_IN2_8 GTM_TIM0_IN2_8 QSPI4_SCLKA FSP[1..0] Output Signals - Generated by SMU_core FAST / PU1 / VEVRSB / ES5 General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 102 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W16 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_6 GTM_TIM2_IN0_6 QSPI4_MTSRA Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Slave SPI data input CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 ASCLIN1_ATX Monitor input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MTSR O3 Master SPI data output ASCLIN1_ASCLK O4 Shift clock output CAN22_TXD O5 CAN transmit output node 2 EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 103 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y16 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_5 GTM_TIM2_IN1_5 ASCLIN1_ARXF Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 Receive input EDSADC_SGNB Carrier sign signal input QSPI4_MRSTA Master SPI data input MSC1_INJ1 Injection signal from port CAN22_RXDA CAN receive input node 2 P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 104 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-15 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function T14 P33.14 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN0_8 GTM_TIM4_IN5_14 GTM_TIM2_IN0_8 U14 Mux input channel 0 of TIM module 5 Mux input channel 5 of TIM module 4 Mux input channel 0 of TIM module 2 QSPI2_SCLKD Slave SPI clock inputs CBS_TGI6 Trigger input P33.14 O0 General-purpose output GTM_TOUT143 O1 GTM muxed output — O2 Reserved QSPI2_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 CBS_TGO6 O P33.15 I GTM_TIM5_IN1_9 GTM_TIM4_IN6_12 GTM_TIM2_IN1_7 Trigger output SLOW / PU1 / VEVRSB / ES5 General-purpose input Mux input channel 1 of TIM module 5 Mux input channel 6 of TIM module 4 Mux input channel 1 of TIM module 2 CBS_TGI7 Trigger input P33.15 O0 General-purpose output GTM_TOUT144 O1 GTM muxed output — O2 Reserved QSPI2_SLSO11 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 CBS_TGO7 Data Sheet O Trigger output 105 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-16 Port 34 Functions Ball Symbol Ctrl. Buffer Type Function U11 P34.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN3_9 GTM_TIM3_IN4_12 GTM_TIM2_IN3_9 T12 Mux input channel 3 of TIM module 5 Mux input channel 4 of TIM module 3 Mux input channel 3 of TIM module 2 EVADC_G10CH11 AI Analog input channel 11, group 10 P34.1 O0 General-purpose output GTM_TOUT146 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output — O3 Reserved CAN00_TXD O4 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 CAN20_TXD O5 CAN transmit output node 0 — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 P34.2 I GTM_TIM5_IN4_9 GTM_TIM3_IN5_13 GTM_TIM2_IN4_8 SLOW / PU1 / VEVRSB / ES General-purpose input Mux input channel 4 of TIM module 5 Mux input channel 5 of TIM module 3 Mux input channel 4 of TIM module 2 ASCLIN4_ARXB Receive input CAN00_RXDG CAN receive input node 0 CAN20_RXDC CAN receive input node 0 EVADC_G10CH10 AI Analog input channel 10, group 10 P34.2 O0 General-purpose output GTM_TOUT147 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 106 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-16 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function U12 P34.3 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN5_10 GTM_TIM3_IN6_13 GTM_TIM2_IN5_9 T13 Mux input channel 5 of TIM module 5 Mux input channel 6 of TIM module 3 Mux input channel 5 of TIM module 2 EVADC_G10CH9 AI Analog input channel 9, group 10 P34.3 O0 General-purpose output GTM_TOUT148 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved QSPI2_SLSO10 O4 Master slave select output — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 P34.4 I GTM_TIM5_IN6_10 GTM_TIM3_IN7_12 GTM_TIM2_IN6_8 SLOW / PU1 / VEVRSB / ES General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 7 of TIM module 3 Mux input channel 6 of TIM module 2 QSPI2_MRSTD Master SPI data input EVADC_G10CH8 AI Analog input channel 8, group 10 P34.4 O0 General-purpose output GTM_TOUT149 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved QSPI2_MRST O4 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O5 Reserved — O6 Reserved CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 107 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-16 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function U13 P34.5 I FAST / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN7_9 GTM_TIM4_IN7_12 GTM_TIM2_IN7_9 Mux input channel 7 of TIM module 5 Mux input channel 7 of TIM module 4 Mux input channel 7 of TIM module 2 QSPI2_MTSRD Slave SPI data input ASCLIN8_ARXE Receive input P34.5 O0 General-purpose output GTM_TOUT150 O1 GTM muxed output ASCLIN8_ATX O2 Transmit output — O3 Reserved QSPI2_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-17 Analog Inputs Ball Symbol Ctrl. Buffer Type T10 AN0 I D / HighZ Analog Input 0 / VDDM Analog input channel 0, group 0 EVADC_G0CH0 EDSADC_EDS3PA U10 AN1 Positive analog input channel 3, pin A I EVADC_G0CH1 EDSADC_EDS3NA W9 AN2 I EDSADC_EDS0PA AN3 I EDSADC_EDS0NA AN4 I EVADC_G0CH4 AN5 EVADC_G11CH1 EVADC_G0CH5 Data Sheet D / HighZ Analog Input 3 / VDDM Analog input channel 3, group 0 Negative analog input channel 0, pin A EVADC_G11CH0 Y9 D / HighZ Analog Input 2 / VDDM Analog input channel 2, group 0 Positive analog input channel 0, pin A EVADC_G0CH3 T9 D / HighZ Analog Input 1 / VDDM Analog input channel 1, group 0 Negative analog input channel 3, pin A EVADC_G0CH2 U9 Function D / HighZ Analog Input 4 / VDDM Analog input channel 0, group 11 Analog input channel 4, group 0 I D / HighZ Analog Input 5 / VDDM Analog input channel 1, group 11 Analog input channel 5, group 0 108 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-17 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type T8 AN6 I D / HighZ Analog Input 6 / VDDM Analog input channel 2, group 11 EVADC_G11CH2 EVADC_G0CH6 U8 AN7 Analog input channel 6, group 0 I EVADC_G11CH3 EVADC_G0CH7 W8 AN8 I EVADC_G1CH0 AN9 I EVADC_G1CH1 AN10 I EVADC_G1CH2 AN11 I EVADC_G1CH3 AN12 I EDSADC_EDS0PB AN13 I EDSADC_EDS0NB AN14 I EDSADC_EDS3PB AN15 I EDSADC_EDS3NB AN16 I EVADC_FC0CH0 AN17/P40.10 SENT_SENT10A D / HighZ Analog Input 15 / VDDM Analog input channel 7, group 1 Negative analog input channel 3, pin N EVADC_G2CH0 U5 D / HighZ Analog Input 14 / VDDM Analog input channel 6, group 1 Positive analog input channel 3, pin B EVADC_G1CH7 W5 D / HighZ Analog Input 13 / VDDM Analog input channel 5, group 1 Negative analog input channel 0, pin B EVADC_G1CH6 T6 D / HighZ Analog Input 12 / VDDM Analog input channel 4, group 1 Positive analog input channel 0, pin B EVADC_G1CH5 U6 D / HighZ Analog Input 11 / VDDM Analog input channel 7, group 11 Analog input channel 3, group 1 EVADC_G1CH4 W6 D / HighZ Analog Input 10 / VDDM Analog input channel 6, group 11 Analog input channel 2, group 1 EVADC_G11CH7 T7 D / HighZ Analog Input 9 / VDDM Analog input channel 5, group 11 Analog input channel 1, group 1 EVADC_G11CH6 W7 D / HighZ Analog Input 8 / VDDM Analog input channel 4, group 11 Analog input channel 0, group 1 EVADC_G11CH5 Y8 D / HighZ Analog Input 7 / VDDM Analog input channel 3, group 11 Analog input channel 7, group 0 EVADC_G11CH4 U7 Function D / HighZ Analog Input 16 / VDDM Analog input channel 0, group 2 Analog input FC channel 0 I S / HighZ Analog Input 17 / VDDM Receive input channel 10 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 Data Sheet 109 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-17 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type W4 AN18/P40.11 I S / HighZ Analog Input 18 / VDDM Receive input channel 11 SENT_SENT11A W3 EVADC_G11CH8 Analog input channel 8, group 11 EVADC_G2CH2 Analog input channel 2, group 2 AN19/P40.12 I SENT_SENT12A Y3 Analog input channel 9, group 11 EVADC_G2CH3 Analog input channel 3, group 2 AN20 I EDSADC_EDS2PA AN21 I EDSADC_EDS2NA AN22 AN23 I D / HighZ Analog Input 22 / VDDM Analog input channel 6, group 2 I D / HighZ Analog Input 23 / VDDM Analog input channel 7, group 2 I S / HighZ Analog Input 24 / VDDM Receive input channel 0 EVADC_G2CH7 W2 AN24/P40.0 SENT_SENT0A W1 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B AN25/P40.1 I SENT_SENT1A V2 S / HighZ Analog Input 25 / VDDM Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B AN26/P40.2 I SENT_SENT2A V1 D / HighZ Analog Input 21 / VDDM Analog input channel 5, group 2 Negative analog input channel 2, pin A EVADC_G2CH6 R5 D / HighZ Analog Input 20 / VDDM Analog input channel 4, group 2 Positive analog input channel 2, pin A EVADC_G2CH5 T5 S / HighZ Analog Input 19 / VDDM Receive input channel 12 EVADC_G11CH9 EVADC_G2CH4 Y2 Function S / HighZ Analog Input 26 / VDDM Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 EVADC_G11CH10 Analog input channel 10, group 11 AN27/P40.3 SENT_SENT3A I S / HighZ Analog Input 27 / VDDM Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2 EVADC_G11CH11 Analog input channel 11, group 11 Data Sheet 110 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-17 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type U2 AN28/P40.13 I S / HighZ Analog Input 28 / VDDM Receive input channel 13 SENT_SENT13A EVADC_G3CH4 U1 AN29/P40.14 Analog input channel 4, group 3 I SENT_SENT14A EVADC_G3CH5 T4 AN30 AN31 I D / HighZ Analog Input 30 / VDDM Analog input channel 6, group 3 I D / HighZ Analog Input 31 / VDDM Analog input channel 7, group 3 I S / HighZ Analog Input 32 / VDDM Receive input channel 4 EVADC_G3CH7 P4 AN32/P40.4 SENT_SENT4A R1 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 EVADC_G11CH12 Analog input channel 12, group 11 AN33/P40.5 I SENT_SENT5A P5 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 EVADC_G11CH13 Analog input channel 13, group 11 AN34 I EVADC_G11CH14 AN35 I EVADC_G11CH15 AN36/P40.6 D / HighZ Analog Input 35 / VDDM Analog input channel 3, group 8 Analog input channel 15, group 11 I SENT_SENT6A P2 D / HighZ Analog Input 34 / VDDM Analog input channel 2, group 8 Analog input channel 14, group 11 EVADC_G8CH3 N4 S / HighZ Analog Input 33 / VDDM Receive input channel 5 EVADC_G8CH1 EVADC_G8CH2 R2 S / HighZ Analog Input 29 / VDDM Receive input channel 14 Analog input channel 5, group 3 EVADC_G3CH6 R4 Function S / HighZ Analog Input 36 / VDDM Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A AN37/P40.7 SENT_SENT7A I S / HighZ Analog Input 37 / VDDM Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A Data Sheet 111 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-17 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type N5 AN38/P40.8 I S / HighZ Analog Input 38 / VDDM Receive input channel 8 SENT_SENT8A P1 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B AN39/P40.9 I SENT_SENT9A M5 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B AN40 I D / HighZ Analog Input 40 / VDDM Analog input channel 8, group 8 AN41 I D / HighZ Analog Input 41 / VDDM Analog input channel 9, group 8 I D / HighZ Analog Input 42 / VDDM Analog input channel 10, group 8 I D / HighZ Analog Input 43 / VDDM Analog input channel 11, group 8 I D / HighZ Analog Input 44 / VDDM Analog input channel 12, group 8 EVADC_G8CH9 L5 AN42 EVADC_G8CH10 L4 AN43 EVADC_G8CH11 N1 AN44 EVADC_G8CH12 EDSADC_EDS1PC N2 AN45 Positive analog input channel 1, pin C I EVADC_G8CH13 EDSADC_EDS1NC M1 AN46 I EDSADC_EDS1PD AN47 EVADC_G8CH15 EDSADC_EDS1ND Data Sheet D / HighZ Analog Input 45 / VDDM Analog input channel 13, group 8 Negative analog input channel 1, pin C EVADC_G8CH14 M2 S / HighZ Analog Input 39 / VDDM Receive input channel 9 EVADC_G8CH7 EVADC_G8CH8 M4 Function D / HighZ Analog Input 46 / VDDM Analog input channel 14, group 8 Positive analog input channel 1, pin D I D / HighZ Analog Input 47 / VDDM Analog input channel 15, group 8 Negative analog input channel 1, pin D 112 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-18 System I/O Ball Symbol Ctrl. Buffer Type Function L7 AGBTCLKN (VSS) I AGBT_C LK / VEXT Input PAD (negative pole) for the external 100 MHz differential clock. AGBT Input; (TC3xx devices without AGBT: VSS) K7 AGBTCLKP (VSS) I AGBT_C LK / VEXT Input PAD (positive pole) for the external 100 MHz differential clock. AGBT Input; (TC3xx devices without AGBT: VSS) P10 AGBTTXN (VSS) O AGBT_T Off-chip driver output PAD of the 2.5Gbps transmitter, X / VEXT negative pole AGBT Output; (TC3xx devices without AGBT: VSS) P11 AGBTTXP (VSS) O AGBT_T Off-chip driver output PAD of the 2.5Gbps transmitter, X / VEXT positive pole AGBT Output; (TC3xx devices without AGBT: VSS) L14 AGBTERR (VSS) I FAST / PD / VEXT Input PAD for CRC error from FPGA. AGBT Input; (TC3xx devices without AGBT: VSS) Y17 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC W17 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC M20 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. M19 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT G10 DAPE2 I/O FAST / PD2 / VEXT DAPE: DAPE2 Data I/O DAPE: DAPE2 Data I/O (TC3xx devices without DAPE: VSS) G11 DAPE1 I/O FAST / PD2 / VEXT DAPE: DAPE1 Data I/O DAPE: DAPE1 Data I/O (TC3xx devices without DAPE: VSS) K16 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input TMS: JTAG Module State Machine Control Input. DAP: DAP1 Data I/O. DAP1 I/O K14 DAPE0 I FAST / PD2 / VEXT DAPE: DAPE0 Clock Input DAPE: DAPE0 clock input (TC3xx devices without DAPE: NC) L19 TRST I FAST / PU2 / VEXT JTAG Module Reset/Enable Input TRST_N: JTAG Module Reset/Enable Input. DAPE: DAPE0 Clock Input DAPE0 I Data Sheet DAP: DAP1 Data I/O DAPE: DAPE0 Clock Input 113 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-18 System I/O (cont’d) Ball Symbol Ctrl. Buffer Type Function J16 TCK I JTAG Module Clock Input TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input. DAP0 I FAST / PD2 / VEXT ESR1 I FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I G17 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. F16 ESR0 I FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I G16 DAP: DAP0 Clock Input ESR1 pin input ESR0 pin input Table 2-19 Supply Ball Ctrl. Buffer Type Function P8, P13, N7, VDD N14, E15, H14, D16, G13 I — Digital Core Power Supply (1.25V) A2, B3, V19, VEXT W20 I — External Power Supply (5V / 3.3V) D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) Y5 VDDM I — ADC Analog Power Supply (5V / 3.3V) B18, A19 VDDP3 I — Flash Power Supply (3.3V) B2, D4, E5, T16, U17, W19, Y20, E16, D17, B19, A20 VSS I — Digital Ground Data Sheet Symbol 114 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-19 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function Y4 VSSM I — Analog Ground for VDDM P9, P12, N9, VSS N10, N11, N12, M7, M8, M10, M11, M13, M14, L8, L9, L10, L11, L12, L13, K8, K9, K10, K11, K12, K13, J7, J8, J10, J11, J13, J14, H9, H10, H11, H12, G9, G12 I — Digital Ground L20 VSS I — Oscillator Ground, VSS(OSC) Y6 VAREF1 I — Positive Analog Reference Voltage 1 Y7 VAGND1 I — Negative Analog Reference Voltage 1 T1 VAREF2 I — Positive Analog Reference Voltage 2 T2 VAGND2 I — Negative Analog Reference Voltage 2 A1, Y1, U4 NC1 I — Not connected. These pins are not connected on package level and will not be used for future extensions G8, H7 VDDSB (VDD) I — Devices with integrated EMEM: EMEM SRAM Standby Power Supply, VDDSB (1.25V); Devices without integrated EMEM: VDD (1.25V) T11 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM N19 VDD I — Digital Power Supply for Oscillator (1.25V), VDD(OSC) N20 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT), VEXT(OSC) Data Sheet 115 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of 2.2 LFBGA-292 Package Pinning of TC37xEXT TX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A NC1 VEXT P10.7 P10.6 P10.2 P10.3 P10.0 P11.11 P11.9 P11.2 P13.3 P13.1 P14.8 P14.5 P14.1 P15.6 P15.4 P15.1 VDDP3 VSS A B P02.0 VSS VEXT P10.8 P10.5 P10.4 P10.1 P11.12 P11.10 P11.3 P13.2 P13.0 P14.6 P14.3 P14.4 P14.0 P15.3 VDDP3 VSS P15.0 B C P02.2 P02.1 P15.2 P20.14 C D P02.4 P02.3 VSS VFLEX P11.15 P11.14 P11.5 P11.6 P11.4 P14.10 P14.9 P14.7 P15.8 P15.7 VDD VSS P20.12 P20.13 D E P02.6 P02.5 P02.9 VSS P11.13 P11.8 P11.7 P11.1 P11.0 P12.1 P12.0 P14.2 P15.5 VDD VSS P20.9 P20.10 P20.11 E F P02.8 P02.7 P02.11 P02.10 ESR0 P20.6 P20.7 P20.8 F G P00.0 P00.1 P01.4 P01.3 ESR1 PORST P20.1 P20.3 G H P00.2 P00.3 P01.6 P01.5 VDDSB (VDD) VDD P21.7 / TDO P21.6 / TDI P20.2 P20.0 H J P00.4 P00.5 P00.6 P01.7 VSS VSS VSS VSS TCK P21.1 P21.3 P21.5 J K P00.7 P00.9 P00.8 P00.10 AGBTC LKP (VSS) VSS L P00.11 P00.12 AN43 AN42 AGBTC LKN (VSS) VSS M AN46 AN47 AN41 AN40 VSS VSS N AN44 AN45 AN36 / P40.6 AN38 / P40.8 VDD P AN39 / P40.9 AN37 / P40.7 AN32 / P40.4 AN34 R AN33 / P40.5 AN35 AN31 AN23 T VAREF 2 VAGND 2 AN30 AN22 AN15 AN12 AN6 AN4 AN0 VEVRS B P34.2 P34.4 P33.14 U AN29 / P40.14 AN28 / P40.13 NC1 AN17 / P40.10 AN14 AN9 AN7 AN3 AN1 P34.1 P34.3 P34.5 P33.15 V AN27 / P40.3 AN26 / P40.2 W AN25 / P40.1 AN24 / P40.0 AN19 / P40.12 AN18 / P40.11 AN16 AN13 AN11 AN8 AN2 P33.0 P33.2 P33.4 P33.6 P33.8 P33.10 P33.12 P32.1 / VGATE 1P Y NC1 AN21 AN20 VSSM VDDM VAREF 1 VAGND 1 AN10 AN5 P33.1 P33.3 P33.5 P33.7 P33.9 P33.11 P33.13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDDSB (VDD) VDD VSS DAPE2 DAPE1 VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DAPE0 TMS P21.0 P21.2 P21.4 K VSS VSS VSS VSS VSS AGBTE RR (VSS) P22.0 P22.1 TRST VSS L VSS VSS VSS VSS P22.8 P22.9 XTAL2 XTAL1 M VSS VSS VSS VSS VDD P22.6 P22.7 VDD VEXT N VSS AGBTT XN (VSS) AGBTT XP (VSS) VSS P22.4 P22.5 P22.11 P22.10 P P23.7 P23.6 P22.3 P22.2 R P32.5 VSS P23.5 P22.12 P23.4 T P32.6 P32.7 VSS P23.1 P23.3 U VFLEX 2 P23.2 V P32.4 VSS VEXT W P32.0 / VGATE 1N P32.2 P32.3 VSS Y 17 18 19 20 VDD TC37xed_geth - (top view) Figure 2-2 TC37xEXT TX package variant LFBGA-292 Data Sheet 116 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions Ball Symbol Ctrl. Buffer Type Function G1 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_10 GTM_TIM3_IN0_1 GTM_TIM2_IN0_1 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port CIF_D9 sensor pixel data input GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O4 Reserved CAN10_TXD O5 CAN transmit output node 0 — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO Data Sheet O MDIO Output 117 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function G2 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_11 GTM_TIM3_IN1_1 GTM_TIM2_IN1_1 Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input EDSADC_DSCIN5A Modulator clock input, channel 5 CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CIF_D10 sensor pixel data input CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI EDSADC_EDS5NA Analog input channel 11, group 9 Negative analog input channel 5, pin A P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 ASCLIN3_ATX Reference input 0 O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 118 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H1 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN6_11 GTM_TIM3_IN1_2 GTM_TIM2_IN1_2 Mux input channel 6 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 EDSADC_DSDIN5A Digital datastream input, channel 5 SENT_SENT1B Receive input channel 1 CIF_D11 sensor pixel data input EVADC_G9CH10 AI EDSADC_EDS5PA Analog input channel 10, group 9 Positive analog input channel 5, pin A P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output CAN21_TXD O3 CAN transmit output node 1 PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 119 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H2 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN7_10 GTM_TIM3_IN2_1 GTM_TIM2_IN2_1 Mux input channel 7 of TIM module 5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 EDSADC_ITR5F Trigger/Gate input, channel 5 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 CAN21_RXDA CAN receive input node 1 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CIF_D12 sensor pixel data input CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI EDSADC_EDS5NB Analog input channel 9, group 9 Negative analog input channel 5, pin B P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output — O5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 120 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J1 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN3_1 GTM_TIM2_IN3_1 SCU_E_REQ2_2 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input CIF_D13 sensor pixel data input EVADC_G9CH8 AI EDSADC_EDS5PB Analog input channel 8, group 9 Positive analog input channel 5, pin B P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 — O5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Data Sheet 121 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J2 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN4_1 GTM_TIM3_IN0_11 GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CIF_D14 sensor pixel data input CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 122 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J4 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN5_1 GTM_TIM3_IN1_14 GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 3 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 2 EDSADC_ITR4F Trigger/Gate input, channel 4 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 CIF_D15 sensor pixel data input ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output — O3 Reserved — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Data Sheet 123 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K1 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN6_1 GTM_TIM3_IN2_11 GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 3 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 EDSADC_DSCIN4A Modulator clock input, channel 4 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 CIF_PCLK Sensor Pixel Clock input GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI EDSADC_EDS4NA Analog input channel 5, group 9 Negative analog input channel 4, pin A P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output EVADC_FC2BFLOUT O3 Boundary flag output, FC channel 2 EDSADC_DSCOUT4 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 124 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K4 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN7_1 GTM_TIM3_IN3_11 GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 3 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 EDSADC_DSDIN4A Digital datastream input, channel 4 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CIF_VSYNC vertical synchronization signal input CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI EDSADC_EDS4PA Analog input channel 4, group 9 Positive analog input channel 4, pin A P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output — O4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 125 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K2 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN0_7 GTM_TIM1_IN0_1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CIF_HSYNC horizontal synchronization signal input CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI EDSADC_EDS4NB Analog input channel 3, group 9 Negative analog input channel 4, pin B P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 126 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K5 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN1_11 GTM_TIM1_IN1_1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 EDSADC_EDS4PB L1 Mux input channel 1 of TIM module 4 Positive analog input channel 4, pin B P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 P00.11 I GTM_TIM4_IN2_11 GTM_TIM1_IN2_1 GTM_TIM0_IN2_1 SLOW / PU1 / VEXT / ES1 General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 SENT_SENT10B Receive input channel 10 EVADC_G9CH1 AI EVADC_FC3CH0 Analog input channel 1, group 9 Analog input FC channel 3 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT0 O4 Modulator clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 127 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-20 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function L2 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN3_11 GTM_TIM1_IN3_1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input SENT_SENT11B Receive input channel 11 EVADC_G9CH0 AI EVADC_FC2CH0 Analog input channel 0, group 9 Analog input FC channel 2 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Data Sheet 128 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-21 Port 01 Functions Ball Symbol Ctrl. Buffer Type Function G5 P01.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_2 GTM_TIM2_IN0_14 GTM_TIM0_IN5_8 Mux input channel 0 of TIM module 2 Mux input channel 5 of TIM module 0 QSPI3_SLSIB G4 Mux input channel 5 of TIM module 4 Slave select input EVADC_G9CH14 AI Analog input channel 14, group 9 P01.3 O0 General-purpose output GTM_TOUT111 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI3_SLSO9 O4 Master slave select output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 — O6 Reserved — O7 Reserved P01.4 I GTM_TIM4_IN6_2 GTM_TIM2_IN1_14 GTM_TIM0_IN6_8 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 4 Mux input channel 1 of TIM module 2 Mux input channel 6 of TIM module 0 CAN01_RXDC CAN receive input node 1 EVADC_G9CH13 AI Analog input channel 13, group 9 P01.4 O0 General-purpose output GTM_TOUT112 O1 GTM muxed output — O2 Reserved ASCLIN9_ASLSO O3 Slave select signal output QSPI3_SLSO10 O4 Master slave select output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 129 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-21 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H5 P01.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_2 GTM_TIM2_IN3_7 GTM_TIM2_IN2_7 H4 Mux input channel 3 of TIM module 5 Mux input channel 3 of TIM module 2 Mux input channel 2 of TIM module 2 QSPI3_MRSTC Master SPI data input ASCLIN9_ARXA Receive input EVADC_G9CH12 AI Analog input channel 12, group 9 P01.5 O0 General-purpose output GTM_TOUT113 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI3_MRST O4 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 — O5 Reserved — O6 Reserved — O7 Reserved P01.6 I GTM_TIM5_IN6_2 GTM_TIM5_IN5_3 GTM_TIM2_IN5_7 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 5 of TIM module 5 Mux input channel 5 of TIM module 2 QSPI3_MTSRC Slave SPI data input P01.6 O0 General-purpose output GTM_TOUT114 O1 GTM muxed output — O2 Reserved ASCLIN9_ASCLK O3 Shift clock output QSPI3_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 130 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-21 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function J5 P01.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_2 GTM_TIM2_IN7_7 QSPI3_SCLKC Mux input channel 7 of TIM module 5 Mux input channel 7 of TIM module 2 Slave SPI clock inputs ASCLIN9_ARXB Receive input P01.7 O0 General-purpose output GTM_TOUT115 O1 GTM muxed output — O2 Reserved ASCLIN9_ATX O3 Transmit output QSPI3_SCLK O4 Master SPI clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 131 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions Ball Symbol Ctrl. Buffer Type Function B1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 GTM_TIM0_IN0_2 CCU61_CC60INB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D0 sensor pixel data input GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 ASCLIN2_ATX Reference input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 132 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function C2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 GTM_TIM0_IN1_2 ERAY0_RXDA2 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D1 sensor pixel data input P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 QSPI4_SLSO7 O2 Master slave select output QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 133 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function C1 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 GTM_TIM0_IN2_2 CCU61_CC61INB Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 T12 capture input 61 CCU60_CC61INA T12 capture input 61 CIF_D2 sensor pixel data input SENT_SENT14B Receive input channel 14 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 ASCLIN1_ATX Reference input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 134 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D2 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 GTM_TIM0_IN3_2 EDSADC_DSCIN5B Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Modulator clock input, channel 5 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input MSC1_SDI1 Upstream assynchronous input signal PSI5_RX0B RXD inputs (receive data) channel 0 CIF_D3 sensor pixel data input SENT_SENT13B Receive input channel 13 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved — O6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 135 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D1 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 GTM_TIM0_IN4_1 CCU61_CC62INB Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 T12 capture input 62 EDSADC_DSDIN5B Digital datastream input, channel 5 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input CIF_D4 sensor pixel data input SENT_SENT12B Receive input channel 12 P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 136 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E2 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 GTM_TIM0_IN5_1 EDSADC_DSCIN4B Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Modulator clock input, channel 4 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input CIF_D5 sensor pixel data input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 EDSADC_DSCOUT4 O4 Modulator clock output I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 137 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E1 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_10 GTM_TIM1_IN6_1 GTM_TIM0_IN6_1 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 EDSADC_DSDIN4B Digital datastream input, channel 4 EDSADC_ITR5E Trigger/Gate input, channel 5 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input CIF_D6 sensor pixel data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 138 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F2 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_10 GTM_TIM1_IN7_1 GTM_TIM0_IN7_1 Mux input channel 1 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 EDSADC_ITR4E Trigger/Gate input, channel 4 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 CIF_D7 sensor pixel data input QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 — O2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 139 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F1 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_10 GTM_TIM3_IN0_2 GTM_TIM2_IN0_2 Mux input channel 2 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CIF_D8 sensor pixel data input CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output — O4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 140 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E4 P02.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN2_2 GTM_TIM3_IN3_10 GTM_TIM0_IN2_10 Mux input channel 3 of TIM module 3 Mux input channel 2 of TIM module 0 ASCLIN8_ARXA F5 Mux input channel 2 of TIM module 4 Receive input P02.9 O0 General-purpose output GTM_TOUT116 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 ASCLIN8_ATX O3 Transmit output — O4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 — O6 Reserved — O7 Reserved P02.10 I GTM_TIM4_IN3_2 GTM_TIM3_IN4_11 GTM_TIM0_IN3_10 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 3 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 3 of TIM module 0 ASCLIN2_ARXC Receive input CAN01_RXDE CAN receive input node 1 ASCLIN8_ARXB Receive input P02.10 O0 General-purpose output GTM_TOUT117 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 141 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-22 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F4 P02.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_3 GTM_TIM3_IN5_12 GTM_TIM0_IN7_7 Mux input channel 4 of TIM module 4 Mux input channel 5 of TIM module 3 Mux input channel 7 of TIM module 0 EVADC_G9CH15 AI Analog input channel 15, group 9 P02.11 O0 General-purpose output GTM_TOUT118 O1 GTM muxed output — O2 Reserved ASCLIN8_ASLSO O3 Slave select signal output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-23 Port 10 Functions Ball Symbol Ctrl. Buffer Type Function A7 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_12 GTM_TIM1_IN4_2 GTM_TIM0_IN4_2 Mux input channel 0 of TIM module 4 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 142 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-23 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B7 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_12 GTM_TIM1_IN1_3 GTM_TIM0_IN1_3 A5 Mux input channel 4 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 — O6 Reserved — O7 Reserved P10.2 I GTM_TIM4_IN5_12 GTM_TIM1_IN2_3 GTM_TIM0_IN2_3 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMT2_2 CDTM2_DTM0 P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 — O2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select EVADC_FC3BFLOUT O5 Boundary flag output, FC channel 3 — O6 Reserved — O7 Reserved Data Sheet 143 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-23 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A6 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_10 GTM_TIM1_IN3_3 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 B6 Mux input channel 6 of TIM module 4 Monitor input 2 — O2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select — O5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 — O7 P10.4 I GTM_TIM4_IN7_3 GTM_TIM1_IN6_2 GTM_TIM0_IN6_2 Reserved FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 4 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 — O2 Reserved QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select — O6 Reserved — O7 Reserved Data Sheet 144 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-23 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B5 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN3_13 GTM_TIM1_IN2_4 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input CAN20_RXDA CAN receive input node 0 MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 ASCLIN2_ATX A4 Mux input channel 3 of TIM module 4 Reference input 2 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output — O7 Reserved P10.6 I GTM_TIM4_IN2_13 GTM_TIM1_IN3_4 GTM_TIM0_IN3_4 SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 CAN20_TXD O5 CAN transmit output node 0 QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 — Data Sheet O7 Reserved 145 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-23 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A3 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 GTM_TIM0_IN0_3 GPT120_T3EUDB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 — O2 Reserved QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 — O4 Reserved CAN20_TXD O5 CAN transmit output node 0 CAN12_TXD O6 CAN transmit output node 2 — O7 Reserved Data Sheet 146 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-23 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B4 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_13 GTM_TIM1_IN5_2 GTM_TIM0_IN5_2 Mux input channel 0 of TIM module 4 Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 CAN20_RXDB CAN receive input node 0 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-24 Port 11 Functions Ball Symbol Ctrl. Buffer Type Function E10 P11.0 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_4 GTM_TIM2_IN0_7 ASCLIN3_ARXB Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 2 Receive input GTM_DTMA2_1 CDTM2_DTM4 P11.0 O0 General-purpose output GTM_TOUT119 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved — O4 Reserved CAN11_TXD O5 CAN transmit output node 1 GETH_TXD3 O6 Transmit Data — O7 Reserved Data Sheet 147 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E9 P11.1 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_5 GTM_TIM2_IN1_6 A10 Mux input channel 1 of TIM module 4 Mux input channel 1 of TIM module 2 P11.1 O0 GTM_TOUT120 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output General-purpose output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O4 Reserved CAN12_TXD O5 CAN transmit output node 2 GETH_TXD2 O6 Transmit Data — O7 Reserved P11.2 I GTM_TIM3_IN1_3 GTM_TIM2_IN1_3 RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 P11.2 O0 GTM_TOUT95 O1 GTM muxed output — O2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 General-purpose output IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Data Sheet 148 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B10 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN2_2 GTM_TIM2_IN2_2 MSC0_SDI3 Mux input channel 2 of TIM module 2 Upstream assynchronous input signal QSPI1_MRSTB D10 Mux input channel 2 of TIM module 3 Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output — O2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A — O5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 P11.4 I GTM_TIM4_IN2_5 GTM_TIM2_IN2_6 GETH_RXCLKB RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 2 Receive Clock MII P11.4 O0 General-purpose output GTM_TOUT121 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved CAN13_TXD O5 CAN transmit output node 3 GETH_TXER O6 Transmit Error MII GETH_TXCLK O7 Transmit Clock Output for RGMII Data Sheet 149 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D8 P11.5 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN3_5 GTM_TIM2_IN3_8 GETH_TXCLKA GETH_GREFCLK D9 Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 2 Transmit Clock Input for MII Gigabit Reference Clock input for RGMII (125 MHz high precission) P11.5 O0 General-purpose output GTM_TOUT122 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved CAN20_TXD O5 CAN transmit output node 0 — O6 Reserved — O7 Reserved P11.6 I GTM_TIM3_IN3_2 GTM_TIM2_IN3_2 QSPI1_SCLKB RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL CCU60_COUT61 Transmit Control for RGMII O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 150 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E8 P11.7 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN4_5 GTM_TIM2_IN4_7 GETH_RXD3A CAN11_RXDD E7 Mux input channel 4 of TIM module 4 Mux input channel 4 of TIM module 2 Receive Data 3 MII and RGMII (RGMII can use RXD3A only) CAN receive input node 1 P11.7 O0 General-purpose output GTM_TOUT123 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P11.8 I GTM_TIM4_IN5_5 GTM_TIM2_IN5_8 GETH_RXD2A CAN12_RXDD SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 5 of TIM module 2 Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 151 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A9 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN4_2 GTM_TIM2_IN4_2 QSPI1_MTSRB Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output — O2 Reserved QSPI1_MTSR O3 Master SPI data output — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 152 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B9 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN5_2 GTM_TIM2_IN5_2 GTM_TIM2_IN0_9 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output — O2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output — O5 Reserved — O6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 153 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A8 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN6_2 GTM_TIM3_IN0_14 GTM_TIM2_IN6_2 B8 Mux input channel 6 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output — O2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P11.12 I GTM_TIM3_IN7_2 GTM_TIM2_IN7_2 GETH_REFCLKA FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 154 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E6 P11.13 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN6_5 GTM_TIM2_IN6_7 GETH_RXERA Mux input channel 6 of TIM module 2 Receive Error MII CAN13_RXDD D7 Mux input channel 6 of TIM module 4 CAN receive input node 3 P11.13 O0 General-purpose output GTM_TOUT125 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P11.14 I GTM_TIM4_IN7_4 GTM_TIM2_IN7_8 GETH_CRSDVB SLOW / PU1 / VFLEX / ES General-purpose input Mux input channel 7 of TIM module 4 Mux input channel 7 of TIM module 2 Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVB Receive Data Valid MII GETH_CRSA Carrier Sense MII CAN20_RXDF CAN receive input node 0 P11.14 O0 General-purpose output GTM_TOUT126 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 155 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-24 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D6 P11.15 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN7_5 GTM_TIM0_IN7_8 GETH_COLA Mux input channel 7 of TIM module 4 Mux input channel 7 of TIM module 0 Collision MII P11.15 O0 General-purpose output GTM_TOUT127 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-25 Port 12 Functions Ball Symbol Ctrl. Buffer Type Function E12 P12.0 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_5 GTM_TIM3_IN0_7 CAN00_RXDC Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 3 CAN receive input node 0 GETH_RXCLKC Receive Clock MII GTM_DTMA4_0 CDTM4_DTM4 P12.0 O0 General-purpose output GTM_TOUT128 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH_MDC O6 MDIO clock — O7 Reserved Data Sheet 156 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-25 Port 12 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E11 P12.1 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_6 GTM_TIM3_IN1_6 GETH_MDIOC Mux input channel 1 of TIM module 4 Mux input channel 1 of TIM module 3 MDIO Input P12.1 O0 General-purpose output GTM_TOUT129 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved — O7 Reserved GETH_MDIO O MDIO Output Table 2-26 Port 13 Functions Ball Symbol Ctrl. Buffer Type Function B12 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN5_3 GTM_TIM2_IN5_3 ASCLIN10_ARXC Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved CAN10_TXD O7 CAN transmit output node 0 Data Sheet 157 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-26 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A12 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN6_3 GTM_TIM2_IN6_3 I2C0_SCLB B11 Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output — O2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) — O4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output — O7 Reserved P13.2 I GTM_TIM3_IN7_3 GTM_TIM2_IN7_3 GPT120_CAPINA I2C0_SDAB LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Trigger input to capture value of timer T5 into CAPREL register Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output — O7 Reserved Data Sheet 158 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-26 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A11 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN0_3 GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 P13.3 O0 GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved General-purpose output Table 2-27 Port 14 Functions Ball Symbol Ctrl. Buffer Type Function B16 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 P14.0 O0 GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output General-purpose output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 159 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-27 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A15 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 GTM_TIM0_IN4_3 ERAY0_RXDA3 E13 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 P14.2 I GTM_TIM1_IN5_3 GTM_TIM0_IN5_3 PMS_HWCFG2IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output — O4 Reserved — O5 Reserved ASCLIN2_ASCLK O6 Shift clock output — O7 Reserved Data Sheet 160 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-27 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function B14 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 GTM_TIM0_IN6_3 PMS_HWCFG3IN B15 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output — O6 Reserved — O7 Reserved P14.4 I GTM_TIM1_IN7_2 GTM_TIM0_IN7_2 PMS_HWCFG6IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH_PPS O6 Pulse Per Second — O7 Reserved Data Sheet 161 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-27 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A14 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 GTM_TIM0_IN0_4 PMS_HWCFG1IN Mux input channel 0 of TIM module 0 HWCFG1 pin input GTM_DTMA2_0 B13 Mux input channel 0 of TIM module 1 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved ERAY0_TXDB O6 Transmit Channel B — O7 Reserved P14.6 I GTM_TIM1_IN1_4 GTM_TIM0_IN1_4 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 P14.6 O0 GTM_TOUT86 O1 GTM muxed output — O2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 — O5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B — O7 Reserved Data Sheet General-purpose output 162 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-27 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D13 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_10 GTM_TIM1_IN0_5 GTM_TIM0_IN0_5 A13 Mux input channel 7 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output — O5 Reserved — O6 Reserved — O7 Reserved P14.8 I GTM_TIM3_IN2_3 GTM_TIM2_IN2_3 ERAY0_RXDA0 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 163 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-27 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D12 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_3 GTM_TIM2_IN3_3 ASCLIN0_ACTSA D11 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output CAN23_TXD O2 CAN transmit output node 3 MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A — O7 Reserved P14.10 I GTM_TIM3_IN4_3 GTM_TIM2_IN4_3 CAN23_RXDA QSPI2_MRSTFP LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 3 Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output — O2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A — O7 Reserved Data Sheet 164 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-28 Port 15 Functions Ball Symbol Ctrl. Buffer Type Function B20 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_4 GTM_TIM2_IN3_4 SDMMC0_DAT7_IN A18 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 read data in P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output — O4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output — O7 Reserved SDMMC0_DAT7 O write data out P15.1 I GTM_TIM3_IN4_4 GTM_TIM2_IN4_4 CAN02_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved SDMMC0_CLK O7 card clock Data Sheet 165 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-28 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function C19 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_4 GTM_TIM2_IN5_4 QSPI2_SLSIA B17 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Slave select input SENT_SENT10D Receive input channel 10 QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output — O4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output — O7 Reserved P15.3 I GTM_TIM3_IN6_4 GTM_TIM2_IN6_4 CAN01_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs SDMMC0_CMD_IN command in P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output — O4 Reserved MSC0_EN1 O5 Chip Select — O6 Reserved — O7 Reserved SDMMC0_CMD O command out Data Sheet 166 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-28 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function A17 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_4 GTM_TIM2_IN7_4 I2C0_SCLC Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT11D Receive input channel 11 P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 167 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-28 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E14 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_4 GTM_TIM2_IN0_4 ASCLIN1_ARXB A16 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P15.6 I GTM_TIM2_IN2_14 GTM_TIM1_IN0_6 GTM_TIM0_IN0_6 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 2 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 168 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-28 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D15 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 GTM_TIM0_IN1_5 ASCLIN3_ARXA Mux input channel 1 of TIM module 0 Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST D14 Mux input channel 1 of TIM module 1 O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 P15.8 I GTM_TIM1_IN2_5 GTM_TIM0_IN2_5 QSPI2_SCLKB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output — O2 Reserved QSPI2_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 169 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-29 Port 20 Functions Ball Symbol Ctrl. Buffer Type Function H20 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 GTM_TIM1_IN4_9 GTM_TIM0_IN6_7 G19 Mux input channel 6 of TIM module 1 Mux input channel 4 of TIM module 1 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CAN21_RXDC CAN receive input node 1 CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output — O6 Reserved — O7 Reserved CBS_TGO0 O Trigger output P20.1 I GTM_TIM4_IN4_11 GTM_TIM3_IN3_5 GTM_TIM2_IN3_5 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 4 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved CBS_TGO1 O Trigger output Data Sheet 170 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-29 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H19 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE G20 P20.3 Testmode Enable Input I GTM_TIM4_IN5_11 GTM_TIM3_IN4_5 GTM_TIM2_IN4_5 F17 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P20.6 I GTM_TIM3_IN6_5 GTM_TIM2_IN6_5 CAN12_RXDA SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 171 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-29 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function F19 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_5 GTM_TIM2_IN7_5 GTM_TIM1_IN5_8 F20 Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input SDMMC0_DAT0_IN read data in P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output — O3 Reserved — O4 Reserved CAN12_TXD O5 CAN transmit output node 2 — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 SDMMC0_DAT0 O P20.8 I GTM_TIM1_IN7_3 GTM_TIM0_IN7_3 SDMMC0_DAT1_IN write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 read data in P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 SDMMC0_DAT1 Data Sheet O write data out 172 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-29 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E17 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_5 GTM_TIM2_IN5_5 CAN03_RXDE E19 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output — O2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output — O5 Reserved — O6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 P20.10 I GTM_TIM3_IN6_6 GTM_TIM2_IN6_6 SDMMC0_DAT2_IN FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 read data in P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 SDMMC0_DAT2 Data Sheet O write data out 173 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-29 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function E20 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_6 GTM_TIM2_IN7_6 QSPI0_SCLKA Mux input channel 7 of TIM module 2 Slave SPI clock inputs SDMMC0_DAT3_IN D19 Mux input channel 7 of TIM module 3 read data in P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output — O2 Reserved QSPI0_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 SDMMC0_DAT3 O P20.12 I GTM_TIM3_IN0_5 GTM_TIM2_IN0_5 QSPI0_MRSTA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Master SPI data input SDMMC0_DAT4_IN read data in IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 — O2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SDMMC0_DAT4 Data Sheet O write data out 174 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-29 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function D20 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_4 GTM_TIM2_IN1_4 QSPI0_SLSIA Mux input channel 1 of TIM module 2 Slave select input SDMMC0_DAT5_IN read data in IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 C20 Mux input channel 1 of TIM module 3 Monitor input 0 — O2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SDMMC0_DAT5 O P20.14 I GTM_TIM3_IN2_4 GTM_TIM2_IN2_4 QSPI0_MTSRA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Slave SPI data input SDMMC0_DAT6_IN read data in IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 — O2 Reserved QSPI0_MTSR O3 Master SPI data output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved SDMMC0_DAT6 O write data out Data Sheet 175 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-30 Port 21 Functions Ball Symbol Ctrl. Buffer Type Function K17 P21.0 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_11 GTM_TIM3_IN4_6 GTM_TIM2_IN4_6 J17 Mux input channel 0 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 QSPI4_MRSTDN Master SPI data input (LVDS N line) ASCLIN11_ARXC Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved GETH1_PPS O6 Pulse Per Second — O7 Reserved HSM_HSM1 O Pin Output Value P21.1 I GTM_TIM4_IN1_13 GTM_TIM3_IN5_6 GTM_TIM2_IN5_6 LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 4 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 QSPI4_MRSTDP Master SPI data input (LVDS P line) ASCLIN11_ARXD Receive input GTM_DTMA4_1 CDTM4_DTM4 P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSM_HSM2 O Pin Output Value Data Sheet 176 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-30 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K19 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_11 GTM_TIM1_IN0_7 GTM_TIM0_IN0_7 J19 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data QSPI4_MRSTCN Master SPI data input (LVDS N line) ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved GETH_MDC O5 MDIO clock — O6 Reserved — O7 Reserved P21.3 I GTM_TIM5_IN5_12 GTM_TIM1_IN1_6 GTM_TIM0_IN1_6 LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data QSPI4_MRSTCP Master SPI data input (LVDS P line) P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved GETH_MDIO O MDIO Output Data Sheet 177 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-30 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function K20 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN6_12 GTM_TIM1_IN2_6 GTM_TIM0_IN2_6 J20 Mux input channel 6 of TIM module 5 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDN O Tx data P21.5 I GTM_TIM5_IN7_11 GTM_TIM1_IN3_6 GTM_TIM0_IN3_6 ASCLIN11_ARXF LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 7 of TIM module 5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDP O Tx data Data Sheet 178 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-30 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H17 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O. GTM_TIM4_IN2_12 Mux input channel 2 of TIM module 4 GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O DAPE1 I/O DAPE: DAPE1 Data I/O Data Sheet 179 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-30 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function H16 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O. GTM_TIM4_IN3_12 GTM_TIM1_IN5_7 Mux input channel 3 of TIM module 4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O DAPE2 I/O DAPE: DAPE2 Data I/O TDO O JTAG Module Data Output Data Sheet 180 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-31 Port 22 Functions Ball Symbol Ctrl. Buffer Type Function L16 P22.0 I LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input GTM_TIM1_IN1_7 GTM_TIM0_IN1_7 QSPI4_MTSRB L17 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Slave SPI data input ASCLIN6_ARXE Receive input GETH1_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH1_RXDVB Receive Data Valid MII GETH1_CRSA Carrier Sense MII P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATXN O2 Differential Transmit output (low active) QSPI4_MTSR O3 Master SPI data output QSPI4_SCLKN O4 Master SPI clock output (LVDS N line) MSC1_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved ASCLIN6_ATX O7 Transmit output P22.1 I GTM_TIM1_IN0_8 GTM_TIM0_IN0_8 QSPI4_MRSTB LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Master SPI data input ASCLIN7_ARXE Receive input GETH1_RXERA Receive Error MII P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATXP O2 Differential Transmit output (high active) QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI4_SCLKP O4 Master SPI clock output (LVDS P line) MSC1_FCLP O5 Shift-clock direct part of the differential signal — O6 Reserved ASCLIN7_ATX O7 Transmit output Data Sheet 181 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-31 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function R20 P22.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 GTM_TIM0_IN3_7 QSPI4_SLSIB GETH1_COLA R19 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Slave select input Collision MII P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI4_SLSO3 O3 Master slave select output QSPI4_MTSRN O4 Master SPI data output (LVDS N line) MSC1_SON O5 Data output - inverted part of the differential signal — O6 Reserved — O7 Reserved P22.3 I GTM_TIM1_IN4_4 GTM_TIM0_IN4_4 QSPI4_SCLKB ASCLIN5_ARXC LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Slave SPI clock inputs Receive input P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output — O2 Reserved QSPI4_SCLK O3 Master SPI clock output QSPI4_MTSRP O4 Master SPI data output (LVDS P line) MSC1_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Data Sheet 182 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-31 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function P16 P22.4 I SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM3_IN0_8 ASCLIN7_ARXF GETH1_RXD0A GTM_DTMA3_0 P17 Mux input channel 0 of TIM module 3 Receive input Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) CDTM3_DTM4 P22.4 O0 General-purpose output GTM_TOUT130 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved QSPI0_SLSO12 O4 Master slave select output — O5 Reserved CAN13_TXD O6 CAN transmit output node 3 — O7 Reserved P22.5 I GTM_TIM3_IN1_7 QSPI0_MTSRC CAN13_RXDC SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input Mux input channel 1 of TIM module 3 Slave SPI data input CAN receive input node 3 GETH1_REFCLKA Reference Clock input for RMII (50 MHz) GETH1_TXCLKB Transmit Clock Input for MII GETH1_RXCLKA Receive Clock MII P22.5 O0 General-purpose output GTM_TOUT131 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output — O3 Reserved QSPI0_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 183 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-31 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function N16 P22.6 I SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM3_IN2_6 GTM_TIM2_IN6_14 QSPI0_MRSTC N17 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 2 Master SPI data input ASCLIN4_ARXC Receive input GETH1_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH1_RXDVA Receive Data Valid MII GETH1_CRSB Carrier Sense MII GETH1_RCTLA Receive Control for RGMII P22.6 O0 General-purpose output GTM_TOUT132 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 CAN21_TXD O5 CAN transmit output node 1 — O6 Reserved — O7 Reserved P22.7 I GTM_TIM3_IN3_7 QSPI0_SCLKC CAN21_RXDF SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input Mux input channel 3 of TIM module 3 Slave SPI clock inputs CAN receive input node 1 GETH1_TXCLKA Transmit Clock Input for MII GETH1_GREFCLK Gigabit Reference Clock input for RGMII (125 MHz high precission) P22.7 O0 General-purpose output GTM_TOUT133 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved QSPI0_SCLK O4 Master SPI clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 184 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-31 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type M16 P22.8 I General-purpose input SLOW / PU1 / Mux input channel 0 of TIM module 5 VFLEX2 / Mux input channel 4 of TIM module 3 ES Slave SPI clock inputs GTM_TIM5_IN0_4 GTM_TIM3_IN4_7 QSPI0_SCLKB GETH1_RXCLKC M17 Function Receive Clock MII P22.8 O0 General-purpose output GTM_TOUT134 O1 GTM muxed output ASCLIN5_ASCLK O2 Shift clock output — O3 Reserved QSPI0_SCLK O4 Master SPI clock output CAN22_TXD O5 CAN transmit output node 2 GETH1_MDC O6 MDIO clock — O7 Reserved P22.9 I GTM_TIM5_IN1_10 GTM_TIM3_IN5_7 QSPI0_MRSTB General-purpose input SLOW / PU1 / Mux input channel 1 of TIM module 5 VFLEX2 / Mux input channel 5 of TIM module 3 ES Master SPI data input ASCLIN4_ARXD Receive input CAN22_RXDE CAN receive input node 2 GETH1_MDIOC MDIO Input GTM_DTMA3_1 CDTM3_DTM4 P22.9 O0 General-purpose output GTM_TOUT135 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 — O5 Reserved — O6 Reserved — O7 Reserved GETH1_MDIO O MDIO Output Data Sheet 185 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-31 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type P20 P22.10 I RFAST / General-purpose input PU1 / Mux input channel 2 of TIM module 5 VFLEX2 / Mux input channel 6 of TIM module 3 ES Slave SPI data input GTM_TIM5_IN2_8 GTM_TIM3_IN6_7 QSPI0_MTSRB P19 P22.10 O0 General-purpose output GTM_TOUT136 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output — O3 Reserved QSPI0_MTSR O4 Master SPI data output CAN23_TXD O5 CAN transmit output node 3 GETH1_TXD0 O6 Transmit Data — O7 Reserved P22.11 I GTM_TIM5_IN3_10 GTM_TIM3_IN7_7 CAN23_RXDE RFAST / General-purpose input PU1 / Mux input channel 3 of TIM module 5 VFLEX2 / Mux input channel 7 of TIM module 3 ES CAN receive input node 3 P22.11 O0 General-purpose output GTM_TOUT137 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved QSPI0_SLSO10 O4 Master slave select output — O5 Reserved GETH1_TXEN O6 Transmit Enable MII and RMII GETH1_TCTL T19 Function Transmit Control for RGMII — O7 P22.12 I GETH1_RXCLKB Reserved RFAST / General-purpose input PU1 / Receive Clock MII VFLEX2 / General-purpose output ES Reserved P22.12 O0 — O1 — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH1_TXER O6 Transmit Error MII GETH1_TXCLK O7 Transmit Clock Output for RGMII Data Sheet 186 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-32 Port 23 Functions Ball Symbol Ctrl. Buffer Type Function U19 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 GTM_TIM0_IN6_4 MSC1_SDI0 Mux input channel 6 of TIM module 0 Upstream assynchronous input signal ASCLIN6_ARXF V20 Mux input channel 6 of TIM module 1 Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI4_SLSO6 O3 Master slave select output GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output P23.2 I GTM_TIM1_IN6_5 GTM_TIM0_IN6_5 ASCLIN7_ARXC RFAST / General-purpose input PU1 / Mux input channel 6 of TIM module 1 VFLEX2 / Mux input channel 6 of TIM module 0 ES Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output — O2 Reserved — O3 Reserved CAN23_TXD O4 CAN transmit output node 3 CAN12_TXD O5 CAN transmit output node 2 GETH1_TXD3 O6 Transmit Data — O7 Reserved Data Sheet 187 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-32 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type U20 P23.3 I RFAST / General-purpose input PU1 / Mux input channel 7 of TIM module 1 VFLEX2 / Mux input channel 7 of TIM module 0 ES Injection signal from port GTM_TIM1_IN7_4 GTM_TIM0_IN7_4 MSC1_INJ0 T20 Function ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 CAN23_RXDB CAN receive input node 3 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved GETH1_TXD2 O6 Transmit Data — O7 Reserved P23.4 I GTM_TIM1_IN7_5 GTM_TIM0_IN7_5 RFAST / General-purpose input PU1 / Mux input channel 7 of TIM module 1 VFLEX2 / Mux input channel 7 of TIM module 0 ES General-purpose output P23.4 O0 GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output QSPI4_SLSO5 O3 Master slave select output — O4 Reserved MSC1_EN0 O5 Chip Select GETH1_TXD1 O6 Transmit Data — O7 Reserved Data Sheet 188 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-32 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function T17 P23.5 I FAST / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM1_IN2_7 GTM_TIM0_IN2_7 GETH1_RXD3A R17 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Receive Data 3 MII and RGMII (RGMII can use RXD3A only) P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output QSPI4_SLSO4 O3 Master slave select output — O4 Reserved MSC1_EN1 O5 Chip Select CAN22_TXD O6 CAN transmit output node 2 — O7 Reserved P23.6 I GTM_TIM4_IN2_7 GTM_TIM1_IN2_10 CAN22_RXDC GETH1_RXD2A SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 1 CAN receive input node 2 Receive Data 2 MII and RGMII (RGMII can use RXD2A only) P23.6 O0 General-purpose output GTM_TOUT138 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI0_SLSO11 O4 Master slave select output CAN11_TXD O5 CAN transmit output node 1 — O6 Reserved — O7 Reserved Data Sheet 189 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-32 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function R16 P23.7 I SLOW / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM4_IN3_7 GTM_TIM1_IN3_10 CAN11_RXDC GETH1_RXD1A Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 1 CAN receive input node 1 Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P23.7 O0 General-purpose output GTM_TOUT139 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-33 Port 32 Functions Ball Symbol Ctrl. Buffer Type Function Y17 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM3_IN2_5 GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 190 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-33 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W17 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC GTM_TIM3_IN3_15 Y18 Mux input channel 3 of TIM module 3 P32.1 O0 GTM_TOUT37 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P32.2 I GTM_TIM1_IN3_8 GTM_TIM0_IN3_8 CAN03_RXDB SLOW / PU1 / VEXT / ES General-purpose output General-purpose input Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 3 ASCLIN3_ARXD Receive input CAN21_RXDD CAN receive input node 1 P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output — O7 Reserved Data Sheet 191 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-33 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y19 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 GTM_TIM0_IN4_5 W18 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 P32.3 O0 GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output General-purpose output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P32.4 I GTM_TIM1_IN5_5 GTM_TIM0_IN5_5 ASCLIN1_ACTSB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Clear to send input MSC1_SDI2 Upstream assynchronous input signal P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output — O2 Reserved — O3 Reserved GTM_CLK1 O4 CGM generated clock MSC1_EN0 O5 Chip Select CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO Data Sheet O DC-DC synchronization output 192 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-33 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function T15 P32.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_9 GTM_TIM4_IN1_14 GTM_TIM3_IN5_8 Mux input channel 1 of TIM module 4 Mux input channel 5 of TIM module 3 SENT_SENT10C U15 Mux input channel 5 of TIM module 5 Receive input channel 10 P32.5 O0 General-purpose output GTM_TOUT140 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 — O7 P32.6 I GTM_TIM5_IN6_9 GTM_TIM4_IN4_15 GTM_TIM3_IN6_8 Reserved SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 4 of TIM module 4 Mux input channel 6 of TIM module 3 CAN02_RXDC CAN receive input node 2 CBS_TGI4 Trigger input ASCLIN2_ARXF Receive input ASCLIN6_ARXC Receive input SENT_SENT11C Receive input channel 11 P32.6 O0 General-purpose output GTM_TOUT141 O1 GTM muxed output — O2 Reserved — O3 Reserved QSPI2_SLSO12 O4 Master slave select output CAN22_TXD O5 CAN transmit output node 2 — O6 Reserved — O7 Reserved CBS_TGO4 O Trigger output Data Sheet 193 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-33 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function U16 P32.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_8 GTM_TIM4_IN0_15 GTM_TIM3_IN7_8 Mux input channel 7 of TIM module 5 Mux input channel 0 of TIM module 4 Mux input channel 7 of TIM module 3 CBS_TGI5 Trigger input CAN22_RXDB CAN receive input node 2 SENT_SENT12C Receive input channel 12 P32.7 O0 General-purpose output GTM_TOUT142 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved CBS_TGO5 O Trigger output Data Sheet 194 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions Ball Symbol Ctrl. Buffer Type Function W10 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_13 GTM_TIM1_IN4_6 GTM_TIM0_IN4_6 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 SENT_SENT13C Receive input channel 13 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 EVADC_G10CH7 AI Analog input channel 7, group 10 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 — O7 Reserved Data Sheet 195 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y10 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_15 GTM_TIM1_IN5_6 GTM_TIM0_IN5_6 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC EVADC_G10CH6 AI Analog input channel 6, group 10 P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 — O6 Reserved — O7 Reserved Data Sheet 196 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W11 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN2_14 GTM_TIM1_IN6_6 GTM_TIM0_IN6_6 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC EVADC_G10CH5 AI Analog input channel 5, group 10 P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 197 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y11 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN3_12 GTM_TIM1_IN7_6 GTM_TIM0_IN7_6 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC EVADC_G10CH4 AI Analog input channel 4, group 10 P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output QSPI4_SLSO2 O3 Master slave select output EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved — O7 Reserved Data Sheet 198 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W12 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_10 GTM_TIM1_IN0_10 GTM_TIM0_IN0_10 Mux input channel 4 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC GTM_DTMT2_0 CDTM2_DTM0 EVADC_G10CH3 AI Analog input channel 3, group 10 P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Data Sheet 199 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y12 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN5_10 GTM_TIM1_IN1_8 GTM_TIM0_IN1_8 Mux input channel 5 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC EVADC_G10CH2 AI Analog input channel 2, group 10 P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 ASCLIN5_ASLSO O7 Slave select signal output Data Sheet 200 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W13 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 GTM_TIM0_IN2_9 EDSADC_ITR2F Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC GTM_DTMT2_1 CDTM2_DTM0 EVADC_G10CH1 AI Analog input channel 1, group 10 P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Data Sheet 201 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y13 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 GTM_TIM0_IN3_9 CAN00_RXDE Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT14C Receive input channel 14 IOM_PIN_7 GPIO pad input to FPC EVADC_G10CH0 AI Analog input channel 0, group 10 P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output QSPI4_SLSO7 O3 Master slave select output ASCLIN8_ATX O4 Transmit output — O5 Reserved EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 202 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W14 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO2 O3 Master slave select output — O4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 Data Sheet O FSP[1..0] Output Signals - Generated by SMU_core 203 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y14 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 GTM_TIM0_IN1_9 IOM_PIN_9 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO1 O3 Master slave select output ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 204 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W15 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 GTM_TIM1_IN0_9 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Y15 Mux input channel 4 of TIM module 4 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O P33.11 I GTM_TIM1_IN2_8 GTM_TIM0_IN2_8 QSPI4_SCLKA FSP[1..0] Output Signals - Generated by SMU_core FAST / PU1 / VEVRSB / ES5 General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 205 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function W16 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_6 GTM_TIM2_IN0_6 QSPI4_MTSRA Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Slave SPI data input CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 ASCLIN1_ATX Monitor input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MTSR O3 Master SPI data output ASCLIN1_ASCLK O4 Shift clock output CAN22_TXD O5 CAN transmit output node 2 EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 206 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function Y16 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_5 GTM_TIM2_IN1_5 ASCLIN1_ARXF Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 Receive input EDSADC_SGNB Carrier sign signal input QSPI4_MRSTA Master SPI data input MSC1_INJ1 Injection signal from port CAN22_RXDA CAN receive input node 2 P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 207 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-34 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function T14 P33.14 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN0_8 GTM_TIM4_IN5_14 GTM_TIM2_IN0_8 U14 Mux input channel 0 of TIM module 5 Mux input channel 5 of TIM module 4 Mux input channel 0 of TIM module 2 QSPI2_SCLKD Slave SPI clock inputs CBS_TGI6 Trigger input P33.14 O0 General-purpose output GTM_TOUT143 O1 GTM muxed output — O2 Reserved QSPI2_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 CBS_TGO6 O P33.15 I GTM_TIM5_IN1_9 GTM_TIM4_IN6_12 GTM_TIM2_IN1_7 Trigger output SLOW / PU1 / VEVRSB / ES5 General-purpose input Mux input channel 1 of TIM module 5 Mux input channel 6 of TIM module 4 Mux input channel 1 of TIM module 2 CBS_TGI7 Trigger input P33.15 O0 General-purpose output GTM_TOUT144 O1 GTM muxed output — O2 Reserved QSPI2_SLSO11 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 CBS_TGO7 Data Sheet O Trigger output 208 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-35 Port 34 Functions Ball Symbol Ctrl. Buffer Type Function U11 P34.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN3_9 GTM_TIM3_IN4_12 GTM_TIM2_IN3_9 T12 Mux input channel 3 of TIM module 5 Mux input channel 4 of TIM module 3 Mux input channel 3 of TIM module 2 EVADC_G10CH11 AI Analog input channel 11, group 10 P34.1 O0 General-purpose output GTM_TOUT146 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output — O3 Reserved CAN00_TXD O4 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 CAN20_TXD O5 CAN transmit output node 0 — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 P34.2 I GTM_TIM5_IN4_9 GTM_TIM3_IN5_13 GTM_TIM2_IN4_8 SLOW / PU1 / VEVRSB / ES General-purpose input Mux input channel 4 of TIM module 5 Mux input channel 5 of TIM module 3 Mux input channel 4 of TIM module 2 ASCLIN4_ARXB Receive input CAN00_RXDG CAN receive input node 0 CAN20_RXDC CAN receive input node 0 EVADC_G10CH10 AI Analog input channel 10, group 10 P34.2 O0 General-purpose output GTM_TOUT147 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 209 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-35 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function U12 P34.3 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN5_10 GTM_TIM3_IN6_13 GTM_TIM2_IN5_9 T13 Mux input channel 5 of TIM module 5 Mux input channel 6 of TIM module 3 Mux input channel 5 of TIM module 2 EVADC_G10CH9 AI Analog input channel 9, group 10 P34.3 O0 General-purpose output GTM_TOUT148 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved QSPI2_SLSO10 O4 Master slave select output — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 P34.4 I GTM_TIM5_IN6_10 GTM_TIM3_IN7_12 GTM_TIM2_IN6_8 SLOW / PU1 / VEVRSB / ES General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 7 of TIM module 3 Mux input channel 6 of TIM module 2 QSPI2_MRSTD Master SPI data input EVADC_G10CH8 AI Analog input channel 8, group 10 P34.4 O0 General-purpose output GTM_TOUT149 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved QSPI2_MRST O4 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O5 Reserved — O6 Reserved CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 210 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-35 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function U13 P34.5 I FAST / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN7_9 GTM_TIM4_IN7_12 GTM_TIM2_IN7_9 Mux input channel 7 of TIM module 5 Mux input channel 7 of TIM module 4 Mux input channel 7 of TIM module 2 QSPI2_MTSRD Slave SPI data input ASCLIN8_ARXE Receive input P34.5 O0 General-purpose output GTM_TOUT150 O1 GTM muxed output ASCLIN8_ATX O2 Transmit output — O3 Reserved QSPI2_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-36 Analog Inputs Ball Symbol Ctrl. Buffer Type T10 AN0 I D / HighZ Analog Input 0 / VDDM Analog input channel 0, group 0 EVADC_G0CH0 EDSADC_EDS3PA U10 AN1 Positive analog input channel 3, pin A I EVADC_G0CH1 EDSADC_EDS3NA W9 AN2 I EDSADC_EDS0PA AN3 I EDSADC_EDS0NA AN4 I EVADC_G0CH4 AN5 EVADC_G11CH1 EVADC_G0CH5 Data Sheet D / HighZ Analog Input 3 / VDDM Analog input channel 3, group 0 Negative analog input channel 0, pin A EVADC_G11CH0 Y9 D / HighZ Analog Input 2 / VDDM Analog input channel 2, group 0 Positive analog input channel 0, pin A EVADC_G0CH3 T9 D / HighZ Analog Input 1 / VDDM Analog input channel 1, group 0 Negative analog input channel 3, pin A EVADC_G0CH2 U9 Function D / HighZ Analog Input 4 / VDDM Analog input channel 0, group 11 Analog input channel 4, group 0 I D / HighZ Analog Input 5 / VDDM Analog input channel 1, group 11 Analog input channel 5, group 0 211 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-36 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type T8 AN6 I D / HighZ Analog Input 6 / VDDM Analog input channel 2, group 11 EVADC_G11CH2 EVADC_G0CH6 U8 AN7 Analog input channel 6, group 0 I EVADC_G11CH3 EVADC_G0CH7 W8 AN8 I EVADC_G1CH0 AN9 I EVADC_G1CH1 AN10 I EVADC_G1CH2 AN11 I EVADC_G1CH3 AN12 I EDSADC_EDS0PB AN13 I EDSADC_EDS0NB AN14 I EDSADC_EDS3PB AN15 I EDSADC_EDS3NB AN16 I EVADC_FC0CH0 AN17/P40.10 SENT_SENT10A D / HighZ Analog Input 15 / VDDM Analog input channel 7, group 1 Negative analog input channel 3, pin N EVADC_G2CH0 U5 D / HighZ Analog Input 14 / VDDM Analog input channel 6, group 1 Positive analog input channel 3, pin B EVADC_G1CH7 W5 D / HighZ Analog Input 13 / VDDM Analog input channel 5, group 1 Negative analog input channel 0, pin B EVADC_G1CH6 T6 D / HighZ Analog Input 12 / VDDM Analog input channel 4, group 1 Positive analog input channel 0, pin B EVADC_G1CH5 U6 D / HighZ Analog Input 11 / VDDM Analog input channel 7, group 11 Analog input channel 3, group 1 EVADC_G1CH4 W6 D / HighZ Analog Input 10 / VDDM Analog input channel 6, group 11 Analog input channel 2, group 1 EVADC_G11CH7 T7 D / HighZ Analog Input 9 / VDDM Analog input channel 5, group 11 Analog input channel 1, group 1 EVADC_G11CH6 W7 D / HighZ Analog Input 8 / VDDM Analog input channel 4, group 11 Analog input channel 0, group 1 EVADC_G11CH5 Y8 D / HighZ Analog Input 7 / VDDM Analog input channel 3, group 11 Analog input channel 7, group 0 EVADC_G11CH4 U7 Function D / HighZ Analog Input 16 / VDDM Analog input channel 0, group 2 Analog input FC channel 0 I S / HighZ Analog Input 17 / VDDM Receive input channel 10 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 Data Sheet 212 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-36 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type W4 AN18/P40.11 I S / HighZ Analog Input 18 / VDDM Receive input channel 11 SENT_SENT11A W3 EVADC_G11CH8 Analog input channel 8, group 11 EVADC_G2CH2 Analog input channel 2, group 2 AN19/P40.12 I SENT_SENT12A Y3 Analog input channel 9, group 11 EVADC_G2CH3 Analog input channel 3, group 2 AN20 I EDSADC_EDS2PA AN21 I EDSADC_EDS2NA AN22 AN23 I D / HighZ Analog Input 22 / VDDM Analog input channel 6, group 2 I D / HighZ Analog Input 23 / VDDM Analog input channel 7, group 2 I S / HighZ Analog Input 24 / VDDM Receive input channel 0 EVADC_G2CH7 W2 AN24/P40.0 SENT_SENT0A W1 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B AN25/P40.1 I SENT_SENT1A V2 S / HighZ Analog Input 25 / VDDM Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B AN26/P40.2 I SENT_SENT2A V1 D / HighZ Analog Input 21 / VDDM Analog input channel 5, group 2 Negative analog input channel 2, pin A EVADC_G2CH6 R5 D / HighZ Analog Input 20 / VDDM Analog input channel 4, group 2 Positive analog input channel 2, pin A EVADC_G2CH5 T5 S / HighZ Analog Input 19 / VDDM Receive input channel 12 EVADC_G11CH9 EVADC_G2CH4 Y2 Function S / HighZ Analog Input 26 / VDDM Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 EVADC_G11CH10 Analog input channel 10, group 11 AN27/P40.3 SENT_SENT3A I S / HighZ Analog Input 27 / VDDM Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2 EVADC_G11CH11 Analog input channel 11, group 11 Data Sheet 213 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-36 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type U2 AN28/P40.13 I S / HighZ Analog Input 28 / VDDM Receive input channel 13 SENT_SENT13A EVADC_G3CH4 U1 AN29/P40.14 Analog input channel 4, group 3 I SENT_SENT14A EVADC_G3CH5 T4 AN30 AN31 I D / HighZ Analog Input 30 / VDDM Analog input channel 6, group 3 I D / HighZ Analog Input 31 / VDDM Analog input channel 7, group 3 I S / HighZ Analog Input 32 / VDDM Receive input channel 4 EVADC_G3CH7 P4 AN32/P40.4 SENT_SENT4A R1 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 EVADC_G11CH12 Analog input channel 12, group 11 AN33/P40.5 I SENT_SENT5A P5 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 EVADC_G11CH13 Analog input channel 13, group 11 AN34 I EVADC_G11CH14 AN35 I EVADC_G11CH15 AN36/P40.6 D / HighZ Analog Input 35 / VDDM Analog input channel 3, group 8 Analog input channel 15, group 11 I SENT_SENT6A P2 D / HighZ Analog Input 34 / VDDM Analog input channel 2, group 8 Analog input channel 14, group 11 EVADC_G8CH3 N4 S / HighZ Analog Input 33 / VDDM Receive input channel 5 EVADC_G8CH1 EVADC_G8CH2 R2 S / HighZ Analog Input 29 / VDDM Receive input channel 14 Analog input channel 5, group 3 EVADC_G3CH6 R4 Function S / HighZ Analog Input 36 / VDDM Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A AN37/P40.7 SENT_SENT7A I S / HighZ Analog Input 37 / VDDM Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A Data Sheet 214 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-36 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type N5 AN38/P40.8 I S / HighZ Analog Input 38 / VDDM Receive input channel 8 SENT_SENT8A P1 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B AN39/P40.9 I SENT_SENT9A M5 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B AN40 I D / HighZ Analog Input 40 / VDDM Analog input channel 8, group 8 AN41 I D / HighZ Analog Input 41 / VDDM Analog input channel 9, group 8 I D / HighZ Analog Input 42 / VDDM Analog input channel 10, group 8 I D / HighZ Analog Input 43 / VDDM Analog input channel 11, group 8 I D / HighZ Analog Input 44 / VDDM Analog input channel 12, group 8 EVADC_G8CH9 L5 AN42 EVADC_G8CH10 L4 AN43 EVADC_G8CH11 N1 AN44 EVADC_G8CH12 EDSADC_EDS1PC N2 AN45 Positive analog input channel 1, pin C I EVADC_G8CH13 EDSADC_EDS1NC M1 AN46 I EDSADC_EDS1PD AN47 EVADC_G8CH15 EDSADC_EDS1ND Data Sheet D / HighZ Analog Input 45 / VDDM Analog input channel 13, group 8 Negative analog input channel 1, pin C EVADC_G8CH14 M2 S / HighZ Analog Input 39 / VDDM Receive input channel 9 EVADC_G8CH7 EVADC_G8CH8 M4 Function D / HighZ Analog Input 46 / VDDM Analog input channel 14, group 8 Positive analog input channel 1, pin D I D / HighZ Analog Input 47 / VDDM Analog input channel 15, group 8 Negative analog input channel 1, pin D 215 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-37 System I/O Ball Symbol Ctrl. Buffer Type Function L7 AGBTCLKN (VSS) I AGBT_C LK / VEXT Input PAD (negative pole) for the external 100 MHz differential clock. AGBT Input; (TC3xx devices without AGBT: VSS) K7 AGBTCLKP (VSS) I AGBT_C LK / VEXT Input PAD (positive pole) for the external 100 MHz differential clock. AGBT Input; (TC3xx devices without AGBT: VSS) P10 AGBTTXN (VSS) O AGBT_T Off-chip driver output PAD of the 2.5Gbps transmitter, X / VEXT negative pole AGBT Output; (TC3xx devices without AGBT: VSS) P11 AGBTTXP (VSS) O AGBT_T Off-chip driver output PAD of the 2.5Gbps transmitter, X / VEXT positive pole AGBT Output; (TC3xx devices without AGBT: VSS) L14 AGBTERR (VSS) I FAST / PD / VEXT Input PAD for CRC error from FPGA. AGBT Input; (TC3xx devices without AGBT: VSS) Y17 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC W17 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC M20 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. M19 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT G10 DAPE2 I/O FAST / PD2 / VEXT DAPE: DAPE2 Data I/O DAPE: DAPE2 Data I/O (TC3xx devices without DAPE: VSS) G11 DAPE1 I/O FAST / PD2 / VEXT DAPE: DAPE1 Data I/O DAPE: DAPE1 Data I/O (TC3xx devices without DAPE: VSS) K16 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input TMS: JTAG Module State Machine Control Input. DAP: DAP1 Data I/O. DAP1 I/O K14 DAPE0 I FAST / PD2 / VEXT DAPE: DAPE0 Clock Input DAPE: DAPE0 clock input (TC3xx devices without DAPE: NC) L19 TRST I FAST / PU2 / VEXT JTAG Module Reset/Enable Input TRST_N: JTAG Module Reset/Enable Input. DAPE: DAPE0 Clock Input DAPE0 I Data Sheet DAP: DAP1 Data I/O DAPE: DAPE0 Clock Input 216 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-37 System I/O (cont’d) Ball Symbol Ctrl. Buffer Type Function J16 TCK I JTAG Module Clock Input TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input. DAP0 I FAST / PD2 / VEXT ESR1 I FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I G17 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. F16 ESR0 I FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I G16 DAP: DAP0 Clock Input ESR1 pin input ESR0 pin input Table 2-38 Supply Ball Ctrl. Buffer Type Function P8, P13, N7, VDD N14, E15, H14, D16, G13 I — Digital Core Power Supply (1.25V) A2, B3, W20 VEXT I — External Power Supply (5V / 3.3V) D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) V19 VFLEX2 I — Digital Power Supply for Flex Port Pads (5V / 3.3V) Y5 VDDM I — ADC Analog Power Supply (5V / 3.3V) B18, A19 VDDP3 I — Flash Power Supply (3.3V) B2, D4, E5, T16, U17, W19, Y20, E16, D17, B19, A20 VSS I — Digital Ground Data Sheet Symbol 217 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LFBGA-292 Package Pinning of Table 2-38 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function Y4 VSSM I — Analog Ground for VDDM P9, P12, N9, VSS N10, N11, N12, M7, M8, M10, M11, M13, M14, L8, L9, L10, L11, L12, L13, K8, K9, K10, K11, K12, K13, J7, J8, J10, J11, J13, J14, H9, H10, H11, H12, G9, G12 I — Digital Ground L20 VSS I — Oscillator Ground, VSS(OSC) Y6 VAREF1 I — Positive Analog Reference Voltage 1 Y7 VAGND1 I — Negative Analog Reference Voltage 1 T1 VAREF2 I — Positive Analog Reference Voltage 2 T2 VAGND2 I — Negative Analog Reference Voltage 2 A1, Y1, U4 NC1 I — Not connected. These pins are not connected on package level and will not be used for future extensions G8, H7 VDDSB (VDD) I — Devices with integrated EMEM: EMEM SRAM Standby Power Supply, VDDSB (1.25V); Devices without integrated EMEM: VDD (1.25V) T11 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM N19 VDD I — Digital Power Supply for Oscillator (1.25V), VDD(OSC) N20 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT), VEXT(OSC) Data Sheet 218 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of P14.8 P14.7 P14.6 P14.5 P14.4 P14.3 P14.2 P14.1 P14.0 P15.8 P15.7 P15.6 P15.5 150 149 148 147 146 145 144 143 142 141 140 139 138 P15.0 P14.9 151 P15.1 P14.10 152 P15.2 VEXT 153 133 VDDP3 154 134 VDD 155 135 P13.0 156 P15.4 P13.1 157 P15.3 P13.2 158 136 P13.3 159 137 P11.3 P11.6 P11.2 P11.9 162 160 VFLEX 163 161 P11.10 164 P10.0 168 165 P10.1 169 P11.12 P10.2 170 P11.11 P10.3 171 166 P10.4 172 167 P10.6 P10.5 173 P10.7 174 P10.8 175 LQFP-176 Package Pinning of TC37xEXT 176 2.3 P02.0 1 132 P20.14 P02.1 2 131 P20.13 P02.2 3 130 P20.12 P02.3 4 129 P20.11 P02.4 5 128 P20.10 P02.5 6 127 P20.9 P02.6 7 126 P20.8 P02.7 8 125 P20.7 P02.8 9 124 P20.6 VDDSB (VDD) 10 123 VDD P00.0 11 122 ESR0 P00.1 12 121 PORST P00.2 13 120 ESR1 P00.3 14 119 P20.3 P00.4 15 118 P20.2 P00.5 16 117 P20.1 P00.6 17 116 P20.0 P00.7 18 115 TCK P00.8 19 114 TRST P00.9 20 113 P21.7 / TDO P00.10 21 112 TMS P00.11 22 111 P21.6 / TDI P00.12 23 110 P21.5 VDD 24 109 P21.4 VEXT 25 108 P21.3 VAREF2 26 107 P21.2 VAGND2 27 106 P21.1 AN47 28 105 P21.0 AN46 29 104 VEXT AN45 30 103 XTAL2 AN44 31 102 XTAL1 AN39 / P40.9 32 101 VSS AN38 / P40.8 33 100 VDD AN37 / P40.7 34 99 VEXT AN36 / P40.6 TC37xed (Top View) 79 80 81 82 83 84 85 86 87 88 P33.10 P33.11 P33.12 P33.13 P32.0 / VGATE1N P32.1 / VGATE1P P32.2 P32.3 P32.4 71 P33.1 P33.9 70 P33.0 78 69 VEVRSB P33.8 68 VDD 77 67 AN0 P33.7 66 AN1 76 65 AN2 P33.6 64 AN3 75 63 P33.5 62 AN5 AN4 74 61 AN6 P33.4 60 AN7 72 59 AN8 73 58 P33.2 57 P33.3 56 P23.0 AN12 89 AN10 44 AN11 P23.1 AN24 / P40.0 55 90 AN13 43 54 P23.2 AN25 / P40.1 VDDM 91 53 42 VSSM P23.3 AN26 / P40.2 52 92 VAREF1 41 51 P23.4 AN27 / P40.3 VAGND1 93 50 40 49 P23.5 AN28 / P40.13 AN16 94 AN17 / P40.10 39 48 P22.0 AN29 / P40.14 AN18 / P40.11 95 47 38 AN19 / P40.12 P22.1 AN32 / P40.4 46 P22.2 96 45 P22.3 97 37 AN20 98 36 AN21 35 AN35 AN33 / P40.5 Figure 2-3 TC37xEXT package variant LQFP-176 Data Sheet 219 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions Pin Symbol Ctrl. Buffer Type Function 11 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_10 GTM_TIM3_IN0_1 GTM_TIM2_IN0_1 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port CIF_D9 sensor pixel data input GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O4 Reserved CAN10_TXD O5 CAN transmit output node 0 — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO Data Sheet O MDIO Output 220 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 12 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_11 GTM_TIM3_IN1_1 GTM_TIM2_IN1_1 Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input EDSADC_DSCIN5A Modulator clock input, channel 5 CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CIF_D10 sensor pixel data input CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI EDSADC_EDS5NA Analog input channel 11, group 9 Negative analog input channel 5, pin A P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 ASCLIN3_ATX Reference input 0 O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 221 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 13 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN6_11 GTM_TIM3_IN1_2 GTM_TIM2_IN1_2 Mux input channel 6 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 EDSADC_DSDIN5A Digital datastream input, channel 5 SENT_SENT1B Receive input channel 1 CIF_D11 sensor pixel data input EVADC_G9CH10 AI EDSADC_EDS5PA Analog input channel 10, group 9 Positive analog input channel 5, pin A P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output CAN21_TXD O3 CAN transmit output node 1 PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 222 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 14 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN7_10 GTM_TIM3_IN2_1 GTM_TIM2_IN2_1 Mux input channel 7 of TIM module 5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 EDSADC_ITR5F Trigger/Gate input, channel 5 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 CAN21_RXDA CAN receive input node 1 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CIF_D12 sensor pixel data input CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI EDSADC_EDS5NB Analog input channel 9, group 9 Negative analog input channel 5, pin B P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output — O5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 223 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 15 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN3_1 GTM_TIM2_IN3_1 SCU_E_REQ2_2 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input CIF_D13 sensor pixel data input EVADC_G9CH8 AI EDSADC_EDS5PB Analog input channel 8, group 9 Positive analog input channel 5, pin B P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 — O5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Data Sheet 224 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 16 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN4_1 GTM_TIM3_IN0_11 GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CIF_D14 sensor pixel data input CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 225 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 17 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN5_1 GTM_TIM3_IN1_14 GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 3 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 2 EDSADC_ITR4F Trigger/Gate input, channel 4 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 CIF_D15 sensor pixel data input ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output — O3 Reserved — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Data Sheet 226 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 18 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN6_1 GTM_TIM3_IN2_11 GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 3 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 EDSADC_DSCIN4A Modulator clock input, channel 4 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 CIF_PCLK Sensor Pixel Clock input GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI EDSADC_EDS4NA Analog input channel 5, group 9 Negative analog input channel 4, pin A P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output EVADC_FC2BFLOUT O3 Boundary flag output, FC channel 2 EDSADC_DSCOUT4 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 227 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 19 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN7_1 GTM_TIM3_IN3_11 GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 3 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 EDSADC_DSDIN4A Digital datastream input, channel 4 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CIF_VSYNC vertical synchronization signal input CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI EDSADC_EDS4PA Analog input channel 4, group 9 Positive analog input channel 4, pin A P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output — O4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 228 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 20 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN0_7 GTM_TIM1_IN0_1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CIF_HSYNC horizontal synchronization signal input CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI EDSADC_EDS4NB Analog input channel 3, group 9 Negative analog input channel 4, pin B P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 229 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 21 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN1_11 GTM_TIM1_IN1_1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 EDSADC_EDS4PB 22 Mux input channel 1 of TIM module 4 Positive analog input channel 4, pin B P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 P00.11 I GTM_TIM4_IN2_11 GTM_TIM1_IN2_1 GTM_TIM0_IN2_1 SLOW / PU1 / VEXT / ES1 General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 SENT_SENT10B Receive input channel 10 EVADC_G9CH1 AI EVADC_FC3CH0 Analog input channel 1, group 9 Analog input FC channel 3 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT0 O4 Modulator clock output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 230 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-39 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 23 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN3_11 GTM_TIM1_IN3_1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input SENT_SENT11B Receive input channel 11 EVADC_G9CH0 AI EVADC_FC2CH0 Analog input channel 0, group 9 Analog input FC channel 2 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Data Sheet 231 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions Pin Symbol Ctrl. Buffer Type Function 1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 GTM_TIM0_IN0_2 CCU61_CC60INB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D0 sensor pixel data input GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 ASCLIN2_ATX Reference input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 232 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 GTM_TIM0_IN1_2 ERAY0_RXDA2 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D1 sensor pixel data input P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 QSPI4_SLSO7 O2 Master slave select output QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 233 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 3 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 GTM_TIM0_IN2_2 CCU61_CC61INB Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 T12 capture input 61 CCU60_CC61INA T12 capture input 61 CIF_D2 sensor pixel data input SENT_SENT14B Receive input channel 14 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 ASCLIN1_ATX Reference input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 234 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 4 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 GTM_TIM0_IN3_2 EDSADC_DSCIN5B Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Modulator clock input, channel 5 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input MSC1_SDI1 Upstream assynchronous input signal PSI5_RX0B RXD inputs (receive data) channel 0 CIF_D3 sensor pixel data input SENT_SENT13B Receive input channel 13 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved — O6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 235 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 5 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 GTM_TIM0_IN4_1 CCU61_CC62INB Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 T12 capture input 62 EDSADC_DSDIN5B Digital datastream input, channel 5 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input CIF_D4 sensor pixel data input SENT_SENT12B Receive input channel 12 P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 236 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 6 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 GTM_TIM0_IN5_1 EDSADC_DSCIN4B Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Modulator clock input, channel 4 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input CIF_D5 sensor pixel data input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 EDSADC_DSCOUT4 O4 Modulator clock output I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 237 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 7 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_10 GTM_TIM1_IN6_1 GTM_TIM0_IN6_1 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 EDSADC_DSDIN4B Digital datastream input, channel 4 EDSADC_ITR5E Trigger/Gate input, channel 5 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input CIF_D6 sensor pixel data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 238 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 8 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_10 GTM_TIM1_IN7_1 GTM_TIM0_IN7_1 Mux input channel 1 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 EDSADC_ITR4E Trigger/Gate input, channel 4 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 CIF_D7 sensor pixel data input QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 — O2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 239 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-40 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 9 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_10 GTM_TIM3_IN0_2 GTM_TIM2_IN0_2 Mux input channel 2 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CIF_D8 sensor pixel data input CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output — O4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 240 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-41 Port 10 Functions Pin Symbol Ctrl. Buffer Type Function 168 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_12 GTM_TIM1_IN4_2 GTM_TIM0_IN4_2 169 Mux input channel 0 of TIM module 4 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P10.1 I GTM_TIM4_IN4_12 GTM_TIM1_IN1_3 GTM_TIM0_IN1_3 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 — O6 Reserved — O7 Reserved Data Sheet 241 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-41 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 170 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_12 GTM_TIM1_IN2_3 GTM_TIM0_IN2_3 Mux input channel 5 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMT2_2 CDTM2_DTM0 P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 — O2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select EVADC_FC3BFLOUT O5 Boundary flag output, FC channel 3 — O6 Reserved — O7 Reserved Data Sheet 242 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-41 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 171 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_10 GTM_TIM1_IN3_3 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 172 Mux input channel 6 of TIM module 4 Monitor input 2 — O2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select — O5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 — O7 P10.4 I GTM_TIM4_IN7_3 GTM_TIM1_IN6_2 GTM_TIM0_IN6_2 Reserved FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 4 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 — O2 Reserved QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select — O6 Reserved — O7 Reserved Data Sheet 243 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-41 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 173 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN3_13 GTM_TIM1_IN2_4 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input CAN20_RXDA CAN receive input node 0 MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 ASCLIN2_ATX 174 Mux input channel 3 of TIM module 4 Reference input 2 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output — O7 Reserved P10.6 I GTM_TIM4_IN2_13 GTM_TIM1_IN3_4 GTM_TIM0_IN3_4 SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 CAN20_TXD O5 CAN transmit output node 0 QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 — Data Sheet O7 Reserved 244 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-41 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 175 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 GTM_TIM0_IN0_3 GPT120_T3EUDB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 — O2 Reserved QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 — O4 Reserved CAN20_TXD O5 CAN transmit output node 0 CAN12_TXD O6 CAN transmit output node 2 — O7 Reserved Data Sheet 245 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-41 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 176 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_13 GTM_TIM1_IN5_2 GTM_TIM0_IN5_2 Mux input channel 0 of TIM module 4 Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 CAN20_RXDB CAN receive input node 0 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Table 2-42 Port 11 Functions Pin Symbol Ctrl. Buffer Type Function 160 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN1_3 GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 P11.2 O0 GTM_TOUT95 O1 GTM muxed output — O2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 General-purpose output IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Data Sheet 246 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-42 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 161 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN2_2 GTM_TIM2_IN2_2 MSC0_SDI3 Mux input channel 2 of TIM module 2 Upstream assynchronous input signal QSPI1_MRSTB 162 Mux input channel 2 of TIM module 3 Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output — O2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A — O5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 P11.6 I GTM_TIM3_IN3_2 GTM_TIM2_IN3_2 QSPI1_SCLKB RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL CCU60_COUT61 Transmit Control for RGMII O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 247 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-42 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 163 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN4_2 GTM_TIM2_IN4_2 QSPI1_MTSRB Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output — O2 Reserved QSPI1_MTSR O3 Master SPI data output — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 248 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-42 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 165 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN5_2 GTM_TIM2_IN5_2 GTM_TIM2_IN0_9 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output — O2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output — O5 Reserved — O6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 249 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-42 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 166 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN6_2 GTM_TIM3_IN0_14 GTM_TIM2_IN6_2 167 Mux input channel 6 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output — O2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P11.12 I GTM_TIM3_IN7_2 GTM_TIM2_IN7_2 GETH_REFCLKA FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 250 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-43 Port 13 Functions Pin Symbol Ctrl. Buffer Type Function 156 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN5_3 GTM_TIM2_IN5_3 ASCLIN10_ARXC 157 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved CAN10_TXD O7 CAN transmit output node 0 P13.1 I GTM_TIM3_IN6_3 GTM_TIM2_IN6_3 I2C0_SCLB LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output — O2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) — O4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output — O7 Reserved Data Sheet 251 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-43 Port 13 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 158 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN7_3 GTM_TIM2_IN7_3 GPT120_CAPINA I2C0_SDAB 159 Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Trigger input to capture value of timer T5 into CAPREL register Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output — O7 Reserved P13.3 I GTM_TIM3_IN0_3 GTM_TIM2_IN0_3 LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 P13.3 O0 GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Data Sheet General-purpose output 252 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-44 Port 14 Functions Pin Symbol Ctrl. Buffer Type Function 142 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 P14.0 O0 GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output General-purpose output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 253 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-44 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 143 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 GTM_TIM0_IN4_3 ERAY0_RXDA3 144 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 P14.2 I GTM_TIM1_IN5_3 GTM_TIM0_IN5_3 PMS_HWCFG2IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output — O4 Reserved — O5 Reserved ASCLIN2_ASCLK O6 Shift clock output — O7 Reserved Data Sheet 254 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-44 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 145 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 GTM_TIM0_IN6_3 PMS_HWCFG3IN 146 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output — O6 Reserved — O7 Reserved P14.4 I GTM_TIM1_IN7_2 GTM_TIM0_IN7_2 PMS_HWCFG6IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH_PPS O6 Pulse Per Second — O7 Reserved Data Sheet 255 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-44 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 147 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 GTM_TIM0_IN0_4 PMS_HWCFG1IN Mux input channel 0 of TIM module 0 HWCFG1 pin input GTM_DTMA2_0 148 Mux input channel 0 of TIM module 1 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved ERAY0_TXDB O6 Transmit Channel B — O7 Reserved P14.6 I GTM_TIM1_IN1_4 GTM_TIM0_IN1_4 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 P14.6 O0 GTM_TOUT86 O1 GTM muxed output — O2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 — O5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B — O7 Reserved Data Sheet General-purpose output 256 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-44 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 149 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_10 GTM_TIM1_IN0_5 GTM_TIM0_IN0_5 150 Mux input channel 7 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output — O5 Reserved — O6 Reserved — O7 Reserved P14.8 I GTM_TIM3_IN2_3 GTM_TIM2_IN2_3 ERAY0_RXDA0 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 257 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-44 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 151 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_3 GTM_TIM2_IN3_3 ASCLIN0_ACTSA 152 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output CAN23_TXD O2 CAN transmit output node 3 MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A — O7 Reserved P14.10 I GTM_TIM3_IN4_3 GTM_TIM2_IN4_3 CAN23_RXDA QSPI2_MRSTFP LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 3 Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output — O2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A — O7 Reserved Data Sheet 258 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-45 Port 15 Functions Pin Symbol Ctrl. Buffer Type Function 133 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_4 GTM_TIM2_IN3_4 SDMMC0_DAT7_IN 134 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 read data in P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output — O4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output — O7 Reserved SDMMC0_DAT7 O write data out P15.1 I GTM_TIM3_IN4_4 GTM_TIM2_IN4_4 CAN02_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved SDMMC0_CLK O7 card clock Data Sheet 259 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-45 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 135 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_4 GTM_TIM2_IN5_4 QSPI2_SLSIA 136 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Slave select input SENT_SENT10D Receive input channel 10 QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output — O4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output — O7 Reserved P15.3 I GTM_TIM3_IN6_4 GTM_TIM2_IN6_4 CAN01_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs SDMMC0_CMD_IN command in P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output — O4 Reserved MSC0_EN1 O5 Chip Select — O6 Reserved — O7 Reserved SDMMC0_CMD O command out Data Sheet 260 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-45 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 137 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_4 GTM_TIM2_IN7_4 I2C0_SCLC Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT11D Receive input channel 11 P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 261 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-45 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 138 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_4 GTM_TIM2_IN0_4 ASCLIN1_ARXB 139 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P15.6 I GTM_TIM2_IN2_14 GTM_TIM1_IN0_6 GTM_TIM0_IN0_6 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 2 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 262 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-45 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 140 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 GTM_TIM0_IN1_5 ASCLIN3_ARXA Mux input channel 1 of TIM module 0 Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST 141 Mux input channel 1 of TIM module 1 O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 P15.8 I GTM_TIM1_IN2_5 GTM_TIM0_IN2_5 QSPI2_SCLKB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output — O2 Reserved QSPI2_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 263 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-46 Port 20 Functions Pin Symbol Ctrl. Buffer Type Function 116 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 GTM_TIM1_IN4_9 GTM_TIM0_IN6_7 117 Mux input channel 6 of TIM module 1 Mux input channel 4 of TIM module 1 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CAN21_RXDC CAN receive input node 1 CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output — O6 Reserved — O7 Reserved CBS_TGO0 O Trigger output P20.1 I GTM_TIM4_IN4_11 GTM_TIM3_IN3_5 GTM_TIM2_IN3_5 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 4 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved CBS_TGO1 O Trigger output Data Sheet 264 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-46 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 118 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE 119 P20.3 Testmode Enable Input I GTM_TIM4_IN5_11 GTM_TIM3_IN4_5 GTM_TIM2_IN4_5 124 SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P20.6 I GTM_TIM3_IN6_5 GTM_TIM2_IN6_5 CAN12_RXDA SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 265 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-46 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 125 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_5 GTM_TIM2_IN7_5 GTM_TIM1_IN5_8 126 Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input SDMMC0_DAT0_IN read data in P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output — O3 Reserved — O4 Reserved CAN12_TXD O5 CAN transmit output node 2 — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 SDMMC0_DAT0 O P20.8 I GTM_TIM1_IN7_3 GTM_TIM0_IN7_3 SDMMC0_DAT1_IN write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 read data in P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 SDMMC0_DAT1 Data Sheet O write data out 266 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-46 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 127 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_5 GTM_TIM2_IN5_5 CAN03_RXDE 128 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output — O2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output — O5 Reserved — O6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 P20.10 I GTM_TIM3_IN6_6 GTM_TIM2_IN6_6 SDMMC0_DAT2_IN FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 read data in P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 SDMMC0_DAT2 Data Sheet O write data out 267 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-46 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 129 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_6 GTM_TIM2_IN7_6 QSPI0_SCLKA Mux input channel 7 of TIM module 2 Slave SPI clock inputs SDMMC0_DAT3_IN 130 Mux input channel 7 of TIM module 3 read data in P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output — O2 Reserved QSPI0_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 SDMMC0_DAT3 O P20.12 I GTM_TIM3_IN0_5 GTM_TIM2_IN0_5 QSPI0_MRSTA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Master SPI data input SDMMC0_DAT4_IN read data in IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 — O2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SDMMC0_DAT4 Data Sheet O write data out 268 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-46 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 131 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_4 GTM_TIM2_IN1_4 QSPI0_SLSIA Mux input channel 1 of TIM module 2 Slave select input SDMMC0_DAT5_IN read data in IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 132 Mux input channel 1 of TIM module 3 Monitor input 0 — O2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SDMMC0_DAT5 O P20.14 I GTM_TIM3_IN2_4 GTM_TIM2_IN2_4 QSPI0_MTSRA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Slave SPI data input SDMMC0_DAT6_IN read data in IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 — O2 Reserved QSPI0_MTSR O3 Master SPI data output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved SDMMC0_DAT6 O write data out Data Sheet 269 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-47 Port 21 Functions Pin Symbol Ctrl. Buffer Type Function 105 P21.0 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_11 GTM_TIM3_IN4_6 GTM_TIM2_IN4_6 106 Mux input channel 0 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 QSPI4_MRSTDN Master SPI data input (LVDS N line) ASCLIN11_ARXC Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved GETH1_PPS O6 Pulse Per Second — O7 Reserved HSM_HSM1 O Pin Output Value P21.1 I GTM_TIM4_IN1_13 GTM_TIM3_IN5_6 GTM_TIM2_IN5_6 LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 4 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 QSPI4_MRSTDP Master SPI data input (LVDS P line) ASCLIN11_ARXD Receive input GTM_DTMA4_1 CDTM4_DTM4 P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSM_HSM2 O Pin Output Value Data Sheet 270 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-47 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 107 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_11 GTM_TIM1_IN0_7 GTM_TIM0_IN0_7 108 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data QSPI4_MRSTCN Master SPI data input (LVDS N line) ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved GETH_MDC O5 MDIO clock — O6 Reserved — O7 Reserved P21.3 I GTM_TIM5_IN5_12 GTM_TIM1_IN1_6 GTM_TIM0_IN1_6 LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data QSPI4_MRSTCP Master SPI data input (LVDS P line) P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved GETH_MDIO O MDIO Output Data Sheet 271 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-47 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 109 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN6_12 GTM_TIM1_IN2_6 GTM_TIM0_IN2_6 110 Mux input channel 6 of TIM module 5 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDN O Tx data P21.5 I GTM_TIM5_IN7_11 GTM_TIM1_IN3_6 GTM_TIM0_IN3_6 ASCLIN11_ARXF LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 7 of TIM module 5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDP O Tx data Data Sheet 272 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-47 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 111 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O. GTM_TIM4_IN2_12 Mux input channel 2 of TIM module 4 GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O DAPE1 I/O DAPE: DAPE1 Data I/O Data Sheet 273 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-47 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 113 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O. GTM_TIM4_IN3_12 GTM_TIM1_IN5_7 Mux input channel 3 of TIM module 4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O DAPE2 I/O DAPE: DAPE2 Data I/O TDO O JTAG Module Data Output Data Sheet 274 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-48 Port 22 Functions Pin Symbol Ctrl. Buffer Type Function 95 P22.0 I LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input GTM_TIM1_IN1_7 GTM_TIM0_IN1_7 QSPI4_MTSRB 96 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Slave SPI data input ASCLIN6_ARXE Receive input GETH1_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH1_RXDVB Receive Data Valid MII GETH1_CRSA Carrier Sense MII P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATXN O2 Differential Transmit output (low active) QSPI4_MTSR O3 Master SPI data output QSPI4_SCLKN O4 Master SPI clock output (LVDS N line) MSC1_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved ASCLIN6_ATX O7 Transmit output P22.1 I GTM_TIM1_IN0_8 GTM_TIM0_IN0_8 QSPI4_MRSTB LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Master SPI data input ASCLIN7_ARXE Receive input GETH1_RXERA Receive Error MII P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATXP O2 Differential Transmit output (high active) QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI4_SCLKP O4 Master SPI clock output (LVDS P line) MSC1_FCLP O5 Shift-clock direct part of the differential signal — O6 Reserved ASCLIN7_ATX O7 Transmit output Data Sheet 275 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-48 Port 22 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 97 P22.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 GTM_TIM0_IN3_7 QSPI4_SLSIB GETH1_COLA 98 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Slave select input Collision MII P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI4_SLSO3 O3 Master slave select output QSPI4_MTSRN O4 Master SPI data output (LVDS N line) MSC1_SON O5 Data output - inverted part of the differential signal — O6 Reserved — O7 Reserved P22.3 I GTM_TIM1_IN4_4 GTM_TIM0_IN4_4 QSPI4_SCLKB ASCLIN5_ARXC LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Slave SPI clock inputs Receive input P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output — O2 Reserved QSPI4_SCLK O3 Master SPI clock output QSPI4_MTSRP O4 Master SPI data output (LVDS P line) MSC1_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Data Sheet 276 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-49 Port 23 Functions Pin Symbol Ctrl. Buffer Type Function 89 P23.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_4 GTM_TIM0_IN5_4 CAN10_RXDC 90 Mux input channel 5 of TIM module 0 CAN receive input node 0 P23.0 O0 General-purpose output GTM_TOUT41 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P23.1 I GTM_TIM1_IN6_4 GTM_TIM0_IN6_4 MSC1_SDI0 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 Upstream assynchronous input signal ASCLIN6_ARXF 91 Mux input channel 5 of TIM module 1 Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI4_SLSO6 O3 Master slave select output GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output P23.2 I GTM_TIM1_IN6_5 GTM_TIM0_IN6_5 ASCLIN7_ARXC RFAST / General-purpose input PU1 / Mux input channel 6 of TIM module 1 VFLEX2 / Mux input channel 6 of TIM module 0 ES Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output — O2 Reserved — O3 Reserved CAN23_TXD O4 CAN transmit output node 3 CAN12_TXD O5 CAN transmit output node 2 GETH1_TXD3 O6 Transmit Data — O7 Reserved Data Sheet 277 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-49 Port 23 Functions (cont’d) Pin Symbol Ctrl. Buffer Type 92 P23.3 I RFAST / General-purpose input PU1 / Mux input channel 7 of TIM module 1 VFLEX2 / Mux input channel 7 of TIM module 0 ES Injection signal from port GTM_TIM1_IN7_4 GTM_TIM0_IN7_4 MSC1_INJ0 93 Function ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 CAN23_RXDB CAN receive input node 3 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved GETH1_TXD2 O6 Transmit Data — O7 Reserved P23.4 I GTM_TIM1_IN7_5 GTM_TIM0_IN7_5 RFAST / General-purpose input PU1 / Mux input channel 7 of TIM module 1 VFLEX2 / Mux input channel 7 of TIM module 0 ES General-purpose output P23.4 O0 GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output QSPI4_SLSO5 O3 Master slave select output — O4 Reserved MSC1_EN0 O5 Chip Select GETH1_TXD1 O6 Transmit Data — O7 Reserved Data Sheet 278 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-49 Port 23 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 94 P23.5 I FAST / RGMII_In put / PU1 / VFLEX2 / ES General-purpose input GTM_TIM1_IN2_7 GTM_TIM0_IN2_7 GETH1_RXD3A Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Receive Data 3 MII and RGMII (RGMII can use RXD3A only) P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output QSPI4_SLSO4 O3 Master slave select output — O4 Reserved MSC1_EN1 O5 Chip Select CAN22_TXD O6 CAN transmit output node 2 — O7 Reserved Table 2-50 Port 32 Functions Pin Symbol Ctrl. Buffer Type Function 84 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM3_IN2_5 GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 279 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-50 Port 32 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 85 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC GTM_TIM3_IN3_15 86 Mux input channel 3 of TIM module 3 P32.1 O0 GTM_TOUT37 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P32.2 I GTM_TIM1_IN3_8 GTM_TIM0_IN3_8 CAN03_RXDB SLOW / PU1 / VEXT / ES General-purpose output General-purpose input Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 3 ASCLIN3_ARXD Receive input CAN21_RXDD CAN receive input node 1 P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output — O7 Reserved Data Sheet 280 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-50 Port 32 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 87 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 GTM_TIM0_IN4_5 88 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 P32.3 O0 GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output General-purpose output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P32.4 I GTM_TIM1_IN5_5 GTM_TIM0_IN5_5 ASCLIN1_ACTSB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Clear to send input MSC1_SDI2 Upstream assynchronous input signal P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output — O2 Reserved — O3 Reserved GTM_CLK1 O4 CGM generated clock MSC1_EN0 O5 Chip Select CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO Data Sheet O DC-DC synchronization output 281 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions Pin Symbol Ctrl. Buffer Type Function 70 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_13 GTM_TIM1_IN4_6 GTM_TIM0_IN4_6 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 SENT_SENT13C Receive input channel 13 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 EVADC_G10CH7 AI Analog input channel 7, group 10 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output — O3 Reserved — O4 Reserved — O5 Reserved EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 — O7 Reserved Data Sheet 282 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 71 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_15 GTM_TIM1_IN5_6 GTM_TIM0_IN5_6 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC EVADC_G10CH6 AI Analog input channel 6, group 10 P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 — O6 Reserved — O7 Reserved Data Sheet 283 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 72 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN2_14 GTM_TIM1_IN6_6 GTM_TIM0_IN6_6 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC EVADC_G10CH5 AI Analog input channel 5, group 10 P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 284 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 73 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN3_12 GTM_TIM1_IN7_6 GTM_TIM0_IN7_6 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC EVADC_G10CH4 AI Analog input channel 4, group 10 P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output QSPI4_SLSO2 O3 Master slave select output EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved — O7 Reserved Data Sheet 285 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 74 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_10 GTM_TIM1_IN0_10 GTM_TIM0_IN0_10 Mux input channel 4 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC GTM_DTMT2_0 CDTM2_DTM0 EVADC_G10CH3 AI Analog input channel 3, group 10 P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Data Sheet 286 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 75 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN5_10 GTM_TIM1_IN1_8 GTM_TIM0_IN1_8 Mux input channel 5 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC EVADC_G10CH2 AI Analog input channel 2, group 10 P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 ASCLIN5_ASLSO O7 Slave select signal output Data Sheet 287 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 76 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 GTM_TIM0_IN2_9 EDSADC_ITR2F Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC GTM_DTMT2_1 CDTM2_DTM0 EVADC_G10CH1 AI Analog input channel 1, group 10 P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Data Sheet 288 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 77 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 GTM_TIM0_IN3_9 CAN00_RXDE Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT14C Receive input channel 14 IOM_PIN_7 GPIO pad input to FPC EVADC_G10CH0 AI Analog input channel 0, group 10 P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output QSPI4_SLSO7 O3 Master slave select output ASCLIN8_ATX O4 Transmit output — O5 Reserved EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 289 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 78 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO2 O3 Master slave select output — O4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 Data Sheet O FSP[1..0] Output Signals - Generated by SMU_core 290 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 79 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 GTM_TIM0_IN1_9 IOM_PIN_9 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO1 O3 Master slave select output ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 291 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 80 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 GTM_TIM1_IN0_9 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 81 Mux input channel 4 of TIM module 4 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O P33.11 I GTM_TIM1_IN2_8 GTM_TIM0_IN2_8 QSPI4_SCLKA FSP[1..0] Output Signals - Generated by SMU_core FAST / PU1 / VEVRSB / ES5 General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 292 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 82 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_6 GTM_TIM2_IN0_6 QSPI4_MTSRA Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Slave SPI data input CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 ASCLIN1_ATX Monitor input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MTSR O3 Master SPI data output ASCLIN1_ASCLK O4 Shift clock output CAN22_TXD O5 CAN transmit output node 2 EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 293 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-51 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 83 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_5 GTM_TIM2_IN1_5 ASCLIN1_ARXF Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 Receive input EDSADC_SGNB Carrier sign signal input QSPI4_MRSTA Master SPI data input MSC1_INJ1 Injection signal from port CAN22_RXDA CAN receive input node 2 P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-52 Analog Inputs Pin Symbol Ctrl. Buffer Type 67 AN0 I D / HighZ Analog Input 0 / VDDM Analog input channel 0, group 0 EVADC_G0CH0 EDSADC_EDS3PA 66 AN1 Positive analog input channel 3, pin A I EVADC_G0CH1 EDSADC_EDS3NA 65 AN2 EVADC_G0CH2 EDSADC_EDS0PA Data Sheet Function D / HighZ Analog Input 1 / VDDM Analog input channel 1, group 0 Negative analog input channel 3, pin A I D / HighZ Analog Input 2 / VDDM Analog input channel 2, group 0 Positive analog input channel 0, pin A 294 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-52 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 64 AN3 I D / HighZ Analog Input 3 / VDDM Analog input channel 3, group 0 EVADC_G0CH3 EDSADC_EDS0NA 63 AN4 Negative analog input channel 0, pin A I EVADC_G11CH0 EVADC_G0CH4 62 AN5 I EVADC_G0CH5 AN6 I EVADC_G0CH6 AN7 I EVADC_G0CH7 AN8 I EVADC_G1CH0 AN10 I EVADC_G1CH2 AN11 I EVADC_G1CH3 AN12 I EDSADC_EDS0PB AN13 I EDSADC_EDS0NB AN16 I EVADC_FC0CH0 AN17/P40.10 SENT_SENT10A D / HighZ Analog Input 13 / VDDM Analog input channel 5, group 1 Negative analog input channel 0, pin B EVADC_G2CH0 49 D / HighZ Analog Input 12 / VDDM Analog input channel 4, group 1 Positive analog input channel 0, pin B EVADC_G1CH5 50 D / HighZ Analog Input 11 / VDDM Analog input channel 7, group 11 Analog input channel 3, group 1 EVADC_G1CH4 55 D / HighZ Analog Input 10 / VDDM Analog input channel 6, group 11 Analog input channel 2, group 1 EVADC_G11CH7 56 D / HighZ Analog Input 8 / VDDM Analog input channel 4, group 11 Analog input channel 0, group 1 EVADC_G11CH6 57 D / HighZ Analog Input 7 / VDDM Analog input channel 3, group 11 Analog input channel 7, group 0 EVADC_G11CH4 58 D / HighZ Analog Input 6 / VDDM Analog input channel 2, group 11 Analog input channel 6, group 0 EVADC_G11CH3 59 D / HighZ Analog Input 5 / VDDM Analog input channel 1, group 11 Analog input channel 5, group 0 EVADC_G11CH2 60 D / HighZ Analog Input 4 / VDDM Analog input channel 0, group 11 Analog input channel 4, group 0 EVADC_G11CH1 61 Function D / HighZ Analog Input 16 / VDDM Analog input channel 0, group 2 Analog input FC channel 0 I S / HighZ Analog Input 17 / VDDM Receive input channel 10 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 Data Sheet 295 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-52 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 48 AN18/P40.11 I S / HighZ Analog Input 18 / VDDM Receive input channel 11 SENT_SENT11A 47 EVADC_G11CH8 Analog input channel 8, group 11 EVADC_G2CH2 Analog input channel 2, group 2 AN19/P40.12 I SENT_SENT12A 46 Analog input channel 9, group 11 EVADC_G2CH3 Analog input channel 3, group 2 AN20 I EDSADC_EDS2PA AN21 I EDSADC_EDS2NA AN24/P40.0 I Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B AN25/P40.1 I Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B AN26/P40.2 I S / HighZ Analog Input 26 / VDDM Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 EVADC_G11CH10 Analog input channel 10, group 11 AN27/P40.3 I SENT_SENT3A 40 S / HighZ Analog Input 25 / VDDM Receive input channel 1 EVADC_G3CH1 SENT_SENT2A 41 S / HighZ Analog Input 24 / VDDM Receive input channel 0 EVADC_G3CH0 SENT_SENT1A 42 D / HighZ Analog Input 21 / VDDM Analog input channel 5, group 2 Negative analog input channel 2, pin A SENT_SENT0A 43 D / HighZ Analog Input 20 / VDDM Analog input channel 4, group 2 Positive analog input channel 2, pin A EVADC_G2CH5 44 S / HighZ Analog Input 19 / VDDM Receive input channel 12 EVADC_G11CH9 EVADC_G2CH4 45 Function S / HighZ Analog Input 27 / VDDM Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2 EVADC_G11CH11 Analog input channel 11, group 11 AN28/P40.13 SENT_SENT13A EVADC_G3CH4 Data Sheet I S / HighZ Analog Input 28 / VDDM Receive input channel 13 Analog input channel 4, group 3 296 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-52 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 39 AN29/P40.14 I S / HighZ Analog Input 29 / VDDM Receive input channel 14 SENT_SENT14A EVADC_G3CH5 38 AN32/P40.4 Analog input channel 5, group 3 I SENT_SENT4A 37 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 EVADC_G11CH12 Analog input channel 12, group 11 AN33/P40.5 I Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 EVADC_G11CH13 Analog input channel 13, group 11 AN35 I EVADC_G11CH15 AN36/P40.6 I Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A AN37/P40.7 I S / HighZ Analog Input 37 / VDDM Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A AN38/P40.8 I SENT_SENT8A 32 S / HighZ Analog Input 36 / VDDM Receive input channel 6 EVADC_G8CH4 SENT_SENT7A 33 D / HighZ Analog Input 35 / VDDM Analog input channel 3, group 8 Analog input channel 15, group 11 SENT_SENT6A 34 S / HighZ Analog Input 33 / VDDM Receive input channel 5 EVADC_G8CH1 EVADC_G8CH3 35 S / HighZ Analog Input 32 / VDDM Receive input channel 4 EVADC_G8CH0 SENT_SENT5A 36 Function S / HighZ Analog Input 38 / VDDM Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B AN39/P40.9 SENT_SENT9A I S / HighZ Analog Input 39 / VDDM Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B Data Sheet 297 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-52 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 31 AN44 I D / HighZ Analog Input 44 / VDDM Analog input channel 12, group 8 EVADC_G8CH12 EDSADC_EDS1PC 30 AN45 Positive analog input channel 1, pin C I EVADC_G8CH13 D / HighZ Analog Input 45 / VDDM Analog input channel 13, group 8 EDSADC_EDS1NC 29 AN46 Negative analog input channel 1, pin C I EVADC_G8CH14 D / HighZ Analog Input 46 / VDDM Analog input channel 14, group 8 EDSADC_EDS1PD 28 AN47 Function Positive analog input channel 1, pin D I EVADC_G8CH15 D / HighZ Analog Input 47 / VDDM Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D Table 2-53 System I/O Pin Symbol Ctrl. Buffer Type Function 84 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC 85 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC 102 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. 103 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT 112 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input TMS: JTAG Module State Machine Control Input. DAP: DAP1 Data I/O. DAP1 I/O TRST I DAPE0 I TCK I DAP0 I 114 115 Data Sheet DAP: DAP1 Data I/O FAST / PU2 / VEXT JTAG Module Reset/Enable Input TRST_N: JTAG Module Reset/Enable Input. DAPE: DAPE0 Clock Input DAPE: DAPE0 Clock Input FAST / PD2 / VEXT JTAG Module Clock Input TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input. DAP: DAP0 Clock Input 298 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-53 System I/O (cont’d) Pin Symbol Ctrl. Buffer Type Function 120 ESR1 I FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I 121 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. 122 ESR0 I FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR1 pin input ESR0 pin input Table 2-54 Supply Pin Symbol Ctrl. Buffer Type Function 164 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) 54 VDDM I — ADC Analog Power Supply (5V / 3.3V) 154 VDDP3 I — Flash Power Supply (3.3V) 52 VAREF1 I — Positive Analog Reference Voltage 1 26 VAREF2 I — Positive Analog Reference Voltage 2 10 VDDSB (VDD) I — Devices with integrated EMEM: EMEM SRAM Standby Power Supply, VDDSB (1.25V); Devices without integrated EMEM: VDD (1.25V) 69 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM 155 VDD I — Digital Core Power Supply (1.25V) 24 VDD I — Digital Core Power Supply (1.25V) 68 VDD I — Digital Core Power Supply (1.25V) 100 VDD I — Digital Core Power Supply (1.25V) 123 VDD I — Digital Core Power Supply (1.25V) 153 VEXT I — External Power Supply (5V / 3.3V) Data Sheet 299 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-176 Package Pinning of Table 2-54 Supply (cont’d) Pin Symbol Ctrl. Buffer Type Function 25 VEXT I — External Power Supply (5V / 3.3V) 99 VEXT I — External Power Supply (5V / 3.3V) 177 VSS I — Digital Ground (Exposed PAD), VSS 53 VSSM I — Analog Ground for VDDM 51 VAGND1 I — Negative Analog Reference Voltage 1 27 VAGND2 I — Negative Analog Reference Voltage 2 101 VSS I — Oscillator Ground, VSS(OSC) 104 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT), VEXT(OSC) Data Sheet 300 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of P14.5 P14.4 P14.3 P14.2 P14.1 123 122 121 120 119 P15.0 P14.6 124 P15.1 VEXT 125 109 VDDP3 126 P15.2 VDD 127 110 P13.0 128 P15.3 P13.1 129 111 P13.2 130 P15.4 P13.3 131 112 P11.2 132 P15.5 P11.3 133 113 P11.6 134 P15.6 P11.9 135 114 VFLEX 136 P15.7 P11.10 137 115 P11.11 138 116 P11.12 139 P14.0 P10.1 140 P15.8 P10.2 141 117 P10.3 142 118 P10.6 P10.5 144 LQFP-144 Package Pinning of TC37xEXT 143 2.4 P02.0 1 108 P20.14 P02.1 2 107 P20.13 P02.2 3 106 P20.12 P02.3 4 105 P20.11 P02.4 5 104 P20.10 P02.5 6 103 P20.9 P02.6 7 102 P20.8 P02.7 8 101 P20.7 P02.8 9 100 P20.6 VDDSB (VDD) 10 99 VDD P00.0 11 98 ESR0 P00.1 12 97 PORST P00.2 13 96 ESR1 P00.3 14 95 P20.3 P00.4 15 94 P20.2 P00.5 16 93 P20.0 P00.6 17 92 TCK P00.7 18 P00.8 19 TC37xed 91 TRST 90 P21.7 / TDO P00.9 20 89 TMS P00.12 21 88 P21.6 / TDI VDD 22 87 P21.5 VEXT 23 86 P21.4 VAREF2 24 85 P21.3 VAGND2 25 84 P21.2 AN47 26 83 VEXT AN46 27 82 XTAL2 AN45 28 81 XTAL1 AN44 29 80 VSS AN39 / P40.9 30 79 VDD AN38 / P40.8 31 78 VEXT AN37 / P40.7 32 77 P22.3 AN36 / P40.6 33 76 P22.2 AN35 34 75 P22.1 AN25 / P40.1 35 74 P22.0 AN24 / P40.0 36 73 P23.1 65 66 67 68 69 70 71 72 P33.11 P33.12 P33.13 P32.0 / VGATE1N P32.1 / VGATE1P P32.4 64 P33.8 P33.9 63 P33.7 P33.10 62 P33.6 53 AN4 61 52 AN5 P33.5 51 AN6 60 50 AN7 P33.4 49 AN8 59 48 AN10 VEVRSB 47 AN11 58 46 AN12 VDD 45 AN13 57 44 VDDM AN0 43 VSSM 56 42 VAREF1 AN1 41 VAGND1 55 40 AN16 AN2 39 AN17 / P40.10 54 38 AN20 AN3 37 AN21 (Top View) Figure 2-4 TC37xEXT package variant LQFP-144 Data Sheet 301 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions Pin Symbol Ctrl. Buffer Type Function 11 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_10 GTM_TIM3_IN0_1 GTM_TIM2_IN0_1 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port CIF_D9 sensor pixel data input GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O4 Reserved CAN10_TXD O5 CAN transmit output node 0 — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO Data Sheet O MDIO Output 302 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 12 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_11 GTM_TIM3_IN1_1 GTM_TIM2_IN1_1 Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input EDSADC_DSCIN5A Modulator clock input, channel 5 CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CIF_D10 sensor pixel data input CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI EDSADC_EDS5NA Analog input channel 11, group 9 Negative analog input channel 5, pin A P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 ASCLIN3_ATX Reference input 0 O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 — O3 Reserved EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 303 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 13 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN6_11 GTM_TIM3_IN1_2 GTM_TIM2_IN1_2 Mux input channel 6 of TIM module 5 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 EDSADC_DSDIN5A Digital datastream input, channel 5 SENT_SENT1B Receive input channel 1 CIF_D11 sensor pixel data input EVADC_G9CH10 AI EDSADC_EDS5PA Analog input channel 10, group 9 Positive analog input channel 5, pin A P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output CAN21_TXD O3 CAN transmit output node 1 PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 304 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 14 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN7_10 GTM_TIM3_IN2_1 GTM_TIM2_IN2_1 Mux input channel 7 of TIM module 5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 EDSADC_ITR5F Trigger/Gate input, channel 5 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 CAN21_RXDA CAN receive input node 1 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CIF_D12 sensor pixel data input CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI EDSADC_EDS5NB Analog input channel 9, group 9 Negative analog input channel 5, pin B P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output — O5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 305 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 15 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN3_1 GTM_TIM2_IN3_1 SCU_E_REQ2_2 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input CIF_D13 sensor pixel data input EVADC_G9CH8 AI EDSADC_EDS5PB Analog input channel 8, group 9 Positive analog input channel 5, pin B P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 — O5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Data Sheet 306 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 16 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN4_1 GTM_TIM3_IN0_11 GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CIF_D14 sensor pixel data input CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 307 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 17 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN5_1 GTM_TIM3_IN1_14 GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 3 Mux input channel 1 of TIM module 3 Mux input channel 5 of TIM module 2 EDSADC_ITR4F Trigger/Gate input, channel 4 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 CIF_D15 sensor pixel data input ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output — O3 Reserved — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Data Sheet 308 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 18 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN6_1 GTM_TIM3_IN2_11 GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 3 Mux input channel 2 of TIM module 3 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 EDSADC_DSCIN4A Modulator clock input, channel 4 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 CIF_PCLK Sensor Pixel Clock input GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI EDSADC_EDS4NA Analog input channel 5, group 9 Negative analog input channel 4, pin A P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output EVADC_FC2BFLOUT O3 Boundary flag output, FC channel 2 EDSADC_DSCOUT4 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Data Sheet 309 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 19 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN7_1 GTM_TIM3_IN3_11 GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 3 Mux input channel 3 of TIM module 3 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 EDSADC_DSDIN4A Digital datastream input, channel 4 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CIF_VSYNC vertical synchronization signal input CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI EDSADC_EDS4PA Analog input channel 4, group 9 Positive analog input channel 4, pin A P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output — O4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 310 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 20 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN0_7 GTM_TIM1_IN0_1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CIF_HSYNC horizontal synchronization signal input CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI EDSADC_EDS4NB Analog input channel 3, group 9 Negative analog input channel 4, pin B P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 311 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-55 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 21 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN3_11 GTM_TIM1_IN3_1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input SENT_SENT11B Receive input channel 11 EVADC_G9CH0 AI EVADC_FC2CH0 Analog input channel 0, group 9 Analog input FC channel 2 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Data Sheet 312 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions Pin Symbol Ctrl. Buffer Type Function 1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 GTM_TIM0_IN0_2 CCU61_CC60INB Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D0 sensor pixel data input GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 ASCLIN2_ATX Reference input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 313 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 GTM_TIM0_IN1_2 ERAY0_RXDA2 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CIF_D1 sensor pixel data input P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 QSPI4_SLSO7 O2 Master slave select output QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 314 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 3 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 GTM_TIM0_IN2_2 CCU61_CC61INB Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 T12 capture input 61 CCU60_CC61INA T12 capture input 61 CIF_D2 sensor pixel data input SENT_SENT14B Receive input channel 14 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 ASCLIN1_ATX Reference input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 315 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 4 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 GTM_TIM0_IN3_2 EDSADC_DSCIN5B Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Modulator clock input, channel 5 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input MSC1_SDI1 Upstream assynchronous input signal PSI5_RX0B RXD inputs (receive data) channel 0 CIF_D3 sensor pixel data input SENT_SENT13B Receive input channel 13 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output EDSADC_DSCOUT5 O4 Modulator clock output — O5 Reserved — O6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 316 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 5 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 GTM_TIM0_IN4_1 CCU61_CC62INB Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 T12 capture input 62 EDSADC_DSDIN5B Digital datastream input, channel 5 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input CIF_D4 sensor pixel data input SENT_SENT12B Receive input channel 12 P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 317 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 6 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 GTM_TIM0_IN5_1 EDSADC_DSCIN4B Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Modulator clock input, channel 4 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input CIF_D5 sensor pixel data input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 EDSADC_DSCOUT4 O4 Modulator clock output I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 318 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 7 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_10 GTM_TIM1_IN6_1 GTM_TIM0_IN6_1 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 EDSADC_DSDIN4B Digital datastream input, channel 4 EDSADC_ITR5E Trigger/Gate input, channel 5 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input CIF_D6 sensor pixel data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 — O6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 319 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 8 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_10 GTM_TIM1_IN7_1 GTM_TIM0_IN7_1 Mux input channel 1 of TIM module 3 Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 EDSADC_ITR4E Trigger/Gate input, channel 4 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 CIF_D7 sensor pixel data input QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 — O2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Data Sheet 320 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-56 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 9 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_10 GTM_TIM3_IN0_2 GTM_TIM2_IN0_2 Mux input channel 2 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CIF_D8 sensor pixel data input CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output — O4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 321 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-57 Port 10 Functions Pin Symbol Ctrl. Buffer Type Function 140 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_12 GTM_TIM1_IN1_3 GTM_TIM0_IN1_3 141 Mux input channel 4 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 — O6 Reserved — O7 Reserved P10.2 I GTM_TIM4_IN5_12 GTM_TIM1_IN2_3 GTM_TIM0_IN2_3 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMT2_2 CDTM2_DTM0 P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 — O2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select EVADC_FC3BFLOUT O5 Boundary flag output, FC channel 3 — O6 Reserved — O7 Reserved Data Sheet 322 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-57 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 142 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_10 GTM_TIM1_IN3_3 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 143 Mux input channel 6 of TIM module 4 Monitor input 2 — O2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select — O5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 — O7 P10.5 I GTM_TIM4_IN3_13 GTM_TIM1_IN2_4 GTM_TIM0_IN2_4 Reserved SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 3 of TIM module 4 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input CAN20_RXDA CAN receive input node 0 MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 ASCLIN2_ATX Reference input 2 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output — O7 Reserved Data Sheet 323 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-57 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 144 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN2_13 GTM_TIM1_IN3_4 GTM_TIM0_IN3_4 Mux input channel 2 of TIM module 4 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 CAN20_TXD O5 CAN transmit output node 0 QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 — O7 Reserved Table 2-58 Port 11 Functions Pin Symbol Ctrl. Buffer Type Function 132 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN1_3 GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 P11.2 O0 GTM_TOUT95 O1 GTM muxed output — O2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 General-purpose output IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Data Sheet 324 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-58 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 133 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN2_2 GTM_TIM2_IN2_2 MSC0_SDI3 Mux input channel 2 of TIM module 2 Upstream assynchronous input signal QSPI1_MRSTB 134 Mux input channel 2 of TIM module 3 Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output — O2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A — O5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 P11.6 I GTM_TIM3_IN3_2 GTM_TIM2_IN3_2 QSPI1_SCLKB RFAST / PU1 / VFLEX / ES General-purpose input Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL CCU60_COUT61 Transmit Control for RGMII O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 325 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-58 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 135 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN4_2 GTM_TIM2_IN4_2 QSPI1_MTSRB Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output — O2 Reserved QSPI1_MTSR O3 Master SPI data output — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Data Sheet 326 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-58 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 137 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN5_2 GTM_TIM2_IN5_2 GTM_TIM2_IN0_9 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output — O2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output — O5 Reserved — O6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 327 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-58 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 138 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN6_2 GTM_TIM3_IN0_14 GTM_TIM2_IN6_2 139 Mux input channel 6 of TIM module 3 Mux input channel 0 of TIM module 3 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output — O2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P11.12 I GTM_TIM3_IN7_2 GTM_TIM2_IN7_2 GETH_REFCLKA FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 328 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-59 Port 13 Functions Pin Symbol Ctrl. Buffer Type Function 128 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN5_3 GTM_TIM2_IN5_3 ASCLIN10_ARXC 129 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved CAN10_TXD O7 CAN transmit output node 0 P13.1 I GTM_TIM3_IN6_3 GTM_TIM2_IN6_3 I2C0_SCLB LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output — O2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) — O4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output — O7 Reserved Data Sheet 329 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-59 Port 13 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 130 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN7_3 GTM_TIM2_IN7_3 GPT120_CAPINA I2C0_SDAB 131 Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Trigger input to capture value of timer T5 into CAPREL register Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output — O7 Reserved P13.3 I GTM_TIM3_IN0_3 GTM_TIM2_IN0_3 LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 P13.3 O0 GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) — O4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Data Sheet General-purpose output 330 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-60 Port 14 Functions Pin Symbol Ctrl. Buffer Type Function 118 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 P14.0 O0 GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output General-purpose output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Data Sheet 331 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 119 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 GTM_TIM0_IN4_3 ERAY0_RXDA3 120 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 P14.2 I GTM_TIM1_IN5_3 GTM_TIM0_IN5_3 PMS_HWCFG2IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output — O4 Reserved — O5 Reserved ASCLIN2_ASCLK O6 Shift clock output — O7 Reserved Data Sheet 332 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 121 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 GTM_TIM0_IN6_3 PMS_HWCFG3IN 122 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output — O6 Reserved — O7 Reserved P14.4 I GTM_TIM1_IN7_2 GTM_TIM0_IN7_2 PMS_HWCFG6IN SLOW / PU2 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved GETH_PPS O6 Pulse Per Second — O7 Reserved Data Sheet 333 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 123 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 GTM_TIM0_IN0_4 PMS_HWCFG1IN Mux input channel 0 of TIM module 0 HWCFG1 pin input GTM_DTMA2_0 124 Mux input channel 0 of TIM module 1 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved ERAY0_TXDB O6 Transmit Channel B — O7 Reserved P14.6 I GTM_TIM1_IN1_4 GTM_TIM0_IN1_4 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 P14.6 O0 GTM_TOUT86 O1 GTM muxed output — O2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 — O5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B — O7 Reserved Data Sheet General-purpose output 334 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-61 Port 15 Functions Pin Symbol Ctrl. Buffer Type Function 109 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_4 GTM_TIM2_IN3_4 SDMMC0_DAT7_IN 110 Mux input channel 3 of TIM module 3 Mux input channel 3 of TIM module 2 read data in P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output — O4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output — O7 Reserved SDMMC0_DAT7 O write data out P15.1 I GTM_TIM3_IN4_4 GTM_TIM2_IN4_4 CAN02_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output — O4 Reserved — O5 Reserved — O6 Reserved SDMMC0_CLK O7 card clock Data Sheet 335 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 111 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_4 GTM_TIM2_IN5_4 QSPI2_SLSIA 112 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 Slave select input SENT_SENT10D Receive input channel 10 QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output — O4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output — O7 Reserved P15.3 I GTM_TIM3_IN6_4 GTM_TIM2_IN6_4 CAN01_RXDA FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs SDMMC0_CMD_IN command in P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output — O4 Reserved MSC0_EN1 O5 Chip Select — O6 Reserved — O7 Reserved SDMMC0_CMD O command out Data Sheet 336 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 113 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_4 GTM_TIM2_IN7_4 I2C0_SCLC Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT11D Receive input channel 11 P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Data Sheet 337 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 114 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_4 GTM_TIM2_IN0_4 ASCLIN1_ARXB 115 Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 P15.6 I GTM_TIM2_IN2_14 GTM_TIM1_IN0_6 GTM_TIM0_IN0_6 FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 2 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output — O4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Data Sheet 338 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 116 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 GTM_TIM0_IN1_5 ASCLIN3_ARXA Mux input channel 1 of TIM module 0 Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST 117 Mux input channel 1 of TIM module 1 O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 — O4 Reserved — O5 Reserved — O6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 P15.8 I GTM_TIM1_IN2_5 GTM_TIM0_IN2_5 QSPI2_SCLKB FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output — O2 Reserved QSPI2_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Data Sheet 339 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-62 Port 20 Functions Pin Symbol Ctrl. Buffer Type Function 93 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 GTM_TIM1_IN4_9 GTM_TIM0_IN6_7 94 Mux input channel 6 of TIM module 1 Mux input channel 4 of TIM module 1 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CAN21_RXDC CAN receive input node 1 CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output — O6 Reserved — O7 Reserved CBS_TGO0 O Trigger output P20.2 I TESTMODE Data Sheet S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. Testmode Enable Input 340 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 95 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_11 GTM_TIM3_IN4_5 GTM_TIM2_IN4_5 100 Mux input channel 5 of TIM module 4 Mux input channel 4 of TIM module 3 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 — O7 Reserved P20.6 I GTM_TIM3_IN6_5 GTM_TIM2_IN6_5 CAN12_RXDA SLOW / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 341 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 101 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_5 GTM_TIM2_IN7_5 GTM_TIM1_IN5_8 102 Mux input channel 7 of TIM module 3 Mux input channel 7 of TIM module 2 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input SDMMC0_DAT0_IN read data in P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output — O3 Reserved — O4 Reserved CAN12_TXD O5 CAN transmit output node 2 — O6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 SDMMC0_DAT0 O P20.8 I GTM_TIM1_IN7_3 GTM_TIM0_IN7_3 SDMMC0_DAT1_IN write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 7 of TIM module 1 Mux input channel 7 of TIM module 0 read data in P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 SDMMC0_DAT1 Data Sheet O write data out 342 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 103 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_5 GTM_TIM2_IN5_5 CAN03_RXDE 104 Mux input channel 5 of TIM module 3 Mux input channel 5 of TIM module 2 CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output — O2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output — O5 Reserved — O6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 P20.10 I GTM_TIM3_IN6_6 GTM_TIM2_IN6_6 SDMMC0_DAT2_IN FAST / PU1 / VEXT / ES General-purpose input Mux input channel 6 of TIM module 3 Mux input channel 6 of TIM module 2 read data in P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 SDMMC0_DAT2 Data Sheet O write data out 343 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 105 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_6 GTM_TIM2_IN7_6 QSPI0_SCLKA Mux input channel 7 of TIM module 2 Slave SPI clock inputs SDMMC0_DAT3_IN 106 Mux input channel 7 of TIM module 3 read data in P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output — O2 Reserved QSPI0_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved — O6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 SDMMC0_DAT3 O P20.12 I GTM_TIM3_IN0_5 GTM_TIM2_IN0_5 QSPI0_MRSTA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Master SPI data input SDMMC0_DAT4_IN read data in IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 — O2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output — O5 Reserved — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SDMMC0_DAT4 Data Sheet O write data out 344 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 107 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_4 GTM_TIM2_IN1_4 QSPI0_SLSIA Mux input channel 1 of TIM module 2 Slave select input SDMMC0_DAT5_IN read data in IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 108 Mux input channel 1 of TIM module 3 Monitor input 0 — O2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SDMMC0_DAT5 O P20.14 I GTM_TIM3_IN2_4 GTM_TIM2_IN2_4 QSPI0_MTSRA write data out FAST / PU1 / VEXT / ES General-purpose input Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 Slave SPI data input SDMMC0_DAT6_IN read data in IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 — O2 Reserved QSPI0_MTSR O3 Master SPI data output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved SDMMC0_DAT6 O write data out Data Sheet 345 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-63 Port 21 Functions Pin Symbol Ctrl. Buffer Type Function 84 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_11 GTM_TIM1_IN0_7 GTM_TIM0_IN0_7 Mux input channel 4 of TIM module 5 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data QSPI4_MRSTCN Master SPI data input (LVDS N line) ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved GETH_MDC O5 MDIO clock — O6 Reserved — O7 Reserved Data Sheet 346 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-63 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 85 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_12 GTM_TIM1_IN1_6 GTM_TIM0_IN1_6 86 Mux input channel 5 of TIM module 5 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data QSPI4_MRSTCP Master SPI data input (LVDS P line) P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved GETH_MDIO O MDIO Output P21.4 I GTM_TIM5_IN6_12 GTM_TIM1_IN2_6 GTM_TIM0_IN2_6 LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 6 of TIM module 5 Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDN O Tx data Data Sheet 347 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-63 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 87 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN7_11 GTM_TIM1_IN3_6 GTM_TIM0_IN3_6 ASCLIN11_ARXF 88 Mux input channel 7 of TIM module 5 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved HSCT0_TXDP O Tx data P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O. GTM_TIM4_IN2_12 Mux input channel 2 of TIM module 4 GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O DAPE1 I/O DAPE: DAPE1 Data I/O Data Sheet 348 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-63 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 90 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O. GTM_TIM4_IN3_12 GTM_TIM1_IN5_7 Mux input channel 3 of TIM module 4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output — O4 Reserved — O5 Reserved — O6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O DAPE2 I/O DAPE: DAPE2 Data I/O TDO O JTAG Module Data Output Data Sheet 349 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-64 Port 22 Functions Pin Symbol Ctrl. Buffer Type Function 74 P22.0 I LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input GTM_TIM1_IN1_7 GTM_TIM0_IN1_7 QSPI4_MTSRB 75 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 Slave SPI data input ASCLIN6_ARXE Receive input GETH1_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH1_RXDVB Receive Data Valid MII GETH1_CRSA Carrier Sense MII P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATXN O2 Differential Transmit output (low active) QSPI4_MTSR O3 Master SPI data output QSPI4_SCLKN O4 Master SPI clock output (LVDS N line) MSC1_FCLN O5 Shift-clock inverted part of the differential signal — O6 Reserved ASCLIN6_ATX O7 Transmit output P22.1 I GTM_TIM1_IN0_8 GTM_TIM0_IN0_8 QSPI4_MRSTB LVDS_TX / FAST / PU1 / VFLEX2 / ES6 General-purpose input Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 Master SPI data input ASCLIN7_ARXE Receive input GETH1_RXERA Receive Error MII P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATXP O2 Differential Transmit output (high active) QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI4_SCLKP O4 Master SPI clock output (LVDS P line) MSC1_FCLP O5 Shift-clock direct part of the differential signal — O6 Reserved ASCLIN7_ATX O7 Transmit output Data Sheet 350 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-64 Port 22 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 76 P22.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 GTM_TIM0_IN3_7 QSPI4_SLSIB GETH1_COLA 77 Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 Slave select input Collision MII P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI4_SLSO3 O3 Master slave select output QSPI4_MTSRN O4 Master SPI data output (LVDS N line) MSC1_SON O5 Data output - inverted part of the differential signal — O6 Reserved — O7 Reserved P22.3 I GTM_TIM1_IN4_4 GTM_TIM0_IN4_4 QSPI4_SCLKB ASCLIN5_ARXC LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 Slave SPI clock inputs Receive input P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output — O2 Reserved QSPI4_SCLK O3 Master SPI clock output QSPI4_MTSRP O4 Master SPI data output (LVDS P line) MSC1_SOP O5 Data output - direct part of the differential signal — O6 Reserved — O7 Reserved Data Sheet 351 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-65 Port 23 Functions Pin Symbol Ctrl. Buffer Type Function 73 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 GTM_TIM0_IN6_4 MSC1_SDI0 Mux input channel 6 of TIM module 1 Mux input channel 6 of TIM module 0 Upstream assynchronous input signal ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI4_SLSO6 O3 Master slave select output GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output Table 2-66 Port 32 Functions Pin Symbol Ctrl. Buffer Type Function 70 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM3_IN2_5 GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 3 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved Data Sheet 352 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-66 Port 32 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 71 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC GTM_TIM3_IN3_15 72 Mux input channel 3 of TIM module 3 P32.1 O0 GTM_TOUT37 O1 GTM muxed output — O2 Reserved — O3 Reserved — O4 Reserved — O5 Reserved — O6 Reserved — O7 Reserved P32.4 I GTM_TIM1_IN5_5 GTM_TIM0_IN5_5 ASCLIN1_ACTSB FAST / PU1 / VEXT / ES General-purpose output General-purpose input Mux input channel 5 of TIM module 1 Mux input channel 5 of TIM module 0 Clear to send input MSC1_SDI2 Upstream assynchronous input signal P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output — O2 Reserved — O3 Reserved GTM_CLK1 O4 CGM generated clock MSC1_EN0 O5 Chip Select CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO Data Sheet O DC-DC synchronization output 353 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions Pin Symbol Ctrl. Buffer Type Function 60 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_10 GTM_TIM1_IN0_10 GTM_TIM0_IN0_10 Mux input channel 4 of TIM module 4 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC GTM_DTMT2_0 CDTM2_DTM0 EVADC_G10CH3 AI Analog input channel 3, group 10 P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Data Sheet 354 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 61 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN5_10 GTM_TIM1_IN1_8 GTM_TIM0_IN1_8 Mux input channel 5 of TIM module 4 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC EVADC_G10CH2 AI Analog input channel 2, group 10 P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 ASCLIN5_ASLSO O7 Slave select signal output Data Sheet 355 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 62 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 GTM_TIM0_IN2_9 EDSADC_ITR2F Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC GTM_DTMT2_1 CDTM2_DTM0 EVADC_G10CH1 AI Analog input channel 1, group 10 P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output — O4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Data Sheet 356 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 63 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 GTM_TIM0_IN3_9 CAN00_RXDE Mux input channel 3 of TIM module 1 Mux input channel 3 of TIM module 0 CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT14C Receive input channel 14 IOM_PIN_7 GPIO pad input to FPC EVADC_G10CH0 AI Analog input channel 0, group 10 P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output QSPI4_SLSO7 O3 Master slave select output ASCLIN8_ATX O4 Transmit output — O5 Reserved EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 — O7 Reserved Data Sheet 357 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 64 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 1 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO2 O3 Master slave select output — O4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 Data Sheet O FSP[1..0] Output Signals - Generated by SMU_core 358 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 65 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 GTM_TIM0_IN1_9 IOM_PIN_9 Mux input channel 1 of TIM module 1 Mux input channel 1 of TIM module 0 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 ASCLIN2_ATX Monitor input 0 O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO1 O3 Master slave select output ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Data Sheet 359 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 66 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 GTM_TIM1_IN0_9 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 1 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 67 Mux input channel 4 of TIM module 4 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. — O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O P33.11 I GTM_TIM1_IN2_8 GTM_TIM0_IN2_8 QSPI4_SCLKA FSP[1..0] Output Signals - Generated by SMU_core FAST / PU1 / VEVRSB / ES5 General-purpose input Mux input channel 2 of TIM module 1 Mux input channel 2 of TIM module 0 Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output — O4 Reserved — O5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Data Sheet 360 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 68 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_6 GTM_TIM2_IN0_6 QSPI4_MTSRA Mux input channel 0 of TIM module 3 Mux input channel 0 of TIM module 2 Slave SPI data input CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 ASCLIN1_ATX Monitor input 0 O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MTSR O3 Master SPI data output ASCLIN1_ASCLK O4 Shift clock output CAN22_TXD O5 CAN transmit output node 2 EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Data Sheet 361 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function 69 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_5 GTM_TIM2_IN1_5 ASCLIN1_ARXF Mux input channel 1 of TIM module 3 Mux input channel 1 of TIM module 2 Receive input EDSADC_SGNB Carrier sign signal input QSPI4_MRSTA Master SPI data input MSC1_INJ1 Injection signal from port CAN22_RXDA CAN receive input node 2 P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 — O6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-68 Analog Inputs Pin Symbol Ctrl. Buffer Type 57 AN0 I D / HighZ Analog Input 0 / VDDM Analog input channel 0, group 0 EVADC_G0CH0 EDSADC_EDS3PA 56 AN1 Positive analog input channel 3, pin A I EVADC_G0CH1 EDSADC_EDS3NA 55 AN2 EVADC_G0CH2 EDSADC_EDS0PA Data Sheet Function D / HighZ Analog Input 1 / VDDM Analog input channel 1, group 0 Negative analog input channel 3, pin A I D / HighZ Analog Input 2 / VDDM Analog input channel 2, group 0 Positive analog input channel 0, pin A 362 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-68 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 54 AN3 I D / HighZ Analog Input 3 / VDDM Analog input channel 3, group 0 EVADC_G0CH3 EDSADC_EDS0NA 53 AN4 Negative analog input channel 0, pin A I EVADC_G11CH0 EVADC_G0CH4 52 AN5 I EVADC_G0CH5 AN6 I EVADC_G0CH6 AN7 I EVADC_G0CH7 AN8 I EVADC_G1CH0 AN10 I EVADC_G1CH2 AN11 I EVADC_G1CH3 AN12 I EDSADC_EDS0PB AN13 I EDSADC_EDS0NB AN16 I EVADC_FC0CH0 AN17/P40.10 SENT_SENT10A D / HighZ Analog Input 13 / VDDM Analog input channel 5, group 1 Negative analog input channel 0, pin B EVADC_G2CH0 39 D / HighZ Analog Input 12 / VDDM Analog input channel 4, group 1 Positive analog input channel 0, pin B EVADC_G1CH5 40 D / HighZ Analog Input 11 / VDDM Analog input channel 7, group 11 Analog input channel 3, group 1 EVADC_G1CH4 45 D / HighZ Analog Input 10 / VDDM Analog input channel 6, group 11 Analog input channel 2, group 1 EVADC_G11CH7 46 D / HighZ Analog Input 8 / VDDM Analog input channel 4, group 11 Analog input channel 0, group 1 EVADC_G11CH6 47 D / HighZ Analog Input 7 / VDDM Analog input channel 3, group 11 Analog input channel 7, group 0 EVADC_G11CH4 48 D / HighZ Analog Input 6 / VDDM Analog input channel 2, group 11 Analog input channel 6, group 0 EVADC_G11CH3 49 D / HighZ Analog Input 5 / VDDM Analog input channel 1, group 11 Analog input channel 5, group 0 EVADC_G11CH2 50 D / HighZ Analog Input 4 / VDDM Analog input channel 0, group 11 Analog input channel 4, group 0 EVADC_G11CH1 51 Function D / HighZ Analog Input 16 / VDDM Analog input channel 0, group 2 Analog input FC channel 0 I S / HighZ Analog Input 17 / VDDM Receive input channel 10 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 Data Sheet 363 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-68 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 38 AN20 I D / HighZ Analog Input 20 / VDDM Analog input channel 4, group 2 EVADC_G2CH4 EDSADC_EDS2PA 37 AN21 Positive analog input channel 2, pin A I EVADC_G2CH5 EDSADC_EDS2NA 36 AN24/P40.0 I Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B AN25/P40.1 I Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B AN35 I EVADC_G11CH15 AN36/P40.6 I S / HighZ Analog Input 36 / VDDM Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A AN37/P40.7 I SENT_SENT7A 31 D / HighZ Analog Input 35 / VDDM Analog input channel 3, group 8 Analog input channel 15, group 11 SENT_SENT6A 32 S / HighZ Analog Input 25 / VDDM Receive input channel 1 EVADC_G3CH1 EVADC_G8CH3 33 S / HighZ Analog Input 24 / VDDM Receive input channel 0 EVADC_G3CH0 SENT_SENT1A 34 D / HighZ Analog Input 21 / VDDM Analog input channel 5, group 2 Negative analog input channel 2, pin A SENT_SENT0A 35 Function S / HighZ Analog Input 37 / VDDM Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A AN38/P40.8 SENT_SENT8A I S / HighZ Analog Input 38 / VDDM Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B Data Sheet 364 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-68 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type 30 AN39/P40.9 I S / HighZ Analog Input 39 / VDDM Receive input channel 9 SENT_SENT9A 29 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B AN44 I EVADC_G8CH12 D / HighZ Analog Input 44 / VDDM Analog input channel 12, group 8 EDSADC_EDS1PC 28 AN45 Positive analog input channel 1, pin C I EVADC_G8CH13 D / HighZ Analog Input 45 / VDDM Analog input channel 13, group 8 EDSADC_EDS1NC 27 AN46 Negative analog input channel 1, pin C I EVADC_G8CH14 D / HighZ Analog Input 46 / VDDM Analog input channel 14, group 8 EDSADC_EDS1PD 26 Function AN47 Positive analog input channel 1, pin D I EVADC_G8CH15 D / HighZ Analog Input 47 / VDDM Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D Table 2-69 System I/O Pin Symbol Ctrl. Buffer Type Function 70 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC 71 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC 81 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. 82 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT 89 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input TMS: JTAG Module State Machine Control Input. DAP: DAP1 Data I/O. DAP1 I/O TRST I DAPE0 I 91 Data Sheet DAP: DAP1 Data I/O FAST / PU2 / VEXT JTAG Module Reset/Enable Input TRST_N: JTAG Module Reset/Enable Input. DAPE: DAPE0 Clock Input DAPE: DAPE0 Clock Input 365 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-69 System I/O (cont’d) Pin Symbol Ctrl. Buffer Type Function 92 TCK I JTAG Module Clock Input TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input. DAP0 I FAST / PD2 / VEXT ESR1 I FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I 97 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. 98 ESR0 I FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I 96 DAP: DAP0 Clock Input ESR1 pin input ESR0 pin input Table 2-70 Supply Pin Symbol Ctrl. Buffer Type Function 136 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) 44 VDDM I — ADC Analog Power Supply (5V / 3.3V) 126 VDDP3 I — Flash Power Supply (3.3V) 42 VAREF1 I — Positive Analog Reference Voltage 1 24 VAREF2 I — Positive Analog Reference Voltage 2 10 VDDSB (VDD) I — Devices with integrated EMEM: EMEM SRAM Standby Power Supply, VDDSB (1.25V); Devices without integrated EMEM: VDD (1.25V) 59 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM 125 VEXT I — External Power Supply (5V / 3.3V) 23 VEXT I — External Power Supply (5V / 3.3V) 78 VEXT I — External Power Supply (5V / 3.3V) Data Sheet 366 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions LQFP-144 Package Pinning of Table 2-70 Supply (cont’d) Pin Symbol Ctrl. Buffer Type Function 127 VDD I — Digital Core Power Supply (1.25V) 22 VDD I — Digital Core Power Supply (1.25V) 58 VDD I — Digital Core Power Supply (1.25V) 79 VDD I — Digital Core Power Supply (1.25V) 99 VDD I — Digital Core Power Supply (1.25V) 145 VSS I — Digital Ground (Exposed PAD), VSS 43 VSSM I — Analog Ground for VDDM 41 VAGND1 I — Negative Analog Reference Voltage 1 25 VAGND2 I — Negative Analog Reference Voltage 2 80 VSS I — Oscillator Ground, VSS(OSC) 83 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT), VEXT(OSC) Data Sheet 367 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of 2.5 Pad Position Configuration of TC37xEXT Table 2-71 Pad List Number Pad Name Pad Type X Y Comment 1 VEXT Vx 255699 175644 Supply Voltage 2 VSS Vx 356499 185148 Supply Voltage 3 VSS Vx 457299 185148 Supply Voltage 4 VDD Vx 507699 344106 Supply Voltage 5 P15.0 FAST / PU1 / VEXT / ES 558099 185148 General-purpose I/O 6 P15.1 FAST / PU1 / VEXT / ES 608499 344106 General-purpose I/O 7 P15.2 FAST / PU1 / VEXT / ES 658899 185148 General-purpose I/O 8 P15.3 FAST / PU1 / VEXT / ES 709299 344106 General-purpose I/O 9 P15.4 FAST / PU1 / VEXT / ES 756297 185148 General-purpose I/O 10 P15.5 FAST / PU1 / VEXT / ES 803295 344106 General-purpose I/O 11 P15.6 FAST / PU1 / VEXT / ES 850293 185148 General-purpose I/O 12 P15.7 FAST / PU1 / VEXT / ES 897291 344106 General-purpose I/O 13 P15.8 FAST / PU1 / VEXT / ES 944289 185148 General-purpose I/O 14 P14.0 FAST / PU1 / VEXT / ES2 991287 344106 General-purpose I/O 15 VDD Vx 1076499 185148 Supply Voltage 16 P14.1 FAST / PU1 / VEXT / ES2 1161999 344106 General-purpose I/O 17 VSS Vx 1238499 185148 Supply Voltage 18 P14.2 SLOW / PU2 / 1319499 VEXT / ES 344106 General-purpose I/O 19 VSS Vx 1366497 185148 Supply Voltage 20 P14.3 SLOW / PU2 / 1413495 VEXT / ES 344106 General-purpose I/O 21 VEXT Vx 1460493 175644 Supply Voltage 22 P14.4 SLOW / PU2 / 1507491 VEXT / ES 344106 General-purpose I/O 23 P14.5 FAST / PU2 / VEXT / ES 1554489 185148 General-purpose I/O 24 P14.6 FAST / PU1 / VEXT / ES 1601487 344106 General-purpose I/O Data Sheet 368 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 25 P14.7 26 Y Comment SLOW / PU1 / 1648485 VEXT / ES 185148 General-purpose I/O P14.8 SLOW / PU1 / 1695483 VEXT / ES 344106 General-purpose I/O 27 P14.9 LVDS_RX / FAST / PU1 / VEXT / ES 1770534 185148 General-purpose I/O 28 P14.10 LVDS_RX / FAST / PU1 / VEXT / ES 1864530 185148 General-purpose I/O 29 VDD Vx 1939581 344106 Supply Voltage 30 VSS Vx 1986579 185148 Supply Voltage 31 VEXT Vx 2033577 344106 Supply Voltage 32 VEXT Vx 2093499 185148 Supply Voltage 33 VEXT Vx 2164599 344106 Supply Voltage 34 VDDP3 Vx 2346597 185148 Supply Voltage 35 VDDP3 Vx 2453499 344106 Supply Voltage 36 VDDP3 Vx 2543499 185148 Supply Voltage 37 VDD Vx 2669499 344106 Supply Voltage 38 VDD Vx 2768499 185148 Supply Voltage 39 VDD Vx 2826477 344106 Supply Voltage 40 VSS Vx 2873475 185148 Supply Voltage 41 P13.0 LVDS_TX / FAST / PU1 / VEXT / ES6 2984976 344106 General-purpose I/O 42 P13.1 LVDS_TX / FAST / PU1 / VEXT / ES6 3078972 344106 General-purpose I/O 43 VSS Vx 3190473 185148 Supply Voltage 44 P13.2 LVDS_TX / FAST / PU1 / VEXT / ES6 3301974 344106 General-purpose I/O 45 P13.3 LVDS_TX / FAST / PU1 / VEXT / ES6 3395970 344106 General-purpose I/O 46 VDDP3 Vx 3507471 338112 Supply Voltage 47 VSS Vx 3554469 185148 Supply Voltage 48 VDD Vx 3645999 322614 Supply Voltage 49 VEXT Vx 3692997 175644 Supply Voltage 50 P12.0 SLOW / PU1 / 3767211 VFLEX / ES 322614 General-purpose I/O Data Sheet X 369 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 51 P12.1 52 Y Comment SLOW / PU1 / 3814209 VFLEX / ES 175644 General-purpose I/O P11.0 RFAST / PU1 / 3918213 VFLEX / ES 322614 General-purpose I/O 53 VFLEX Vx 3965211 175644 Supply Voltage 54 P11.1 RFAST / PU1 / 4040415 VFLEX / ES 338112 General-purpose I/O 55 VSS Vx 4087413 185148 Supply Voltage 56 P11.2 RFAST / PU1 / 4162617 VFLEX / ES 344106 General-purpose I/O 57 VDD Vx 4209615 175644 Supply Voltage 58 P11.4 RFAST / PU1 / 4325319 VFLEX / ES 322614 General-purpose I/O 59 VSS Vx 4412817 185148 Supply Voltage 60 P11.3 RFAST / PU1 / 4488021 VFLEX / ES 344106 General-purpose I/O 61 VFLEX Vx 4535019 175644 Supply Voltage 62 P11.6 RFAST / PU1 / 4610223 VFLEX / ES 344106 General-purpose I/O 63 VSS Vx 4657221 185148 Supply Voltage 64 P11.5 4704219 SLOW / RGMII_Input / PU1 / VFLEX / ES 338112 General-purpose I/O 65 P11.7 4756617 SLOW / RGMII_Input / PU1 / VFLEX / ES 175644 General-purpose I/O 66 P11.9 4807215 FAST / RGMII_Input / PU1 / VFLEX / ES 344106 General-purpose I/O 67 VFLEX Vx 4857813 185148 Supply Voltage 68 P11.8 4904811 SLOW / RGMII_Input / PU1 / VFLEX / ES 338112 General-purpose I/O 69 P11.10 4955409 FAST / RGMII_Input / PU1 / VFLEX / ES 185148 General-purpose I/O Data Sheet X 370 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 70 P11.11 71 Y Comment 5006007 FAST / RGMII_Input / PU1 / VFLEX / ES 344106 General-purpose I/O VSS Vx 5056605 185148 Supply Voltage 72 P11.12 5103603 FAST / RGMII_Input / PU1 / VFLEX / ES 344106 General-purpose I/O 73 VSS Vx 5211999 185148 Supply Voltage 74 VDD Vx 5312493 322614 Supply Voltage 75 P11.14 SLOW / PU1 / 5397291 VFLEX / ES 175644 General-purpose I/O 76 P11.13 SLOW / PU1 / 5444289 VFLEX / ES 322614 General-purpose I/O 77 P11.15 SLOW / PU1 / 5491287 VFLEX / ES 175644 General-purpose I/O 78 P10.0 SLOW / PU1 / 5565501 VEXT / ES 344106 General-purpose I/O 79 P10.1 FAST / PU1 / VEXT / ES 5612499 185148 General-purpose I/O 80 VDD Vx 5702499 322614 Supply Voltage 81 VSS Vx 5792499 185148 Supply Voltage 82 VDDSB (VDD) Vx 5839497 338112 Supply Voltage 83 VDDSB (VDD) Vx 5940999 338112 Supply Voltage 84 VSS Vx 5987997 185148 Supply Voltage 85 P10.2 FAST / PU1 / VEXT / ES 6068601 344106 General-purpose I/O 86 P10.3 FAST / PU1 / VEXT / ES 6115599 185148 General-purpose I/O 87 P10.4 FAST / PU1 / VEXT / ES 6165999 344106 General-purpose I/O 88 P10.5 SLOW / PU2 / 6216399 VEXT / ES 185148 General-purpose I/O 89 P10.6 SLOW / PU2 / 6266799 VEXT / ES 344106 General-purpose I/O 90 P10.7 SLOW / PU1 / 6317199 VEXT / ES 185148 General-purpose I/O 91 P10.8 SLOW / PU1 / 6367599 VEXT / ES 344106 General-purpose I/O 92 VSS Vx 6436899 185148 Supply Voltage 93 VEXT Vx 6537699 175644 Supply Voltage Data Sheet X 371 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 94 P02.0 FAST / PU1 / VEXT / ES 6611292 259700 General-purpose I/O 95 P02.1 SLOW / PU1 / 6611292 VEXT / ES 360500 General-purpose I/O 96 P02.2 FAST / PU1 / VEXT / ES 6611292 461300 General-purpose I/O 97 P02.3 SLOW / PU1 / 6611292 VEXT / ES 562100 General-purpose I/O 98 P02.4 FAST / PU1 / VEXT / ES 6611292 662900 General-purpose I/O 99 VSS Vx 6611292 772898 Supply Voltage 100 VDDSB (VDD) Vx 6452334 827896 Supply Voltage 101 VDDSB (VDD) Vx 6452334 972500 Supply Voltage 102 VSS Vx 6611292 1027498 Supply Voltage 103 P02.5 FAST / PU1 / VEXT / ES 6452334 1107500 General-purpose I/O 104 P02.6 FAST / PU1 / VEXT / ES 6611292 1170500 General-purpose I/O 105 P02.7 FAST / PU1 / VEXT / ES 6452334 1233500 General-purpose I/O 106 P02.8 SLOW / PU1 / 6611292 VEXT / ES 1296500 General-purpose I/O 107 VDD Vx 6458328 1377500 Supply Voltage 108 VDD Vx 6620796 1467500 Supply Voltage 109 VSS Vx 6611292 1602500 Supply Voltage 110 VSS Vx 6611292 1746500 Supply Voltage 111 VDDSB (VDD) Vx 6452334 1801498 Supply Voltage 112 VDDSB (VDD) Vx 6452334 1962500 Supply Voltage 113 VSS Vx 6611292 2017498 Supply Voltage 114 P02.9 SLOW / PU1 / 6473826 VEXT / ES 2124500 General-purpose I/O 115 P02.10 SLOW / PU1 / 6620796 VEXT / ES 2187500 General-purpose I/O 116 P02.11 SLOW / PU1 / 6458328 VEXT / ES 2250500 General-purpose I/O 117 VEXT Vx 6620796 2313500 Supply Voltage 118 P01.3 SLOW / PU1 / 6458328 VEXT / ES 2376500 General-purpose I/O 119 VSS Vx 6611292 2431498 Supply Voltage 120 VSS Vx 6611292 2529500 Supply Voltage 121 VDDSB (VDD) Vx 6458328 2584498 Supply Voltage Data Sheet 372 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name 122 X Y Comment VDDSB (VDD) Vx 6458328 2718500 Supply Voltage 123 VSS Vx 6611292 2773498 Supply Voltage 124 VDD Vx 6458328 2907500 Supply Voltage 125 VSS Vx 6611292 2970500 Supply Voltage 126 VDD Vx 6458328 3033500 Supply Voltage 127 VEXT Vx 6620796 3096500 Supply Voltage 128 P01.4 SLOW / PU1 / 6473826 VEXT / ES 3159500 General-purpose I/O 129 P01.5 SLOW / PU1 / 6620796 VEXT / ES 3222500 General-purpose I/O 130 P01.6 FAST / PU1 / VEXT / ES 6473826 3285500 General-purpose I/O 131 P01.7 FAST / PU1 / VEXT / ES 6473826 3411500 General-purpose I/O 132 VSS Vx 6611292 3537500 Supply Voltage 133 VSS — 6611292 3672500 Supply Voltage 134 P00.0 FAST / PU1 / VEXT / ES 6452334 3807500 General-purpose I/O 135 VDD Vx 6620796 3942500 Supply Voltage 136 VDD — 6620796 4055000 Supply Voltage 137 P00.1 SLOW / PU1 / 6611292 VEXT / ES 4209430 General-purpose I/O 138 P00.2 SLOW / PU1 / 6433794 VEXT / ES1 4264430 General-purpose I/O 139 P00.3 SLOW / PU1 / 6611292 VEXT / ES1 4319428 General-purpose I/O 140 P00.4 SLOW / PU1 / 6433794 VEXT / ES1 4374428 General-purpose I/O 141 P00.5 SLOW / PU1 / 6611292 VEXT / ES1 4429426 General-purpose I/O 142 P00.6 SLOW / PU1 / 6433794 VEXT / ES1 4484426 General-purpose I/O 143 P00.7 SLOW / PU1 / 6611292 VEXT / ES1 4539424 General-purpose I/O 144 P00.8 SLOW / PU1 / 6433794 VEXT / ES1 4594424 General-purpose I/O 145 P00.9 SLOW / PU1 / 6611292 VEXT / ES1 4649422 General-purpose I/O 146 P00.10 SLOW / PU1 / 6433794 VEXT / ES1 4704422 General-purpose I/O 147 P00.11 SLOW / PU1 / 6611292 VEXT / ES1 4759420 General-purpose I/O Data Sheet Pad Type 373 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 148 P00.12 149 Y Comment SLOW / PU1 / 6433794 VEXT / ES1 4814420 General-purpose I/O VSS Vx 6611292 4869418 Supply Voltage 150 VSS Vx 6611292 4968518 Supply Voltage 151 VDD Vx 6611292 5067616 Supply Voltage 152 VDD Vx 6611292 5166716 Supply Voltage 153 VEXT Vx 6611292 5265814 Supply Voltage 154 VAREF3 Vx 6611292 5404730 Supply Voltage 155 VAGND3 Vx 6611292 5503828 Supply Voltage 156 VAREF2 Vx 6433794 5558828 Supply Voltage 157 VAGND2 Vx 6611292 5613826 Supply Voltage 158 AN47 D / HighZ / VDDM 6611292 5712926 Analog Input 47 159 AN46 D / HighZ / VDDM 6433794 5767924 Analog Input 46 160 AN45 D / HighZ / VDDM 6611292 5822924 Analog Input 45 161 AN44 D / HighZ / VDDM 6433794 5877922 Analog Input 44 162 AN43 D / HighZ / VDDM 6611292 5932922 Analog Input 43 163 AN42 D / HighZ / VDDM 6433794 5987920 Analog Input 42 164 AN41 D / HighZ / VDDM 6611292 6042920 Analog Input 41 165 AN40 D / HighZ / VDDM 6433794 6097918 Analog Input 40 166 AN39/P40.9 S / HighZ / VDDM 6611292 6262916 Analog Input 39 167 AN38/P40.8 S / HighZ / VDDM 6433794 6317914 Analog Input 38 168 AN37/P40.7 S / HighZ / VDDM 6611292 6372914 Analog Input 37 169 AN36/P40.6 S / HighZ / VDDM 6433794 6427912 Analog Input 36 170 AN35 D / HighZ / VDDM 6611292 6482912 Analog Input 35 171 AN34 D / HighZ / VDDM 6433794 6537910 Analog Input 34 172 AN33/P40.5 S / HighZ / VDDM 6611292 6592910 Analog Input 33 Data Sheet X 374 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 173 AN32/P40.4 S / HighZ / VDDM 6433794 6647908 Analog Input 32 174 AN31 D / HighZ / VDDM 6611292 6702908 Analog Input 31 175 AN30 D / HighZ / VDDM 6433794 6757906 Analog Input 30 176 AN29/P40.14 S / HighZ / VDDM 6611292 6812906 Analog Input 29 177 AN28/P40.13 S / HighZ / VDDM 6433794 6867904 Analog Input 28 178 AN27/P40.3 S / HighZ / VDDM 6611292 6922904 Analog Input 27 179 AN26/P40.2 S / HighZ / VDDM 6433794 6977902 Analog Input 26 180 AN25/P40.1 S / HighZ / VDDM 6611292 7032902 Analog Input 25 181 AN24/P40.0 S / HighZ / VDDM 6611292 7156300 Analog Input 24 182 AN23 D / HighZ / VDDM 6526440 7241292 Analog Input 23 183 AN22 D / HighZ / VDDM 6403140 7241292 Analog Input 22 184 AN21 D / HighZ / VDDM 6348141 7063794 Analog Input 21 185 AN20 D / HighZ / VDDM 6293142 7241292 Analog Input 20 186 AN19/P40.12 S / HighZ / VDDM 6238143 7063794 Analog Input 19 187 AN18/P40.11 S / HighZ / VDDM 6183144 7241292 Analog Input 18 188 AN17/P40.10 S / HighZ / VDDM 6128145 7063794 Analog Input 17 189 AN16 D / HighZ / VDDM 6073146 7241292 Analog Input 16 190 AN15 D / HighZ / VDDM 6018147 7063794 Analog Input 15 191 VAGND1 Vx 5963148 7241292 Supply Voltage 192 VAREF1 Vx 5908149 7063794 Supply Voltage 193 VAGND0 Vx 5853150 7241292 Supply Voltage 194 VAREF0 Vx 5798151 7063794 Supply Voltage 195 VSSM Vx 5743152 7241292 Supply Voltage 196 VDDM Vx 5688153 7063794 Supply Voltage Data Sheet 375 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 197 VSSM Vx 5633154 7241292 Supply Voltage 198 VDDM Vx 5578155 7063794 Supply Voltage 199 VSSM Vx 5523156 7241292 Supply Voltage 200 VDDM Vx 5468157 7063794 Supply Voltage 201 AN14 D / HighZ / VDDM 5413158 7241292 Analog Input 14 202 AN13 D / HighZ / VDDM 5358159 7063794 Analog Input 13 203 AN12 D / HighZ / VDDM 5303160 7241292 Analog Input 12 204 AN11 D / HighZ / VDDM 5248161 7063794 Analog Input 11 205 AN10 D / HighZ / VDDM 5193162 7241292 Analog Input 10 206 AN9 D / HighZ / VDDM 5138163 7063794 Analog Input 9 207 AN8 D / HighZ / VDDM 5083164 7241292 Analog Input 8 208 AN7 D / HighZ / VDDM 5028165 7063794 Analog Input 7 209 AN6 D / HighZ / VDDM 4973166 7241292 Analog Input 6 210 AN5 D / HighZ / VDDM 4918167 7063794 Analog Input 5 211 AN4 D / HighZ / VDDM 4863168 7241292 Analog Input 4 212 AN3 D / HighZ / VDDM 4808169 7063794 Analog Input 3 213 AN2 D / HighZ / VDDM 4753170 7241292 Analog Input 2 214 AN1 D / HighZ / VDDM 4698171 7063794 Analog Input 1 215 AN0 D / HighZ / VDDM 4643172 7241292 Analog Input 0 216 VDD Vx 4525070 7241292 Supply Voltage 217 VDD Vx 4467501 7082334 Supply Voltage 218 VSS Vx 4386501 7241292 Supply Voltage 219 AGBTCLKN (VSS) AGBT_CLK / VEXT 4230531 7250841 Input PAD (negative pole) for the external 100 MHz differential clock. AGBT Input; (TC3xx devices without AGBT: VSS) Data Sheet 376 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 220 AGBTCLKP (VSS) AGBT_CLK / VEXT 4149441 7250841 Input PAD (positive pole) for the external 100 MHz differential clock. AGBT Input; (TC3xx devices without AGBT: VSS) 221 VEXT Vx 4068531 7241336 Supply Voltage 222 VSS Vx 3979071 7241337 Supply Voltage 223 AGBTTXN (VSS) AGBT_TX / VEXT 3879599 7250841 Off-chip driver output PAD of the 2.5Gbps transmitter, negative pole AGBT Output; (TC3xx devices without AGBT: VSS) 224 AGBTTXP (VSS) AGBT_TX / VEXT 3798509 7250841 Off-chip driver output PAD of the 2.5Gbps transmitter, positive pole AGBT Output; (TC3xx devices without AGBT: VSS) 225 AGBTERR (VSS) FAST / PD / VEXT 3608311 7250702 Input PAD for CRC error from FPGA. AGBT Input; (TC3xx devices without AGBT: VSS) 226 VSS Vx 3464001 7241292 Supply Voltage 227 VDD Vx 3417003 7082334 Supply Voltage 228 VDD Vx 3295503 7241292 Supply Voltage 229 VEVRSB Vx 3189501 7082334 Supply Voltage 230 VEVRSB Vx 3125997 7241292 Supply Voltage 231 P33.0 SLOW / PU1 / 3078999 VEVRSB / ES5 7082334 General-purpose I/O 232 VSS Vx 3032001 7241292 Supply Voltage 233 VDD Vx 2933001 7082334 Supply Voltage 234 VSS Vx 2886003 7241292 Supply Voltage 235 P33.1 SLOW / PU1 / 2781495 VEVRSB / ES5 7082334 General-purpose I/O 236 P33.2 SLOW / PU1 / 2734497 VEVRSB / ES5 7241292 General-purpose I/O 237 P33.3 SLOW / PU1 / 2687499 VEVRSB / ES5 7082334 General-purpose I/O 238 P34.1 SLOW / PU1 / 2640501 VEVRSB / ES5 7250796 General-purpose I/O Data Sheet 377 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 239 VDD Vx 2541501 7082334 Supply Voltage 240 VSS Vx 2494503 7241292 Supply Voltage 241 P33.4 SLOW / PU1 / 2380491 VEVRSB / ES5 7082334 General-purpose I/O 242 P34.2 SLOW / PU1 / 2333493 VEVRSB / ES 7250796 General-purpose I/O 243 P33.5 SLOW / PU1 / 2286495 VEVRSB / ES5 7082334 General-purpose I/O 244 P34.3 SLOW / PU1 / 2239497 VEVRSB / ES 7250796 General-purpose I/O 245 P33.6 SLOW / PU1 / 2192499 VEVRSB / ES5 7082334 General-purpose I/O 246 P34.4 SLOW / PU1 / 2145501 VEVRSB / ES 7250796 General-purpose I/O 247 VDD_1V2_FL CS Vx 2098503 7082334 Supply Voltage 248 VSS Vx 2051505 7241292 Supply Voltage 249 P34.5 FAST / PU1 / 1947195 VEVRSB / ES 7250796 General-purpose I/O 250 P33.7 SLOW / PU1 / 1900197 VEVRSB / ES5 7082334 General-purpose I/O 251 P33.8 FAST / HighZ / 1853199 VEVRSB 7241292 General-purpose I/O 252 P33.9 SLOW / PU1 / 1806201 VEVRSB / ES5 7082334 General-purpose I/O 253 VSS Vx 1713501 7241292 Supply Voltage 254 VDD Vx 1666503 7082334 Supply Voltage 255 VEVRSB Vx 1578519 7250796 Supply Voltage 256 P33.10 FAST / PU1 / VEVRSB / ES5 1531521 7082334 General-purpose I/O 257 P33.14 FAST / PU1 / VEVRSB / ES5 1451907 7250796 General-purpose I/O 258 P33.11 FAST / PU1 / VEVRSB / ES5 1352907 7241292 General-purpose I/O Data Sheet 378 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 259 P33.15 260 P33.12 261 Y Comment SLOW / PU1 / 1305909 VEVRSB / ES5 7088328 General-purpose I/O FAST / PU1 / VEVRSB / ES5 1258911 7241292 General-purpose I/O P33.13 FAST / PU1 / VEVRSB / ES5 1211913 7082334 General-purpose I/O 262 VSS Vx 1164915 7241292 Supply Voltage 263 VDD Vx 1038501 7082334 Supply Voltage 264 VSS Vx 977301 7241292 Supply Voltage 265 VSS Vx 876501 7241292 Supply Voltage 266 P32.0 SLOW / PU1 / 771597 VEXT / ES 7241292 General-purpose I/O 267 VGATE1N Vx 724599 7082334 DCDC N ch. MOSFET gate driver output 268 P32.1 SLOW / PU1 / 677601 VEXT / ES 7241292 General-purpose I/O 269 VGATE1P Vx 627201 7082334 DCDC P ch. MOSFET gate driver output 270 P32.2 SLOW / PU1 / 576801 VEXT / ES 7241292 General-purpose I/O 271 P32.3 SLOW / PU1 / 526401 VEXT / ES 7082334 General-purpose I/O 272 P32.4 FAST / PU1 / VEXT / ES 476001 7241292 General-purpose I/O 273 P32.5 SLOW / PU1 / 425601 VEXT / ES 7088328 General-purpose I/O 274 P32.6 SLOW / PU1 / 356301 VEXT / ES 7250796 General-purpose I/O 275 P32.7 SLOW / PU1 / 255951 VEXT / ES 7250796 General-purpose I/O 276 VDD Vx 175644 7169301 Supply Voltage 277 VSS Vx 185148 7068501 Supply Voltage 278 VSS Vx 185148 6967701 Supply Voltage 279 VEXT Vx 185148 6866901 Supply Voltage 280 P23.0 SLOW / PU1 / 344106 VEXT / ES 6766101 General-purpose I/O 281 P23.1 FAST / PU1 / VEXT / ES 6719103 General-purpose I/O Data Sheet X 185148 379 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 282 P23.2 283 Y Comment RFAST / PU1 / 344106 VFLEX2 / ES 6616683 General-purpose I/O VFLEX Vx 175644 6569685 Supply Voltage 284 P23.3 RFAST / PU1 / 344106 VFLEX2 / ES 6494481 General-purpose I/O 285 VSS Vx 185148 6447483 Supply Voltage 286 P23.4 RFAST / PU1 / 344106 VFLEX2 / ES 6372279 General-purpose I/O 287 VDD Vx 175644 6325281 Supply Voltage 288 P22.12 RFAST / PU1 / 322614 VFLEX2 / ES 6209577 General-purpose I/O 289 VSS Vx 185148 6122079 Supply Voltage 290 P22.10 RFAST / PU1 / 338112 VFLEX2 / ES 6046875 General-purpose I/O 291 VFLEX Vx 175644 5999877 Supply Voltage 292 P22.11 RFAST / PU1 / 338112 VFLEX2 / ES 5924673 General-purpose I/O 293 VSS Vx 185148 5877675 Supply Voltage 294 P22.7 338112 SLOW / RGMII_Input / PU1 / VFLEX2 / ES 5830677 General-purpose I/O 295 P23.5 185148 FAST / RGMII_Input / PU1 / VFLEX2 / ES 5764059 General-purpose I/O 296 P23.7 338112 SLOW / RGMII_Input / PU1 / VFLEX2 / ES 5713461 General-purpose I/O 297 VFLEX Vx 185148 5662863 Supply Voltage 298 P23.6 338112 SLOW / RGMII_Input / PU1 / VFLEX2 / ES 5615865 General-purpose I/O 299 P22.4 175644 SLOW / RGMII_Input / PU1 / VFLEX2 / ES 5565267 General-purpose I/O 300 P22.6 338112 SLOW / RGMII_Input / PU1 / VFLEX2 / ES 5514669 General-purpose I/O Data Sheet X 380 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 301 VSS Vx 185148 5464071 Supply Voltage 302 P22.5 338112 SLOW / RGMII_Input / PU1 / VFLEX2 / ES 5417073 General-purpose I/O 303 P22.8 SLOW / PU1 / 175644 VFLEX2 / ES 5366475 General-purpose I/O 304 P22.9 SLOW / PU1 / 322614 VFLEX2 / ES 5319477 General-purpose I/O 305 P22.0 185148 LVDS_TX / FAST / PU1 / VFLEX2 / ES6 5207976 General-purpose I/O 306 P22.1 LVDS_TX / 185148 FAST / PU1 / VFLEX2 / ES6 5113980 General-purpose I/O 307 VDDP_3V3_F — LANA1 344106 4966263 Supply Voltage 308 VSS Vx 185148 4919265 Supply Voltage 309 VDD Vx 338112 4872267 Supply Voltage 310 P22.2 LVDS_TX / FAST / PU1 / VEXT / ES6 344106 4760766 General-purpose I/O 311 P22.3 LVDS_TX / FAST / PU1 / VEXT / ES6 344106 4666770 General-purpose I/O 312 VEXT Vx 185148 4555269 Supply Voltage 313 VEXT Vx 344106 4508271 Supply Voltage 314 VEXT Vx 185148 4461273 Supply Voltage 315 RESERVED Vx 185148 4364001 Must be bonded to VSS 316 VDD Vx 344106 4317003 Supply Voltage 317 VSS Vx 185148 4256001 Supply Voltage 318 VDD Vx 344106 4184001 Supply Voltage 319 VDD Vx 362646 4071951 Supply Voltage 320 VSS — 185148 4022541 Supply Voltage 321 XTAL1 XTAL / VEXT 185148 3865392 XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. 322 XTAL2 XTAL / VEXT 185148 3766392 XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT 323 VSS — 185148 3609243 Supply Voltage Data Sheet 381 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 324 VEXT Vx 362646 3559833 Supply Voltage 325 VEXT Vx 185148 3423501 Supply Voltage 326 VDD Vx 185148 3261501 Supply Voltage 327 VSS Vx 185148 3135501 Supply Voltage 328 P21.0 LVDS_RX / FAST / PU1 / VEXT / ES 344106 3044646 General-purpose I/O 329 P21.1 LVDS_RX / FAST / PU1 / VEXT / ES 344106 2950650 General-purpose I/O 330 VSS Vx 185148 2875599 Supply Voltage 331 P21.2 LVDS_RX / FAST / PU1 / VEXT / ES 344106 2800548 General-purpose I/O 332 P21.3 LVDS_RX / FAST / PU1 / VEXT / ES 344106 2706552 General-purpose I/O 333 VSS Vx 185148 2631501 Supply Voltage 334 VDD Vx 185148 2519001 Supply Voltage 335 P21.4 LVDS_TX / FAST / PU1 / VEXT / ES6 344106 2363976 General-purpose I/O 336 P21.5 LVDS_TX / FAST / PU1 / VEXT / ES6 344106 2269980 General-purpose I/O 337 DAPE2 FAST / PD2 / VEXT 175644 2158479 DAPE: DAPE2 Data I/O DAPE: DAPE2 Data I/O (PD Devices: VSS) 338 P21.6/TDI FAST / PD / PU2 / VEXT / ES3 344106 2111481 General-purpose I/O PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O. 339 DAPE1 FAST / PD2 / VEXT 175644 2064483 DAPE: DAPE1 Data I/O DAPE: DAPE1 Data I/O (PD Devices: VSS) 340 TMS FAST / PD2 / VEXT 344106 2017485 JTAG Module State Machine Control Input TMS: JTAG Module State Machine Control Input. DAP: DAP1 Data I/O. Data Sheet 382 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type X Y Comment 341 DAPE0 FAST / PD2 / VEXT 175644 1970487 DAPE: DAPE0 Clock Input DAPE: DAPE0 clock input (PD Devices: NC) 342 P21.7/TDO FAST / PU2 / VEXT / ES4 344106 1923489 General-purpose I/O DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O. 343 VSS Vx 185148 1876491 Supply Voltage 344 TRST FAST / PU2 / VEXT 344106 1829493 JTAG Module Reset/Enable Input TRST_N: JTAG Module Reset/Enable Input. DAPE: DAPE0 Clock Input 345 TCK FAST / PD2 / VEXT 185148 1782495 JTAG Module Clock Input TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input. 346 P20.0 FAST / PU1 / VEXT / ES 344106 1735497 General-purpose I/O 347 VEXT Vx 185148 1688499 Supply Voltage 348 P20.1 SLOW / PU1 / 344106 VEXT / ES 1641501 General-purpose I/O 349 VSS Vx 185148 1542501 Supply Voltage 350 VDD Vx 185148 1434501 Supply Voltage 351 P20.2 S / PU / VEXT 344106 1334493 General-purpose I/O This pin is latched at power on reset release to enter test mode. 352 P20.3 SLOW / PU1 / 185148 VEXT / ES 1287495 General-purpose I/O 353 ESR1 FAST / PU1 / VEXT 1240497 ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin Data Sheet 344106 383 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Table 2-71 Pad List (cont’d) Number Pad Name Pad Type 354 PORST 355 Y Comment PORST / PD / 185148 VEXT 1193499 PORST pin Power On Reset Input. Additional strong PD in case of power fail. ESR0 FAST / OD / VEXT 344106 1146501 ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin 356 VSS Vx 185148 1056501 Supply Voltage 357 VDD Vx 344106 944001 Supply Voltage 358 VDD Vx 185148 831501 Supply Voltage 359 P20.6 SLOW / PU1 / 344106 VEXT / ES 725499 General-purpose I/O 360 P20.7 FAST / PU1 / VEXT / ES 185148 678501 General-purpose I/O 361 P20.8 FAST / PU1 / VEXT / ES 344106 628101 General-purpose I/O 362 P20.9 FAST / PU1 / VEXT / ES 185148 577701 General-purpose I/O 363 P20.10 FAST / PU1 / VEXT / ES 344106 527301 General-purpose I/O 364 P20.11 FAST / PU1 / VEXT / ES 185148 476901 General-purpose I/O 365 P20.12 FAST / PU1 / VEXT / ES 344106 426501 General-purpose I/O 366 P20.13 FAST / PU1 / VEXT / ES 185148 357201 General-purpose I/O 367 P20.14 FAST / PU1 / VEXT / ES 185148 256401 General-purpose I/O Data Sheet X 384 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Pad Position Configuration of Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is provided by Figure 2-71. This statement is also valid for next/nearest neighbor pads. This statement is also valid for next/nearest neighbor pads. In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads (ACNP) has to be defined. Finding close-neighbor pads. The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends. Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one neighbor. Similarly, each pad has two indirect (second) neighbors unless it or its first neighbor is located at the end of the edge. These first and second neighbors we will collectively call Close-Neighbor pads. Therefore each pad has 2 to 4 close-neighbor pads. Finding close-neighbors can be done with the following sequence: 1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-71. 2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-71 is sorted by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might end up with less than 4 close-neighbors). Defining active pads: Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name. Figuring out number of active close-neighbor pads follow next rules: - If the first neighbor is active, then we count it and also check if second neighbor (on the same side of selected pad) is active. - If the first neighbor is not active, then we do not check the second on the same side. Data Sheet 385 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Legend 2.6 Legend The data in this chapter 2 for TE and TX match with the file TC37xed_IO_Spirit_v2.0.0.1.25.xml. Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB) O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function) O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column “Buffer Type”: RFAST = Pad class RFAST (5V/3.3V) FAST = Pad class FAST (5V/3.3V) SLOW = Pad class SLOW (5V/3.3V) LVDS_TX = Pad class LVDS Transmit LVDS_RX = Pad class LVDS Receive S = Pad class S (Analog Input overlayed with General Purpose Input) D = Pad class D (Analog Input) Porst = Porst input Pad XTAL1 = XTAL1 input Pad XTAL2 = XTAL2 input Pad PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) PU2 = with pull-up device connected during startup and reset, HighZ in Standby mode PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) PD2 = with pull-down device connected during startup and reset, HighZ in Standby mode OD = open drain during reset (PORST = 0) ES = Supports Emergency Stop ES1 = ES. ES can be overruled by VADC, control via P00_PCSR ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over CAN message ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter PMS, HWCFG[6]. Data Sheet 386 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step TC37xEXT Pin Definition and Functions Legend ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via the control register P33_PCSR and P34_PCSR ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event Data Sheet 387 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Parameter Interpretation 3 Electrical Specification 3.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC37xEXT and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”: • CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC37xEXT and must be regarded for a system design. • SR Such parameters indicate System Requirements which must be provided by the microcontroller system in which the TC37xEXT designed in. Data Sheet 388 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Absolute Maximum Ratings 3.2 Absolute Maximum Ratings Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3-1 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Storage Temperature TST SR -65 - 150 °C upto 65h @ TJ = 150°C Voltage at VDD power supply pins with respect to VSS 1) 2) VDD SR - - 1.65 V upto 2.8h - - 1.45 V upto 72h Voltage at VDDP3 power supply VDDP3 SR pins with respect to VSS - - 4.43 V Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS - - 6.75 V upto 2.8h - - 5.6 V upto 72h Voltage on all analog and class VIN SR S input pins with respect to VSS -0.7 - 6.75 V VIN SR -0.7 - 6.75 V -10 - 10 mA -100 - 100 mA VDDM SR 3) Voltage on all other input pins with respect to VSS 3) Input current on any pin during IIN SR overload condition 4) 5) Absolute maximum sum of all input circuit currents during overload condition. 4) ΣIIN SR 1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise and fall times are related to the system capacities and coils. 2) Due to EVRC output voltage oscillation during switch off phase VDD can drop down to -0.72V. For VDD an input level down to -0.72V during switch off phase will not cause any damage or reliability problem. 3) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin Reliability in Overload for the affected pad(s) are not violated. 4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may damage the device. 5) The specified min. and max. values represent the current limits, which have to be maintained, in case of a short circuit condition on the output of any Fast, RFast, Slow and Class S pad, not being used during operation. This cover also output currents due to switching in operation for CL=200pF. Data Sheet 389 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Pin Reliability in Overload 3.3 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. The following table defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: • full operation life-time is not exceeded • Operating Conditions are met for – pad supply levels – temperature If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Table 3-2 Overload Parameters Parameter Symbol Input current on any digital pin IIN during overload condition Values Min. Typ. Max. -5 - 5 -15 1) - 15 1) Unit Note / Test Condition mA except LVDS pins mA except LVDS pins; limited to max. 20 pulses with 1ms pulse length Input current on LVDS pin during overload condition IINLVDS -3 - 3 mA Input current on analog input pin during overload condition IINANA -3 - 3 mA -5 - 5 mA -20 - 20 mA -100 - 100 mA VSS - 2 - VEXT/FLEX/F V Absolute sum of all analog IINSA input currents for analog inputs during overload conditon Absolute maximum sum of all input circuit currents during overload condition (digital and analog combined) ΣIINS Signal voltage over/undershoot VOUS at GPIOs LEX2 +2 limited to 60h over lifetime limited to 60h over lifetime; Valid for non LVDS and analoge pads Sum of all inactive device pin currents IIDS -100 - 100 mA Static pin output current IOUT CC - - 2.5 mA 100% duty cycle; output driver = medium - - 5 mA 100% duty cycle; output driver = strong Data Sheet 390 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Pin Reliability in Overload Table 3-2 Overload Parameters (cont’d) Parameter Overload coupling factor for digital inputs, negative Overload coupling factor for digital inputs, positive Overload coupling factor for analog inputs, negative 2) Data Sheet Symbol KOVDN CC KOVDP CC KOVAN CC Values Unit Note / Test Condition Min. Typ. Max. - - 3*10-4 Overload injected on GPIO non LVDS pad and affecting neighbor fast pads; -5mA < IIN < 0mA - - 2*10-3 Overload injected on GPIO non LVDS pad and affecting neighbor slow pads VGASTE1N and VGATE1P; -5mA < IIN < 0mA - - 1*10-4 Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -5mA < IIN < 0mA - - 0.8 Overload injected on LVDS RX pad and affecting neighbor LVDS pads - - 0.5 Overload injected on LVDS TX pad and affecting neighbor LVDS pads - - 1.5*10-3 Overload injected on GPIO non LVDS pad and affecting neighbor GPIO non LVDS pads - - 1 Overload injected on LVDS RX pad and affecting neighbor LVDS pads - - 5*10-3 Overload injected on LVDS TX pad and affecting neighbor LVDS pads - - 1*10-4 Analog inputs overlaid with slow pads or pull down diagnostics; 5mA < IIN < 0mA - - 1*10-5 else; -5mA < IIN < 0mA 391 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Pin Reliability in Overload Table 3-2 Overload Parameters (cont’d) Parameter Overload coupling factor for analog inputs, positive 2) Symbol KOVAP CC Values Unit Min. Typ. Max. - - 2*10-4 Note / Test Condition Analoge inputs overlaid with slow pads or pull down diagnostics; 0mA < IIN < 5mA 2*10-5 else; 0mA < IIN < 5mA 1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters. - - 2) Overload coupling on analog inputs is caused by parasitic effects between pads, input multiplexers and surrounding structures. The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to several channels. Data Sheet 392 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Operating Conditions 3.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC37xEXT. All parameters specified in the following tables refer to these operating conditions, unless otherwise noticed. Digital supply voltages applied to the TC37xEXT must be static regulated voltages. All parameters specified in the following tables refer to these operating conditions (see table below), unless otherwise noticed in the Note / Test Condition column. Table 3-3 Operating Conditions Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition SRI frequency fSRI SR - - 300 MHz CPU Frequency (All CPUs) fCPUx SR - - 300 MHz PLL0 output frequency fPLL0 SR 20 - 300 MHz SPB frequency fSPB SR - - 100 MHz FSI2 frequency fFSI2 SR - - 300 MHz FSI frequency fFSI SR 20 - 100 MHz GTM frequency fGTM SR - - 200 MHz STM frequency fSTM SR - - 100 MHz ERAY frequency fERAY SR - 80 - MHz BBB frequency fBBB SR - - 150 MHz VADC frequency fADC SR - - 160 MHz ASCLIN Operating Frequency fASCLINx SR - - 200 MHz CAN frequency fCAN SR - - 80 MHz I2C frequency fI2C SR - - 100 MHz Operating MSC Frequency fMSC SR - - 200 MHz PLL1 output frequency from PER PLL fPLL1 SR 20 - 320 MHz PLL2 output frequency from PER PLL fPLL2 SR 20 - 200 MHz QSPI Frequency fQSPI SR - - 200 MHz ADAS clock frequency fADAS CC 200 - 300 MHz MCANH frequency fMCANH CC - - 100 MHz GETH frequency fGETH CC 150 - 200 MHz Ambient Temperature TA SR -40 - 125 °C valid for all SAK products -40 - 150 °C valid for all SAL products with package -40 - 170 °C valid for all SAL products without package Data Sheet 393 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Operating Conditions Table 3-3 Operating Conditions (cont’d) Parameter Junction Temperature Symbol TJ SR Values Unit Note / Test Condition Min. Typ. Max. -40 - 150 °C valid for all SAK products -40 - 170 °C valid for all SAL products Core Supply Voltage VDD SR 1.125 1) 1.25 1.375 2) V ADC analog supply voltage VDDM SR 2.97 5.0 5.5 3) V 4.5 5.0 5.5 3) V Nominal 5V Pad / Port Pin supply range. 5V pad parameters are valid. 2.97 3.3 3.63 V Nominal 3.3V Pad / Port Pin supply range with VDDP3 supplied externally and EVR33 inactive. 3.3V pad parameters are valid. 3.6 - 4.5 V Flash configured in cranking mode; Flash read operation with reduced performance. EVR33 active in low voltage mode. 3.3V pad parameters are valid. 2.97 - 3.6 V Incase EVR33 is active, Flash configured in sleep mode and execution switched to RAM. 3.3V pad parameters are valid. 2.97 - 4.0 V 3.3V pad parameters are valid; also vaild for Digital external supply voltage for pads and EVR Digital supply voltage for Flex port VEXT SR VFLEX SR VFLEX2 4.5 5.0 5.5 3) V 5V pad parameters are valid; also vaild for VFLEX2 Digital supply voltage for Flash VDDP3 SR Digital ground voltage VSS SR Analog ground voltage for VDDM VSSM CC Data Sheet 4) 2.97 3.3 3.63 2.6 - 3.63 V 0 - - V -0.1 0 0.1 V 394 OPEN MARKET VERSION V Flash configured in cranking mode; Flash read operation with reduced performance. V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Operating Conditions Table 3-3 Operating Conditions (cont’d) Parameter Symbol Values Min. 5) Unit Typ. Max. - 5.5 V Note / Test Condition Digital external supply voltage for EVR and during Standby mode VEVRSB SR 2.97 Voltage to ensure defined pad states VDDPPA CC 1.3 6) - - V 2.97 3.3 3.63 V 3.3V pad parameters are valid 3.63 5 5.5 V 5V pad parameters are valid Digital supply voltage for Flex2 VFLEX2 SR port 1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters. 2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 3) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 4) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB supply pin. 6) HWCFG[6] pin is latched and pull-up or tristate is activated at Port pins when VEXT has reached this level. Limitation of Supply Voltage over Time The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime. The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. Table 3-4 Example Voltage Profile VEXT/FLEX/DDM= Duration [h] 5.4 V < VEXT/FLEX/DDM ≤ 5.5 V ≤ 5% of lifetime 5.15 V < VEXT/FLEX/DDM ≤ 5.4 V ≤ 15% of lifetime 4.85 V < VEXT/FLEX/DDM ≤ 5.15 V ≤ 60% of lifetime 4.6 V < VEXT/FLEX/DDM ≤ 4.85 V ≤ 15% of lifetime 4.5 V < VEXT/FLEX/DDM ≤ 4.6 V ≤ 5% of lifetime The maximum operation voltage for VDD supply rails is limited over the complete lifetime. The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. Table 3-5 Example Voltage Profile VDD= Duration [h] 1.325 V < VDD ≤ 1.375 V ≤ 5% of lifetime 1.275 V < VDD ≤ 1.325 V ≤ 15% of lifetime 1.225 V < VDD ≤ 1.275 V ≤ 60% of lifetime Data Sheet 395 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Operating Conditions Table 3-5 Example Voltage Profile VDD= Duration [h] 1.175 V < VDD ≤ 1.225 V ≤ 15% of lifetime 1.125 V < VDD ≤ 1.175 V ≤ 5% of lifetime Data Sheet 396 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads 3.5 5 V / 3.3 V switchable Pads Pad classes slow GPIO and fast GPIO support both Automotive Level (AL) or TTL level (TTL) operation. Parameters are defined for AL operation and degrade in TTL operation. Table 3-6 PORST Pad Parameter PORST pad Output current Symbol IPORST CC Values Min. Typ. Max. 13 - - Unit Note / Test Condition mA VEXT = 2.97V; VPORST = 0.9V Spike filter always blocked pulse duration tSF1 CC - - 80 ns Spike filter pass-through blocked pulse duration tSF2 CC 260 - - ns without additional PORST Digtial Filter active (PORSTDF = 0). Input hysteresis 1) HYS CC 0.055 * - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) - |130| µA VIH; TTL (degraded, VEXT Pull-down current 2) IPDL CC - used for CIF) |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current Input high voltage level Input low voltage level Pin capacitance IOZ CC VIH SR VIL SR CIO CC -450 - 450 nA TJ≤150°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT) -500 - 500 nA TJ≤150°C ;else -900 - 900 nA TJ≤170°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT) -950 - 950 nA TJ≤170°C ; else 1.4 - - V TTL (degraded, used for CIF); VEXT = 2.97V 2.0 - - V TTL; VEXT = 4.5V - - 0.5 V TTL (degraded, used for CIF); VEXT = 2.97V - - 0.8 V TTL; VEXT = 4.5V - 2 3 pF in addition 2.5pF from package to be added 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Data Sheet 397 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-7 Fast 5V GPIO Parameter Symbol On-Resistance of pad output Rise / Fall time 1) 2) RDSON CC tRF CC Values Unit Note / Test Condition Min. Typ. Max. 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA 1.6 - 3.2 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX/FLEX2/EVRSB to 0.8 * VEXT/FLEX/FLEX2/EVRSB 4+0.55*C 4+0.75*C 12+1.0*C ns L L L 1.0+0.18* 2.5+0.27* 5.0+0.35* ns CL CL CL 0.5+0.08* 0.5+0.11* 1.0+0.17* ns CL CL CL driver = medium; CL≤200pF driver = strong edge = medium; CL≤200pF driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns Input frequency fIN CC - - 160 MHz 0.09 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL |30| - - µA VIH; AL or TTL - - |130| µA VIL; AL or TTL - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Input hysteresis 3) HYS CC VEXT/FLEX/F LEX2/EVRSB 0.075 * VEXT/FLEX/F LEX2/EVRSB Pull-up current 4) Pull-down current 5) Data Sheet IPUH CC IPDL CC 398 OPEN MARKET VERSION CL; valid for all data rates excluding clock tolerance V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-7 Fast 5V GPIO (cont’d) Parameter Input leakage current Symbol IOZ CC Values Unit Note / Test Condition Min. Typ. Max. -1100 - 1100 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -2500 - 2500 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/FLEX2) < VIN < (0.9 * VEXT/FLEX/FLEX2) ; LVDS_TX / Fast pad type -6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX / Fast pad type ; else -3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX / Fast pad type ; else -1500 - 1500 nA TJ ≤ 150°C ; else -2000 - 2000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -4000 - 4000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/FLEX2) < VIN < (0.9 * VEXT/FLEX/FLEX2) ; LVDS_TX / Fast pad type -13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX / Fast pad type ; else -5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX / Fast pad type ; else Input high voltage level VIH SR -2500 - 2500 nA TJ ≤ 170°C ; else 0.7 * - - V AL 2.0 - - V TTL - - 0.44 * V AL VEXT/FLEX/F LEX2/EVRSB Input low voltage level VIL SR VEXT/FLEX/F LEX2/EVRSB Input low threshold variation Data Sheet VILD SR - - 0.8 V TTL -50 - 50 mV max. variation of 1ms; VEXT/FLEX/FLEX2/EVRSB = constant; AL 399 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-7 Fast 5V GPIO (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition in addition 2.5pF from package to be added Pin capacitance CIO CC - 2 3 pF Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-8 Fast 3.3V GPIO Parameter On-Resistance of pad output Rise / Fall time 1) 2) Symbol RDSON CC tRF CC Values Unit Note / Test Condition Min. Typ. Max. 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA 1.6 - 4.5 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX/FLEX2/EVRSB to 0.8 * VEXT/FLEX/FLEX2/EVRSB ns CL = 25pF; driver = strong sharp edge; from 0.8V to 2.0V (RMII) ns driver = medium; CL≤200pF ns driver = strong edge = medium; CL≤200pF 0.75+0.08 0.75+0.11 2.5+0.21* ns *CL *CL CL driver = strong edge = sharp ; CL≤200pF - - 5 2+0.57*C 5.5+0.75* 10+1.25* L CL CL 1.5+0.18* 1.5+0.28* 8+0.4*CL CL CL Asymmetry of sending tTX_ASYM CC -1 - 1 ns Input frequency fIN CC - 160 MHz Data Sheet - 400 OPEN MARKET VERSION CL; valid for all data rates excluding clock tolerance V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Input hysteresis Symbol 3) HYS CC Values Unit Note / Test Condition Min. Typ. Max. 0.055 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL |17| - - µA VIH; AL and TTL VEXT/FLEX/F LEX2/EVRSB 0.09 * VEXT/FLEX/F LEX2/EVRSB 0.055 * VEXT/FLEX/F LEX2/EVRSB Pull-up current 4) IPUH CC (degraded, used for CIF) Pull-down current 5) IPDL CC |11| - - µA VIH; TTL - - |80| µA VIL; AL and TTL and TTL (degraded, used for CIF) - - |105| µA VIH; AL and TTL (degraded, used for CIF) Data Sheet - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) 401 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Input leakage current Symbol IOZ CC Values Unit Note / Test Condition Min. Typ. Max. -1100 - 1100 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -2500 - 2500 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/FLEX2) < VIN < (0.9 * VEXT/FLEX/FLEX2) ; LVDS_TX / Fast pad type -6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX / Fast pad type ; else -3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX / Fast pad type ; else -1500 - 1500 nA TJ ≤ 150°C ; else -2000 - 2000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -4000 - 4000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/FLEX2) < VIN < (0.9 * VEXT/FLEX/FLEX2) ; LVDS_TX / Fast pad type -13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX / Fast pad type ; else -5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX / Fast pad type ; else Input high voltage level VIH SR -2500 - 2500 nA TJ ≤ 170°C ; else 0.7 * - - V AL 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) - - 0.42 * V AL VEXT/FLEX/F LEX2/EVRSB Input low voltage level VIL SR VEXT/FLEX/F LEX2/EVRSB Input low/high voltage level Data Sheet VILH SR - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) 1.0 - 1.9 V RGMII; no hysteresis available 402 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VEXT/FLEX/FLEX2/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-9 Slow 5V GPIO Parameter Symbol Values Unit Note / Test Condition Ohm medium driver; IOH / OL = 2mA ns driver = medium edge = medium ; CL≤200pF 1.5+0.25* 2.5+0.40* 7+0.55*C ns driver = medium edge = sharp ; CL≤200pF Min. Typ. Max. 225 320 On-Resistance of pad output RDSON CC 125 Rise / Fall time 1) 2) tRF CC 4+0.55*C 4+0.75*C 12+1*CL L L CL CL L Asymmetry of sending tTX_ASYM CC -1 - 1 ns Input frequency fIN CC - - 160 MHz Input hysteresis 3) HYS CC 0.09 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL VEXT/FLEX/F LEX2/EVRSB 0.075 * VEXT/FLEX/F LEX2/EVRSB 75 Data Sheet 403 OPEN MARKET VERSION CL; valid for all data rates excluding clock tolerance V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-9 Slow 5V GPIO (cont’d) Parameter Pull-up current Symbol 4) IPUH CC Values Min. Typ. Max. |30| - - Unit Note / Test Condition µA VIH;AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C Pull-down current 5) Input leakage current Input high voltage level IPDL CC IOZ CC VIH SR - - |130| µA VIL; AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL -300 - 300 nA TJ ≤ 150°C; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -400 - 400 nA TJ ≤ 150°C; else -600 - 600 nA TJ ≤ 170°C; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -750 - 750 nA TJ ≤ 170°C; else -18000 - 18000 nA P32.0 and P32.1;TJ≤150°C -38000 - 38000 nA P32.0 and P32.1;TJ≤170°C 0.7 * - - V AL 2.0 - - V TTL - - 0.44 * V AL VEXT/FLEX/F LEX2/EVRSB Input low voltage level VIL SR VEXT/FLEX/F LEX2/EVRSB - - 0.8 V TTL Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VEXT/FLEX/FLEX2/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. Data Sheet 404 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads 2) Rise / fall times are defined 10% - 90% of pad supply voltage. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-10 Slow 3.3V GPIO Parameter Symbol Values Unit Note / Test Condition Ohm medium driver; IOH / OL = 2mA ns driver = medium edge = medium ; CL≤200pF 2+0.30*C 3.5+0.50* 5+0.70*C ns driver = medium edge = sharp ; CL≤200pF Min. Typ. Max. 225 320 On-Resistance of pad output RDSON CC 125 Rise / Fall time 1) 2) tRF CC 2+0.57*C 5.5+0.75* 10+1.25* CL L L CL CL L Asymmetry of sending tTX_ASYM CC -1 - 1 ns Input frequency fIN CC - - 160 MHz Input hysteresis 3) HYS CC 0.055 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL VEXT/FLEX/F LEX2/EVRSB 0.09 * VEXT/FLEX/F LEX2/EVRSB 0.055 * VEXT/FLEX/F LEX2/EVRSB 125 Data Sheet 405 OPEN MARKET VERSION CL; valid for all data rates excluding clock tolerance V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-10 Slow 3.3V GPIO (cont’d) Parameter Pull-up current Symbol 4) IPUH CC Values Min. Typ. Max. |17| - - Unit Note / Test Condition µA VIH; AL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C |11| - - µA VIH; TTL; exept VGATE1P; except VGATE1N and TJ > 150°C Pull-down current 5) IPDL CC - - |80| µA VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C - - |105| µA VIH; AL and TTL (degraded, used for CIF) Input leakage current Input high voltage level IOZ CC VIH SR - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) -300 - 300 nA TJ ≤ 150°C; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -400 - 400 nA TJ ≤ 150°C; else -600 - 600 nA TJ ≤ 170°C; (0.1 * VEXT/FLEX/FLEX2/EVRSB) < VIN < (0.9 * VEXT/FLEX/FLEX2/EVRSB) -750 - 750 nA TJ ≤ 170°C; else -18000 - 18000 nA P32.0 and P32.1;TJ≤150°C -38000 - 38000 nA P32.0 and P32.1;TJ≤170°C 0.7 * - - V AL 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) VEXT/FLEX/F LEX2/EVRSB Data Sheet 406 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-10 Slow 3.3V GPIO (cont’d) Parameter Input low voltage level Symbol VIL SR Values Min. Typ. - - Unit Note / Test Condition V AL Max. 0.42 * VEXT/FLEX/F LEX2/EVRSB - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis available Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VEXT/FLEX/FLEX2/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-11 RFast 5V GPIO Parameter On-Resistance of pad output Rise / Fall time 1) 2) Symbol RDSON CC tRF CC Values Unit Note / Test Condition Min. Typ. Max. 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA 1.6 - 3.2 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX/FLEX2 to 0.8 * VFLEX/FLEX2 4+0.55*C 4+0.75*C 12+1.0*C ns L L L 1.0+0.18* 2.5+0.27* 5.0+0.35* ns CL CL CL 0.5+0.08* 0.5+0.11* 1.0+0.17* ns CL Asymmetry of sending Data Sheet tTX_ASYM CC -0.5 CL CL - 0.5 407 OPEN MARKET VERSION ns driver = medium; CL≤200pF driver = strong edge = medium; CL≤200pF driver = strong edge = sharp ; CL≤200pF CL; valid for all data rates excluding clock tolerance V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-11 RFast 5V GPIO (cont’d) Parameter Symbol fIN CC Input frequency Input hysteresis 3) HYS CC Values Unit Min. Typ. Max. - - 160 MHz 0.09 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL |30| - - µA VIH; AL or TTL - - |130| µA VIL; AL or TTL - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL -1700 - 1700 nA TJ ≤ 150°C ; (0.1 * VFLEX/FLEX2) < VIN < (0.9 * VFLEX/FLEX2) -2100 - 2100 nA TJ ≤ 150°C ; else -3000 - 3000 nA TJ ≤ 170°C ; (0.1 * VFLEX/FLEX2) < VIN < (0.9 * VFLEX/FLEX2) -4000 - 4000 nA TJ ≤ 170°C ; else 0.7 * - - V AL 2.0 - - V TTL - - 0.44 * V AL VFLEX/FLEX 2 0.075 * VFLEX/FLEX 2 Pull-up current 4) Pull-down current IPUH CC 5) Input leakage current Input high voltage level IPDL CC IOZ CC VIH SR Note / Test Condition VFLEX/FLEX 2 Input low voltage level VIL SR VFLEX/FLEX 2 - - 0.8 V TTL Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VFLEX/FLEX2 = constant; AL Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. Data Sheet 408 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads 2) Rise / fall times are defined 10% - 90% of pad supply voltage. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-12 RFast 3.3V pad Parameter Symbol On-Resistance of pad output Input Duty Cycle Rise / Fall time 1) 2) Values Note / Test Condition Min. Typ. Max. 8 20 30 Ohm Driver = RGMII; IOH / OL = 8mA 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA fD SR 47.5 50 52.5 tRF CC 1.6 - 4.5 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX/FLEX2 to 0.8 * VFLEX/FLEX2 - - 5 ns CL = 25pF; driver = strong sharp edge; from 0.8V to 2.0V (RMII) - - 1 ns Driver = RGMII; from 20%V to 80%V; CL=15pF ns driver = medium; CL≤200pF ns driver = strong edge = medium; CL≤200pF 0.75+0.08 0.75+0.11 2.5+0.21* ns *CL CL *CL driver = strong edge = sharp ; CL≤200pF RDSON CC 2+0.57*C 5.5+0.75* 10+1.25* L CL CL 1.5+0.18* 1.5+0.28* 8+0.4*CL CL Asymmetry of sending Unit tTX_ASYM CC -0.4 CL - 0.4 ns CL; valid for all data rates excluding clock tolerance Input frequency Data Sheet fIN CC - - 409 OPEN MARKET VERSION 160 MHz V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-12 RFast 3.3V pad (cont’d) Parameter Input hysteresis Symbol 3) HYS CC Values Unit Note / Test Condition Min. Typ. Max. 0.055 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL |17| - - µA VIH; AL and TTL VFLEX/FLEX 2 0.09 * VFLEX/FLEX 2 0.055 * VFLEX/FLEX 2 Pull-up current 4) IPUH CC (degraded, used for CIF) Pull-down current 5) IPDL CC |11| - - µA VIH; TTL - - |80| µA VIL; AL and TTL and TTL (degraded, used for CIF) - - |105| µA VIH; AL and TTL (degraded, used for CIF) Input leakage current Input high voltage level IOZ CC VIH SR - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) -1700 - 1700 nA TJ ≤ 150°C ; (0.1 * VFLEX/FLEX2) < VIN < (0.9 * VFLEX/FLEX2) -2100 - 2100 nA TJ ≤ 150°C ; else -3000 - 3000 nA TJ ≤ 170°C ; (0.1 * VFLEX/FLEX2) < VIN < (0.9 * VFLEX/FLEX2) -4000 - 4000 nA TJ ≤ 170°C ; else 0.7 * - - V AL 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) VFLEX/FLEX 2 Data Sheet 410 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-12 RFast 3.3V pad (cont’d) Parameter Symbol Input low voltage level VIL SR Values Min. Typ. - - Unit Note / Test Condition V AL Max. 0.42 * VFLEX/FLEX 2 - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VFLEX = constant; AL Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-13 Class S 5V Parameter Symbol fIN CC Input frequency Input hysteresis 1) HYS CC Values Unit Min. Typ. Max. - - 160 MHz 0.09 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL |30| - - µA VIH; AL or TTL - - |130| µA VIL; AL or TTL - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL VDDM 0.075 * VDDM Pull-up current 2) Pull-down current Data Sheet IPUH CC 3) IPDL CC Note / Test Condition 411 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-13 Class S 5V (cont’d) Parameter Input leakage current Symbol IOZ CC Values Unit Note / Test Condition Min. Typ. Max. -150 - 150 nA TJ ≤ 150°C; else -300 - 300 nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected -300 - 300 nA TJ ≤ 170°C; else -600 - 600 nA TJ ≤ 170°C; PDD option available, or AltRef option available and EDSADC channel connected Input high voltage level Input low voltage level VIH SR VIL SR 0.7 * VDDM - - V AL 2.0 - - V TTL - - 0.44 * V AL VDDM - - 0.8 V TTL Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VDDM = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-14 Class S 3.3V Parameter Input frequency Data Sheet Symbol fIN CC Values Unit Min. Typ. Max. - - 160 412 OPEN MARKET VERSION Note / Test Condition MHz V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-14 Class S 3.3V (cont’d) Parameter Input hysteresis Symbol 1) HYS CC Values Unit Note / Test Condition Min. Typ. Max. 0.055 * - - V non of the neighbor pads are used as output; AL - - V non of the neighbor pads are used as output; TTL - - V non of the neighbor pads are used as output; TTL (degraded used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL |17| - - µA VIH; AL and TTL VDDM 0.09 * VDDM 0.065 * VDDM Pull-up current 2) IPUH CC (degraded, used for CIF) Pull-down current 3) IPDL CC |11| - - µA VIH; TTL - - |80| µA VIL - - |105| µA VIH; AL and TTL (degraded, used for CIF) Input leakage current IOZ CC - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) -150 - 150 nA TJ ≤ 150°C; else -300 - 300 nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected -300 - 300 nA TJ ≤ 170°C; else -600 - 600 nA TJ ≤ 170°C; PDD option available Input high voltage level Data Sheet VIH SR 0.7 * VDDM - - V AL 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) 413 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-14 Class S 3.3V (cont’d) Parameter Input low voltage level Symbol Values VIL SR Min. Typ. Max. - - 0.42 * Unit Note / Test Condition V AL VDDM - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VDDM = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V. Table 3-15 Class D Parameter Symbol Values Min. Input leakage current IOZ CC -150 -300 1) Typ. Max. - 150 - 300 1) Unit Note / Test Condition nA TJ ≤ 150°C; else nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected -300 -600 2) - 300 600 2) nA TJ ≤ 170°C; else nA TJ ≤ 170°C; PDD option available, or AltRef option available and EDSADC channel connected Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added 1) For AN11 100 nA need to be added. 2) For AN11 200 nA need to be added. Data Sheet 414 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-16 ADC Reference Pads Parameter Symbol Input leakage current for VAREF IOZ2 CC Values Unit Note / Test Condition Min. Typ. Max. -1 - 1 µA TJ ≤ 150°C; VAREF < VDDM; used for EVADC -2 - 2 µA TJ ≤ 170°C; VAREF < VDDM; used for EVADC -3.5 - 3.5 µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EVADC -7 - 7 µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EVADC - 2 1) µA TJ ≤ 150°C; VAREF < VDDM; for EDSADC -4 1) - 4 1) µA TJ ≤ 170°C; VAREF < VDDM; for EDSADC -6 1) - 6 1) µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; for -2 1) EDSADC -12 1) - 12 1) µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; for EDSADC 1) Limit is valid for VAREF1 pin. Table 3-17 Driver Mode Selection for Slow Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X X 0 Speed grade 1 medium sharp edge (sm) X X 1 Speed grade 2 medium medium edge (m) Table 3-18 Driver Mode Selection for Fast Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (ss) X 0 1 Speed grade 2 Strong medium edge (sm) X 1 0 Speed grade 3 medium (m) X 1 1 Speed grade 4 Reserved, do not use this combination Table 3-19 Driver Mode Selection for RFast Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (ss) X 0 1 Speed grade 2 Strong medium edge (sm) Data Sheet 415 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification 5 V / 3.3 V switchable Pads Table 3-19 Driver Mode Selection for RFast Pads (cont’d) PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 1 0 Speed grade 3 medium (m) X 1 1 Speed grade 4 RGMII function active Data Sheet 416 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification High performance LVDS Pads 3.6 High performance LVDS Pads This LVDS pad type is used for the high speed chip to chip communication interface of the new TC37xEXT. It compose out of a LVDSH pad and a fast pad. CL = 2.5 pF for all LVDSH parameters. Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Output impedance R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V Rise time (20% - 80%) trise20 CC - - 0.75 1) ns ZL = 100 Ohm ±20% @2pF external load Fall time (20% - 80%) tfall20 CC - - 0.75 2) ns ZL = 100 Ohm ±20% @2pF external load Output differential voltage 3) VOD CC 240 - 330 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=00 280 - 370 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=01 320 - 410 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=10 Output voltage high Output voltage low VOH CC VOL CC Output offset (Common mode) VOS CC voltage Input voltage range Input differential threshold Data Sheet VI SR Vidth SR 380 - 500 mV RT = 100 Ohm ± 1%; LPCRx.VDIFFADJ=11 ; Multi slave operation - - 1475 mV RT = 100 Ohm +/- 1% VDIFFADJ=00 and 01 - - 1500 mV RT = 100 Ohm ± 1% VDIFFADJ=10 and 11 925 - - mV RT = 100 Ohm ± 1% VDIFFADJ=00 and 01 900 - - mV RT = 100 Ohm +/- 1% VDIFFADJ=10 and 11 1125 - 1275 mV RT = 100 Ohm ± 1% 0 - 1600 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±10% 0 - 2400 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±20% -100 - 100 mV Driver ground potential difference < 900 mV; VDIFFADJ=10 and 11 -100 - 100 mV Driver ground potential difference < 925 mV; VDIFFADJ=00 and 01 417 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification High performance LVDS Pads Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Receiver differential input impedance Rin CC 80 - 120 Ohm VI ≤ 2400 mV Output differential voltage Sleep Mode 4) VODSM CC -5 - 20 mV RT = 100 Ohm ± 20%; LPCRx.VDIFFADJ=xx Delta output impedance dR0 SR - - 10 % Vcm = 1.0 V and 1.4 V Change in VOS between 0 and dVOS CC 1 - - 25 mV RT = 100 Ohm ±1% Change in Vod between 0 and dVod CC 1 - - 25 mV RT = 100 Ohm ±1% tSET_LVDS - 10 13 µs 55 % Pad set-up time CC tduty CC 45 Duty cycle 1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load. 2) tfall20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load. 3) Potencial violations of the IEEE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE Std 1596.3 LPCRx.VDIFFADJ has to be configure to 01. 4) Common Mode voltage of Tx is maintained. Note: Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted signal. Note: RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by RIN or by RT=100Ohm but not both. default after start-up = CMOS function Data Sheet 418 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification High performance LVDS Pads P Htotal=5nH Ctotal=3.5pF Cext=2pF Rin LVDS IN RT=100Ohm N Htotal=5nH Ctotal=3.5pF Cext=2pF LVDS_Input_Pad_Model.vsd Figure 3-1 LVDS pad Input model Data Sheet 419 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification VADC Parameters 3.7 VADC Parameters The accuracy of the converter results depends on the reference voltage range. The parameters in the table below are valid for a reference voltage range of (VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V by a factor of k (e.g. 3.3 V), the accuracy parameters increase by a factor of 1.1/k (e.g. 1.1 × 4.5 / 3.3 = 1.5). Noise on the voltage supply influences the conversion. The accuracy parameters are defined for a supply voltage ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10 MHz). Digital functions overlapping analog inputs influence accuracy. The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS (depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional peak-peak noise error is 8 LSB. Fast compare operations are executed with 10-bit values. The noise reduction feature improves the result by adding additional conversion steps. The conversion times, therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps). Table 3-21 VADC 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 1.15 - 1.35 V Measured at low temperature. Deviation of IVR output voltage dVDDK CC -2 - 2 % Based on devicespecific value Analog reference voltage 1) 4.5 5.0 VDDM + V 4.5 V ≤ VDDM ≤ 5.5 V V 2.97 V ≤ VDDM < 4.5 V EVADC IVR output voltage VDDK CC VDDK VAREF SR 0.05 2.97 3.3 VDDM + 0.05 Analog reference ground VAGND SR VSSM VSSM VSSM V VSSM and VAGND are connected together Analog input voltage range VAIN SR VAGND - VAREF V VAIN is limited by the respective pad supply voltage; see pin configuration (buffer type) Converter reference clock Total Unadjusted Error INL Error 2) 2) 3) fADCI SR 16 40 53.33 MHz 4.5 V ≤ VDDM ≤ 5.5 V 16 20 26.67 MHz 2.97 V ≤ VDDM < 4.5 V TUE CC -4 - 4 LSB 12-bit resolution for primary/secondary groups, 10-bit resolution for fast compare channels EAINL CC -3 - 3 LSB DNL error 2)4) EADNL CC -1 - 3 LSB Gain Error 2) EAGAIN CC -3.5 - 3.5 LSB EAOFF CC -4 - 4 LSB ENRMS CC - 0.5 0.8 LSB Noise reduction level 3 - 0.5 1.0 LSB Standard conversion Offset Error 2)3) RMS Noise 2)5) 6) Data Sheet 420 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification VADC Parameters Table 3-21 VADC 5V (cont’d) Parameter Reference input charge consumption per conversion (from VAREF) 7) 8) 9) Symbol QCONV CC Values Min. Typ. Max. - - 20 Unit Note / Test Condition pC VAIN = 0 V (worst case), precharging disabled - - 10 pC VAIN = 0 V (worst case), precharging enabled, VDDM - 5% < VAREF < VDDM + 50 mV Switched capacitance of an analog input CAINS CC - 2.5 3.4 pF Input buffer disabled Analog input charge consumption 10) QAINS CC - - 3.5 pC Primary groups and fast compare channels; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ ≤ 150°C - - 3.8 pC Primary groups and fast compare channels; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ > 150°C - - 4.4 pC Secondary groups; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ ≤ 150 °C - - 4.8 pC Secondary groups; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ > 150°C Data Sheet 421 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification VADC Parameters Table 3-21 VADC 5V (cont’d) Parameter Sampling time Sampling time for calibration Symbol tS SR tSCAL SR Values Unit Note / Test Condition Min. Typ. Max. 100 - - ns Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled 300 - - ns Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled 500 - - ns Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled 700 - - ns Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled 200 - - ns Primary Group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled 400 - - ns Primary group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled 1000 - - ns Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled 1200 - - ns Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled 50 - - ns 4.5 V ≤ VDDM ≤ 5.5 V 100 - - ns 2.97 V ≤ VDDM < 4.5 V Input buffer switch-on time tBUF CC - 0.4 1 µs Wakeup time tWU CC - 0.1 0.2 µs Fast standby mode - 1.6 3 µs Slow standby mode Broken wire detection delay against VAREF tBWR CC - 100 - cycles Result above 80% of full scale range, analog input buffer disabled Broken wire detection delay against VAGND tBWG CC - 100 - cycles Result below 10% of full scale range, analog input buffer disabled Converter diagnostics unit resistance 11) RCSD CC 45 - 75 kOhm Converter diagnostics voltage accuray dVCSD CC -10 - 10 % Data Sheet Percentage refers to VDDM 422 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification VADC Parameters Table 3-21 VADC 5V (cont’d) Parameter Symbol Resistance of the multiplexer diagnostics pull-up device Resistance of the multiplexer diagnostics pull-down device Values RMDU CC RMDD CC RPDD CC Resistance of the pull-down test device Unit Note / Test Condition Min. Typ. Max. 30 - 42 kOhm 0 V ≤ VIN ≤ 0.9* VDDM, Automotive Levels 56 - 78 kOhm 0 V ≤ VIN ≤ 0.9* VDDM, TTL Levels 43 - 58 kOhm 0.1*VDDM ≤ VIN ≤ VDDM, Automotive level 18 - 25 kOhm 0.1*VDDM ≤ VIN ≤ VDDM, TTL level - - 0.3 kOhm Measured at pad input voltage VIN = VDDM / 2. 1) These limits apply to the standard reference input as well as to the alternate reference input. 2) Parameter depends on reference voltage range and supply ripple, see introduction. Resulting worst case combined error is arithmetic combination of TUE and ENRMS. Tests are done with postcalibration disabled, after completing the startup calibration. 3) Digital functions on analog inputs influence accuracy. The values for this parameter increase by 3 LSB12. 4) Monotonic characteristic, no missing codes when calibrated. 5) Parameter ENRMS refers to a 1 sigma distribution. 6) For analog inputs with overlaid digital GPIOs the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC enabled). 7) For reduced reference voltages the consumed charge is reduced by factor k. 8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active. 9) Fast compare channels only consume 1/3 of the charge for a primary/secondary group. 10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC. 11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage. External Circuitry AD Converter CHy CHx CExt VS RAIN ... RExt (P) ZAIN (S) (P/S) CParasit (C) CSWT VAIN CExt >> CParasit CADC VAREF VAGND CParasit = CIO + CPackage ZAIN = (tS / Ceff) + RAIN Å Input impedance RAIN = (tSmin / CAINS) / 10 Å Resistance of MUX CSWT = QAINS / VAREF Å Capacitance of switch tree Precharge enabled: Ceff = CSWT Precharge disabled: Ceff = CAINS CSWT + CADC = CAINS (P): Precharge sampling (S): Sampling (direct) (C): Conversion mc_evadc_equivpath.vsd Figure 3-2 Equivalent Circuitry for Analog Inputs Data Sheet 423 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification DSADC Parameters 3.8 DSADC Parameters The DSADC parameters are valid only for voltage range 4.5 V 150°C; Resulting -5 5) Signal-Noise Ratio value is SNR - DSNR Spurious-free dynamic range 3) SFDR CC 60 - - dB fMOD = 26.67 MHz Output sampling rate fD CC 3.906 - 300 kHz 16 MHz / 4096, without integrator Pass band fPB CC 1.302 - 100 kHz Output data rate: fD = fPB * 3; without integrator 1.302 - 10 kHz Output data rate: fD = fPB * 6; without integrator Pass band ripple dfPB CC -0.08 - 0.08 dB FIR filters enabled Stop band attenuation SBA CC 40 - - dB 0.5 fD ... 1.0 fD 45 - - dB 1.0 fD ... 1.5 fD 50 - - dB 1.5 fD ... 2.0 fD 55 - - dB 2.0 fD ... 2.5 fD 60 - - dB 2.5 fD ... OSR/2 fD 10-5 fD, offset compensation filter enabled (FCFGMx.OCEN = 001B) DC compensation factor DCF CC -3 - - dB Modulator settling time tMSET CC - - 20 µs After switching on, voltage regulator already running 1) On pins with overlaid GPIO function the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C. 2) For detailed information, refer to the User Manual chapter. 3) This parameter is valid within the defined range of fMOD. 4) Gain mismatch error between the different EDSADC channels is within ±0.5%. Data Sheet 425 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification DSADC Parameters 5) Recalibration needed in case of a temperature change >20ºC 6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor. 7) For single ended input signals and gain1, the SNR is reduced by 6 dB. Data Sheet 426 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification MHz Oscillator 3.9 MHz Oscillator OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external outside of the device. Support of ceramic resonators is also provided. Table 3-23 OSC_XTAL Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Input current at XTAL1 IIX1 CC -70 - 70 µA VIN>0V ; VIN 25MHz 0.35*VEXT - VEXT + 1.0 V If shaper is not bypassed; fOSC ≤ 25MHz Input amplitude (peak to peak) VPPX SR at XTAL1 Internal load capacitor CL0 CC 1.30 1.40 1.55 pF enabled via bit OSCCON.CAP0EN Internal load capacitor CL1 CC 3.05 3.35 3.70 pF enabled via bit OSCCON.CAP1EN Internal load capacitor CL2 CC 7.85 8.70 9.55 pF enabled via bit OSCCON.CAP2EN Internal load capacitor CL3 CC 12.05 13.35 14.65 pF enabled via bit OSCCON.CAP3EN Internal load stray capacitor between XTAL1 and XTAL2 CXINTS CC 1.15 1.20 1.25 pF Internal load stray capacitor between XTAL1 and ground CXTAL1 CC - 2.5 4 pF DCX1 SR 35 - 65 % VXTAL1 = 0.5*VPPX JABSX1 SR - - 28 ps 10 KHz to fOSC/2 - - V/ns Maximum 30% difference between rising and falling slew rate Duty cycle at XTAL1 3) Absolute RMS jitter at XTAL1 Slew rate at XTAL1 3) 3) SRXTAL1 SR 0.3 1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an amplitude at XTAL1 of 0.3 * VEXT. This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease. 2) For supply (VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause and damage or riability problem operating with an external crystal. Data Sheet 427 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification MHz Oscillator 3) Square wave input signal for XTAL1. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Data Sheet 428 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Back-up Clock 3.10 Back-up Clock The back-up clock provides an alternative clock source. Table 3-24 Back-up Clock Parameter Symbol Back-up clock accuracy before fBACKUT CC trimming Values Unit Note / Test Condition Min. Typ. Max. 70 100 130 MHz VEXT≥2.97V Back-up clock accuracy after trimming 1) fBACKT CC 98 100 102 MHz VEXT≥2.97V Standby clock fSB CC 25 70 110 kHz VEXT≥2.97V 1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for temperature and voltage drifts up to temperatures of 125 celcius Data Sheet 429 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Temperature Sensor 3.11 Temperature Sensor Table 3-25 DTS PMS Parameter Measurement time for each conversion 1) Symbol tM CC Values TNL CC Note / Test Condition Min. Typ. Max. - - 2.7 ms Measured from cold power-on reset release - 1 °C calibration points @ TJ=-40°C and TJ=127°C - 2 °C TCALACC has to be added in addition Calibration reference accuracy TCALACC CC -1 Accuracy over temperature range Unit -2 DTS temperature range TSR SR -40 170 1) After warm reset tM is not restarted and is measured from last conversion. °C Table 3-26 DTS Core Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Measured from cold power-on reset release Measurement time for each conversion 1) tM CC - - 2.7 ms Temperature difference between on chip temperature sensors ∆T CC -3 - 3 °C Calibration reference accuracy TCALACC CC -2 - 2 °C calibration points @ TJ=-40°C and TJ=127°C - 2 °C TCALACC has to be added in addition Accuracy over temperature range TNL CC -2 TSR SR -40 170 DTS temperature range 1) After warm reset tM is not restarted and is measured from last conversion. Data Sheet 430 OPEN MARKET VERSION °C V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current 3.12 Power Supply Current The total power supply current defined below consists of leakage and switching component. Application relevant values are typically lower than those given in the following table and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: The real (realistic) power pattern defines the following conditions: • TJ = 150 °C fSRI = fCPUx = 300 MHz fGTM = 200 MHz fSPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz VDD = 1.275 V VDDP3 / FLEX = 3.366 V VEXT / EVRSB / M = VDDM = 5.1 V • all cores are active including two lockstep core (IPC=0.6) • the following peripherals are inactive: HSM, HSCT, GETH, Ethernet, PSI5, I2C, FCE, CIF, and MTU • • • • • • The max power pattern defines the following conditions: • TJ = 150 °C fSRI = fCPUx = 300 MHz fGTM = 200 MHz fSPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz VDD = 1.375 V VDDP3 / FLEX = 3.63 V VEXT / EVRSB / M = VDDM = 5.5 V • all cores are active including three lockstep cores (IPC=1.2) • the following modules are inactive: GETH, FCE, CIF, and MTU • • • • • • Table 3-27 Current Consumption Parameter Symbol ∑ Sum of IDD core and IDDRAIL CC peripheral supply currents (incl. IDDPORST+ ∑ IDDCx0+ ∑ IDDCxx+ IDDGTM+IDDSB) Data Sheet Values Unit Note / Test Condition Min. Typ. Max. - - 960 1) mA max power pattern; valid for Feature Package TE, and TX products - - 775 mA real power pattern; valid for Feature Package TE, and TX products 431 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current Table 3-27 Current Consumption (cont’d) Parameter Symbol Values Min. IDD core current during active power-on reset (PORST pin held low). Leakage current of core domain. 2) IDDPORST CC - Typ. Max. - 190 Unit Note / Test Condition mA VDD = 1.275V; TJ=125°C; valid for Feature Package TE, and TX products - - 315 mA VDD = 1.275V; TJ=150°C; valid for Feature Package TE, and TX products - - 425 mA VDD = 1.275V; TJ=165°C; valid for Feature Package TE, and TX products ∑ Sum of IDDP3 3.3 V supply currents IDDP3RAIL CC - - 45 2) mA max power pattern incl. Flash read current and Dflash programming current. - - 36 3) mA real power pattern incl. Flash read current and Dflash programming current. - - 50 mA max power pattern mA real power pattern ∑ Sum of external IEXT supply currents (incl. IEXTFLEX+IEVRSB+IEXTLVDS) IEXTRAIL CC - - 35 IEXT and IFLEX supply current IEXTFLEX CC - - 11 5) 6) mA real power pattern with port activity absent; PORST output inactive. IEVRSB supply current 2) IEVRSB CC - - 8.5 mA real power pattern; PMS/EVR module current considered without SCR and Standby RAM during RUN mode. ∑ Sum of external IDDM supply currents (incl. IDDMEVADC+IDDMEDSADC) IDDM CC - - 27 mA real power pattern; sum of currents of EDSADC and EVADC modules ∑ Sum of all currents (incl. IEXTRAIL+IDDMRAIL+IDDx3RAIL+IDD) IDDTOT CC - - 873 mA real power pattern; TJ=150°C; valid for Feature Package TE, and TX products - - 1015 mA real power pattern; TJ=160°C; valid for Feature Package TE, and TX products Data Sheet 432 OPEN MARKET VERSION 4) V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current Table 3-27 Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 430 mA real power pattern; EVRC reset settings with 72% efficiency; VEXT = 3.3V; TJ=150°C - - 320 mA real power pattern; EVRC reset settings with 72% efficiency; VEXT = 5V; TJ=150°C ∑ Sum of all currents with DCDC EVRC regulator active 7) IDDTOTDC3 ∑ Sum of all currents with DCDC EVRC regulator active 7) IDDTOTDC5 ∑ Sum of all currents (SLEEP mode) 2) ISLEEP CC - - 25 mA All CPUs in idle, All peripherals in sleep, fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C ∑ Sum of all currents (STANDBY mode) drawn at VEVRSB supply pin 8) ISTANDBY CC - - 130 9) µA 32 kB Standby RAM block active. SCR inactive. Power to remaining domains switched off. TJ = 25°C; VEVRSB = 5V Maximum power dissipation PD SR - - 1855 mW max power pattern; valid for Feature Package TE, and TX products - - 1425 mW real power pattern; valid for Feature Package TE, and TX products CC CC 1) In QFP package for TC37xED emulation device, the total (IDDED + IDD) current need to be limited to 700 mA. The maximum (IDDED + IDD) current for TC37xED is supported only in BGA packages. 2) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22. 3) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to x mA for maximum x us which is handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal considerations. 4) Limits are defined for real power pattern. For ADAS power pattern limit sum up to 42mA. 5) The current consumption includes only minimal port activity. 6) Limits are defined for real power pattern. For ADAS power pattern limit has to be multiplied by the factor 0.7. 7) The total current drawn from external regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and IDDM. 8) The same current limits apply also for the other power pattern. 9) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current + ISCRSB if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby SRAM contributes less than 10uA to ISTANDBY current. Data Sheet 433 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current Table 3-28 Module Current Consumption Parameter Symbol Max. - - 25 mA Pflash 3.3V programming current adder when using external 3.3V supply. - - 9 2) mA Pflash 3.3V programming current adder when using external 5V supply. IEXTLVDS CC - - 16 mA real power pattern; 4 pairs of LVDS pins active with transmit function - - 9 3) mA real power pattern; 6 pairs of LVDS pins active with receive function - - 14 mA real power pattern; current for EDSADC modules only and EVADC modules are inactive; 4 EDSADC channels active continuously. - - 22 4) mA max power pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active continuously. - - 13 5) mA real power pattern; current for EVADC modules only and EDSADC modules are inactive; 8 EVADC modules active. - - 15 6) mA max power pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active. IDDP3PROG CC Data Sheet Note / Test Condition Typ. programming of a Pflash or Dflash bank 1) ∑ Sum of external IDDM supply currents (incl. IDDMEVADC+IDDMEDSADC) Unit Min. IDDP3 supply current for IEXT supply current added by LVDS pads in LVDS mode 1) Values IDDM CC 434 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current Table 3-28 Module Current Consumption (cont’d) Parameter Symbol IDDP3 supply current for erasing IDDP3ERASE of a Pflash or Dflash bank 1) 2) 3) 4) 5) 6) 7) 8) Unit Note / Test Condition Min. Typ. Max. - - 25 mA Pflash 3.3V erasing current adder when using external 3.3V supply. - - 7 7) mA SCR power pattern incl. PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C - 0.150 - mA SCR power pattern incl. PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C - 3.5 mA real power pattern. CPU set into idle mode. CC SCR 8-bit Standby Controller ISCRSB CC current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin SCR 8-bit Standby Controller CPU in IDLE mode 8) Values ISCRIDLE CC - The same current limits apply also for the other power pattern. During Pflash programming at 5V, additional 2 mA is drawn at VEXT supply rail. A single LVDS pair with receive function is limited to 1.5mA (tEXTLVDS). A single DS channel instance consumes 4 mA. EVADC current is limited to 3mA in "ADAS power pattern with 2 EVADC" at (IDDM). A single VADC unit consumes 1.3 mA. If SCR ADCOMP is activated, an additional 0.6 mA adder is to be considered. Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22. Table 3-29 Module Core Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. IDD core current of CPUx main IDDCx0 CC - - 72 mA core with CPUx lockstep core inactive max power pattern; IPC=1.2 - - 48 mA real power pattern; IPC=0.6 - - IDDCx0 + mA max power pattern; IPC=1.2 mA real power pattern; IPC=0.6 IDD core current of CPUx main IDDCxx CC core with CPUx lockstep core active 48 - - IDDCx0 + 37 Data Sheet 435 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current Table 3-29 Module Core Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 110 mA max power pattern - - 90 mA real power pattern; TIMx, TOMx, ATOMx , MCSx active. 2 clusters at 200 MHz. - - 50 mA TIMx, TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive. 2 clusters at 100 MHz. IDD core current added by HSM IDDHSM CC - - 20 1) mA max power pattern; HSM running at 100MHz. IDD core current added by CIF - - 48 mA conditions t.b.d. mA LBIST Configuration A; 1.2V ≤ VDD mA fMBIST = 300MHz; tMBIST < 6ms. MTU Ganging procedure for SRAM test and initialization; VDD = 1.375V. IDD core current added by GTM IDDGTM CC IDDCIF CC IDD core dynamic current added IDDLBIST CC - - 200 - 225 2) by LBIST IDD core dynamic current added IDDMBIST CC by MBIST 1) The current consumption includes basic HSM activity incl. AES module. 2) LBIST is executed either during start-up phase or can be triggered by application software. Secondary voltage monitors are inactive during the LBIST execution time (tLBIST). During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static accuracy. If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit. Data Sheet 436 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Current 3.12.1 Calculating the 1.25 V Current Consumption The current consumption of the 1.25 V rail compose out of two parts: • Static current consumption • Dynamic current consumption The static current consumption is related to the device temperature TJ and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption. (3.1) I 0 mA = 6, 5 --------- × e 0, 02 × T J [ C ] C (3.2) mA I 0 = 15, 6 --------- × e 0, 02 × T J [ C ] C Equation (3.1) defines the typical static current consumption and Equation (3.2) defines the maximum static current consumption. Both functions are valid for VDD = 1.275 V. Data Sheet 437 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up 3.13 Power Supply Infrastructure and Supply Start-up 3.13.1 Supply Ramp-up and Ramp-down Behavior 3.13.1.1 Single Supply mode (a) Data Sheet 438 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up VEXT (externally supplied) 0 1 2 3 4 5 5.5 V 5.0 V 4.5 V LVD Reset release HWCFG[1,2] latch VRST5 VLVDRST5 Primary cold PORST Reset Threshold LVD Reset Threshold VDDPPA HWCFG[6] latch 0V PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds PORST (output driven by PMS) PORST (input driven by external regulator) PORST input deasserted by external regulator when all input voltages have reached their minimum operational level VDD (internally generated by EVRC) 1.375 V 1.25 V VRSTC Primary Reset Threshold EVRC_tSTR 0V VDDP3 (internally generated by EVR33) 3.63 V 3.30 V VRST33 Primary Reset Threshold tEVRstartup (incl. tSTR) EVR33 is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD EVR33_tSTR 0V tBP (incl. tEVRstartup) T0 T1 Basic Supply & Clock Infrastructure T2 EVRC & EVR33 Ramp-up Phase T3 Firmware Execution T4 User Code Execution fC PU0=100MHz default on firmware exit T5 Power Ramp-down phase Startup_Diag_2 v 0.3 Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal regulators. • The rate at which current is drawn from the external regulator (dIEXT /dt) is limited during the basic infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. Data Sheet 439 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up • Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA (dIDD) is expected. • The power sequence as shown in Figure 3-3 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated. PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up. PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is completed and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. Data Sheet 440 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up 3.13.1.2 Single Supply mode (e) VEXT/VDDP3 0 (externally supplied) VLVDRST5 2 3 4 5 LVD Reset release HWCFG[1,2] latch 3.63 V 3.30 V VRST5/ VRST33 1 Primary cold PORST Reset Threshold LVD Reset Threshold VDDPPA HWCFG[6] latch 0V PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds PORST (output driven by PMS) PORST (input driven by external regulator) PORST input deasserted by external regulator when all input voltages have reached their minimum operational level VDD (internally generated 1.375 V by EVRC) 1.25 V VRSTC Primary Reset Threshold tEVRstartup (incl. tSTR) EVRC is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD EVRC_tSTR 0V tBP (incl. tEVRstartup) T0 Figure 3-4 T2 T1 EVRC Ramp-up Basic Supply & Clock Phase Infrastructure T3 Firmware Execution T4 User Code Execution fC PU0=100MHz default on firmware exit T5 Power Ramp-down phase Startup_Diag_4 v 0.3 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator. • The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the Data Sheet 441 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA (dIDD) is expected. • The power sequence as shown in Figure 3-4 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input) does not have any affect on EVRC output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is deasserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is completed and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. Data Sheet 442 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up 3.13.1.3 External Supply mode (d) VEXT (externally supplied) 0 1 2 3 4 5 5.5 V 5.0 V 4.5 V LVD Reset release HWCFG[1,2] latch VRST5 VLVDRST5 Primary cold PORST Reset Threshold LVD Reset Threshold VDDPPA HWCFG[6] latch 0V VDD (externally supplied) 1.375 V 1.25 V VRSTC Primary Reset Threshold 0V PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds PORST (output driven by PMS) PORST (input driven by external regulator) PORST input deasserted by external regulator when all input voltages have reached their minimum operational level VDDP3 (internally generated by EVR33) 3.63 V 3.30 V VRST33 Primary Reset Threshold tEVRstartup (incl. tSTR) EVR33 is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD EVR33_tSTR 0V tBP (incl. tEVRstartup) T0 T1 Basic Supply & Clock Infrastructure Figure 3-5 T3 T2 EVR33 Ramp-up Phase Firmware Execution T4 User Code Execution fC PU0 =100MHz default on firmware exit T5 Power Ramp-down phase Startup_Diag_1 v 0.3 External Supply mode (d) - VEXT and VDD externally supplied VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator. • External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. If VDD voltage Data Sheet 443 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the operational voltage range. • The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA (dIDD) is expected. • The power sequence as shown in Figure 3-5 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input) does not have any affect on EVR33 output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is deasserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is completed and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. Data Sheet 444 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up 3.13.1.4 External Supply mode (h) VEXT (externally supplied) 0 1 3 4 5 5.5 V 5.0 V 4.5 V LVD Reset release HWCFG[1,2] latch VRST5 VLVDRST5 Primary cold PORST Reset Threshold LVD Reset Threshold VDDPPA HWCFG[6] latch 0V VDD (externally supplied) 1.375 V 1.25 V VRSTC Primary Reset Threshold 0V VDDP3 (externally supplied) 3.63 V 3.30 V VRST33 Primary Reset Threshold 0V PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds tPOA time to ensure adequate time between reset releases PORST (input driven by external regulator) PORST (output driven by PMS) tBP T0 T1 Basic Supply & Clock Infrastructure T3 T4 T5 User Code Execution fC PU0 =100MHz default on firmware exit Firmware Execution Power Ramp-down phase Startup_Diag_3 v 0.4 Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied All supplies, namely VEXT, VDDP3 & VDD are externally supplied. • External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails. If smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall be limited within the operational voltage ranges of the respective rails. Data Sheet 445 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Power Supply Infrastructure and Supply Start-up • The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA (dIDD) is expected. • The power sequence as shown in Figure 3-6 is enumerated below – T1 up to T3 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. – T4 refers to the point in time when Firmware execution is completed and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. Data Sheet 446 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Reset Timing 3.14 Reset Timing Table 3-30 Reset Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Application Reset Boot Time tB CC - - 400 µs operating with max. frequencies, with valid BMI header System Reset Boot Time tBS CC - - 1.1 ms RAM initialization and HSM boot time are not included, with valid BMI header Cold Power on Reset Boot Time 1) tBP CC - - 3.1 ms dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time after Cold PORST including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot time are not included. - Minimum cold PORST reset hold time incase of power fail event issued by EVR primary monitors tEVRPOR CC 10 2) - 1.6 ms - - µs - 1 ms PMS Infrastructure, EVRC and tEVRstartup EVR33 overall start-up time till CC cold PORST reset release - tPOA SR Minimum PORST active hold time externally after power supplies are stable at operating levels after start-up 1 3) - - ms tPORSTDF CC 600 Configurable PORST digital filter delay in addition to analog pad filter delay - 1200 ns Warm Reset Sequencing Delay tWARMRSTSEQ CC - 180 µs - - ns HWCFG pins hold time from ESR0 rising edge Data Sheet tHDH CC Firmware execution time after PORST release without EVR ramp-up; RAM initialization and HSM boot time is not included dV/dT=1V/ms. EVRC and EVR33 active 16 / fSPB 447 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Reset Timing Table 3-30 Reset (cont’d) Parameter HWCFG pins setup time to ESR0 rising edge Symbol tHDS CC Ports inactive after ESR0 reset tPI CC active Values Unit Min. Typ. Max. 0 - - ns - - 8/fSPB ns Note / Test Condition Ports inactive after PORST reset active tPIP CC - - 160 ns Hold time from PORST rising edge tPOH SR 150 - - ns Setup time to PORST rising edge tPOS SR 0 - - ns Warm PORST reset boot time tBWP CC - - 1.5 ms without RAM initalization LBIST execution time extending the boot time tLBIST CC - - 6 ms LBIST Configuration A; 1.2V ≤ VDD SCR reset boot time tSCR CC - - 5 µs User Mode 0 - - 16 µs User Mode 1 - 13.3 - µs WDT double bit ECC, soft reset - 250 µs Minimum external supplies hold time after warm reset assertion tSUPHOLD CC - external supplies are VEVRSB, VEXT, VFLEX/FLEX2, VDDM, VDDP3 and VDD 1) RAM initialization add 500µs in addition. 2) Cold PORST reset is driven by uC and maintained in an extended voltage range between VDDPPA limit and absolute maximum rating voltage limits. 3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. Data Sheet 448 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Reset Timing VDDP V D D PPA VD D PPA V D D PR VDD tPOA tPOA PORST Warm Cold ESR0 t PI tP I tP IP Tristate Z / pullup H Pads Programmed Z/ H Programmed Z /H Programmed Padstate undefined TRST Padstate undefined t P OS t P OS t P OH tP OH TESTMODE t HDH HWCFG power -on config t HDA t HDH t HDA config t HDH config reset_beh_aurix Figure 3-7 Power, Pad and Reset Timing Data Sheet 449 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS 3.15 PMS Table 3-31 EVR33 LDO Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. 3.60 1) - 5.50 V Normal RUN mode 2.97 2) - 5.50 V Low voltage cranking mode 2.97 3.3 3.63 V Normal RUN mode 2.60 3.3 3.63 V Low voltage cranking mode; IDDP3=50mA 3.225 3.3 3.375 V Normal RUN mode 2.78 3.3 3.375 V Low voltage cranking mode; IDDP3=50mA 1.45 2.2 3 µF - 100 4) mOhm f > 0.5MHz; f < 10MHz 60 5) - - mA Normal RUN mode - 500 1000 µs Normal RUN mode dVin/dt SR - 1 - V/ms Ripple on Output Voltage ∆VOUTTC CC - 33 mV VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IOUTTC ≥ 10mA ; IOUTTC ≤ 60mA; ∆VOUTTC = (peak to peak ripple / 2) Load step response 7) dVout/dIout -165 - - mV Normal RUN mode; dI=10 to 60mA; dt=20ns; Tsettle=20us - - 165 mV Normal RUN mode; dI=60 to 10mA; dt=20ns; Tsettle=20us -180 - - mV Low voltage cranking mode; dI=10 to 50 mA; dt=20ns; Tsettle=20us - - 180 mV Low voltage cranking mode; dI=50 to 10mA; dt=20ns; Tsettle=20us VIN SR Input voltage range Output voltage operational range including load/line regulation and aging 3) VOUT CC Output VDDx3 static voltage VOUTT CC accuracy after trimming and aging without dynamic load/line regulation. Output buffer capacitance on VOUT Output buffer capacitor ESR COUT SR COUTESR SR - Maximum output current of the IMAX CC regulator tSTR CC Startup time External VIN supply ramp 6) - CC Data Sheet 450 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-31 EVR33 LDO (cont’d) Parameter Symbol Values Min. Line step response Unit Note / Test Condition Typ. Max. - 40 mV dVin/dT=1V/ms; dV= 3.6 to 5V; IMAX=60mA; ∆VOUTTC is included -40 - - mV dVin/dT=1V/ms; dV= 5 to 3.6V; IMAX=60mA; ∆VOUTTC is included - - 280 mV dVin/dT=50V/ms; dV= 3.6 to 5V; IMAX=60mA -165 - - mV dVin/dT=50V/ms; dV= 5 to 3.6V; IMAX=60mA dVout/dVin CC 1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device performance during normal operation. 2) VEXT Input voltage drop up to 2.97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched before to low performance mode. 3) No external inductive load permissible if EVR33 is used. 4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm. An additional decoupling capacitor of 100nF shall be located close to the pin before Cout. 5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator. 6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid overshoots. 7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device. Table 3-32 Supply Monitors Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Primary Undervoltage Reset threshold for VDDP3 before trimming 1) VRST33 CC - - 3.00 V by reset release before EVR trimming on supply ramp-up Primary undervoltage reset threshold for VDD before trimming VRSTC CC - - 1.138 V by reset release before trimming on supply ramp-up including 2 LSB voltage Hysteresis VEXTPRIUV 2.86 2.92 2.97 V VEXT = Undervoltage cold PORST Primary Monitor Threshold 2.86 3) 2.90 2.97 V VDDP3 = Undervoltage cold PORST Primary Monitor Threshold VEXT primary undervoltage monitor accuracy after trimming 2) CC VDDP3 primary undervoltage VDDP3PRIUV monitor accuracy after trimming 2) CC Data Sheet 451 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Min. VDD primary undervoltage VDDPRIUV monitor accuracy after trimming 2) CC EVR primary monitor tPRIUV CC measurement latency for a new supply value Data Sheet 1.08 - 3) Unit Note / Test Condition Typ. Max. 1.105 1.125 V VDD = Undervoltage cold PORST Primary Monitor Threshold - 300 ns The supply ramp / line jump slope is limited to 50V/ms for VEXT, VDDP3 and VDD rails. 452 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. VEXT, VDDM & VEVRSB secondary VEXTMON CC 3.2 supply monitor accuracy after trimming 4) 5) 3.3 3.4 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=3.3V=90h( OV,UV). For BGA packages: EVRMONFILT.SWDFI L=1. 3.2 3.3 3.4 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=3.3V=90h( OV,UV). For QFP packages: EVRMONFILT.SWDFI L=2 4.5 4.6 4.7 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=4.6V=C8h( UV)/C9h(OV). For BGA packages: EVRMONFILT.SWDFI L=1 4.5 4.6 4.7 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=4.6V=C8h( UV)/C9h(OV). For QFP packages: EVRMONFILT.SWDFI L=2 5.3 5.4 5.5 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5.4V=EAh( UV)/ECh(OV). For BGA packages: EVRMONFILT.SWDFI L=1 5.3 5.4 5.5 V 4.9 453 5.0 SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5.4V=EAh( UV)/ECh(OV). For QFP packages: EVRMONFILT.SWDFI L=2 V 1.0 2019-10 5.1 V SWDxxV VDDMxxVAL & Data Sheet OPEN MARKET VERSION TC37xEXT AB-Step Electrical Specification PMS Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 2.97 3.035 3.1 V EVR33xxVAL monitoring threshold=3.035V=CB h(UV)/CCh(OV). EVRMONFILT.EVR33 FIL = 3. 3.235 3.30 3.365 V EVR33xxVAL monitoring threshold=3.3V=DDh( OV,UV). EVRMONFILT.EVR33 FIL = 3. 3.5 3.565 3.63 V EVR33xxVAL monitoring threshold=3.565V=EE h(UV)/EFh(OV). EVRMONFILT.EVR33 FIL = 3. VDD & VDDPD secondary supply VDDMON CC 1.125 monitor accuracy after trimming 5) 1.15 1.175 V EVRCxxVAL & PRExxVAL monitoring threshold=1.15V=C7h( UV)/C8h(OV). EVRMONFILT.EVRC FIL = 1. 1.225 1.25 1.275 V EVRCxxVAL & PRExxVAL monitoring threshold=1.25V=D9h( OV,UV). EVRMONFILT.EVRC FIL = 1. 1.325 1.35 1.375 V EVRCxxVAL & PRExxVAL monitoring threshold=1.35V=EAh (UV)/EBh(OV). EVRMONFILT.EVRC FIL = 1. VDDP3 secondary supply monitor accuracy after trimming 5) VDDP3MON CC VEXT LVD Primary undervoltage reset Monitor threshold VLVDRST5 2.3 - 2.72 V Power-down CC 2.4 - 2.75 V Power-up VEVRSB LVD Primary undervoltage reset Monitor threshold VLVDRSTSB 2.18 - 2.47 V Power-down CC 2.21 - 2.5 V Power-up 5.63 - - V VEXT and VEVRSB PBIST primary VPBIST5 CC overvoltage Monitor threshold Data Sheet 454 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Primary undervoltage reset threshold for VEXT before trimming VRST5 CC - - 3.0 V by last cold PORST release on supply ramp-up including voltage hysteresis. EVR secondary monitor measurement latency for all 6 supply rails tMON CC - - 3.2 µs HPOSC and SHPBG bandgap trimmed. Filter inactive. 1) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold and by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin. 2) The monitor tolerances constitute the inherent variation of the band gap and ADC over process, voltage and temperature operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the VxxPRIUV limits. All voltages are measured on pins. 3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware and reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a voltage hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior. 4) In case the application is using 3.3V single supply (Single Supply mode (e), i.e. VEXT and VDDP3 are shorted together), it is recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter VDDP3MON. 5) To monitor voltage level not provided in conditions the values for OV and UV thresholds can be generated by a linear interpolation or extrapolation based on the given points. Table 3-33 Supply Ramp Parameter Symbol Values Unit Min. Typ. Max. 8.3E-6 1 100 V/ms External VDDP3 supply ramp-up dVDDP3/dt 8.3E-6 and ramp-down slope 1)3) SR 1 100 V/ms External VDD supply ramp-up and ramp-down slope 1)3) dVDD/dt 8.3E-6 1 100 V/ms External VDDM supply ramp-up and ramp-down slope 1)3) dVDDM/dt 8.3E-6 1 100 V/ms External VEXT & VEVRSB supply dVEXT/dt ramp-up and ramp-down slope SR Note / Test Condition 1) 2) 3) SR SR 1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation. 2) Also valid incase EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid overshoots. 3) The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. • Up to 1000000 power-cycles, matching the limits defined in the table ’Supply Ramp’ are allowed for TC38x, without any restriction to reliability. Data Sheet 455 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-34 EVRC SMPS Parameter Input VEXT Voltage range Symbol VIN SR SMPS regulator output voltage VDDDC CC range including load/line regulation and aging Values Unit Note / Test Condition Min. Typ. Max. 2.97 - 5.5 V Start-up VEXT voltage > 2.6 V 1.125 - 1.375 V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 1mA ; IDDDC ≤ 1.5A ; untrimmed SMPS regulator static voltage VDDDCT CC output accuracy after trimming without dynamic load/line regulation. Programmable switching frequency fDCDC SR 1.225 1.25 1.275 V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 1mA ; IDDDC ≤ 1.5A 1.6 1.82 2.0 MHz Start-up frequency switches from 500 KHz in open loop operation to 1.82 MHz in closed loop Operation. - 0.8 - MHz Start-up frequency switches from 500 KHz in open loop operation to 1.82 MHz in closed loop Operation. 0.8 MHz to be set in SW. - - 900 µs SMPS Start-up Mode. It is is defined beween VEXTPRIUV reset threshold till PORST release, on condition that all other PORST requirements were released before. ISTART < 700mA. Startup time tSTRDC CC Switching frequency modulation spread ∆fDCSPR CC - 1.8% - MHz Maximum ripple at IMAX ∆VDDDC CC - - 16 mV VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 300mA ; IDDDC ≤ 1.5A ; ∆VDDDC = (Peak to Peak ripple / 2) - 15 19 mA fDCDC=1.82MHz; IDDDC=ISLEEP; VEXT > 2.97 V; TJ=25°C - 5 - mA LPM mode; IDDDC=ISLEEP; VEXT > 2.97 V; TJ=25°C No load current consumption of IDCNL CC SMPS regulator Data Sheet 456 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-34 EVRC SMPS (cont’d) Parameter SMPS regulator load transient response Maximum output current Symbol dVDDDCT / Values Unit Note / Test Condition Min. Typ. Max. -50 - 75 mV dI < -250mA ; IDDDC=280-1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=100 us -50 - 87 mV dI < -450mA ; IDDDC=500-1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=100 us -100 - 145 mV dI < -700mA ; IDDDC=750-1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=100 us -26 - 26 mV dI < 100mA ; IDDDC=50-1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=20us; 100 - - mA LPM mode. Typical current in LPM Mode = dlOUT CC IMAX CC ISLEEP SMPS regulator line transient response SMPS regulator efficiency Input Synchronisation frequency Data Sheet dVDDDCT / 1.5 - - A limited by thermal constraints and component choice -75 - 75 mV dV/dT=120V/ms; dV < 2.97 - 5.5V ; IDDDC=501500mA; -12.5 - 12.5 mV dV/dT=1V/ms; dV < 2.97 - 5.5V ; IDDDC=501500mA; - 80 - % VIN=3.3V; IDDDC=1500mA; fDCDC=1.82MHz - 75 - % VIN=5V; IDDDC=1500mA; fDCDC=1.82MHz 1.6 1.82 2.0 MHz dVIN CC nDC CC fDCDCSYNC SR 457 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-35 EVRC SMPS External components Parameter Symbol External output capacitor value COUT SR Values Unit Note / Test Condition Min. Typ. Max. 20.8 32 43.2 µF IDDDC=1.5A; fDDDC = 0.8MHz 15.4 22 29.7 µF IDDDC=1.5A; fDDDC = 1) 1.82MHz External output capacitor ESR COUT_ESR SR External input capacitor value 1) External input capacitor ESR External inductor value - - 50 mOhm f≥0.5MHz ; f≤10MHz - - 100 Ohm f=10Hz 6.5 10 13.5 µF IDDDC=1.5A 4.42 6.8 9.18 µF IDDDC=500mA CIN_ESR SR - - 50 mOhm f≥0.5MHz ; f≤10MHz - - 100 Ohm 3.29 4.7 6.11 2.31 3.3 4.29 µH CIN SR LDC SR f=100Hz fDCDC=0.8MHz fDCDC=1.82MHz External inductor DCR LDC_DCR SR - - 0.2 Ohm P + N-channel MOSFET logic level VLL SR - 2.5 V P + N-channel MOSFET drain source breakdown voltage |VBR_DS| SR +7 - - V NMOS - VGS = 0. - - -7 V PMOS - VGS = 0. P + N-channel MOSFET drain source ON-state resistance RON SR - - 150 mOhm IDDDC=1.5A; |VGS|=2.5V ; TA=25°C - - 200 mOhm IDDDC=500mA; |VGS|=2.5V ; TA=25°C - - 8 nC P + N-channel MOSFET Gate Charge QG SR - IDDDC=1.5A; NMOS|VGS|=5V; 1.5A pulsed drain current -8 - - nC IDDDC=1.5A; PMOS|VGS|=5V; 1.5A pulsed drain current - - 4 nC IDDDC=500mA; NMOS|VGS|=5V; 0.5A pulsed drain current -4 - - nC IDDDC=500mA; PMOS|VGS|=5V; 0.5A pulsed drain current External Inductor Saturation Current Margin Data Sheet ∆ISAT SR 400 - 458 OPEN MARKET VERSION - mA The saturation current of the coil must be larger than IDDDC + ∆ISAT V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification PMS Table 3-35 EVRC SMPS External components (cont’d) Parameter Symbol P + N-channel MOSFET Gate threshold voltage VGSTH SR N-channel MOSFET reverse diode forward voltage VRDN SR Values Unit Note / Test Condition Min. Typ. Max. - 1 - V NMOS - -1 - V PMOS - 0.8 - V 1) Capacitor min-max range represent typical +-35% tolerance including DC bias effect. The trace resistance from the capacitor to the supply or ground rail should be limited to 25 mOhm. Data Sheet 459 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification System Phase Locked Loop (SYS_PLL) 3.16 System Phase Locked Loop (SYS_PLL) Table 3-36 PLL System Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition DCO Input frequency range fREF CC 10 - 40 MHz Modulation Amplitude MA CC 0 - 2 % Peak Period jitter DP CC -200 - 200 ps without modulation (PLL output frequency) Peak Accumulated Jitter DPP CC -5 - 5 ns without modulation Total long term jitter JTOT CC - - 11.5 ns including modulation; MA 1.25%; fREF 20MHz System frequency deviation fSYSD CC - - 0.01 % with active modulation DCO frequency range fDCO CC 400 - 800 MHz PLL lock-in time tL CC 4 - 100 µs Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 460 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Peripheral Phase Locked Loop (PER_PLL) 3.17 Peripheral Phase Locked Loop (PER_PLL) Table 3-37 PLL Peripheral Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Peak Accumulated jitter at SYSCLK pin DPP CC -1000 - 1000 ps Peak only Peak accumulated jitter DPPI CC -700 - 700 ps Peak only RMS Accumulated jitter DRMS CC -100 - 100 ps measured over 1 µs; fREF = 20 MHz and fDCO = 640 MHz or fREF = 25 MHz and fDCO = 800 MHz Peak Period jitter DP CC -200 - 200 ps fDCO = 640 MHz or fDCO = 800 MHz Absolute RMS jitter (PLL out) JABS10 CC -125 - 125 ps fREF = 10 MHz; fDCO = 640 MHz Absolute RMS jitter (PLL out) JABS20 CC -85 - 85 ps fREF = 20 MHz; fDCO = 640 MHz Absolute RMS jitter (PLL out) JABS25 CC -85 - 85 ps fREF = 25 MHz; fDCO = 800 MHz DCO frequency range fDCO CC 400 - 800 MHz DCO input frequency range fREF CC 10 - 40 MHz PLL lock-in time tL CC 4 - 100 µs Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 461 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification AC Specifications 3.18 AC Specifications All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted in column Note / Test Condition. Unless otherwise noted in the figures the timings are defined with the following guidelines: VEXT/FL EX / VD D P3 90% VSS 90% 10% 10% tr tf rise_fall Figure 3-8 Definition of rise / fall times VEXT/FL EX / VD D P3 VSS VEXT/FL EX / VD D P3 2 Timing Reference Points VEXT /FL EX / VD D P3 2 timing_reference Figure 3-9 Time Reference Point Definition Data Sheet 462 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification JTAG Parameters 3.19 JTAG Parameters The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Table 3-38 JTAG Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition TCK clock period t1 SR 50 - - ns TCK high time t2 SR 10 - - ns TCK low time t3 SR 10 - - ns TCK clock rise time t4 SR - - 4 ns TCK clock fall time t5 SR - - 4 ns TDI/TMS setup to TCK rising edge t6 SR 6.0 - - ns TDI/TMS hold after TCK rising t7 SR edge 6.0 - - ns TDO valid after TCK falling edge (propagation delay) t8 CC 3.0 - - ns CL≤20pF - - 25 ns CL≤50pF TDO hold after TCK falling edge t18 CC 2 - - ns TDO high impedance to valid from TCK falling edge t9 CC - - 25 ns CL≤50pF TDO valid output to high impedance from TCK falling edge t10 CC - - 25 ns CL≤50pF t1 0.9 VEXT 0.5 VEXT t2 t5 t3 t4 0.1 VEXT MC_ JTAG_ TCK Figure 3-10 Test Clock Timing (TCK) Data Sheet 463 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification JTAG Parameters TCK t6 t7 t6 t7 TMS TDI t9 t8 t1 0 TDO t18 MC_JTAG Figure 3-11 JTAG Timing Data Sheet 464 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification DAP Parameters 3.20 DAP Parameters The following parameters are applicable for communication through the DAP debug interface. Table 3-39 DAP Parameter DAP0 clock rise time DAP0 clock fall time Symbol t14 SR t15 SR Values Unit Note / Test Condition Min. Typ. Max. - - 1 ns f=160MHz - - 4 ns f=40MHz - - 2 ns f=80MHz - - 1 ns f=160MHz - - 4 ns f=40MHz - - 2 ns f=80MHz 4 - - ns 5 - - ns DAP1 setup to DAP0 rising edge t16 SR DAP1 hold after DAP0 rising edge t17 SR 2 - - ns DAP1 valid per DAP0 clock period t19 CC 4 - - ns CL=20pF ; f=160MHz 8 - - ns CL=20pF ; f=80MHz 10 - - ns CL=50pF ; f=40MHz DAP0 high time t12 SR 2 - - ns DAP0 low time t13 SR 2 - - ns DAP0 clock period t11 SR 6.25 - - ns f=40MHz Table 3-40 SCR DAP Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition DAP0 clock rise time t14 SR - - 8 ns f=20MHz DAP0 clock fall time t15 SR - - 8 ns f=20MHz DAP1 setup to DAP0 rising edge t16 SR 10 - - ns DAP1 hold after DAP0 rising edge t17 SR 10 - - ns DAP1 valid per DAP0 clock period t19 CC 30 - - ns DAP0 high time t12 SR 15 - - ns DAP0 low time t13 SR 15 - - ns DAP0 clock period t11 SR 50 - - ns Data Sheet 465 OPEN MARKET VERSION CL=20pF ; f=20MHz V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification DAP Parameters t 11 t13 t12 DAP0 t15 t14 0.9 VEXT 0.5 VEXT 0.1 VEXT t16 t17 DAP1 (Host to Device) t11 DAP11),2) (Device to Host) t19 1) The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. 2) No explicite setup and hold times are given for DAP1 for the direction Device to Host. Only t11 and t19 are guaranteed and the tool may set the sample point freely. Figure 3-12 DAP Timing Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. Data Sheet 466 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification ASCLIN SPI Master Timing 3.21 ASCLIN SPI Master Timing This section defines the timings for the ASCLIN in the TC37xEXT. Note: Pad asymmetry is already included in the following timings. Table 3-41 Master Mode strong sharp (ss) output pads Parameter ASCLKO clock period Symbol t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 20 - - ns CL=25pF -2 - 2 ns CL=25pF MTSR delay from ASCLKO shifting edge t51 CC -3.5 - 3.5 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC -3 - 3.5 ns CL=25pF MRST setup to ASCLKO latching edge t52 SR 25 - - ns CL=25pF MRST hold from ASCLKO latching edge t53 SR -2 - - ns CL=25pF Unit Note / Test Condition Table 3-42 Master Mode strong medium (sm) output pads Parameter ASCLKO clock period Symbol t50 CC Deviation from ideal duty cycle t500 CC Values Min. Typ. Max. 50 - - ns CL=50pF -5 - 5 ns CL=50pF MTSR delay from ASCLKO shifting edge t51 CC -7 - 7 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -7 - 7 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 35 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=50pF Unit Note / Test Condition Table 3-43 Master Mode medium (m) output pads Parameter ASCLKO clock period Symbol t50 CC Deviation from ideal duty cycle t500 CC Values Min. Typ. Max. 160 - - ns CL=50pF -10 - 10 ns CL=50pF MTSR delay from ASCLKO shifting edge t51 CC -20 - 20 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -20 - 20 ns CL=50pF Data Sheet 467 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification ASCLIN SPI Master Timing Table 3-43 Master Mode medium (m) output pads (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition MRST setup to ASCLKO latching edge t52 SR 80 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -15 - - ns CL=50pF t50 ASCLKO t51 t500 t51 MTSR t52 MRST t53 Data valid Data valid t510 ASLSO ASCLIN_TmgMM.vsd Figure 3-13 ASCLIN SPI Master Timing Data Sheet 468 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification QSPI Timings, Master and Slave Mode 3.22 QSPI Timings, Master and Slave Mode This section defines the timings for the QSPI in the TC37xEXT. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings: Note: Pad asymmetry is already included in the following timings. Table 3-44 Master Mode Timing, LVDS output pads for data and clock Parameter Symbol Values Min. 1) Unit Note / Test Condition Typ. Max. - - ns CL=25pF SCLKO clock period t50 CC 20 Deviation from the ideal duty cycle t500 CC -1 1) - 1 1) ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -3 1) - 4 1) ns CL=25pF -4 1) - 5.5 1) ns CL=25pF, driver SLSOn deviation from the ideal t510 CC programmed position strength ss -10 1) -30 1) - 10 1) 30 1) ns CL=25pF, driver strength sm - ns CL=25pF, driver strength m MRST setup to SCLK latching edge t52 SR 18 1) 19.5 1) - - ns CL=25pF; valid for LVDS Input pads of QSPI2 only - - ns CL=25pF; valid for LVDS Input pads of QSPI4 only MRST hold from SCLK latching t53 SR -1 1) ns CL=25pF; valid for edge LVDS Input pads only 1) The load (CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to add an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply. Table 3-45 Master Mode Strong Sharp (ss) output pads Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition SCLKO clock period t50 CC 50 - - ns CL=25pF Deviation from the ideal duty cycle t500 CC -2 - 2 ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -4 - 5 ns CL=25pF -4 - 5 ns CL=25pF 25 1) 2) - - ns CL=25pF -2 1)2) - - ns CL=25pF SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge t52 SR MRST hold from SCLK latching t53 SR edge Data Sheet 469 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification QSPI Timings, Master and Slave Mode 1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-46 Master Mode Strong Medium (sm) output pads Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition SCLKO clock period t50 CC 50 - - ns CL=50pF Deviation from the ideal duty cycle t500 CC -5 - 5 ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC -7 - 7 ns CL=50pF -7 - 7 ns CL=50pF 35 1) 2) - - ns CL=50pF -5 1)2) - - ns CL=50pF SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge t52 SR MRST hold from SCLK latching t53 SR edge 1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-47 Master Mode Medium (m) output pads Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition SCLKO clock period t50 CC 160 - - ns CL=50pF Deviation from the ideal duty cycle t500 CC -10 - 10 ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC -20 - 20 ns CL=50pF -20 - 20 ns CL=50pF t52 SR 80 1) 2) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -15 1)2) - - ns CL=50pF 1)2) - - ns CL=50pF; SCR SSC SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge -13 1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-48 Slave mode timing Parameter Symbol Values Unit Min. Typ. Max. SCLK clock period t54 SR 4 x TMAX - - ns SCLK duty cycle t55/t54 SR 40 - 60 % Data Sheet 470 OPEN MARKET VERSION Note / Test Condition V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification QSPI Timings, Master and Slave Mode Table 3-48 Slave mode timing (cont’d) Parameter Symbol MTSR setup to SCLK latching edge Values t56 SR Unit Note / Test Condition Min. Typ. Max. 6 - - ns Input Level AL 6 - - ns Input Level TTL MTSR hold from SCLK latching t57 SR edge 4 - - ns Input Level AL 6 - - ns Input Level TTL SLSI setup to first SCLK shift edge t58 SR 4 - - ns Input Level AL 6 - - ns Input Level TTL SLSI hold from last SCLK latching edge t59 SR 3 - - ns Input Level AL 6 - - ns Input Level TTL MRST delay from SCLK shift edge t60 CC 5 - 35 ns driver = strong edge = medium ; CL=50pF 2 - 24 ns driver = strong edge = sharp ; CL=50pF 15 - 80 ns medium driver ; CL=50pF 14 - - ns medium driver ; CL=50pF; SCR SSC t50 t500 0.5 VEXT/FLEX SCLK1)2) t51 SAMPLING POINT 0.5 VEXT/FLEX MTSR1) t52 MRST t53 Data valid 1) Data valid t510 SLSOn 0.5 VEXT/FLEX 2) 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0. QSPI_TmgMM.vsd Figure 3-14 Master Mode Timing Data Sheet 471 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification QSPI Timings, Master and Slave Mode t54 SCLKI t55 MTSR 1) MRST 1) Last latching SCLK edge First latching SCLK edge First shift SCLK edge 1) t56 0.5 VEXT/FLEX t55 t56 t57 Data valid t60 t57 Data valid t60 0.5 VEXT/FLEX t58 t59 t61 SLSI 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. QSPI_TmgSM.vsd Figure 3-15 Slave Mode Timing Data Sheet 472 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification MSC Timing 5 V Operation 3.23 MSC Timing 5 V Operation The following section defines the timings. Note: Pad asymmetry is already included in the following timings. Note: Load for LVDS pads are defined as differential loads in the following timings. Table 3-49 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V Parameter Symbol Values Min. FCLPx clock period t40 CC Deviation from ideal duty cycle t400 CC Unit Note / Test Condition ns LVDS; CL=50pF Typ. Max. - - - 1 3) ns LVDS; 0 < CL < 50pF 3) - 3 3) ns CL=50pF 2 * TA 1) 2) 3) -1 3) SOPx output delay t44 CC -3 ENx output delay t45 CC -4 3) - 5 3) ns ss; CL=50pF; ABRA block bypassed -4 3) - 4 3) ns ss; CL=50pF; ABRA block used -2 3) - 10 3) ns sm; CL=50pF - 3) ns m; CL=50pF -30 3) 30 1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC. 2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended. 3) The load (CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply. Table 3-50 Strong sharp (ss) driver for clock/data valid for 5V Parameter FCLPx clock period Symbol t40 CC Deviation from ideal duty cycle t400 CC Values Unit Note / Test Condition Min. Typ. Max. 2 * TA - - ns CL=50pF -2 - 2 ns CL=50pF SOPx output delay t44 CC -4 - 3.5 ns CL=50pF ENx output delay t45 CC -4 - 3.5 ns CL=50pF Unit Note / Test Condition Table 3-51 Strong medium (sm) driver for clock/data valid for 5V Parameter FCLPx clock period Symbol t40 CC Deviation from ideal duty cycle t400 CC Values Min. Typ. Max. 2 * TA - - ns CL=50pF -5 - 5 ns CL=50pF SOPx output delay t44 CC -7 - 7 ns CL=50pF ENx output delay t45 CC -7 - 7 ns CL=50pF Data Sheet 473 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification MSC Timing 5 V Operation Table 3-52 Medium (m) driver for clock/data valid for 5V Parameter Symbol t40 CC FCLPx clock period Deviation from ideal duty cycle t400 CC Values Unit Note / Test Condition Min. Typ. Max. 2 * TA - - ns CL=50pF -10 - 10 ns CL=50pF SOPx output delay t44 CC -20 - 20 ns CL=50pF ENx output delay t45 CC -20 - 20 ns CL=50pF Unit Note / Test Condition Table 3-53 Upstream Interface Parameter Symbol Values Min. Typ. Max. SDI bit time t46 SR 8 * tMSC - - ns SDI rise time t48 SR - - 200 ns SDI fall time t49 SR - - 200 ns t40 t400 FCLP t44 t44 t45 t45 SOP EN 0.5 VEXT/FLEX t48 t49 0.9 VEXT/FLEX SDI 0.1 VEXT/FLEX t46 t46 MSC_Timing_A.vsd Figure 3-16 MSC Interface Timing Note: The SOP data signal is sampled with the falling edge of FCLP in the target device. Data Sheet 474 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Ethernet Interface (ETH) Characteristics 3.24 Ethernet Interface (ETH) Characteristics 3.24.1 ETH Measurement Reference Points ETH Clock 1.4 V 1.4 V ETH I/O 2.0 V 0.8 V 2.0 V 0.8 V tR tF ETH_Testpoints.vsd Figure 3-17 ETH Measurement Reference Points Data Sheet 475 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Ethernet Interface (ETH) Characteristics 3.24.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) Table 3-54 ETH Management Signal Parameters valid for 3.3V Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition ETH_MDC period t1 CC 400 - - ns CL=25pF ETH_MDC high time t2 CC 160 - - ns CL=25pF ETH_MDC low time t3 CC 160 - - ns CL=25pF ETH_MDIO setup time (output) t4 CC 10 - - ns CL=25pF ETH_MDIO hold time (output) t5 CC 10 - - ns CL=25pF ETH_MDIO data valid (input) t6 SR 0 - 300 ns CL=25pF t1 t3 t2 ETH_MDC ETH_MDIO sourced by controller : ETH_MDC t4 ETH_MDIO (output ) t5 Valid Data ETH_MDIO sourced by PHY: ETH_MDC t6 ETH_MDIO (input ) Valid Data ETH_Timing-Mgmt.vsd Figure 3-18 ETH Management Signal Timing Data Sheet 476 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Ethernet Interface (ETH) Characteristics 3.24.3 ETH MII Parameters In the following, the parameters of the MII (Media Independent Interface) are described. Table 3-55 ETH MII Signal Timing Parameters Parameter Symbol t7 SR Clock period t8 SR Clock high time t9 SR Clock low time Values Unit Note / Test Condition Min. Typ. Max. 40 - - ns CL=25pF ; baudrate=100Mbps 400 - - ns CL=25pF ; baudrate=10Mbps 14 - 26 ns CL=25pF ; baudrate=100Mbps 140 1) - 260 2) ns CL=25pF ; baudrate=10Mbps 14 - 26 ns CL=25pF ; baudrate=100Mbps 140 1) - 260 2) ns CL=25pF ; baudrate=10Mbps Input setup time t10 SR 10 - - ns CL=25pF Input hold time t11 SR 10 - - ns CL=25pF Output valid time t12 CC 0 - 25 ns CL=25pF 1) Defined by 35% of clock period. 2) Defined by 65% of clock period. t7 t9 ETH_MII_RX_CLK ETH_MII_TX_CLK t8 ETH_MII_RX_CLK t1 0 ETH_MII_RXD[3:0] ETH_MII_RX_DV ETH_MII_RX_ER (sourced by PHY ) t1 1 Valid Data ETH_MII_TX_CLK t1 2 ETH_MII_TXD[3:0] ETH_MII_TXEN (sourced by controller ) Valid Data ETH_Timing-MII.vsd Figure 3-19 ETH MII Signal Timing Data Sheet 477 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Ethernet Interface (ETH) Characteristics 3.24.4 ETH RMII Parameters In the following, the parameters of the RMII (Reduced Media Independent Interface) are described. Table 3-56 ETH RMII Signal Timing Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 20 - - ns 50ppm ; CL=25pF ETH_RMII_REF_CL clock high t14 CC time 7 1) - 13 2) ns CL=25pF ETH_RMII_REF_CL clock low t15 CC time 7 1) - 13 2) ns CL=25pF t13 CC ETH_RMII_REF_CL clock period ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time t16 CC 4 - - ns CL=25pF ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time t17 CC 2 - - ns CL=25pF 1) Defined by 35% of clock period. 2) Defined by 65% of clock period. t1 3 t1 5 t14 ETH_RMII_REF_CL ETH_RMII_REF_CL t1 6 ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER t17 Valid Data ETH_Timing-RMII .vsd Figure 3-20 ETH RMII Signal Timing Data Sheet 478 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Ethernet Interface (ETH) Characteristics 3.24.5 ETH RGMII Parameters In the following, the parameters of the RGMII are described. Table 3-57 ETH RGMII Signal Timing Parameters valid for 3.3V Parameter TX Clock period Symbol t19 CC Values Unit Note / Test Condition Min. Typ. Max. 36 40 44 ns 100Mbps 360 400 440 ns 10Mbps 7.2 8 8.8 ns Gigabit Data to Clock Output skew t20 CC -500 0 500 ps Data to Clock input skew (at receiver) t21 SR 1 1.8 2.6 ns SKEWCTL.RXCFG = 0; SKEWCTL.TXCFG =0 Clock duty cycle tduty CC 40 50 60 % 10/100Mbps 45 50 55 % Gigabit GREFCLK duty cycle tduty_in SR 45 - 55 % GREFCLK Input accuracy ACC SR -0.005 - 0.005 % Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD)) Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS)) Data Sheet 479 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification E-Ray Parameters 3.25 E-Ray Parameters The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL = 25 pF. Table 3-58 Transmit Parameters Parameter Symbol Values Min. Rise time of TxEN tdCCTxENRise2 5 Fall time of TxEN Unit Note / Test Condition Typ. Max. - 9 ns CL=25pF - 9 ns CL=25pF - 9 ns 20% - 80% ; CL=25pF CC tdCCTxENFall25 CC Sum of rise and fall time tdCCTxRise25+ dCCTxFall25 CC Sum of delay between TP1_FF tdCCTxEN01 and TP1_CC and delays CC derived from TP1_FFi, rising edge of TxEN - - 25 ns Sum of delay between TP1_FF tdCCTxEN10 and TP1_CC and delays CC derived from TP1_FFi, falling edge of TxEN - - 25 ns -2.45 - 2.45 ns Sum of delay between TP1_FF tdCCTxD01 and TP1_CC and delays CC derived from TP1_FFi, rising edge of TxD - - 25 ns Sum of delay between TP1_FF tdCCTxD10 and TP1_CC and delays CC derived from TP1_FFi, falling edge of TxD - - 25 ns TxD signal sum of rise and fall ttxd_sum CC time at TP1_BD - - 9 ns Asymmetry of sending ttx_asym CC CL=25pF Table 3-59 Receive Parameters Parameter Symbol Values Min. Max. - 43.0 ns CL=25pF - 44.0 ns CL=15pF 35 - 70 % 30 - 65 % tdCCTxAsymAcc -30.5 Acceptance of asymmetry at receiving part tdCCTxAsymAcc -31.5 Threshold for detecting logical high TuCCLogic1 Threshold for detecting logical low TuCCLogic0 Data Sheet Note / Test Condition Typ. Acceptance of asymmetry at receiving part ept25 Unit SR ept15 SR SR SR 480 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification E-Ray Parameters Table 3-59 Receive Parameters (cont’d) Parameter Symbol Values Unit Min. Typ. Max. Sum of delay between TP4_CC tdCCRxD01 and TP4_FF and delays CC derived from TP4_FFi, rising edge of RxD - - 10 ns Sum of delay between TP4_CC tdCCRxD10 and TP4_FF and delays CC derived from TP4_FFi, falling edge of RxD - - 10 ns Data Sheet 481 OPEN MARKET VERSION Note / Test Condition V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification HSCT Parameters 3.26 HSCT Parameters Table 3-60 HSCT - Rx parasitics and loads Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Total Budget for complete receiver including silicon, package, pins and bond wire Capacitance total budget Ctotal CC - 3.5 5 pF Parasitic inductance budget Htotal CC - 5 - nH Table 3-61 HSCT - Rx/Tx setup timing Parameter Symbol Values Unit Min. Typ. Max. 40 - 60 % Note / Test Condition RX o/p duty cycle DCrx CC Disable time of the LVDS pad tLVDSDIS CC - - 20 ns Enable time of the LVDS pad tLVDSEN CC - - 400 ns Wakeup time from Sleep Mode tSWU CC - - 250 ns Maximum length of a wake-up glitch that does not wake-up the receiver tWUP CC - - 0.2 ns Bias startup time tbias CC - 5 10 µs Bias distributor waking up from power down and provide stable Bias. RX startup time trxi CC - - 600 ns Wake-up RX from power down. TX startup time ttx CC - - 280 ns Wake-up TX from power down. Data Sheet 482 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Inter-IC (I2C) Interface Timing 3.27 Inter-IC (I2C) Interface Timing This section defines the timings for I2C in the TC37xEXT. All I2C timing parameter are SR for Master Mode and CC for Slave Mode. Table 3-62 I2C Standard Mode Timing Parameter Symbol Values Unit Note / Test Condition Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Min. Typ. Max. - - 300 ns - - 400 pF Bus free time between a STOP t10 and ATART condition 4.7 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 - - 1000 ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data hold time t3 0 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 250 - - ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 4.7 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 4 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Hold time for the (repeated) START condition t7 4 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Fall time of both SDA and SCL t1 Capacitive load for each bus line Data Sheet Cb SR 483 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Inter-IC (I2C) Interface Timing Table 3-62 I2C Standard Mode Timing (cont’d) Parameter Set-up time for (repeated) START condition Symbol t8 Set-up time for STOP condition t9 Values Unit Note / Test Condition Min. Typ. Max. 4.7 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line 4 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Unit Note / Test Condition 300 ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Table 3-63 I2C Fast Mode Timing Parameter Symbol Values Min. Fall time of both SDA and SCL t1 Typ. 20+0.1*C - Max. b Capacitive load for each bus line Cb SR - - 400 pF Bus free time between a STOP t10 and ATART condition 1.3 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 20+0.1*C - 300 ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line b Data hold time t3 0 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 100 - - ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 1.3 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data Sheet 484 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Inter-IC (I2C) Interface Timing Table 3-63 I2C Fast Mode Timing (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Hold time for the (repeated) START condition t7 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for (repeated) START condition t8 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for STOP condition t9 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Unit Note / Test Condition Table 3-64 I2C High Speed Mode Timing Parameter Symbol Values Min. Typ. Max. Capacitive load for each bus line Cb SR - - 400 pF Fall time of SCL t11 10 1) - 40 1) ns bus line load of 100pF t12 10 1) - 80 1) ns bus line load of 100pF 1) - 40 1) ns bus line load of 100pF - 80 1) ns bus line load of 100pF - 70 1) ns bus line load of 100pF - - ns bus line load of 100pF - - ns bus line load of 100pF Fall time of SDA Rise time of SCL t13 10 Rise time of SDA t14 10 1) t3 1) Data hold time Data set-up time Low period of SCL clock High period of SCL clock t4 t5 t6 0 10 1) 160 60 1) 1) - - ns bus line load of 100pF 1) - - ns bus line load of 100pF - - ns bus line load of 100pF Set-up time for STOP condition t9 160 1) ns 1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard. bus line load of 100pF Hold time for the (repeated) START condition t7 160 Set-up time for (repeated) START condition t8 160 1) Data Sheet 485 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Inter-IC (I2C) Interface Timing t1 SDA t2 t4 70% 30% t1 t3 t2 t6 SCL th S t7 9 clock t5 t 10 SDA t8 t7 t9 SCL th 9 clock Sr P S Figure 3-23 I2C Standard and Fast Mode Timing Data Sheet 486 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification SDMMC Interface Timing 3.28 SDMMC Interface Timing Table 3-65 SDMMC Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Clock period Data Transfer Mode t1 CC 20 - - ns push-pull, CL ≤ 30pF, VEXT = 3.3V Clock period Indentification Mode t2 CC - - 2500 ns open-drain, CL ≤ 30pF, VEXT = 3.3V Clock low time t3 CC 6,5 - - ns CL ≤ 30pF, VEXT = 3.3V Clock high time t4 CC 6,5 - - ns CL ≤ 30pF, VEXT = 3.3V Data output valid time before rising clock edge t5 CC 3 - - ns CL ≤ 30pF, VEXT = 3.3V Data output valid time after rising clock edge t6 CC 3 - - ns CL ≤ 30pF, VEXT = 3.3V Data input hold time t7 SR 2,5 - - ns CL ≤ 30pF, VEXT = 3.3V, TTL levels t8 SR Data Input delay time - - 13,7 ns CL ≤ 30pF, VEXT = 3.3V, TTL levels t9 SR Data Input setup time 5,2 - - ns CL ≤ 30pF, VEXT = 3.3V, TTL levels t1 t3 t4 CLK t5 Output t6 DATA DATA t8 t9 t7 Input DATA DATA Figure 3-24 SDMMC Timing Data Sheet 487 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Camera Interface Timing (CIF) 3.29 Camera Interface Timing (CIF) Table 3-66 Timings for 3.3V+-10% pad power supply Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Pixel clock period t70 SR 10.42 - - ns HSYNC, VSYNC set up time t71 SR 2.5 - - ns CIF input level 2.5 - - ns AL input level 2.5 - - ns CIF input level 2.5 - - ns AL input level 2.5 - - ns AL input level 2.5 - - ns CIF input level 2.5 - - ns CIF input level 2.5 - - ns AL input level Unit Note / Test Condition HSYNC, VSYNC hold time Pixel data set up time Pixel data hold time t72 SR t73 SR t74 SR Table 3-67 Timings for 0.4V to 2.4V input signals (2.8V imager) Parameter Symbol Values Min. Typ. Max. Pixel clock period t70 SR 12.5 - - ns HSYNC, VSYNC set up time t71 SR 3 - - ns CIF Input Levels, 3.3V±10% HSYNC, VSYNC hold time t72 SR 3 - - ns CIF Input Levels, 3.3V±10% Pixel data set up time t73 SR 3 - - ns CIF Input Levels, 3.3V±10% Pixel data hold time t74 SR 3 - - ns CIF Input Levels, 3.3V±10% Unit Note / Test Condition Table 3-68 Timings for 1.8V imager, CIF input level Parameter Symbol Values Min. Typ. Max. Pixel clock period t70 SR 10.42 - - ns HSYNC, VSYNC set up time t71 SR 2 - - ns Input signal 0.4V to 1.4V HSYNC, VSYNC hold time t72 SR 2 - - ns Input signal 0.4V to 1.4V Pixel data set up time t73 SR 2 - - ns Input signal 0.4V to 1.4V Pixel data hold time t74 SR 2 - - ns Input signal 0.4V to 1.4V Data Sheet 488 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Flash Target Parameters 3.30 Flash Target Parameters Table 3-69 Flash Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Program Flash Erase Time per tERP CC logical sector 1) - - 0.5 s cycle count < 1000 Program Flash Erase Time per tMERP CC Multi-Sector Command 1) - - 0.5 s For consecutive logical sectors in a physical sector with total range ≤ 512 kByte; cycle count < 1000 Program Flash program time per page in 5 V mode 1) tPRP5 CC - - 80 µs 32 Byte Program Flash program time per page in 3.3 V mode 1) tPRP3 CC - - 115 µs 32 Byte Program Flash program time per burst in 5 V mode 1) tPRPB5 CC - - 220 µs 256 Byte Program Flash program time per burst in 3.3 V mode 1) tPRPB3 CC - - 530 µs 256 Byte Program Flash program time for 1 MByte with burst programming in 3.3 V mode excluding communication 1) tPRPB3_1MB - - 2.2 s Derived value for documentation purpose Program Flash program time for 1 MByte with burst programming in 5 V mode excluding communication 1) tPRPB5_1MB - - 1 s Derived value for documentation purpose Program Flash program time tPRPB5_PF for complete PFlash with burst CC programming in 5 V mode excluding communication 1) - - 6 s Derived value for documentation purpose Write Page Once adder 1) - - 20 µs Adder to Program Time when using Write Page Once Program Flash suspend to read tSPNDP CC latency 1) - - 120 µs For Write Burst, Verify Erased and for multi(logical) sector erase commands Data Flash Erase Disturb Limit NDFD CC (single ended sensing mode) - - 50 cycles Data Flash Erase Disturb Limit NDFDC CC (complement sensing mode) - - 500 cycles NUCBD CC - - 500 cycles UCB Erase Disturb Limit Data Sheet CC CC tADD CC 489 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Flash Target Parameters Table 3-69 Flash (cont’d) Parameter Program time data flash per page 1)2) Symbol tPRD CC Complete Device Flash Erase tER_Dev CC Time PFlash and DFlash 1)3) 4) Values Unit Note / Test Condition Min. Typ. Max. - - 75 µs 8 Byte - 4.3 7 s Valid for less than 1000 cycles, w/o UCB. Derived value for documentation purpose. 32 Byte 5) Data Flash program time per burst 1)2) tPRDB CC - - 140 µs Data Flash suspend to read latency 1) tSPNDD CC - - 120 µs Wait time after margin change tFL_MarginDel - - 2 µs Program Flash Endurance per NE_P CC Logical Sector - - 1000 cycles Replace logical sector command shall be used if a sector fails during erase or program Number of erase operations NERP CC per physical sector in program flash - - 16000 cycles Program Flash Retention Time, tRET CC Sector 20 - - years Max. 1000 erase/program cycles UCB Retention Time tRTU CC 20 - - years Max. 100 erase/program cycles per UCB, max 500 erase/program cycles for all UCBs together Data Flash access delay tDF CC - - 100 ns see RFLASH of DMU register HF_DWAIT Data Flash ECC Delay tDFECC CC - - 20 ns see RECC of DMU register HF_DWAIT Program Flash access delay tPF CC - - 30 ns see RFLASH of DMU register HF_PWAIT Program Flash ECC delay tPFECC CC - - 10 ns see RECC and CECC of DMU register HF_PWAIT Number of erase operations on NERD0C CC DF0 over lifetime (complement sensing mode) 6) - - 4000000 cycles Number of erase operations on NERD0S CC DF0 over lifetime (single ended sensing mode) 7) - - 750000 cycles CC Data Sheet 490 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Flash Target Parameters Table 3-69 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number of erase operations on NERD1C CC DF1 over lifetime (complement sensing mode) 6) - - 2000000 cycles Number of erase operations on NERD1S CC DF1 over lifetime (single ended sensing mode) 7) - - 500000 cycles Data Flash Endurance per NE_EEP10C EEPROMx sector (complement CC sensing mode) 8) - - 500000 cycles Max. data retention time 10 years NE_EEP10S - - 125000 cycles Retention time and Tj according below example temperature profile - - 125000 cycles max data retention time 20y, Tj=110°C - - 125000 cycles max data retention time 8.2y, Tj=125°C Data Flash Endurance per HSMx sector (complement sensing mode) 8) NE_HSMC CC - - 250000 cycles Max. data retention time 10 years Data Flash Endurance per HSMx sector (single ended sensing mode) 8) NE_HSMS CC - - 125000 cycles Retention time and Tj according below example temperature profile - - 125000 cycles max data retention time 20y, Tj=110°C - - 125000 cycles max data retention time 8.2y, Tj=125°C DataFlash Endurance per EEPROMx sector (single ended sensing mode) 8) CC Junction temperature limit for PFlash program/erase operations TJPFlash SR - - 150 °C Data Flash Erase Time per Sector 1)3)5) tERD1 CC - - 0.5 s Max. 1000 erase/program cycles Data Flash Erase Time per Sector 1)3)5) tERDM CC - - 1.5 s Max allowed cycles, see NE_EEP10 and NE_HSM parameters DataFlash Adder on Erase Time per 32kByte erase size when using complement sensing mode 1) tER_ADDC32C - - 50 ms Adder per 32 kByte on erase time; applicable only when using complement mode Data Sheet CC 491 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Flash Target Parameters Table 3-69 Flash (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Data Flash Erase Time per Multi-Sector Command 1)3)5) tMERD1 CC - - 0.5 s Max 1000 erase/program cycles; For consecutive logical sectors ≤ 256KBytes Data Flash Erase Time per Multi-Sector Command 1)3)5) tMERDM CC - - 1.5 s Max allowed cycles, see NE_EEP10x and NE_HSMx Parameters; For consecutive logical sectors ≤ 256 kByte Program Flash Access Delay at tPF_low_VDDP3 reduced VDDP3 voltage supply CC during cranking - 60 ns see register DMU_HF_PWAIT.CFL ASH Data Flash Erase Verify time per page (Complement Sensing) 2) tVER_PAGE_D - - 10 µs Time per 8 Byte page for Verify Erased Page command Data Flash Erase Verify time per page (Single Ended Sensing) 1) tVER_PAGE_D - - 10 µs Time per 8 Byte page for Verify Erased Page command Program Flash Erase Verify time per page 1) tVER_PAGE_P - - 10 µs Time per 32 Byte page for Verify Erased Page command Data Flash Erase Verify time per sector (Complement Sensing) 1) tVER_SEC_DC - - 200 µs Time per 2 KB sector for Verify Erased Logical Sector Range command Data Flash Erase Verify time per sector (Single Ended Sensing) 1) tVER_SEC_DS - - 360 µs Time per 4 KB sector for Verify Erased Logical Sector Range command Program Flash Erase Verify time per sector 1) tVER_SEC_P - - 360 µs Time per 16KB sector for Verify Erased Logical Sector Range command Data Flash Erase Verify time per wordline (Complement Sensing) 1) tVER_WL_DC - - 30 µs Data Flash Erase Verify time per wordline (Single Ended Sensing) 1) tVER_WL_DS - - 50 µs Program Flash Erase Verify time per wordline 1) 1) Only vaild for fFSI = 100MHz. tVER_WL_P - - 30 µs C CC S CC CC CC CC CC CC CC CC 2) Time is not dependent on program mode (5V or 3.3V). Data Sheet 492 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Flash Target Parameters 3) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes may be increased by up to 50%. 4) Using 512 kByte / 256 kByte erase commands (PFlash / DFlash). 5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x tER_ADDC32C 6) Allows segmentation of addressable memory into 8 logical sectors; round robin cycling must still be done to consider erase disturb limit NDFD. 7) Allows segmentation of addressable memory into 6 logical sectors; round robin cycling must still be done to consider erase disturb limit NDFD. 8) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual. Data Sheet 493 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Quality Declarations 3.31 Quality Declarations Table 3-70 Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. MSL CC - - 3 ESD susceptibility according to VCDM SR Charged Device Model (CDM) - - 500 1) V for all other balls/pins; conforming to JESD22-C101-C - - 750 V for corner balls/pins; conforming to JESD22-C101-C ESD susceptibility according to VHBM SR Human Body Model (HBM) - - 2000 2) V Conforming to JESD22-A114-B ESD susceptibility of the LVDS VHBM1 SR pins according to Human Body Model (HBM) - - 2000 V - - 24500 hour Moisture Sensitivity Level Operation Lifetime tOP CC Conforming to Jedec J-STD--020C for 240C see below temperature profile as an example 1) Pads of the AGBT interface are limited to a maximum value of 250V. 2) Pads of the AGBT interface are limited to a maximum value of 1000V. Example Temperature Profile The following temperature profile is an example. Application specific temperature profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. Table 3-71 Example Temperature Profile TJ= Duration [h] ≤ 170°C ≤ 30 ≤ 160°C ≤ 120 ≤ 150°C ≤ 220 ≤ 140°C ≤ 350 ≤ 130°C ≤ 780 ≤ 120°C ≤ 1600 ≤ 110°C ≤ 3000 ≤ 100°C ≤ 7000 ≤ 90°C ≤ 8000 ≤ 80°C ≤ 2400 ≤ 70°C ≤ 1000 Comment ≤ 24500 Data Sheet total time 494 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Package Outline 3.32 Package Outline Figure 3-25 Package Outlines LFBGA-292 Figure 3-26 Package Outlines LQFP-176 Data Sheet 495 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Package Outline Figure 3-27 Package Outlines LQFP-144 Table 3-72 Exposed Pad Dimensions Ex; nominal EPad size 8.7 mm ± 50 μm Ey; nominal EPad size 8.7 mm ± 50 μm Ax; solderable EPad size 7.9 mm ± 50 μm Ay; solderable EPad size 7.9 mm ± 50 μm You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/packages. 3.32.1 Package Parameters Table 3-73 Package Parameters Parameter Symbol Thermal resistance (junction to RTH_JA ambient) 1) CC Thermal resistance (junction to RTH_JCB case bottom) 1) CC Data Sheet Values Unit Note / Test Condition Min. Typ. Max. - - 22 K/W LFBGA-292 - - 18 K/W LQFP-144 - - 17 K/W LQFP-176 - - 4.5 K/W LFBGA-292 - - 2 K/W LQFP-144 - - 2 K/W LQFP-176 496 OPEN MARKET VERSION V 1.0 2019-10 TC37xEXT AB-Step Electrical Specification Package Outline Table 3-73 Package Parameters (cont’d) Parameter Symbol Thermal resistance (junction to RTH_JCT case top) 1) CC Values Unit Note / Test Condition Min. Typ. Max. - - 5 K/W LFBGA-292 - - 10 K/W LQFP-144 - - 10 K/W LQFP-176 1) The top and bottom thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) are to be combined with the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate the total thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is the total thermal resistance between the junction and the ambient. Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1). Data Sheet 497 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 4 History Version 0.4 is the first version of this document. 4.1 Changes from Version 0.4 to Version 0.6 Changes in chapter “Pin Definition and Functions” • • Changes in chapter TC37x T and TP - Pin Definition and Functions for package variant LFBGA-292 – Changes in LFBGA-292 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12 – Changes in LFBGA-292 Package Variant 'Port 01 Functions' table; P01.5 – Changes in LFBGA-292 Package Variant 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4, P02.5, P02.6, P02.7, P02.8, – Changes in LFBGA-292 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6, P10.7, P10.8 – Changes in LFBGA-292 Package Variant 'Port 11 Functions' table; P11.0, P11.1, P11.2, P11.3, P11.4, P11.5, P11.6, P11.10, P11.12, P11.14 – Changes in LFBGA-292 Package Variant 'Port 13 Functions' table; P13.1, P13.2 – Changes in LFBGA-292 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5, P14.9, P14.10 – Changes in LFBGA-292 Package Variant 'Port 15 Functions' table; P15.4, P15.5 – Changes in LFBGA-292 Package Variant 'Port 20 Functions' table; P20.0, P20.3, P20.14 – Changes in LFBGA-292 Package Variant 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5 – Changes in LFBGA-292 Package Variant 'Port 22 Functions' table; P22.0, P22.1, P22.2, P22.4, P22.5, P22.6, P22.7, P22.8, P22.9, P22.10, P22.11 – Changes in LFBGA-292 Package Variant 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5, P23.6, P23.7 – Changes in LFBGA-292 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.2, P32.3, P32.4, P32.6, P32.7 – Changes in LFBGA-292 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10, P33.12, P33.13 – Changes in LFBGA-292 Package Variant 'Port 34 Functions' table; P34.1, P34.2 – Changes in LFBGA-292 Package Variant; Buffer Type changed for all Ports – Changes in LFBGA-292 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all balls – Changes in LFBGA-292 Package Variant 'System I/O' table; Buffer Type changed for all balls – Changes in LFBGA-292 Package Variant 'System I/O' table; Symbol changed for balls Y17, W17 – Changes in LFBGA-292 Package Variant 'System I/O' table; Function changed for balls Y17, W17, – Changes in LFBGA-292 Package Variant; 'Supply' table; Symbol and Function changed for balls L20, N19, N20 Changes in chapter TC37x TE - Pin Definition and Functions for package variant LFBGA-292 – Changes in LFBGA-292 Package Variant 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12 – Changes in LFBGA-292 Package Variant 'Port 01 Functions' table; P01.5 – Changes in LFBGA-292 Package Variant 'Port 02 Functions' table; P02.3, P02.4, P02.5 Data Sheet 498 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • • – Changes in LFBGA-292 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6 – Changes in LFBGA-292 Package Variant 'Port 11 Functions' table; P11.0, P11.1, P11.2, P11.3, P11.4, P11.5, P11.10, P11.12 – Changes in LFBGA-292 Package Variant 'Port 13 Functions' table; P13.1, P13.2 – Changes in LFBGA-292 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5 – Changes in LFBGA-292 Package Variant 'Port 15 Functions' table; P15.4, P15.5 – Changes in LFBGA-292 Package Variant 'Port 20 Functions' table; P20.0, P20.6 – Changes in LFBGA-292 Package Variant 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5 – Changes in LFBGA-292 Package Variant 'Port 23 Functions' table; P23.1 – Changes in LFBGA-292 Package Variant 'Port 32 Functions' table; P32.1, P32.2, P32.4 – Changes in LFBGA-292 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10 – Changes in LFBGA-292 Package Variant; Buffer Type changed for all Ports – Changes in LFBGA-292 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all balls – Changes in LFBGA-292 Package Variant 'System I/O' table; Buffer Type changed for all balls – Changes in LFBGA-292 Package Variant 'System I/O' table; Symbol changed for balls Y17, W17, M20, M19 – Changes in LFBGA-292 Package Variant; 'Supply' table; Symbol and Function changed for balls L20, N19, N20 Changes in chapter TC37x T and TP - Pin Definition and Functions for package variant LQFP-176 – Changes in LQFP-176 Package Variant 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12 – Changes in LQFP-176 Package Variant 'Port 02 Functions' table; P02.3, P02.4, P02.5 – Changes in LQFP-176 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6 – Changes in LQFP-176 Package Variant 'Port 11 Functions' table; P11.2, P11.3, P11.6, P11.10, P11.12 – Changes in LQFP-176 Package Variant 'Port 13 Functions' table; P13.1, P13.2 – Changes in LQFP-176 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5 – Changes in LQFP-176 Package Variant 'Port 15 Functions' table; P15.4, P15.5 – Changes in LQFP-176 Package Variant 'Port 20 Functions' table; P20.0 – Changes in LQFP-176 Package Variant 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5 – Changes in LQFP-176 Package Variant 'Port 23 Functions' table; P23.1 – Changes in LQFP-176 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.2, P32.4 – Changes in LQFP-176 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10 – Changes in LQFP-176 Package Variant; Buffer Type changed for all Ports – Changes in LQFP-176 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all pins – Changes in LQFP-176 Package Variant 'System I/O' table; Buffer Type changed for all pins – Changes in LQFP-176 Package Variant 'System I/O' table; Symbol and function changed for pins 84, 85 – Changes in LQFP-176 Package Variant; 'Supply' table; Symbol and Function changed for pins e_pad, 101, 104 Changes in chapter TC37x TE - Pin Definition and Functions for package variant LQFP-176 – Changes in LQFP-176 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12 Data Sheet 499 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • – Changes in LQFP-176 Package Variant 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4, P02.5, P02.6, P02.7, P02.8 – Changes in LQFP-176 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6, P10.7, P10.8 – Changes in LQFP-176 Package Variant 'Port 11 Functions' table; P11.2, P11.3, P11.6, P11.10, P11.12 – Changes in LQFP-176 Package Variant 'Port 13 Functions' table; P13.1, P13.2 – Changes in LQFP-176 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5, P14.9, P14.10 – Changes in LQFP-176 Package Variant 'Port 15 Functions' table; P15.4, P15.5 – Changes in LQFP-176 Package Variant 'Port 20 Functions' table; P20.0, P20.3, – Changes in LQFP-176 Package Variant 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5 – Changes in LQFP-176 Package Variant 'Port 22 Functions' table; P22.0, P22.1, P22.2 – Changes in LQFP-176 Package Variant 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5 – Changes in LQFP-176 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.2, P32.3, P32.4 – Changes in LQFP-176 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10, P33.12, P33.13 – Changes in LQFP-176 Package Variant; Buffer Type changed for all Ports – Changes in LQFP-176 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all pins – Changes in LQFP-176 Package Variant 'System I/O' table; Buffer Type changed for all pins – Changes in LQFP-176 Package Variant 'System I/O' table; Symbol and function changed for pins 84, 85 – Changes in LQFP-176 Package Variant 'System I/O' table; function changed for pins 102, 103 – Changes in LQFP-176 Package Variant; 'Supply' table; Symbols and Functions changed for pins 101, 104 – Changes in LQFP-176 Package Variant; 'Supply' table; Symbol and Function added for pin 177 Changes in chapter TC37x TE - Pin Definition and Functions for package variant LQFP-144 – Changes in LQFP-144 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9, P00.12 – Changes in LQFP-144 Package Variant 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4, P02.5, P02.6, P02.7, P02.8 – Changes in LQFP-144 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6 – Changes in LQFP-144 Package Variant 'Port 11 Functions' table; P11.2, P11.3, P11.6, P11.10, P11.12 – Changes in LQFP-144 Package Variant 'Port 13 Functions' table; P13.1, P13.2 – Changes in LQFP-144 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5 – Changes in LQFP-144 Package Variant 'Port 15 Functions' table; P15.4, P15.5 – Changes in LQFP-144 Package Variant 'Port 20 Functions' table; P20.0, P20.3 – Changes in LQFP-144 Package Variant 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5 – Changes in LQFP-144 Package Variant 'Port 22 Functions' table; P22.0, P22.1, P22.2 – Changes in LQFP-144 Package Variant 'Port 23 Functions' table; P23.1 – Changes in LQFP-144 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.4 – Changes in LQFP-144 Package Variant 'Port 33 Functions' table; P33.5, P33.7, P33.10, P33.12, P33.13 – Changes in LQFP-144 Package Variant; Buffer Type changed for all Ports – Changes in LQFP-144 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all pins – Changes in LQFP-144 Package Variant 'System I/O' table; Buffer Type changed for all pins Data Sheet 500 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • – Changes in LQFP-144 Package Variant 'System I/O' table; Symbol and function changed for pins 70, 71 – Changes in LQFP-144 Package Variant 'System I/O' table; function changed for pins 81,82 – Changes in LQFP-144 Package Variant; 'Supply' table; Symbols and Functions changed for pins 83, 80 – Changes in LQFP-144 Package Variant; 'Supply' table; Symbol and Function added for pin 145 Changes in chapter “Pad Position Configuration of TC37x” – • Changes in table “Pad List” for all positions Changes in chapter 'Pad Position Definition' – Changed description in sub-chapter 'Legend' - Column “Buffer Type”: PU2 Changes in chapter “Electrical Specification” • • • • • Changes in table 'Absolute Maximum Ratings' – Changed max value of VIN from 7.0 V to 6.75 V – Changed description of VDDM from 'Voltage at VDDM, VEXT and VFLEX power supply pins with respect to VSS' to 'Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS' – Changed note of VDDM from '7.0 V' to '6.75 V' – Added footnote 2) to VDD – Changed order of footnotes Changes in table 'Overload Parameters' – Changed note of IINANA – Removed parameters of IID – Changed note of KOVAN – Changed parameter conditions of KOVAP – Added footnote 2) to KOVAP and KOVAN Changes in 'Operating Conditions' table – Added footnote 1) to VDD – Changed order of footnotes Changes in table 'PORST Pad' of Standard Pads – Change value name of parameter HYS – Changed notes of parameter IOZ – Added value of parameter VIH – Added value of parameter VIL – Add footnote 2) to IPDL Changes in table 'Fast 5V GPIO' of Standard Pads – Changed values and conditions of parameter IOZ – Combined equal values of IOZ in single lines – Changed conditions of parameter tRF – Changed value names of parameter of VIH – Changed value names of parameter HYS – Changed value names of parameter VIL – Changed conditions of parameter VILD – Changed parameter tSET – Added footnote 1) for tRF – Changed footnote 2) for tRF Data Sheet 501 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • • • – Added footnote 4) for IPUH – Added footnote 5) for IPDL – Changed order of footnotes Changes in table 'Fast 3.3V GPIO' of Standard Pads – Changed value names of parameter HYS – Changed condition of parameter tRF – Changed value names of parameter VIH – Changed value of parameter VIL – Changed condition of parameter VILD – Changed values and conditions of parameter IOZ – Combined equal values of IOZ in single lines – Changed parameter tSET – Added footnote 1) for tRF – Changed footnote 2) for tRF – Added footnote 4) for IPUH – Added footnote 5) for IPDL – Changed order of footnotes Changes in table 'Slow 5V GPIO' of Standard Pads – Changed value names of parameter HYS – Changed conditions of parameter IPUH – Changed values and conditions of parameter IOZ – Combined equal values of IOZ in single line – Changed value names of parameter VIL – Changed value names of parameter VIH – Changed conditions of parameter VILD – Changed parameter tSET – Added footnote 1) for tRF – Changed footnote 2) for tRF – Added footnote 4) for IPUH – Added footnote 5) for IPDL – Changed order of footnotes Changes in table 'Slow 3.3V GPIO' of Standard Pads – Changed value names of parameter HYS – Changed conditions of parameter IPUH – Changed values and conditions of parameter IOZ – Combined equal values of IOZ in single line – Removed parameter of IOZ – Changed value and name of parameter VIL – Changed value names of parameter VIH – Changed conditions of parameter VILD – Changed parameter of tSET – Added footnote 1) for tRF Data Sheet 502 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • • • • – Changed footnote 2) for tRF – Added footnote 4) for IPUH – Added footnote 5) for IPDL – Changed order of footnotes Changes in table 'RFast 5V GPIO' of Standard Pads – Changed condition of parameter tRF – Changed value names of parameter HYS – Changed conditions of parameter IOZ – Changed value names of parameter VIH – Changed value names of parameter VIL – Changed conditions of parameter VILD – Changed parameter of tSET – Added footnote 1) for tRF – Changed footnote 2) for tRF – Added footnote 4) for IPUH – Added footnote 5) for IPDL – Changed order of footnotes Changes in table 'RFast 3.3V pad' of Standard Pads – Changed condition of parameter tRF – Changed value names of parameter HYS – Changed conditions of parameter IOZ – Changed value name of parameter VIH – Changed value and name of parameter VIL – Changed conditions of parameter VILD – Changed parameter tSET – Added footnote 1) for tRF – Changed footnote 2) for tRF – Added footnote 4) for IPUH – Added footnote 5) for IPDL – Changed order of footnotes Changes in table 'Class S 5V' of Standard Pads – Changed value names of parameter HYS – Changed values of parameter IOZ – Changed value name of parameter VIH – Changed value name of parameter VIL – Changed parameter of tSET – Added footnote 2) for IPUH – Added footnote 3) for IPDL Changes in table 'Class D' of Standard Pads – • Changed values of parameter IOZ Changes in table 'ADC Reference Pads' of Standard Pads – Changed notes of parameter IOZ2 Data Sheet 503 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 – • • • • • • Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' of LVDS Pads – Changed condition of parameter Rin – Added parameter tSET_LVDS – Added footnote 1) for tRISE20 – Added footnote 2) for tFALL20 – Changed order of footnotes Changes in table 'VADC 5V' – Added conditions of parameter VDDK – Changed parameter naming of dVDDK – Added conditions of parameter VAREF – Changed values and conditions of VAREF – Added note for parameter RPDD – Added footnote 1) for VAREF – Changed footnote 2) for TUE, EAINL, EADNL, EAGAIN, EAOFF, ENRMS – Added footnote 9) for QCONV – Changed order of footnotes – Changed figure 'Equivalent Circuitry for Analog Inputs' Changes in table 'DSADC 5V' – Added parameter for RBIAS – Changed parameters of VAREF – Changed parameters of IREF – Added parameters of IREF – Changed parameters of IRMS – Changed parameters of EDGAIN – Changed parameters of EDOFF – Added footnote 2) for IRMS, SNR – Added footnote 3) for SFDR, EDGAIN, EDOFF, – Changed order of footnotes Changes in table 'OSC_XTAL' – Removed parameter for VIHBX – Removed parameter for VILBX – Added parameter for DCX1 – Added parameter for JABSX1 – Added parameter for SRXTAL1 – Added footnote 3) for DCX1, JABSX1, SRXTAL1 Changes in table 'Back-up Clock' – Changed value of fSB – Changed footnote 1) for fBACKT Changes in table 'DTS PMS' – • Added footnote 1) for IOZ2 Added parameter conditions for TNL Changes in table 'DTS Core' Data Sheet 504 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • • • • • • – Added parameter ΔT – Added parameter conditions for TNL Current Consumption – Added values and notes for IDDRAIL – Changed values for IDDRAIL – Added values and notes for IDDPORST – Changed values and notes for IDDPORST – Changed value and note for ISTANDBY – Changed value for IDDTOT – Changed values for PD – Changed footnote 4) for IEXTFLEX – Changed footnote 7) ISTANDBY Changes in table 'Module Current Consumption' – Changed value of parameters of IDDP3PROG – Changed value of parameters of IEXTLVDS – Changed value of IDDP3ERASE – Changed value of parameter ISCRSB – Changed value of parameter ISCRIDLE – Added footnote 5) for ISCRSB – Changed order of footnotes Changes in table 'Module Core Current Consumption' – Changed naming of IDDSPU1 – Changed condition of parameter IDDLBIST – Changed value and condition of parameter IDDLMBIST – Changed footnote 1) for IDDHSM – Added footnote 2) for IDDLBIST Changes in chapter “Single Supply mode” – Changed figure and description for 'Single Supply Mode (a)' – Changed figure and description for 'Single Supply Mode (e)' – Changed figure and description for 'Single Supply Mode (d)' – Changed figure and description for 'Single Supply Mode (h)' Changes in table 'Reset' – Changed value of parameter tB – Changed value of parameter tBS – Added parameter tWARMRSTSEQ – Changed value of parameter tBWP – Changed naming and condition of parameter tLBIST – Added footnote 2) for tEVRPOR – Changed order of footnotes Changes in table 'EVR33 LDO' – Changed condition of parameter tSTR – Added parameter for '∆VOUTTC' Data Sheet 505 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.4 to Version 0.6 • • – Changed values and conditions of parameter dVOUT / dVIN – Added footnote 7) for dVOUT / dIOUT Changes in table 'Supply Monitors' – Changed value of VRSTC – Changed values of parameter VEXTMON – Changed condition of parameter tMON – Changed footnote 2) for VEXTPRIUV, VDDP3PRIUV, VDDPRIUV, – Changed footnote 3) for VDDP3PRIUV, VDDPRIUV, – Added footnote 4) for VEXTMON – Added footnote 5) for VEXTMON, VDDP3MON, VDDMON Changes in table 'EVRC SMPS' – Changed values and notes of parameter of 'fDCDC' – Changed value of parameter of '∆VDDDC' – Removed values and notes of parameter COUT – Added values of parameter 'LDC' – Changed condition of parameter dVDDDCT / dlOUT • Changed chapter naming from 'Phase Locked Loop (PLL)' to 'System Phase Locked Loop (SYS_PLL)' • Changes in table 'PLL System' – • • Changes in table 'PLL Peripheral' – Changed description and values of parameter DPP – Added parameter DPPI – Changed notes of parameter DRMS – Changed notes of parameter DP – Added parameter JABS25 Changes in table 'Master Mode Timing' – • Added footnote 3) for all parameters Changes in table 'Receive Parameters' of ERAY – • Added footnote 1) for all parameters Changes in table 'LVDS clock/data' – • Removed parameter values of 'fMV' Changed description of tdCCRxD10 Changes in table 'Flash' – Changed description of parameter of NDFD – Added parameter NDFDC – Added parameter NUCBD – Changed condition of parameter for NE_EEP10S – Added values for parameter NE_EEP10S – Changed condition of parameter for NE_HSMS – Added values for parameter NE_HSMS – Added parameter tVER_PAGE_DC – Added parameter tVER_PAGE_DS – Removed parameter tVER_PAGE_D Data Sheet 506 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.6 to Version 0.61 – • • • Changed order of footnotes Changes in table 'Quality Parameters' – Changed condition of parameter VHBM1 – Added footnote 1) for VCDM – Added footnote 2) for VHBM Changes in table 'Package Outline' – Added figures for Package Outline – Added tables 'Exposed Pad Dimensions' Changes in table 'Package Parameters' – Added table 'Package Parameters' – Added footnote 1) for all parameters 4.2 Changes from Version 0.6 to Version 0.61 Changes in chapter “Summary of Features” • Changes in table “Platform Feature Overview” for Debug/AGBT and package variants Changes in chapter “TC37x Pin Definition and Functions” • Changes in overview list: spelling of LFBGA-292 • Changes in overview list for package types of LFBGA-292 • Pad Position Configuration for TP, TE and TX variants added • Package variant LQFP-144 deleted • Changes in chapter TC37x TP - Pin Definition and Functions for package variant LFBGA-292 – Changes in 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12 – Changes in 'Port 01 Functions' table; P01.6 – Changes in 'Port 02 Functions' table; P02.3, P02.4, P02.5, P02.6, P02.7, P02.8 – Changes in 'Port 10 Functions' table; P10.3, P10.4, P10.5, P10.6 – Changes in 'Port 11 Functions' table; P11.5, P11.7, P11.8, P11.9, P11.10, P11.11, P11.12, P11.15 – Changes in 'Port 12 Functions' table; P12.0 – Changes in 'Port 13 Functions' table; P13.1, P13.2 – Changes in 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5 – Changes in 'Port 15 Functions' table; P15.4, P15.5, P15.6 – Changes in 'Port 20 Functions' table; P20.0, P20.8, P20.14 – Changes in 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5, P21.6, P21.7 – Changes in 'Port 22 Functions' table; P22.0, P22.1, P22.4, P22.5, P22.6, P22.7, P22.8, P22.9, P22.10, P22.11 – Changes in 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5, P23.6, P23.7 – Changes in 'Port 32 Functions' table; P32.2, P32.4 – Changes in 'Port 33 Functions' table; P33.0, P33.1, P33.2, P33.3, p33.4, P33.5, P33.6, P33.10, P33.12 – Changes in 'Port 34 Functions' table; P34.5 – Changes in table “System I/O” – Changes in table “Supply” Data Sheet 507 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.6 to Version 0.61 • • • Changes in chapter TC37x TE and TX - Pin Definition and Functions for package variant LFBGA-292 – Changed order of Port Function tables – Changed spelling of LFBGA-292 – Changes in 'Port 00 Functions' table; P00.8 – Changes in 'Port 02 Functions' table; P02.4, P02.5 – Changes in 'Port 11 Functions' table; P11.5, P11.12 – Changes in 'Port 13 Functions' table; P13.1, P13.2 – Changes in 'Port 20 Functions' table; P20.0 – Changes in 'Port 23 Functions' table; P23.1 – Changes in 'Port 32 Functions' table; P32.4 Changes in chapter TC37x T and TP - Pin Definition and Functions for package variant LQFP-176 – Changes in 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12 – Changes in 'Port 02 Functions' table; P02.3, P02.4, P02.5, P02.6, P02.7, P02.8 – Changes in 'Port 10 Functions' table; P10.3, P10.4, P10.5, P10.6 – Changes in 'Port 11 Functions' table; P11.9, P11.10, P11.11, P11.12 – Changes in 'Port 13 Functions' table; P13.1, P13.2 – Changes in 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5 – Changes in 'Port 15 Functions' table; P15.4, P15.5, P15.6 – Changes in 'Port 20 Functions' table; P20.0, P20.8, P20.14 – Changes in 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5, P21.6, P21.7 – Changes in 'Port 22 Functions' table; P22.0, P22.1 – Changes in 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5 – Changes in 'Port 32 Functions' table; P32.2, P32.4 – Changes in 'Port 33 Functions' table; P33.0, P33.1, P33.2, P33.3, P33.4, P33.5, P33.6, P33.10, P33.12 – Changes in table “System I/O” – Changes in table “Supply” Changes in chapter TC37x TE - Pin Definition and Functions for package variant LQFP-176 – Changes in 'Port 00 Functions' table; P00.8 – Changes in 'Port 02 Functions' table; P02.4, P02.5 – Changes in 'Port 11 Functions' table; P11.12 – Changes in 'Port 13 Functions' table; P13.1, P13.2 – Changes in 'Port 15 Functions' table; P15.4, P15.5 – Changes in 'Port 20 Functions' table; P20.0 – Changes in 'Port 23 Functions' table; P23.1 – Changes in 'Port 32 Functions' table; P32.4 – Changes in table “Supply” • Deleted chapter TC37x TE - Pin Definition and Functions for package variant LQFP-144 • Changes in chapter “Pad Position Configuration of TC37x TP” – Changes in table “Pad List” for different positions • Added chapter “Pad Position Configuration of TC37x TE and TX” • Changes in chapter “Legend” Data Sheet 508 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.6 to Version 0.61 – Added description concerning pinning DB versions for packages Changes in chapter “Electrical Specification” • Changes in table 'RFast 3.3V pad' – • Changes in table 'VADC 5V' – • • • • • • • Added conditions for parameter VAIN Changes in table 'DSADC 5V' – Added / changed values for parameter IRMS and EDGAIN – Added footnote 4) – Changed order of footnotes Changes in table “Current Consumption” – Added footnotes for IEXTFLEX – Changed footnote for IDDTOTDC3 – Changed footnote for IDDTOTDC5 – Changed footnote for ISTANDBY – Changed footnote 2) – Added footnote 4) and 6) – Changed order of footnotes Changes in table 'Module Current Consumption' – Changed condition of IEXTLVDS – Changed footnotes of IDDM – Changed footnote of ISCRSB – Changed footnote of ISCRIDLE – Added footnote 3) and 5) – Changed order of footnotes Changes in table 'Module Core Current Consumption' – • Added parameter for fIND Changed / added values of parameter IDDGTM Changes in table 'Reset' – Changed value of of parameter TBWP – Changed values of of parameter TSCR Changes in table 'Supply Monitors' – Changed condition of parameter VRST33 – Changed condition of parameter VRSTC Changes in table 'Package Outline' – Changed spelling for figure from LF-BGA-292 to LFBGA-292 – Deleted figure and table for QFP144 Changes in table 'Package Parameters' – Deleted values and notes for QFP144 – Changed value for RTH_JACC Data Sheet 509 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.61 to Version 0.7 4.3 Changes from Version 0.61 to Version 0.7 Changes in chapter “Summary of Features” • Changes in table “Platform Feature Overview” – added package LQFP-144 – change package name from LFBGA-292-10 to LFBGA-292 Changes in chapter “TC37x Pin Definition and Functions” • • Changes in overview list - package variants of LFBGA-292 – Split of package variant description for LFBGA-292 - TE and TX version – Added package variant LQFP-144 – Changed package variant figure numbering Changes in chapter “LFBGA-292 Package Pinning of TC37x TE” – Changes in 'Port 00 Functions' table; P00.3, P00.4, P00.8, P00.9, P00.10 – Changes in ‘Port 01 Functions’ table; P01.6 – Changes in ‘Port 02 Functions’ table; P02.4, P02.5, P02.6, P02.7, P02.8, P02.11 – Changes in ‘Port 10 Functions’ table; P10.3, P10.4, P10.6 – Changes in ‘Port 11 Functions’ table; P11.9, P11.15 – Changes in ‘Port 13 Functions’ table; P13.1, P13.2 – Changes in ‘Port 14 Functions’ table; P14.4 – Changes in ‘Port 15 Functions’ table; P15.4, P15.5, P15.6 – Changes in ‘Port 20 Functions’ table; P20.0, P20.8, P20.14 – Changes in ‘Port 21 Functions’ table; P21.2, P21.3, P21.4, P21.5 – Changes in ‘Port 22 Functions’ table; P22.0, P22.5, P22.10 – Changes in ‘Port 23 Functions’ table; P23.3, P23.4 – Changes in ‘Port 32 Functions’ table; P32.2, P32.4 – Changes in ‘Port 33 Functions’ table; P33.3, P33.10, P33.12 – Changes in ‘Port 34 Functions’ table; P34.5 – Changes in table “Analog Inputs”; ball U6, EDSADC; ball T6, EDSADC; ball W2, EDSADC; ball W1, EDSADC; ball M1, EDSADC; ball M2, EDSADC – Changes in table “System I/O”; ball L7, K7, P10, P11, L14, G11, K14 Added chapter “LFBGA-292 Package Pinning of TC37x TX” • Changes in chapter “LQFP-176 Package Pinning of TC37x TE” – Changes in 'Port 00 Functions' table; P00.3, P00.4, P00.8, P00.9, P00.10 – Changes in ‘Port 02 Functions’ table; P02.4, P02.5, P02.6, P02.7, P02.8 – Changes in ‘Port 10 Functions’ table; P10.3, P10.4, P10.6 – Changes in ‘Port 11 Functions’ table; P11.9 – Changes in ‘Port 13 Functions’ table; P13.1, P13.2 – Changes in ‘Port 14 Functions’ table; P14.4 – Changes in ‘Port 15 Functions’ table; P15.4, P15.5, P15.6 – Changes in ‘Port 20 Functions’ table; P20.0, P20.8, P20.14 – Changes in ‘Port 21 Functions’ table; P21.2, P21.3, P21.4, P21.5 – Changes in ‘Port 22 Functions’ table; P22.0 Data Sheet 510 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.61 to Version 0.7 – Changes in ‘Port 23 Functions’ table; P23.3, P23.4 – Changes in ‘Port 32 Functions’ table; P32.2, P32.4 – Changes in ‘Port 33 Functions’ table; P33.3, P33.10, P33.12 – Changes in table “Analog Inputs”; pin 44, EDSADC; pin 43, EDSADC; pin 29, EDSADC; pin 28, EDSADC; Added chapter “LQFP-144 Package Pinning of TC37x TE” Changes in chapter “Pad Position Configuration of TC37x TE/TX” – Changes in table “Pad List”, number 34, 35, 219, 220, 223, 224, 225, 307, – Added comment concerning “neighbor pads” Changes in chapter “Legend” – Changed refering IO_Spirit_file version Changes in chapter “Electrical Specification” • Changes in table 'Operating Conditions' – • • • Deleted parameter for fEBU Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' – Changed value for parameter VI – Changed test condition for parameter Vidth – Added values for parameter Vidth – Changed test condition for parameter Rin – Added notes to LVDS table Changes in table 'Current Consumption' – Deleted values for parameter IDDRAIL – Deleted value for parameter IDDPORST – Changed value of parameter IEXTRAIL – Changed test condition for parameter IDDTOT – Added values and test condition for parameter IDDTOT – Added value for parameter IDDTOTDC3 – Changed test parameter for IDDTOTDC3 – Added value for parameter IDDTOTDC5 – Changed test conditions for IDDTOTDC5 – Changed test conditions for parameter PD – Added values for parameter PD – Modified footnote 9) for parameter PD Changes in table 'Module Core Current Consumption' – Changed values for parameter IDDCx0 – Changed values for parameter IDDCxx – Deleted parameter for IDDSPU1 – Added value for parameter IDDCIF • Added sub-chapter 'Calculating the 1.25 V Current Consumption' • Changes in table 'Reset' – • Changed value for parameter tPIP Changes in table 'PLL System' – Changed value for parameter fREF Data Sheet 511 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.7 to Version 1.0 • Changes in sub-chapter 'ETH RGMII Parameters' – Added figures for ETH RGMII TXand RX signals • Added sub-chapter 'SDMMC Interface Timing' • Changes in table 'Flash' – Changed value for parameter tPRPB5_PF – Changed values for parameter tER_Dev • Added figure for Package Outlines LQFP-144 • Changes in table 'Package Parameters' – Added value for parameter RTH_JA - QFP144 – Added value for parameter RTH_JCB - QFP144 Added value for parameter RTH_JCT - QFP144 4.4 Changes from Version 0.7 to Version 1.0 • General changes in Data Sheet TC37x: Data Sheet splitted and renamed to TC37xEXT for feature package TE/TX and TC37x for feature package T/TP • Changed Data Sheet version 0.7 to 1.0 and from AA-Step to AB-Step • Changes in table “Platform Feature Overview” • – Changed GTM features – ASIL Level deleted – Debug features deleted – Changed packages name spelling Changes in chapter “TC37x Pin Definition and Functions” – Deleted Package Pinning for LFBGA-292-10, TC37x TP – Deleted Package Pinning for LQFP-176, TC37x T and TP – Deleted Pad Position Configuration of TC37x TP – Changed package name spelling (LFBGA-292) – Updated "CIF.*" symbol and functional description for all packages – Updated EDSADC functional description for all packages – Deleted PMS symbol in package LFBGA-292, Port 02, Ball F1 – Deleted PMS symbol in package LQFP-176, Port 02, Pin 9 – Deleted PMS symbol in package LQFP-144, Port 02, Pin 9 – LFBGA-292 (feature package TE): Changes in table “Analog Inputs”; functional descriptions of ball U6, T6, W2, W1, M1, M2 – LFBGA-292 (feature package TE): Changes in table “System I/O”; functional descriptions of ball G10, G11, K14 – LFBGA-292 (feature package TX): Changes in table “Analog Inputs”; functional descriptions of ball U6, T6, W2, W1, M1, M2 – LFBGA-292 (feature package TX): Changes in table “System I/O”; functional descriptions of ball G10, G11, K14 – LFBGA-176: Changes in table “Analog Inputs”; functional descriptions of pin 44, 43, 29, 28 – LFBGA-144: Changes in table “Analog Inputs”; changed pin naming of pin E-PAD/145 – LFBGA-144: Changes in table “Supply”; functional description of pin 36, 35, 27, 26 Data Sheet 512 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.7 to Version 1.0 – • Changes in table "Legend" – • Added description regarding “neighbor pads” in chapter “Electrical Specification” Spirit version for feature package TC37x TP has been deleted Changes in chapter "Electrical Specification" – Changed description in table “Absolute Maximum Ratings” for parameter ΣIIN – Added footnote to table “Absolute Maximum Ratings” – Added footnote in table “Absolute Maximum Ratings” for parameter IIN – Changed value in table “Overload Parameters” for parameter VOUS – Changed conditions in table “Operating Conditions” for parameter VFLEX – Added parameter in table “Operating Conditions” for VFLEX2 – Changed conditions in table “Fast 5V GPIO” for parameter tRF – Changed values in table “Fast 5V GPIO” for parameter HYS – Changed conditions in table “Fast 5V GPIO” for parameter IOZ – Changed value in table “Fast 5V GPIO” for parameter VIH – Changed value in table “Fast 5V GPIO” for parameter VIL – Changed condition in table “Fast 5V GPIO” for parameter VILD – Changed conditions in table “Fast 3.3V GPIO” for parameter tRF – Changed values in table “Fast 3.3V GPIO” for parameter HYS – Changed conditions in table “Fast 3.3V GPIO” for parameter IOZ – Changed value in table “Fast 3.3V GPIO” for parameter VIH – Changed value in table “Fast 3.3V GPIO” for parameter VIL – Changed condition in table “Fast 5V GPIO” for parameter VILD – Changed values in table “Slow 5V GPIO” for parameter HYS – Changed conditions in table “Slow 5V GPIO” for parameter IOZ – Changed value in table “Slow 5V GPIO” for parameter VIH – Changed value in table “Slow 5V GPIO” for parameter VIL – Changed condition in table “Slow 5V GPIO” for parameter VILD – Changed values in table “Slow 3.3V GPIO” for parameter HYS – Changed conditions in table “Slow 3.3V GPIO” for parameter IOZ – Changed value in table “Slow 3.3V GPIO” for parameter VIH – Changed value in table “Slow 3.3V GPIO” for parameter VIL – Changed condition in table “Slow 3.3V GPIO” for parameter VILD – Changed conditions in table “RFast 5V GPIO” for parameter tRF – Changed values in table “RFast 5V GPIO” for parameter HYS – Changed conditions in table “RFast 5V GPIO” for parameter IOZ – Changed value in table “RFast 5V GPIO” for parameter VIH – Changed value in table “RFast 5V GPIO” for parameter VIL – Changed condition in table “RFast 5V GPIO” for parameter VILD – Changed conditions in table “RFast 3.3V pad” for parameter tRF – Changed values in table “RFast 3.3V pad” for parameter HYS – Changed conditions in table “RFast 3.3V pad” for parameter IOZ – Changed value in table “RFast 3.3V pad” for parameter VIH Data Sheet 513 OPEN MARKET VERSION V 1.0 2019-10 TC37x AB-Step History Changes from Version 0.7 to Version 1.0 • – Changed value in table “RFast 3.3V pad” for parameter VIL – Added table for “Class S 3.3V” parameters to sub-chapter “5V/ 3.3V switchable Pads” – Changed footnote 1) at table “OSC_XTAL” – Added power pattern information to sub-chapter “Power Supply Current” – Deleted values in table “Current Consumption” for parameter IDDPORST – Changed value in table “Current Consumption” for parameter IEXTRAIL – Changed value in table “Current Consumption” for parameter IEVRSB – Changed condition in table “Reset” for parameter tSUPHOLD – Added values and conditions in table “Supply Monitors” for parameter VEXTMON – Changed conditions in table “Supply Monitors” for parameter VDDP3MON – Changed conditions in table “Supply Monitors” for parameter VDDMON – Added note regarding power-cycles to table "Supply Ramp" – Changed symbol in table “EVRC SMPS” for parameter ∆fDCSPR – Changed symbol in table “EVRC SMPS” for parameter nDC – Added sub-chapter “Camera Interface Timing (CIF)” – Changed value in table “Quality Parameters” for parameter VHBM1 Changes in “Package Outline” – Changed package name spelling for figure titles – Changed packages name spelling in table “Package Parameter” Data Sheet 514 OPEN MARKET VERSION V 1.0 2019-10 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG OPEN MARKET VERSION