TDA21231AUMA1

DrMOSProductFamily DrMOS5x5 TDA21231 DataSheet Rev.2.2 Final PowerManagementandMultimarket TDA21231 Applications 1     Desktop and Server VR buck-converter Single Phase and Multiphase POL CPU/GPU Regulation in Notebook, Desktop Graphics Cards, DDR Memory, Graphic Memory High Power Density Voltage Regulator Modules (VRM) Features 2                For synchronous buck converter step down voltage applications Maximum average current of 55 A Input voltage range +4.5 V to +16 V Power MOSFETs rated 25 V Fast switching technology for improved performance at high switching frequencies (> 500 kHz) Remote driver disable function Includes bootstrap diode Undervoltage lockout Shoot through protection +5 V high side and low side MOSFETs driving voltage Compatible to standard +3.3 V PWM controller integrated circuits Tri-state PWM input functionality Small package: PG-IQFN-31-2 (5 x 5 x 0.8 mm³) RoHS compliant Thermal warning Table 1 Product Identification Part Number Temp Range Package Marking TDA21231 -40 to 125C PG-IQFN-31-2 (5 x 5 x 0.8 mm³) DA21231 Figure 1 Data Sheet Picture of the Product 1 TDA21231 3 Description 3.1 Pinout Figure 2 Data Sheet Pinout, Numbering and Name of Pins (transparent top view) 2 TDA21231 Table 2 I/O Signals Pin No. Name Pin Type Buffer Type Function 1 PWM I +3.3 V logic 5 BOOT I Analog 6 GH O Analog 7 PHASE I Analog 16 – 23 SW O Analog 27 GL O Analog 30 PHFLT# O +3.3 V logic 31 EN I +3.3 V logic Table 3 PWM drive logic input The tri-state PWM input is compatible with 3.3 V. Bootstrap voltage pin Connect to BOOT capacitor High-Side Gate Test point for High Side MOSFET gate signal Switch node (reference for Boot voltage) internally connected to SW pin, connect to BOOT capacitor Switch node output High current output switching node Low-Side Gate Test point for Low Side MOSFET gate signal Thermal Warning Connect through a resistor to 3.3V. When the thermal protection threshold is tripped, the PHFLT# pin is being pulled low. Leave open if not used. Enable signal (active high) Connect to GND to disable the IC. Power Supply Pin No. Name Pin Type Function 8 to 11, Vin pad VIN POWER 29 PVCC POWER 3 VCC POWER Table 4 Input voltage Supply of the drain of the high-side MOSFET FET gate supply voltage High- and low-side gate drive supply Logic supply voltage Bias voltage for the internal logic Ground Pins Pin No. Name Pin Type Function 4 AGND GND 12 – 15, 28, PGND pads PGND GND Table 5 Control signal ground Should be connected to PGND externally Power ground All these pins must be connected to the power GND plane through multiple low inductance vias. Not Connected Pin No. Name Pin Type Function 2 NC – 24, 25, 26 NC – Data Sheet No internal connection Leave pin floating or tie to noise-free voltage of 0 (GND) … 7 V. No internal connection Options: Leave floating, tie to GND or SW 3 TDA21231 3.2 General Description The Infineon TDA21231 is a multichip module that incorporates Infineon’s premier MOSFET technology for a single high-side and a single low-side MOSFET coupled with a robust, high performance, high switching frequency gate driver in a single PG-IQFN-31-2 package. The optimized gate timing allows for significant light load efficiency improvements over discrete solutions. When combined with Infineon’s family of digital multi-phase controllers, the TDA21231 forms a complete corevoltage regulator solution for advanced micro and graphics processors as well as point-of-load applications. Figure 3 Data Sheet Simplified Block Diagram 4 TDA21231 4 Electrical Specification 4.1 Absolute Maximum Ratings Note: TA = 25°C Stresses above those listed in Table 6 “Absolute Maximum Ratings” may cause permanent damage to the device. These are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational sections of this specification. Exposure over values of the recommended ratings (Table 8) for extended periods may adversely affect the operation and reliability of the device. Table 6 Absolute Maximum Ratings Parameter Symbol Values Unit Min. Typ. Max. – – 55 Maximum average load current IOUT Input Voltage VIN (DC) -0.30 – 21 Logic supply voltage VVCC (DC) -0.30 – 8 -0.30 – 8 VSW (DC) -1 – 25 VSW (AC) 1 -8 – – VPHASE (DC) -1 – 25 VPHASE (AC) 1 -8 – – VIN-VPHASE (AC) – – 32 2 VPHASE-VPGND (AC) – – 32 2 VBOOT (DC) -0.3 – 25 VBOOT (AC) – – 30 VBOOT-PHASE (DC) -0.3 – 8 EN voltage VEN -0.3 – 4 PWM voltage VPWM -0.3 – 4 PHFLT# VPHFLT# -0.3 – 4 Junction temperature TJmax -40 – 150 Storage temperature TSTG -55 – 150 High- and low-side driver voltage VPVCC (DC) Switch node voltage PHASE node voltage MOSFET voltage spike BOOT voltage Note / Test Condition A V 2 ns above 25 V 1 Maximum value valid for operation up to 1h accumulated over lifetime, else the maximum value is 3.6V C Note: All rated voltages are relative to voltages on the AGND and PGND pins unless otherwise specified. 1 2 AC is limited to 10 ns AC is limited to 2 ns Data Sheet 5 TDA21231 4.2 Table 7 Thermal Characteristics Thermal Characteristics Parameter Symbol Min. Typ. Thermal resistance to case (soldering point) θJC – – 2 Thermal resistance to top of package Thermal resistance to ambient (Ploss = 4.5 W,TA = 70 °C, 8 layer server board with 2 oz copper per layer ) θJCtop – – – 11.5 30 – – Still air – 8.9 – 200 lfm airflow 8.8 – 300 lfm airflow 4.3 Values θJA – Unit Note / Test Condition K/W – Max. Recommended Operating Conditions and Electrical Characteristics Note: VDRV = VCIN = 5 V, TA = 25°C Table 8 3 Recommended Operating Conditions Parameter Symbol Input voltage VIN MOSFET driver voltage Values Unit Min. Typ. Max. 5 – 16 VPVCC 4.5 5 7 Logic supply voltage VVCC 4.5 5 7 Frequency of the PWM fSW – – 1.2 MHz Junction temperature TjOP -40 – 125 °C 3 Note / Test Condition For telecom applications see note 3 V In telecom applications the recommended maximum voltage for V IN is 13.2V unless a boot resistor is used (see Figure 6) to limit the voltage spike VPHASE-VPGND (AC) to 26V. Data Sheet 6 TDA21231 Table 9 Voltage Supply And Biasing Current Parameter Symbol Values Min. VUVLOBOOT_R – 4.0 – UVLO BOOT falling VUVLOBOOT_F – 3.8 – UVLO rising VUVLO_R – – 4.2 UVLO falling VUVLO_F 3.7 – – Driver current IPVCC_300kHz – 12.5 – IPVCC_1MHz – 42 – IPVCC_PWML – 710 – IPVCC_PWMH – 210 – IVCC_PWML – 1 – IVCC_O – 630 – IC quiescent ICC + IPVCC – 840 – Pre-Bias at SW VSW_0 – 160 180 Table 10 PWM V mA μA mA μA mV Symbol Values Min. Typ. Unit VBOOT-VSW rising VBOOT-VSW falling VCC rising VCC falling EN = 3.3 V, fSW = 300 kHz EN = 3.3 V, fSW = 1 MHz EN = 3.3 V, PWM = 0V EN = 0V, PWM=3.3V, EN = 3.3 V, PWM = 0 V EN = 3.3 V, PWM = Open EN = 0V, PWM = Open VCC and PVCC present Note / Test Condition Max. Input low VEN_L – – 0.8 Input high VEN_H 2.0 – – V Sink current IEN – 10 – μA Input low VPWM_L – – 0.6 Input high VPWM_H 2.6 – – V Input resistance RIN-PWM – 2 – k Open voltage VPWM_O – 1.6 – VPWM_S 1.2 – 2.0 V TPHFLT#_T – 140 – °C dTPHFLT#_T -10 – 10 Tri-state shutdown 4 window PHFLT# Warning 5 Temperature Thermal warning 5 accuracy 5 Hysteresis 5 V Logic Inputs And Threshold Parameter EN Note / Test Condition Max. UVLO BOOT rising IC current (control) 4 Typ. Unit VEN falling VEN rising VEN = 1 V VPWM falling VPWM rising VPWM = 1 V VPWM_O K TPHFLT#_H – 10 – On resistance RPHFLT#_PD – 37.5 80 Ω Leakage current IPHFLT#_LK – 0.1 5 μA ILOAD = 8mA Maximum voltage range for tri-state The thresholds for temperature warning are verified by design and not subject to production test. Data Sheet 7 TDA21231 Table 11 Timing Characteristics Parameter Symbol Values Min. Typ. Unit Max. PWM tri-state to SW rising delay t_pts – 15 – PWM tri-state to SW falling delay t_pts2 – 15 – SW Shutdown hold-Off time from PWM low SW Shutdown hold-Off time from PWM high PWM to SW turn-off propagation delay PWM to SW turn-on propagation delay DR_EN turn-off propagation delay falling t_tsshd – 50 – t_tssh – 50 – t_pdlu – 20 – t_pdll – 10 – t_pdl_DR_EN – 20 – DR_EN turn-on propagation delay rising t_pdh_DR_EN – 20 – UVLO-BOOT-on time t_UVLOBOOTon – 200 – UVLO-BOOT-off time PWM minimum pulse width t_UVLOBOOToff ton_min_PWM – – 200 25 – – PWM minimum off time toff_min_PWM – 30 – 5 Note / Test Condition ns Pulse pattern issued to GL in UVLO-BOOT When PWM change is recognized, the output remains in the new state for these minimum times. Theory of Operation The TDA21231 incorporates a high performance gate driver, one high-side power MOSFET and one low-side power MOSFET in a single PG-IQFN-31-2 package. The advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.This module is ideal for use in Synchronous Buck Regulators. The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to 2 +21 V. The power density for transmitted power of this approach is approximately 90 W within a 25 mm area. 5.1 Driver Characteristics The gate driver of the TDA21231 has 2 voltage inputs, VCC and PVCC. VCC is the 5 V logic supply for the driver. PVCC sets the driving voltage for the high side and low side MOSFETs. The reference for the gate driver control circuit (VCC) is AGND. To decouple the sensitive control circuitry (logic supply) from a noisy environment a ceramic capacitor must be placed between VCC and AGND close to the pins. PVCC needs also to be decoupled using a ceramic capacitor (MLCC) between PVCC and PGND in close proximity to the pins. PGND serves as reference for the power circuitry including the driver output stage. Data Sheet 8 TDA21231 Referring to the block diagram page 4, VCC is internally connected to the UVLO circuit. It will force shut-down for insufficient VCC voltage. PVCC supplies the floating high-side drive – consisting of an active boot circuit and the low side drive circuit. During undervoltage both GH and GL are driven low actively; further passive pulldown (10 k) is placed across gate-source of both FETs. An additional UVLO circuitry, sensing the BOOT voltage level, is implemented to enable a recharge of the boot capacitor when its voltage is too low for a complete turn-on of the HS-MOSFET. Proper response of the driver to the PWM signal is only guaranteed when UVLO and UVLO BOOT have been cleared by their respective supply voltages (Table 9). Therefore, it is strongly recommended to only issue pulses to PWM when no UVLO conditions are present. The power down sequence should set PWM to HiZ with regard to the internal threshold before ramping down VIN, PVCC and VCC respectively. 5.2 Inputs to the Internal Control Circuits The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V. The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is held internally at a level of VPWM_O = 1.6 V level. Table 12 PWM Pin Functionality PWM logic level Driver output Low GL= High, GH = Low High GL = Low, GH = High Open (left floating, or High impedance) GL = Low, GH = Low The PWM threshold voltages VPMW_O, VPWM_H, VPWM_L do not vary over the wide range of VCIN supply voltages (4.5 V to 8 V). EN is an active high signal. When EN is being pulled low, the power stage will be disabled. EN Logic Level “H” Enable Shutdown “L” VEN_L Figure 4 Data Sheet Enable (EN) signal logic levels 9 VEN_H VCC TDA21231 Table 13 EN Pin Functionality EN logic level Driver output Low Shutdown : GL = GH = Low High Enable : GL = Active, GH = Active Open (left floating, or High impedance) Shutdown : GL = GH = Low 5.3 Thermal protection The PHFLT# pin is a digital monitoring output for the thermal warning. It does not affect the operation of the driver nor does it shut down the device. When the driver junction temperature exceeds the thermal warning threshold of 140 °C (typ) the open drain output PHFLT# will be pulled low. Externally PHFLT# has to be connected to a supply (e.g. +3.3 V) by a resistor in the range of 10 k When the temperature of the driver junction decreases below the level of thermal warning threshold minus hysteresis (10 K typ.), the pin PHFLT# is released. VPHFLT# is being pulled up by the external resistance. If the thermal warning feature is not used the pin can be left floating. PHFLT# Output Logic Level “H” Rising temperature “L” Falling temperature Hysteresis TPHFLT#_T Tj TPHFLT#_T - TPHFLT#_H Figure 5 5.4 Thermal warning Shoot Through Protection The TDA21231 driver includes gate drive functionality to protect against shoot through. In order to protect the power stage from overlap, both high-side and low-side MOSFETs being on at the same time, the adaptive control circuitry monitors specific voltages. When the PWM signal transitions to low, the high-side MOSFET will begin to turn off after the propagation delay time t_pdlu. When VGS of the high-side MOSFET is discharged below 1 V (a threshold below which the high-side MOSFET is off), a secondary delay t_pdhl is initiated. After that delay the low-side MOSFET turns on regardless of the state of the “SW” pin. It ensures that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See Figure 8 for more detail. Data Sheet 10 TDA21231 5.5 UVLO – BOOT Protection After long tristate conditions the voltage of the boot capacitor may be too small to completely enhance the HSMOSFET when PWM enables GH directly after. Therefore, a monitoring circuit is being implemented to detect a lower threshold at which GH can safely be turned on. If the voltage across the boot capacitor has been dropping to this threshold a boot refresh circuit engages until an upper threshold has been reached. The recharge is being done by intervals of repetitively pulling GL high for t_UVLOBOOTon followed by t_UVLOBOOToff driving GL low to reset the output current to zero. When the voltage across the boot capacitor has reached an upper threshold the recharge cycles stop. The PWM input always takes priority over the boot refresh circuit when it is logic “H” or logic “L”. 6 Application 6.1 Implementation Figure 6 Pin Interconnection Outline (example, transparent top view) Note: 1. Pin PHASE is internally connected to SW node 2. It is recommended to place a RC filter between VCC and PVCC as shown. 3. Pins 24, 25 and 26 are not internally connected. One can leave them open or connect to GND or to SW. 4. RBOOT is only required for telecom applications with VIN > 13.2V (see Table 8). If necessary, its value should be selected to limit the voltage spike VPHASE-VPGND (AC) to 26V. Data Sheet 11 TDA21231 6.2 Figure 7 Data Sheet Typical Application Six-phase voltage regulator - typical application (simplified schematic) 12 TDA21231 Gate Driver Timing Diagram 7 VPWM_H VPWM_H PWM VPWM_H Tri-state VPWM_L VPWM_L t_pdll t_tsshd t_pts2 t_pdhl GL 1V t_tssh t_pdlu t_pts t_pdhu GH 1V SW 1 V (threshold for GL enable) Note: SW during entering/exiting tri-state behaves dependend on inductor current. Figure 8 Data Sheet Adaptive Gate Driver Timing Diagram 13 TDA21231 Active VEN_H Active EN Deactivated VEN_L t_pdh(EN) t_pdl(EN) SW Figure 9 Data Sheet EN Timing Diagram 14 TDA21231 8 Performance Curves – Typical Data Operating conditions (unless otherwise specified): VIN = +12 V, VCC = PVCC = +5 V, VOUT = +1.8 V, fSW = 600 kHz, 150nH (Cooper, FP0906R1-R15, DCR = 0.29 mΩ) inductor, TA = 25 °C, airflow = 300 LFM, no heatsink. Efficiency and power loss reported herein include only TDA21231 losses for a single phase obtained within a 5 phase multiphase operation (CCM to zero load current) on an 8-layer server board. 8.1 Figure 10 Data Sheet Driver Current versus Switching Frequency Driver Current over Switching Frequency in CCM Operation 15 TDA21231 8.2 Efficiency and Power Loss Figure 11 Efficiency at VIN = 12 V, VCC = PVCC = 5 V, fSW = 600 kHz, VOUT = 1.8 V Figure 12 Power Loss at VIN = 12 V, VCC = PVCC = 5 V, fSW = 600 kHz, VOUT = 1.8 V Data Sheet 16 TDA21231 9 Figure 13 Data Sheet Mechanical Drawing PG-IQFN-31-2 Mechanical Dimensions (in mm) 17 TDA21231 Figure 14 Data Sheet Recommended Landing Pattern and Stencil Dimensions (in mm) 18 TDA21231 Board Layout Recommendations 10 The PCB (printed circuit board) layout design follows the listed industry standards: 6 - Recommended vias: 10 mil hole with 20 mil via pad diameter, 12 mil hole with 24 mil via pad diameter - Minimum (typical) via to via center distance: 25 mil (30 … 35 mil) - Minimum feature width: 5 mil - Minimum (typical) clearance: 5 mil (15 … 20 mil) Commonly, 10 mil via drill diameters are used for PCBs up to 150 mil thicknesses (usually 22 layers). For thicker boards, 12 mil vias are recommended. To reduce voltage spikes caused by parasitic circuit inductance, all primary decoupling capacitors for VIN, PVCC, BOOT and VCC should be of MLCC type, X6S or X7R rated and located at the same board side as the powerstage close to their respective pins. This is especially important for the VIN to PGND MLCCs. Electrical and thermal connection of the powerstage to the PCB is crucial for achieving high efficiency. Therefore, vias in VIN and PGND pads are required in the pad areas to connect most effectively to other power and PGND layers. Bigger value MLCC input capacitors should be placed at the bottom side of the PCB close to the vias of the powerstage’s VIN and PGND pads. To reduce the stray inductance in the current commutation loop it is strongly recommended to have the 2 nd layers from the top and the bottom of the board to be monolithic ground planes. All logic and signal connections between powerstage and controller should be embedded between two ground layers. The routing of the current sense lines back to the controller has to be done differentially, for example with 5 mil spacing and 10 – 15 mil distances to other potentials. If the PCB features more than 10 layers, the passive components associated with the current sense lines should be located only at the top side of the board. All resistors and capacitors near the powerstage should be in 0402 case size. For minimizing distribution loss to the load and maintaining signal integrity, have multiple layers/planes in parallel and ensure that the copper cross section for PGND is at least as big as it is for Vout. Figure 15 6 Generic Board Design Unit conversion: 1 mil = 25.4 μm Data Sheet 19 DrMOS5x5 TDA21231 RevisionHistory TDA21231 Revision:2015-10-16,Rev.2.2 Previous Revision Revision Date Subjects (major changes since last revision) 1.0 2015-03-24 Release of preliminary version 2.0 2015-04-23 Release of final version 2.1 2015-06-04 updated IPVCC, added performance data 2.2 2015-10-16 updated section 5.1 (driver) WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2015InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.With respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. 21 Rev.2.2,2015-10-16