TDA21520AUMA1

TDA21520 1 Description • High frequency, low profile DC-DC converters; • Voltage Regulators for DDR memory arrays, and low current voltage rails; The TDA21520 integrated power-stage contains a low quiescent current synchronous buck gate-driver IC which is co-packed with control and synchronous MOSFETs along with an active diode structure that achieves low Vsd similar to a schottky with very little reverse recovery charge. The package is optimized for PCB layout, heat transfer, driver/MOSFET control timing, and minimal switch node ringing when layout guidelines are followed. The paired gate driver and MOSFET combination enables higher efficiency at lower output voltages. The internal MOSFET sensing achieves superior current sense accuracy vs. best-in-class controller-based Inductor DCR sense methods. Protection includes IC temperature reporting and over temperature protection feature (OTP with thermal shutdown), cycle-by-cycle over current protection (OCP), control MOSFET short detection (HSS - High side short detection), VDRV and bootstrap under-voltage protection. The TDA21520 also features "refreshing" of bootstrap capacitor to prevent the bootstrap capacitor from over-discharging. Operation of up to 1.5 MHz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. Features • Integrated driver, active diode, high-side MOSFET and low-side MOSFET • Input voltage range of 4.25 V to 16 V • VCC supply of 4.25 V to 5.5 V • Output voltage range from 0.225 V up to 5.5 V • Output current capability of 20 A • Operation up to 1.5 MHz • VCC under voltage lockout (UVLO) • Bootstrap under voltage protection • On-chip MOSFET current sensing and reporting with 5 µA/A gain • Over temperature protection and thermal shutdown • Cycle-by-cycle over current protection and flag • High-side MOSFET short detection and flag • Auto-replenishment on bootstrap capacitor • Compatible with 3.3 V tri-state PWM Input • Auto SLEEP mode after 20 µs of PWM Tri-state (1.7 mA typ) • DEEP SLEEP mode for power saving via EN= low (32 µA typ) • Small 4 mm x 5 mm x 0.9 mm PQFN package • Lead free RoHS compliant package Please read the Important Notice and Warnings at the end of this document www.infineon.com Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Description Table 1 Product Identification Part Number Temp Range TDA21520 Figure 1 -40 to 125C Package Orderable Part Number PQFN 4 mm x 5 mm TDA21520AUMA1 Picture of the Product 2 Description 2.1 Pinout ` Figure 2 Table 2 Pinout, Numbering and Name of Pins (transparent top view) I/O Signals 2 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Description Pin No. Name Pin Type Buffer Type Function 1 TMON / FLT O Analog The voltage at this pin is defined by the equation 8mV * (Celsius Temperature) + 0.6 V. This pin will be pulled up to 3.3 V under severe over-temperature, overcurrent, high-side MOSFET short or Bootstrap under voltage condition. 5, 27 GL I/O Analog Low-side MOSFET driver pin that can be connected to a test point in order to observe the waveform. 8, 9, 10, SW 11, 12 O Analog Switching node of synchronous buck converter. 19 PHASE I Analog Switching node. For bootstrap capacitor connection only. 20 BOOT I Analog Bootstrap capacitor connection. Connect an X7R ceramic capacitor with value between 0.22uF to 0.56uF from BOOT to PHASE pin. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. 21 PWM I/O +3.3 V logic 3.3 V logic level PWM input. PWM input: “High” turns highside MOSFET on; “Tri-state” turns both MOSFETs off; “Low” turns low-side MOSFET on. 22 EN I +3.3 V logic Pulling EN high enables the driver; pulling EN low disables the driver and enters ultra-low quiescent current mode. Floating this pin is not recommended, however a pulldown resistor is embedded to keep the driver off if the pin is floating. This pin is VCC tolerant. 24 IMONREF I/O Analog This pin provides a system reference for the IMON information and can be tied to a fixed voltage between 1.1 V and 1.9 V such as bias rails of a PWM controller. 25 IMON O Analog Sensed current output signal proportional to high-/lowside MOSFET currents referenced to the IMONREF pin through an external resistor. V (IMON – IMONREF) voltage across the external resistor represents current information. 3 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Description Table 3 Power Supply Pin No. Name Pin Type Buffer Type Function 4 VCC POWER – Bias voltage for control logic and supply of gate driver. Connect a 1 uF cap between VCC and PGND. VCC should be connected to +5 V power supply. 16, 17, 18 VIN POWER – 4.25 V to 16 V high current input voltage connection. Table 4 Not Connected Pin No. Name Pin Type Buffer Type Function 3 NC – – Leave the pin unconnected. 28 NC – – For internal test only, no PCB pad recommended for this pin Table 5 Ground Pins Pin No. Name Pin Type Buffer Type Function 23 AGND GND – Signal ground. All interface signals are referenced to this pin. 2, 7, 13, 14, 15, 26 PGND GND – Power ground. It is also the power ground of the low-side MOSFET. 4 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Simplified Block Diagram 3 Simplified Block Diagram 5 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Electrical Specification 4 Electrical Specification 4.1 Absolute Maximum Ratings Note: TA = 25 °C Stresses above those listed in Table 6 “Absolute Maximum Ratings” may cause permanent damage to the device. These are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational sections of this specification. Exposure over values of the recommended ratings for extended periods may adversely affect the operation and reliability of the device. Table 6 Absolute Maximum Ratings Parameter Min. Typ. Max. Unit Note / Test Condition 0.1 – 1.5 MHz Maximum average load current IMON – – 20 A Input Voltage -0.30 – 25 V Pin VIN Logic and driver supply voltage VCC -0.3 – 6.5 V Pin VCC Switch node voltage VSW (DC) -1 – 25 V Pin SW VSW (AC) -8 for 10ns – 34 for 1 ns VPHASE (DC) -1 – 25 V Pin PHASE VPHASE (AC) -8 for 10ns – 34 for 1 ns VVIN - VPHASE (DC) -1 25 V VIN – PHASE VVIN - VPHASE (AC) -8 for 10ns – – VBOOT (DC) -0.3 – 29 V Pin BOOT VBOOT (AC) Below -0.3V – for 5ns VBOOT-PHASE -0.3 – 6.5V (DC), 7.5V for 3ns GL voltage VGL -0.3 – 6.5 V Pin GL EN voltage VEN -0.3 – 6.5 V Pin EN PWM voltage VPWM -0.3 – 4.0 V Pin PWM TMON voltage VTMON -0.3 – 3.6 V Pin TMON / FLT IMON voltage VIMON -0.3 – 3.6 V Pin IMON IMONREF voltage VIMONREF -0.3 – 3.6 V Pin IMONREF NC pin 28 voltage V28 -0.3 – 0.3 V Pin 28 Junction temperature TJmax -40 – 150 C – Storage temperature TSTG -55 – 150 C – Frequency of the PWM input PHASE voltage VIN – PHASE voltage BOOT voltage Symbol fSW VIN Values 34 for 1 ns V Note: All rated voltages are relative to voltages on the AGND and PGND pins unless otherwise specified. 6 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Electrical Specification 4.2 Table 7 Thermal Characteristics Thermal Characteristics Parameter Symbol Values Min. Typ. Max. – 2.3 – Thermal resistance-Junction to θJC_PCB PCB (pin 15) Unit Note / Test Condition K/W – Thermal resistance-Junction to θJC_Top – 22.2 – – top of package – – – Thermal resistance to ambient θJANote 21.5 Note: Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air. 4.3 Recommended Operating Conditions Table 8 Recommended Operating Conditions Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Input voltage VIN 4.25 – 16 V – Logic and driver supply voltage VCC 4.25 – 5.5 V – Frequency of the PWM fSW 100 – 1500 KHz - EN voltage VEN – – 5.5 V Pin EN PWM voltage VPWM – – 3.6 V Pin PWM Current Sense reference voltage VIMONREF 1.1 – 1.9 V Pins IMON, IMONREF Junction temperature TjOP -40 – +125 °C – 4.4 Electrical Characteristics Note: Typical values represent the median values, which are related to 25°C,VCC = 5 V, VIMONREF = 1.2V Table 9 Voltage Supply, Biasing Current Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. UVLO VCC rising UVLO VCC falling Bootstrap Under-voltage rising threshold Bootstrap Under-voltage falling threshold Supply Current VIN Current VUVLO_R - 4.05 - V VUVLO_F VUVBOOT_R VUVBOOT_F – – – - 3.85 3.82 3.61 22 – – – - mA EN = H, fSW = 600 kHz, D=10% – 1.6 – mA EN = H, PWM floating – 35 – µA EN = L - 1 nA No switching, EN = L IVcc – IVIN 7 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Electrical Specification Table 10 Current Sense Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. 0.8 – 2.35 V DC + AC components IMONREF VIMON_CM reference voltage range 1.1 – 1.9 V Reference Voltage connected externally for the current sense signal Current sense gain – 5 – µA/A IMON IMON Voltage range IMON Gain resistor range Table 11 VIMON Acs RIMON - 1 - Symbol Values Min. TMON Temperature / FLT Sense Slope Temperature Sense Offset Voltage Table 12 Note / Test Condition 25°C ≤ TJ ≤ 125°C, Note 1 Typ. Max. ATMPGAIN - 8.0 - mV/°C VTMPOFFSET - 800 - mV TJ = 25°C, 0.6 V + 8 mV/°C * TJ Other Logic Functions, Inputs/Outputs And Thresholds Parameter Symbol Values Min. Typ. PWM Unit Temperature Sense and FLT Communication Parameter EN kΩ Resistor to be connected between IMON and IMONREF. For 5mV/A, recommended 1kΩ RIMON Unit Note / Test Condition Max. Input High Voltage VEN_H 2.0 – – V Input Low Voltage VEN_L – – 0.8 V Enable Power-on Delay tEN_ondelay – 17 - μs PWM=0. Measured from EN rising edge to VGL> 1 V. Note 1 Enable Power-off tEN_offdelay Delay – - 1 us PWM=0. Measured from EN falling edge to VGL < 4 V. Note 1 When EN is floating Internal Pull down Resistance RPULLDN_EN 210 280 340 kΩ PWM Input High Threshold VIH 2.4 – – V PWM Input Low Threshold VIL – – 0.8 V IPWM_HYS – 40 – mV PWM Hysteresis 8 PWM Low or Tri-state to High PWM High or Tri-state to Low Active to Tri-state or Tri-state to Active Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Electrical Specification Table 13 Protection Parameter OTP HSS FLT OCP Symbol Values Unit Note / Test Condition Min. Typ. Max. Over Temp Rising Threshold TRISE – 140 – °C TMON/FLT pulled up high Note 1 Over Temp Falling Threshold TFALL – 128 – °C TMON/FLT released - 560 - mV – 150 – ns – 36 – A 10 – – Cycle High-side MOSFET Short Threshold VHSS_TH TMON/FLT Delay THSS_DEL Over-Current Threshold IOCP_TH Over-Current Delay TOCP_DEL Note 1 VSW – VPGND After VHSS_TH is detected and TMON/FLT is pulled high PWM High-Low Cycles to TMON/FLT is pulled high Notes 1. Guaranteed by design but not tested in production 9 Rev 2.22 2022-05-19 OptiMOSTM Powerstage TDA21520 Typical operating conditions 5 Typical operating conditions Single Phase Circuit of Figure 18, VIN = 12 V, VOUT = 1 V, ƒSW = 600 kHz, L = 120 nH, VCC = VDRV = 5 V, TAMBIENT = 25 °C, no heat sink, no air flow, 8-layer PCB board of 3.7”(L) x 2.6”(W), no PWM controller loss, no inductor loss, unless specified otherwise. Figure 3 Powerstage Efficiency Figure 5 VCC current v/s Frequency Figure 4 Power stage Loss Figure 6 Thermal derating, Tcase