Dat a Sh ee t, V1.0 , F eb rua ry 2 01 0
S m a r t L E W I S TM R X +
TDA5235
En hanced Sensitivity
Double- Con fig urat ion Receiver with
Digital Baseb and P rocessin g
Wi re less Co ntro l
N e v e r
s t o p
t h i n k i n g .
Edition February 19, 2010
Published by Infineon Technologies AG,
Am Campeon 1 - 12
85579 Neubiberg, Germany
© Infineon Technologies AG February 19, 2010.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies
Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Dat a Sh ee t, V1.0 , F eb rua ry 2 01 0
S m a r t L E W I S TM R X +
TDA5235
En hanced Sensitivity
Double- Con fig urat ion Receiver with
Digital Baseb and P rocessin g
Wi re less Co ntro l
N e v e r
s t o p
t h i n k i n g .
TDA5235
Revision Number:
Revision History:
010
2010-02-19
Previous Version:
TDA5235_V0.1
V1.0
Page
Subjects (major changes since last revision)
Page 25
Update of Figure 9
Page 27
Update of Figure 10
Page 29
AFC limitation added
Page 31
AGC setting proposal added
Page 32
New Section 2.4.6.5 ADC added
Page 34
Additional information on RSSIPRX register inserted
Page 39
Signal and Noise Detector Procedure adapted
Page 43
x_CDRRI register recommendation changed
Page 47, 50, 54
Data Slicer Modes adapted; limitation added
Page 67
Update of Figure 41
Page 68
Update of Figure 42
Page 76
Additional hint on clock and data recovery algorithm of the user
software inserted
Page 82
PLDLEN limitation added
Page 84
Limitation for ISx readout and Burst-read function added
Page 86
Limitation for Burst-read function added
Page 105
Description of “Parallel Wake-up Search” adapted
Page 123
Additional hints added
Page 125
Adaption of Section 4.1
Page 128
New item C7 added
Page 136 f
Comments added for items I6, I7, I8, I9, J11, J12
Page 136
Item J1 updated
Page 139 ff
General test conditions noted for parameters K, L and M
Page 145
BOM components C7, C8, L1, R2 and R3 updated
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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TDA5235
Table of Contents
Page
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.8.3
2.4.8.4
2.4.8.5
2.4.8.6
2.4.8.7
2.4.8.8
2.4.9
2.4.9.1
2.4.9.2
2.5
2.5.1
2.5.1.1
2.5.1.2
2.5.2
2.5.3
2.5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definition and Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RF/IF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Crystal Oscillator and Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sigma-Delta Fractional-N PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLL Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Digital Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ASK and FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Automatic Frequency Control Unit (AFC) . . . . . . . . . . . . . . . . . . . . . 28
Digital Automatic Gain Control Unit (AGC) . . . . . . . . . . . . . . . . . . . . 30
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RSSI Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Digital Baseband (DBB) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Filter and Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Encoding Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Slicer and Line Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Wake-Up Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RUNIN, Synchronization Search Time and Inter-Frame Time . . . . . . 66
Power Supply Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Interfacing to the TDA5235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Digital Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Data Sheet
5
7
7
8
8
V1.0, 2010-02-19
TDA5235
Table of Contents
Page
2.5.5
2.5.5.1
2.5.6
2.6
2.6.1
2.6.1.1
2.6.1.2
2.6.1.3
2.6.1.4
2.6.1.5
2.6.1.6
2.6.1.7
2.6.1.8
2.6.2
2.6.2.1
2.6.2.2
2.6.2.3
2.6.2.4
2.6.2.5
2.6.2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.8.1
2.8.2
Digital Control (4-wire SPI Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
System Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Master Control Unit (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Run Mode Slave (RMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
HOLD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Self Polling Mode (SPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Automatic Modulation Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Multi-Channel in Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . 104
Run Mode Self Polling (RMSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Polling Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Self Polling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Constant On-Off Time (COO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Fast Fall Back to SLEEP (FFB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Mixed Mode (MM, Const On-Off & Fast Fall Back to SLEEP) . . . . . 120
Permanent Wake-Up Search (PWUS) . . . . . . . . . . . . . . . . . . . . . . . 121
Active Idle Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Manchester Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Symbols of SFR Registers and Control Bits . . . . . . . . . . . . . . . . . . . . 126
Digital Control (SFR Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Register List and Detailed SFR Description . . . . . . . . . . . . . . . . 127
3
3.1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4
4.1
4.1.1
4.1.2
4.1.3
4.2
4.3
4.4
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Circuit - Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layout, Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
131
131
131
132
133
154
155
157
Appendix - Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Data Sheet
6
V1.0, 2010-02-19
TDA5235
Product Description
1
Product Description
1.1
Overview
The IC is a low power ASK/FSK Receiver for the frequency bands 300-320, 425-450,
863-870 and 902-928 MHz. Bi-phase modulation schemes, like Manchester, bi-phase
mark, bi-phase space and differential Manchester are supported.
The chip offers best-in-class sensitivity performance at a very high level of integration
and needs only a few external components.
The device is qualified to automotive quality standards and operates between -40 and
+105°C at supply voltage ranges of 3.0-3.6 Volts or 4.5-5.5 Volts.
The receiver is realized as a double down conversion super-heterodyne/low-IF
architecture each with image rejection supplemented by digital signal processing in the
baseband. A fully integrated Sigma-Delta Fractional-N PLL Synthesizer allows for highresolution frequency generation and uses a crystal oscillator as the reference. The onchip temperature sensor may be utilized for temperature drift compensation via the
crystal oscillator.
The digital baseband processing unit together with the high performance down converter
is the key element for the exceptional sensitivity performance of the device which take it
close to the theoretical top-performance limits. It comprises signal and noise detectors,
matched data filter, clock and data recovery, data slicer and a format decoder. It
demodulates the received ASK or FSK data stream independently and recovers the data
clock out of the received data stream with very fast synchronization times which can then
be either accessed via separate pins or used for further processing like frame
synchronization and intermediate storage in the on-chip FIFO. The RSSI output signal is
converted to the digital domain with an ADC. All these signals are accessible via the 4wire SPI interface bus. Up to 2 pre-configured telegram formats can be stored into the
device offering independent pre-processing of the received data to an extent not
available till now. The down converter can be also configured in single-conversion mode
at moderately reduced selectivity performance but at the advantage of omitting the IF
ceramic filter.
Data Sheet
7
V1.0, 2010-02-19
TDA5235
Product Description
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Enhanced sensitivity receiver
Multi-band (300-320, 425-450, 863-870 and 902-928 MHz)
One crystal frequency for all supported frequency bands
21-bit Sigma-Delta Fractional-N PLL synthesizer with high resolution of 10.5 Hz
Up to 2 parallel parameter sets for autonomous scanning and receiving from different
sources reduces significantly host processor power consumption and system
standby power consumption
One frequency channels per parameter set is supported with 10.5 Hz resolution
Autonomous receive mode leads to reduced noise of host processor and improved
system performance
Ultrafast Wake-up on RSSI
Fast synchronization on incoming data stream typically within first 4 bits of a telegram
Selectable IF filter bandwidth and optional external filters possible
Double down conversion image reject mixer
ASK and FSK capability
Automatic Frequency Control (AFC) for carrier frequency offset compensation
Supports bi-phase line codes like Manchester, bi-phase mark/space and differential
Manchester
NRZ data pre-processing capability
Digital base band receiver with clock synch, frame synch, format decoding and FIFO
Separate outputs for recovered data and clock
RSSI peak detectors
Wake-up generator and polling timer unit
Message ID scanning
Unique 32-bit serial number
On-chip temperature sensor
Integrated timer usable for external watch unit
Integrated 4-wire SPI interface bus
Supply voltage range 3.0 Volts to 3.6 Volts or 4.5 Volts to 5.5 Volts
Operating temperature range -40 to +105°C
ESD protection +/- 2 kV on all pins
Package PG-TSSOP-28
1.3
•
•
•
•
•
•
•
Features
Applications
Remote keyless entry systems
Remote start applications
Tire pressure monitoring
Short range radio data transmission
Remote control units
Cordless alarm systems
Remote metering
Data Sheet
8
V1.0, 2010-02-19
TDA5235
Functional Description
2
Functional Description
2.1
Pin Configuration
IFBUF_IN
1
28
IF_OUT
IFBUF_OUT
2
27
VDDA
GNDA
3
26
RSSI
IFMIX_INP
4
25
PP3
IFMIX_INN
5
24
GNDRF
VDD5V
6
23
LNA_INP
VDDD
7
22
LNA_INN
VDDD1V5
8
21
T2
GNDD
9
20
T1
PP0
10
19
SDO
PP1
11
18
SDI
PP2
12
17
SCK
P_ON
13
16
NCS
XTAL1
14
15
XTAL2
Figure 1
Data Sheet
TDA5235
Pin-out
9
V1.0, 2010-02-19
TDA5235
Functional Description
2.2
Pin Definition and Pin Functionality
Table 1
Pin Definition and Function
Pin Pad name
No.
1
Equivalent I/O Schematic
Function
IFBUF_IN
Analog input
IF Buffer input
VDDA
VDDA
330Ω
IFBUF
IFBUF_IN
Note: Input is
biased at VDDA/2
VDDA
330Ω
MIX2BUF
IFMIX_INN
2
IFBUF_OUT
VDDA
Analog output
IF Buffer output
VDDA
330Ω
IFBUF_OUT
IFBUF
GNDA
GNDA
3
GNDA
Analog ground
4
IFMIX_INP
Analog input
+ IF mixer input
VDDA
VDDA
330Ω
IFMIX_INP
MIX2BUF
Note: Input is
biased at VDDA/2
IFMIX_INN
5
IFMIX_INN
6
VDD5V
Data Sheet
see schematic of Pin 1 and 4
Analog input.
- IF mixer input
Analog input
5 Volt supply input
10
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
7
Equivalent I/O Schematic
Function
VDDD
VDD5V
Analog input
digital supply input
+
VReg
-
=
VDDD
GNDD
8
VDDD1V5
VDDD
Analog output
1.5 Volt voltage
regulator
+
VReg
=
-
VDD1V5
GNDD
9
GNDD
Digital ground
10 PP0
VDD5V
VDD5V
PPx
SDO
GNDD
Data Sheet
11
GNDD
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR (Special
Function Register),
default = CLK_OUT
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
11 PP1
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = DATA
12 PP2
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = NINT
13 P_ON
VDD5V
VDDD
Digital input
power-on reset
P_ON
NCS
SCK
SDI
GNDD
Data Sheet
GNDD
12
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
14 XTAL1
VDDD
VDDD
Analog input
crystal oscillator
input
XTAL1
GNDD
....
GNDD
GNDD
15 XTAL2
VDDD
Analog output
crystal oscillator
output
VDDD
XTAL2
....
GNDD
GNDD
GNDD
16 NCS
see schematic of Pin 13
Digital input
SPI enable
17 SCK
see schematic of Pin 13
Digital input
SPI clock
18 SDI
see schematic of Pin 13
Digital input
SPI data in
19 SDO
see schematic of Pin 10
Digital output
SPI data out
20 T1
Digital input,
connect to Digital
Ground
21 T2
Digital input,
connect to Digital
Ground
Data Sheet
13
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
22 LNA_INN
Analog input
LNA - RF input
LNA_INN
GNDRF
23 LNA_INP
Analog input
LNA + RF input
LNA_INP
GNDRF
24 GNDRF
25 PP3
RF analog ground
see schematic of Pin 10
Digital output
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = RX_RUN
26 RSSI
VDDA
VDDA
500Ω
RSSI
GNDA
Data Sheet
Analog output
analog RSSI output/
analog test pin
ANA_TST
GNDA
14
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
27 VDDA
VDD5V
Analog input
Analog supply
+
VReg
=
-
VDDA
GNDA
28 IF_OUT
Analog output
IF output
VDDA
VDDA
330Ω
IF_OUT
PPFBUF
GNDA
Data Sheet
GNDA
15
V1.0, 2010-02-19
Figure 2
Data Sheet
XTAL
21.948717
MHz
16
GNDD
(9)
XTAL2
(15)
XTAL1
(14)
VDDA
(27)
Vreg
3V3
3.3V-Analog
VDD5V
(6)
XOSC
Vreg
3V3
1st LO-Q
ΣΔ PLL
1st LO-I
PPF
BUF
wide
narrow
VDDD
(7)
3.3V Dig-I/O
5V Dig-O
Clock for
Digital Core
2nd LO-Q
2nd LO-I
T2
(21)
Reset
Generator
to
RX
PPF
2
Reset for
Digital Core
nd
IR-Mix2, 2 IF:
274.35897 kHz
1.5V Dig-Core
2 LO
Div 2
nd
M IX2
BUF
VDDD1V5 P_ON T1
(8)
(13) (20)
Vreg
1V5
1st IF = 10.7 MHz
2nd IF = 1st IF / 39
f cry stal = 2nd IF * 80
double/single
conversion (SDCSEL)
IFBUF
IFBUF_IN (1)
PP3 (25)
[RX_RUN]
GNDA (3)
PPF
IFBUF_OUT (2)
GNDRF
(24)
LNA
IFMIX_INN (5)
LNA_INN
(22)
LNA_INP
(23)
IF_OUT (28)
IR-Mix, 1st IF:
10.7 MHz
IFMIX_INP (4)
matching
+
SAW
Antenna
10.7 MHz
narrow ( opt )
VDDD
AAF
LP
D
AFC
Digital
Demod
PP0
(10)
[CLK_OUT]
ADC
I/F
MUX
PP2
(12)
[NINT]
Interrupt
Generator
Peripheral Bus
PLL
Control I/F
Clock
Generator
to
PLL
A
ADC-MUX
RSSI
System
Management
RX
Control I/F
Temp.Sensor
BPF
select
BW
Limiter
RSSI
(26)
Clock
Recovery
Slicer
RX FIFO
NCS SCK SDI SDO
(16) (17) (18) (19)
SPI Interface
Serial
Number
Framer
Signal & Noise
Detectors
Peak
Detectors
Data
Filter
PP1
(11)
[DATA]
TDA5235
2.3
(CERFSEL)
10.7 MHz
wide
TDA5235
Functional Description
Functional Block Diagram
TDA5235 Block Diagram1)
1) The function on each PPx port pin can be programmed via SFR (see also Table 1). Default values are given
in squared brackets in Figure 2.
V1.0, 2010-02-19
TDA5235
Functional Description
2.4
Functional Block Description
2.4.1
Architecture Overview
A fully integrated Sigma-Delta Fractional-N PLL Synthesizer covers the frequency bands
300-320 MHz, 425-450 MHz, 863-870 MHz, 902-928 MHz with a high frequency
resolution, using only one VCO running at around 3.6 GHz.
For Multi-Configuration applications requiring different RF channels a very good channel
separation is essential. To achieve the necessary high sensitivity and selectivity a double
down conversion super-heterodyne architecture is used. The first IF frequency is located
around 10.7 MHz and the second IF frequency around 274 kHz. For both IF frequencies
an adjustment-free image frequency rejection feature is realized. In the second IF
domain the filtering is done with an on-chip third order bandpass polyphase filter. A multistage bandpass limiter completes the RF/IF path of the receiver. For Single-Channel
applications with relaxed requirements to selectivity, a single down conversion low-IF
scheme can be selected.
For Multi-Configuration systems requiring different RF channels where even higher
channel separation is required, up to two (switchable) external ceramic (CER) filters can
be used to improve the selectivity.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via an anti-aliasing filter this signal feeds an ADC
with 10 bits resolution.
The harmonic suppressed limiter output signal feeds a digital FSK demodulator. This
block demodulates the FSK data and delivers an AFC signal which controls the divider
factor of the PLL synthesizer.
A digital receiver, which comprises RSSI peak detectors, a matched data filter, a clock
and data recovery, a data slicer, a frame synchronization and a data FIFO, decodes the
received ASK or FSK data stream. The recovered data and clock signals are accessible
via 2 separate pins. The FIFO data buffer is accessible via the SPI bus interface.
The crystal oscillator serves as the reference frequency for the PLL phase detector, the
clock signal of the Sigma-Delta modulator and divided by two as the 2nd local oscillator
signal. To accelerate the start up time of the crystal oscillator two modes are selectable:
a Low Power Mode (with lower precision) and a High Precision Mode.
Data Sheet
17
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.2
Block Overview
The TDA5235 is separated into the following main blocks:
•
•
•
•
•
•
•
•
•
RF / IF Receiver
Crystal Oscillator and Clock Divider
Sigma-Delta Fractional-N PLL Synthesizer
ASK / FSK Demodulator incl. AFC, AGC and ADC
RSSI Peak Detector
Digital Baseband Receiver
Power Supply Circuitry
System Interface
System Management Unit
2.4.3
RF/IF Receiver
The receiver path uses a double down conversion super-heterodyne/low-IF architecture,
where the first IF frequency is located around 10.7 MHz and the second IF frequency
around 274 kHz. For the first IF frequency an adjustment-free image frequency rejection
is realized by means of two low-side injected I/Q-mixers followed by a second order
passive polyphase filter centered at 10.7 MHz (PPF). The I/Q-oscillator signals for the
first down conversion are delivered from the PLL synthesizer. The frequency selection
in the first IF domain is done by an external CER filter (optionally by two, decoupled by
a buffer amplifier). For moderate or low cost applications, this ceramic filter can be
substituted by a simple LC Pi-filter or completely by-passed using the receiver as a
single down conversion low-IF scheme with 274 kHz IF frequency. The down conversion
to the second IF frequency is done by means of two high-side injected I/Q-mixers
together with an on-chip third order bandpass polyphase filter (PPF2 + BPF). The I/Qoscillator signals for the second down conversion are directly derived by division of two
from the crystal oscillator frequency. The bandwidth of the bandpass filter (BPF) can be
selected from 50 kHz to 300 kHz in 5 steps. For a frequency offset of -150 kHz to -120
kHz, the AFC (Automatic Frequency Control) function is mandatory. Activated AFC
option might require a longer preamble sequence in the receive data stream.
The receiver enable signal (RX_RUN) can be offered at each of the port pins to control
external components. Whenever the receiver is active, the RX_RUN output signal is
active. Active high or active low is configurable via PPCFG2 register.
Data Sheet
18
V1.0, 2010-02-19
TDA5235
Functional Description
The frequency relations are calculated with the following formulas:
f IF1 = 10.7MHz
f IF1
f IF2 = --------39
f crystal = f IF2 × 80
f crystal
f LO2 = ---------------2
f LO1 = f crystal × NF divider
Lim ite r
QMix2
3rd order BP /PP F2
IF2 = 274 kH z
IF
Attenuation
adjust
IMix2
SDCSEL-MUX
MIX2BUF
(var. gain)
CERFilter IF1
10.7 MHz
optional
CERFSEL-MUX
Q-Mix
CERFilter
IF1
10 .7 MHz
IFBUF
LNA
PPFBUF
MUX
RX
Input
2nd order PPF
10.7 MHz
I-Mix
RSSI Generator
LP
harm sup
digital
FSK Demod
LP
alias sup
ASK /
RSSI
ADC
RX
FSK Data
RX
ASK Data
Divider
:N
IQ :2
Channel Filter
Bandwidth select
N
AFC
Filter
ΣΔ Modulator
Channel select
VCO
:1/:2/:3
IQ Divider : 4
Multi Modulos
Divider : N_FN
PD
Crystal
oscil lator
Band select
Channel select
LF select
Channel Filter select
Band select
Loop
Filter
Front end
control unit
IF Attenuation adjust
RSSI Gain/ Offset adjust
LF select
Figure 3
Block Diagram RF Section
The front end of the receiver comprises an LNA, an image reject mixer and a digitally
gain controlled buffer amplifier. This buffer amplifier allows the production spread of the
on-chip signal strip, of external matching circuitry and RF SAW and ceramic IF filters to
be trimmed. The second image reject mixer down converts the first IF to the second IF.
Data Sheet
19
V1.0, 2010-02-19
TDA5235
Functional Description
The bandpass filter follows the subsequent formula:
f center =
f corner, low × f corner, high
Therefore asymmetric corner frequencies can be observed. The use of AFC results in
more symmetry.
A multi-stage bandpass limiter at a center frequency of 274 kHz completes the receiver
chain. The -3dB corner frequencies of the bandpass limiter are typically at 75 kHz and
at 520 kHz.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via a programmable anti-aliasing filter this signal is
converted to the digital domain by means of a 10-bit ADC.
The limiter output signal is connected to a digital FSK demodulator.
The immunity against strong interference frequencies (so called blockers) is determined
by the available filter bandwidth, the filter order and the 3rd order intercept point of the
front end stages. For Single-Channel applications with moderate requirements to the
selectivity the performance of the on-chip 3rd order bandpass polyphase filter might be
sufficient. In this case no external filters are necessary and a single down conversion
architecture can be used, which converts the input signal frequency directly to the 2nd IF
frequency of 274 kHz.
IF
Attenuation
adjust
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 4
L im ite r
QMix2
3 rd o rd e r B P /P P F 2
I F2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
Q-Mix
M IX 2 B U F
( va r. g a i n )
C E RF S E L - M UX
IFB U F
LNA
PPF BU F
MUX
RX
Input
2nd order PPF
1 0 .7 M H z
I-Mix
2nd LO
Single Down Conversion (SDC, no external filters required)
For Multi-Configuration applications requiring different RF channels or systems which
demand higher selectivity the double down conversion scheme together with one or two
external CER filters can be selected. The order of such ceramic filters is in a range of 3,
so the selectivity is further improved and a better channel separation is guaranteed.
Data Sheet
20
V1.0, 2010-02-19
TDA5235
Functional Description
IF
Attenuation
adjust
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 5
L im ite r
QMix2
3 r d o r d e r B P /P P F 2
IF2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
Q-Mix
M IX 2 B U F
( va r. g a in )
C E RF S E L-M UX
CERFilter
IF1
10.7 MHz
IFB U F
LNA
PPFBUF
MUX
RX
Input
2 nd ord er P P F
1 0 .7 M H z
I-Mix
2nd LO
Double Down Conversion (DDC) with one external filter
For applications which demand very high selectivity and/or channel separation even two
CER filters may be used. Also in applications where one configuration/channel requires
a wider bandwidth than the other (e.g. TPMS and RKE) the second filter can be bypassed.
IF
Attenuation
adjust
Data Sheet
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 6
L im ite r
QMix2
3 rd o rde r B P /P P F2
I F2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
M IX 2 B U F
( va r. g a in )
CERFilter IF1
10.7 MHz
optional
C E RF S E L -M UX
Q-Mix
CERFilter
IF1
10.7 MHz
IFB U F
LNA
PPF BU F
MUX
RX
Input
2nd order PPF
1 0 .7 M H z
I-Mix
2nd LO
Double Down Conversion (DDC) with two external filters
21
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.4
Crystal Oscillator and Clock Divider
The crystal oscillator is a Pierce type oscillator which operates together with the crystal
in parallel resonance mode. An automatic amplitude regulation circuitry allows the
oscillator to operate with minimum current consumption. In SLEEP Mode, where the
current consumption should be as low as possible, the load capacitor must be small and
the frequency is slightly detuned, therefore all internal trim capacitors are disconnected.
The internal capacitors are controlled by the crystal oscillator calibration registers
XTALCALx. With a binary weighted capacitor array the necessary load capacitor can be
selected.
Whenever a XTALCALx register value is updated, the selected trim capacitors are
automatically connected to the crystal so that the frequency is precise at the desired
value. The SFR control bit XTALHPMS can be used to activate the High Precision Mode
also during SLEEP Mode.
fsys
9
Setting
automatically
controlled
( ≤ 1pF steps )
XTALCAL0
XTALCAL1
Oscillator -Core
XTAL1
Figure 7
Data Sheet
Binary weighted
Capacitor-Array
Binary weighted
Capacitor-Array
(DGND)
XTALHPMS
XTAL2
Crystal Oscillator
22
V1.0, 2010-02-19
TDA5235
Functional Description
Recommended Trimming Procedure
• Set the registers XTALCAL0 and XTALCAL1 to the expected nominal values
• Set the TDA5235 to Run Mode Slave
• Wait for 0.5ms minimum
• Trim the oscillator by increasing and decreasing the values of XTALCAL0/1
• Register changes larger than 1 pF are automatically handled by the TDA5235 in 1pF
steps
• After the Oscillator is trimmed, the TDA5235 can be set to SLEEP mode and keeps
these values during SLEEP mode
• Add the settings of XTALCAL0/1 to the configuration. It must be set after every power
up or brownout!
Using the High Precision Mode
As discussed earlier, the TDA5235 allows the crystal oscillator to be trimmed by the use
of internal trim capacitors. It is also possible to use the trim functionality to compensate
temperature drift of crystals.
During Run Mode (always when the receiver is active) the capacitors are automatically
connected and the oscillator is working in the High Precision Mode.
On entering SLEEP Mode, the capacitors are automatically disconnected to save
power.
If the High Precision Mode is also required for SLEEP Mode, the automatic disconnection of trim capacitors can be avoided by setting XTALHPMS to 1 (enable XTAL High
Precision Mode during SLEEP Mode).
External Clock Generation Unit
A built in programmable frequency divider can be used to generate an external clock
source out of the crystal reference. The 20 bit wide division factor is stored in the
registers CLKOUT0, CLKOUT1 and CLKOUT2. The minimum value of the
programmable frequency divider is 2. This programmable divider is followed by an
additional divider by 2, which generates a 50% duty cycle of the CLK_OUT signal. So
the maximum frequency at the CLK_OUT signal is the crystal frequency divided by 4.
The minimum CLK_OUT frequency is the crystal frequency divided by 221.
To save power, this programmable clock signal can be disabled by the SFR control bit
CLKOUTEN. In this case the external clock signal is set to low.
Data Sheet
23
V1.0, 2010-02-19
TDA5235
Functional Description
The resulting CLK_OUT frequency can be calculated by:
C L KO UT E N
C LK OU T2
C LK OU T1
C LK OU T0
f sys
f CLKOUT = --------------------------------------------2 ⋅ divisionfactor
Enable
fsys
Enable
2 x f C LK_OU T
20 Bit Counter
Figure 8
Divide
by 2
fC LK _OU T
External Clock Generation Unit
The maximum CLK_OUT frequency is limited by the driver capability of the PPx pin and
depends on the external load connected to this pin. Please be aware that large loads
and/or high clock frequencies at this pin may interfere with the receiver and reduce
performance.
After Reset the PPx pin is activated and the division factor is initialized to 11 (equals
fCLK_OUT = 998 kHz).
A clock output frequency higher than 1 MHz is not supported.
For high sensitivity applications, the use of the external clock generation unit is not
recommended.
Data Sheet
24
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.5
Sigma-Delta Fractional-N PLL Block
The Sigma-Delta Fractional-N PLL is fully integrated on chip. The Voltage Controlled
Oscillator (VCO) with on-chip LC-tank runs at approximately 3.6 GHz and is first divided
with a band select divider by 1, 2 or 3 and then with an I/Q-divider by 4 which provides
an orthogonal local oscillator signal for the first image reject mixer with the necessary
high accuracy.
The multi-modulus divider determines the channel selection and is controlled by a
3rd order Sigma-Delta Modulator (SDM). A type IV phase detector, a charge pump with
programmable current and an on-chip loop filter closes the phase locked loop.
To 1 st mixer
3.6 GHz VCO Loop Filter
IQ Divider
÷4
Band Select
÷1/÷2/÷3
Multimodulus
Divider
Channel FN
CP
PFD
ΣΔ Modulator
QOSC
22MHz
AFC filter
AFC-data
Figure 9
Data Sheet
Synthesizer Block Diagram
25
V1.0, 2010-02-19
TDA5235
Functional Description
When defining a Multi-Configuration system requiring different RF channels, the
correct selection of channel spacing is extremely important. A general rule is not
possible, but following must be considered:
• If an additional SAW filter is used, all channels including their tolerances have to be
inside the SAW filter bandwidth.
• The distance between channels must be high enough, that no overlapping can occur.
Strong input signals may still appear as recognizable input signal in the neighboring
channel because of the limited suppression of IF Filters. Example: a typical 330kHz IF
filter has at 10.3 MHz ( 10.7 MHz - 0.4 MHz ) only 30 dB suppression. A -70 dBm input
signal appears like a -100 dBm signal, which is inside the receiver sensitivity. In critical
cases the use of two IF filters must be considered. See also Chapter 2.4.3 RF/IF
Receiver.
2.4.5.1
PLL Dividers
The divider chain consists of a band select divider 1/2/3, an I/Q-divider by 4 which
provides an orthogonal 1st local oscillator signal for the first image reject mixer with the
necessary high accuracy and a multi-modulus divider controlled by the Sigma-Delta
Modulator. With the band select divider, the wanted frequency band is selected. Divide
by 1 selects the 915 MHz and 868 MHz band, divide by 2 selects the 434 MHz band and
divide by 3 selects the 315 MHz band. The ISM band selection is done via bit group
BANDSEL in x_PLLINTC1 register.
2.4.5.2
Digital Modulator
The 3rd order Sigma-Delta Modulator (SDM) has a 22 bit wide input word, however the
LSB is always high, and is clocked by the XTAL oscillator. This determines the
achievable frequency resolution.
The Automatic Frequency Control Unit filters the actual frequency offset from the FSK
demodulator data and calculates the necessary correction of the divider factor to achieve
the nominal IF center frequency.
Data Sheet
26
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.6
ASK and FSK Demodulator
B = 50..300kHz
channel filter FM limiter
image suppression /
band limitation (noise)
FSK
PPF2
BP
2nd
conversion
33 / 46 / 65 / 93 / 132 /
190 / 239 / 282 kHz
(2sided PDF BW)
RSSI
FSK
demodulator
FSK
demodulator
AFC track/freeze
AFC
loop filter
RF PLL ctrl
FSK/ASK
Rate adapter
Demodulated
Data
Bypass
Rate doubler
Decimation
8 … 16 samples /chip
(data rate dependent )
Temp
VDDD/2
Mux
ADC
RSSI Slope
RSSI Offset
Dig. Gain
Control
Peak Memory
Filter
delog
ASK
buffer
Div
fSystem
RSSI
AGC
RSSI Peak
Detector
register
RSSIPMF
register
RSSIPWU
(internal
signal)
Begin of config /
channel ,
x*WULOT
Figure 10
Analog Gain Control
RSSIPWU
register
End of config/
channel
>
WU event
TH, BL, BH
Functional Block Diagram ASK/FSK Demodulator
The IC comprises two separate demodulators for ASK and FSK.
After combining FSK and ASK data path, a sampling rate adaptation follows to meet an
output oversampling between 8 and 16 samples per chip. Finally, an oversampling of 8
samples per chip can be achieved using a fractional sample rate converter (SRC) with
linear interpolation (for further details see Figure 15).
2.4.6.1
ASK Demodulator
The RSSI generator delivers a DC signal proportional to the applied input power at a
logarithmic scale (dBm) and is also used as an ASK demodulator. Via a programmable
anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit ADC.
For the AM demodulation a signal proportional to the linear power is required. Therefore
a conversion from logarithmic scale to linear scale is necessary. This is done in the digital
domain by a nonlinear filter together with an exponential function. The analog RSSI
signal after the anti-aliasing filter is available at the RSSI pin via a buffer amplifier. To
enable this buffer the SFR control bit RSSIMONEN must be set. The anti-aliasing filter
can be by-passed for visualization on the RSSI pin (see AAFBYP control bit).
Data Sheet
27
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.6.2
FSK Demodulator
The limiter output signal, which has a constant amplitude over a wide range of the input
signal, feeds the FSK demodulator. There is a configurable lowpass filter in front of the
FSK demodulation to suppress the down conversion image and noise/limiter harmonics
(FSK Pre-Demodulation Filter, PDF). This is realized as a 3rd order digital filter. The
sampling rate after FSK demodulation is fixed and independent from the target data rate.
2.4.6.3
Automatic Frequency Control Unit (AFC)
In front of the image suppression filter a second FSK demodulator is used to derive the
control signal for the Automatic Frequency Control Unit, which is actually the DC
value of the FSK demodulated signal. This makes the AFC loop independent from signal
path filtering and allow so a wider frequency capture range of the AFC. The derivation of
the AFC control signal is preferably done during the DC free preamble and is then frozen
for the rest of the datagram.
Since the digital FSK demodulator determines the exact frequency offset between the
received input frequency and the programmed input center frequency of the receiver,
this offset can be corrected through the sigma delta control of the PLL. As shown in
Figure 10, for AFC purposes a parallel demodulation path is implemented. This path
does not contain the digital low pass filter (PDF, Pre-Demodulation Filter). The entire IF
bandwidth, filtered by the analog bandpass filter only, is processed by the AFC
demodulator.
There are two options for the active time of the AFC loop:
•
•
1. always on
2. active for a programmable time relative to a signal identification event (several
options can be programmed in SFR).
In the latter case the AFC can either be started or frozen relative to the signal
identification. After the active time the offset for the sigma-delta PLL (SD PLL) is frozen.
The programming of the active time is especially necessary in case the expected frame
structure contains a gap (noise) between wake-up and payload in order to avoid the AFC
from drifting.
AFC works both for FSK and ASK. In the latter case the AFC loop only regulates during
ASK data = high.
The maximum frequency offset generated by the AFC can be limited by means of the
x_AFCLIMIT register. This limit can be used to avoid the AFC from drifting in the
presence of interferers or when no RF input signal is available (AFC wander). A
maximum AFC limit of 42 kHz is recommended. AFC wandering needs to be kept in mind
especially when using Run Mode Slave.
Data Sheet
28
V1.0, 2010-02-19
TDA5235
Functional Description
K1 = integrator1 gain
x_AFCLIMIT
x_AFCK1CFG0/1
integrator 1
K1
x16
limit
+
AFC Demod out
integrator 2
hold
K2
x4
limit
SDPLL
scaling &
limiting
FreqOffset
HOLD
hold
Freeze* / Track
Delay
x_AFCK2CFG0/1
x_AFCAGCD
K2 = integrator 2 gain
Figure 11
AFC Loop Filter (I-PI Filtering and Mapping)
The bandwidth (and thus settling time) of the loop is programmed by means of the
integrator gain coefficients K1 and K2 (x_AFCK1CFG and x_AFCK2CFG register).
K1 mainly determines the bandwidth. K2 influences the dynamics/damping (overshoot)
- smaller K2 means smaller overshoot, but slower dynamics. The bandwidth of the AFC
loop is approximately 1.3*K1.
To avoid residual FM, limiting the AFC BW to 1/20 ~ 1/40 of the bit rate is suggested,
therefore K1 must be set to approximately 1/50 ~ 1/100 of the bit rate. For most
applications K2 can be set equal to K1 (overshoot is then PMFDN = 2^-round(ln(2bit/2kbps*274kHz)/ln(2))/PMFUP = 2^-round(8.1)/2^-4 = 2^-4
Note: In case of ASK with large modulation index the attack time (PMFUP) can be up to
a factor 2 slower due to the fact that the ASK signal has a duty cycle of 50% - during the
ASK low duration the integrator is actually slightly discharged due to the decay set by
PMFDN.
The AGC start and freeze times are programmable. The same conditions can be used
as in the corresponding AFC section above. They will however, be programmed in
separate SFR registers.
Data Sheet
33
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.6.5
Analog to Digital Converter (ADC)
In front of the AD converter there is a multiplexer so that also temperature and VDDD
can be measured (see Figure 10).
The default value of the ADC-MUX is RSSI (register ADCINSEL: 000 for RSSI; 001 for
Temperature; 010 for VDDD/2).
After switching ADC-MUX to a value other than RSSI in SLEEP Mode, the internal
references are activated and this ADC start-up lasts 100µs. So after this ADC start-up
time the readout measurements may begin. The chip stays in this mode until
reconfiguration of register ADCINSEL to setting RSSI. However, it is recommended to
measure temperature during SLEEP mode (This is also valid for VDDD).
Readout of the 10-bit ADC has to be done via ADCRESH register (the lower 2 bits in
ADCRESL register can be inconsistent and should not be used).
Typical the ADC refresh rate is 3.7 µs. Time duration between two ADC readouts has to
be at least 3.7 µs, so this is already achieved due to the maximum SPI rate (16 bit for
SPI command and address last 8µs at an SPI rate of 2MBit/s). The EOC bit (end of
conversion) indicates a successful conversion additionally. Repetition of the readout
measurement for several times is for averaging purpose.
The input voltage of the ADC is in the range of 1 .. 2 V. Therefore VDDD/2 (= 1.65 V
typical) is used to monitor VDDD.
Further details on the measurement and calibration procedure for temperature and
VDDD can be taken from the corresponding application note.
Data Sheet
34
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.7
RSSI Peak Detector
The IC possesses several digital RSSI peak level detectors. The RSSI level is averaged
over 4 samples before it is fed to any of the peak detectors. This prevents the evaluated
peak values to be dominated by single noise peaks.
f sys
EOM
ADC Sampling
Clock Generation
Compare
Update
Update
Peak Detector
Payload
Peak
Value
Peak Value
Register
RSSIPPL
Load
Divide
by 4
fADC
Integrate
A
from
RSSI
Generator
RSSI Slope
D
FSYNC
Bit
position
Dump
RSSI
I&D Averaging Filter
RSSI Offset
Peak
Detector
Track
Control
fADC/4
Compare
Update
Peak Detector
PeakValue
RSSIPRX
Load
to
ASK path
RX_RUN
&
Read Access to
Register RSSIPRX
from
FSM
from
SPI Controller
RSSIRX
Figure 13
Peak Detector Unit
Peak Detector Payload is used to measure the input signal power of a received and
accepted data telegram. It is read via SFR RSSIPPL.
Observation of the RSSI signal starts at the detection of a TSI (FSYNC) and ends with
the detection of EOM. The internal RSSIPPL value is cleared after FSYNC. The
evaluated RSSI peak level RSSIPPL is transferred to the RSSIPPL register at EOM.
Starting the observation of the RSSI level can be delayed by a selectable number of data
bits and is controlled by the register x_PKBITPOS. A latency in the generation of FSYNC
and EOM of approx. 2..3 bits in relation to the contents of the Peak Detector must be
considered. Within the boundaries described, the register RSSIPPL always contains the
peak value of the last completely received data telegram. The register RSSIPPL is reset
to 0 at power up reset only.
Peak Detector is used to measure RSSI independent of a data transfer and to digitally
trim RSSI. It is read via SFR RSSIPRX.
Observation of the RSSI signal is active whenever the RX_RUN signal is high. The
RSSIPRX register is refreshed and the Peak Detector is reset after every read access to
RSSIPRX.
It may be required to read RSSIPRX twice to obtain the required result. This is because,
for example, during a trim procedure in which the input signal power is reduced, after
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
reading RSSIPRX, the peak detector will still hold the higher RSSI level. After reading
RSSIPRX the lower RSSI level is loaded into the Peak Detector and can be read by
reading RSSIPRX again.
Register RSSIPRX should not be read-out faster than 41µs in case AGC is ON (as
register value would not represent the actual, but a lower value).
When the RX_RUN signal is inactive, a read access has no influence to the peak
detector value. The register RSSIPRX is reset to 0 at power up reset.
Peak Detector Wake-Up RSSIPWU (see Figure 10) is used to measure the input signal
power during Wake-Up search. The internal signal RSSIPWU gets initialized to 0 at start
of the first observation time window at the beginning of each configuration. The peak
value of this signal is tracked during Wake-Up search.
In case of a Wake-Up, the actual peak value is written in the RSSIPWU register. Even
in case no Wake-Up occurred, actual peak value is written in the RSSIPWU register at
the end of the actual configuration of the Self Polling period. So if no Wake-Up occurred,
then the RSSIPWU register contains the peak value of the last configuration of the Self
Polling period, even in a Multi-Configuration setup. This functionality can be used to track
RSSI during unsuccessful Wake-Up search due to no input signal or due to blocking
RSSI detection.
For further details please refer to Chapter 2.4.8.5 Wake-Up Generator and
Chapter 2.6.2 Polling Timer Unit.
Input
Data Pattern
Noise
Run-In
....
TSI D0 D1
Dn
Dn Dn Dn
Dn
-1
+1 +2 +3
....
EOM
Noise
Run-In
TSI D0 D1
....
SPI read out
RSSIPPL&RSSIPRX
internal RSSIPPL
RSSIPPL Register
internal RSSI
FSYNC clears the
internal RSSIPPL
internal RSSIPRX =
RSSIPRX Register
internal RSSI
*1
Reset
*1
FSync
n = PKBITPOS
*1
*1
SPI
EOM
FSync
*1 Computation Delay due to filtering and signal calculation.
Figure 14
Data Sheet
Peak Detector Behavior
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Functional Description
Recommended Digital Trimming Procedure
•
•
•
•
•
•
•
•
•
•
Download configuration file (Run Mode Slave; RSSISLOPE, RSSIOFFS set to
default, i.e. RSSISLOPE=1, RSSIOFFS=0)
Turn off AGC (AGCSTART=0) and set gain to AGCGAIN=0
Apply PIN1 = -85 dBm RF input signal
Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM1
Apply PIN2 = -65 dBm RF input signal
Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM2
Calculate measured RSSI slope SLOPEM=(RSSIM2-RSSIM1)/(PIN2-PIN1)
Adjust RSSISLOPE for required RSSI slope SLOPER as follows:
RSSISLOPE=SLOPER/SLOPEM
Adjust RSSIOFFS for required value RSSIR2 at PIN2 as follows:
RSSIOFFS=(RSSIR2-RSSIM2)+(SLOPEM-SLOPER)*PIN2
The new values for RSSISLOPE and RSSIOFFS have to be added to the
configuration!
Notes:
1. The upper RF input level must stay well below the saturation level of the receiver (see
Chapter 2.4.6.4 Digital Automatic Gain Control Unit (AGC))
2. The lower RF input level must stay well above the noise level of the receiver
3. If IF Attenuation is trimmed, this has to be done before trimming of RSSI
4. If RSSI needs to be trimmed in a higher input power range the AGCGAIN must be set
accordingly
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
2.4.8
Digital Baseband (DBB) Receiver
Blind Sync
Initial Phase & Data rate
FSK
detector
CR PLL
Slicer
CDR PLL
sync
chip_data_clock
adjust_length
CH_STR
SRC
bypass
8 to 16
samples
per chip
Matched Filter
fractional SRC
From ASK/
FSK
Demodulator
Signal
Detector
Data
Slicer
Chip Data
Decoder
Chip
Data
Invert
chip_data
CH_DATA
fs out / fs in = 0.5 … 1.0
CHIPDINV
MUX
RAW Data Slicer
for external
processing
Decoder
SIGN
Data
Invert
DINVEXT
DATA
(Sliced RAW Data for
external processing )
Figure 15
Framer
(TSI Detector)
WU Unit
Data
Invert
data_clk
data
eom
fsync
FIFO
wakeup
RXSTR RXD
DATA_MATCHFIL
(Matched Filtered Data
for external processing )
Functional Block Diagram Digital Baseband Receiver
The digital baseband receiver comprises a matched data filter, a clock and data
recovery, a data slicer, a line decoder, a wake-up generator, a frame synchronization
and a data FIFO. The recovered data and clock signals are accessible via 2 separate
pins. The FIFO data buffer is accessible via the SPI bus interface.
2.4.8.1
Data Filter and Signal Detection
The data filter is a matched filter (MF). The frequency response of a matched filter has
ideally the same shape as the power spectral density (PSD) of the originally transmitted
signal, therefore the signal-to-noise ratio (SNR) at the output of the matched filter
becomes maximum. The input sampling rate of the baseband receiver has to be
between 8 and 16 samples per chip. The oversampling factor within this range is
depending on the data rate (see Figure 10). The MF has to be adjusted accordingly to
this oversampling. After the MF a fractional sample rate converter (SRC) is applied using
linear interpolation. Depending on the data rate decimation is adjusted within the range
1...2. Finally, at the output of the fractional SRC the sampling rate is adjusted to 8
samples per chip for further processing.
To distinguish whether the incoming signal is really a signal or only noise adequate
detectors for ASK and FSK are built in.
Data Sheet
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TDA5235
Functional Description
Signal and Noise Detector
The Signal Detector decides between acceptable and unacceptable data (e.g. noise).
This decision is taken by comparing the signal power of the actually received data
(register SPWR) with a configurable threshold level (registers x_SIGDET0/1), which
must be evaluated. In case the actual signal power is above the threshold, acceptable
data has been detected.
To decide in case of FSK whether there is a data signal or simply noise at the output of
the rate adapter, there is a Noise Detector implemented. The principle is based on a
power measurement of the demodulated signal. The current noise power is stored in the
NPWR register and is updated at every SPI controller access. The Noise Detector is
useful if data signal is transmitted with small FSK deviations. In case the current noise
power (register NPWR) is below the configurable threshold (register x_NDTHRES), a
data signal has been detected.
The Signal Recognition mode must be configured based on whether ASK or FSK
modulation is used. Signal Recognition can be a combination of Signal Detector and
Noise Detector:
•
Signal Detector (=Squelch) only (related registers: x_SIGDET0, x_SIGDET1 and
SPWR). This mode is generally used for ASK and recommended for FSK.
• Noise Detector only (related registers: x_NDTHRES and NPWR).
• Signal and Noise Detector simultaneously.
• Signal and Noise Detector simultaneously, but the FSK noise detect signal is valid
only if the x_SIGDETLO threshold is exceeded. This is the recommended FSK mode,
if minimum FSK deviation is not sufficient to use Signal Detector only.
Signal Recognition can also be used as Wake-up on Level criterion (see
Chapter 2.4.8.5).
Figure 16 shows the system characteristics to consider in choosing the best Signal
Detector level. On the one hand, a higher SIGDET threshold level must be set for
achieving good FAR (False Alarm Rate) performance, but then the MER/BER (Message
Error Rate/Bit Error Rate) performance will decrease. On the other hand, the MER/BER
performance can be increased by setting smaller SIGDET threshold levels but then the
FAR performance will worsen.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
input data
telegram
signal pow er
better FAR
performance
SD TH R level area
better
MER/BER
performance
high SD THR level
low SD TH R level
Figure 16
Signal Detector Threshold Level
Quick Procedure to Determine Signal and Noise Detector Thresholds
Preparation
A setup is required with original RF hardware as in the final application. The values of
SPWR and NPWR can be read via the final application.
A complete configuration file using right modulation, data rate and Run Mode Slave,
must be prepared and downloaded to the TDA5235.
Signal Detector Threshold for ASK
Take 500 readings of SPWR (50 are also possible, but this leads to less accurate results)
with no RF input signal applied (=noise only). Calculate average and Standard Deviation.
Signal Detector Threshold is average plus 2 times the Standard Deviation. To load the
x_SIGDET0/1 register the calculated value must be rounded and converted to
hexadecimals. For a final application, the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Signal and Noise Detector Thresholds for FSK
Signal Detector Threshold
Do 500 (50) readings of SPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Signal Detector Threshold is average plus 2 times the
Standard Deviation. Of course this value has to be rounded and converted to
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
hexadecimals. For a final application the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Verification if Squelch only is possible
Apply a bit pattern (e.g. PRBS9) with correct data rate at about -80 dBm input signal
power and minimum FSK deviation to the RF input. Do 500 (50) readings of SPWR,
calculate average minus three times the Standard Deviation. This value should be higher
than the calculated Signal Detector Threshold calculated above. If this is not the case,
Signal Detector AND Noise Detector must be used.
Noise Detector Threshold
Do 500 (50) readings of NPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Noise Detector Threshold is average minus the
Standard Deviation. Round this value and convert it to hexadecimals. For a final
application, the Noise Detector Threshold should be varied to optimize false alarm rate
and sensitivity.
Signal Detector Low Threshold
The Signal Detector Low Threshold is always required in combination with the Noise
Detector.
Set register bit SDLORE to 1 and set bit group SDLORSEL to 00. Apply a bit pattern (e.g.
PRBS9) at correct data rate at about -80 dBm input signal power and minimum FSK
deviation to the RF input. Do 500 (50) readings of SPWR, calculate average. If average
is larger than 200 dec (=0xC8), SDLORSEL has to be increased to the next larger value
until average is smaller than 200 dec. x_SIGDETLO = 0.8 * (average - 3 * Standard
Deviation). Set register SDLORE back to 0. The last setting of bit group SDLORSEL
must also be used for configuration!
Verification
Threshold settings should be verified by testing receiver sensitivity over the input
frequency range, with a step size of 100Hz, at minimum FSK deviation with all
combinations of minimum and maximum data rate and duty cycle.
Further detailed information can be taken from the corresponding Application Note.
Data Sheet
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TDA5235
Functional Description
2.4.8.2
Encoding Modes
The IC supports the following Bi-phase encodings:
•
•
•
•
Manchester code
Differential Manchester code
Bi-phase space code
Bi-phase mark code
The encoding mode is set and enabled by bit group CODE in x_DIGRXC configuration
register.
Data
1
0
1
0
0
1
1
0
Clock
Manchester
Differential Manchester
Biphase Space
Biphase Mark
Figure 17
Coding Schemes
The encoding modes Inverted Manchester and Inverted Differential Manchester can also
be decoded internally by usage of CHIPDINV bit in x_DIGRXC register (see Figure 15).
All the Manchester symbol combinations including Code Violations are shown in
Figure 18. Digital 0 and 1 are coded with the change of the amplitude in the middle of
the symbol period. The Code Violations (CV) M (mark) and S (space), are coded as
low/high signal levels.
Figure 18
Data Sheet
0
1
S
M
1st 2nd
Chip Chip
1st 2nd
Chip Chip
1st 2nd
Chip Chip
1st 2nd
Chip Chip
Manchester Symbols including Code Violations
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TDA5235
Functional Description
2.4.8.3
Clock and Data Recovery
CDRDRTHRN
CDRDRTHRP
x_CDRRI
x_CDRTOLB
x_CDRTOLC
An all-digital PLL (ADPLL) recovers the data clock from the incoming data stream. The
second main function is the generation of a signal indicating symbol synchronization.
Synchronization on the incoming data stream generally occurs within the first 4 bits of a
telegram.
Tnom / 16
EOM
from Clock
Recovery Slicer
Symbol
Sync found
Timing Extrapolation
Phase
Detector
PI
Loop Filter
Digital
Controlled
Oscillator
Tnom / 2
x_TSIGAP
(GAPVAL)
x_CDRI
x_CDRP
x_TSIMODE
(TSIGRSYN)
Tnom / 2
x_TVWIN
Figure 19
Recovered
Clock
Clock Recovery (ADPLL)
Clock Recovery is implemented as standard ADPLL PI regulator with Timing
Extrapolation Unit for fast settling.
In the unlocked state, the Timing Extrapolation Unit calculates the frequency offset for
the incoming data stream. If the defined number of Bi-phase encoded bits are detected
(the RUNIN length can be set in the x_CDRRI register), the I-part and the PLL oscillator
will be set and the PLL will be locked.
When x_CDRRI.RUNLEN is set to small values, then the I-part is less accurate (residual
error) and can lead to a longer needed PLL settling time and worse performance in the
Data Sheet
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TDA5235
Functional Description
first following bits. Therefore the selected default value is a good compromise between
fast symbol synchronization and accuracy/performance.
Duty cycle and data rate acceptance limits are adjustable via registers. After locking, the
clock must be stable and must follow the reference input. Therefore, a rapid settling
procedure (Timing Extrapolation Unit) and a slow PLL are implemented.
If the PLL is locked, the reference signal from the Clock Recovery Slicer is used in the
phase detector block to compute the actual error. The error is used in the PI loop filter to
set the digital controlled oscillator running frequency. For the P, I and Timing
Extrapolation Unit settings, the default values for the x_CDRP and x_CDRI control
registers are recommended.
The PLL will be unlocked, if a code violation of more than the defined length is detected,
which is set in the x_TVWIN control register. Another criterion for PLL resynchronization
is an End Of Message (EOM) signalled by the Framer block.
The PLL oscillator generates the chip clock (2 * fdata).
The internal PLL lock signal used by the Framer is generated up to 1 bit before RUNIN
ends. The Timing Extrapolation Unit counts the incoming edges and interprets the delay
between two edges as a bit or a chip. Due to the fact that the first edge of a “Low” bit,
coded as ’0’ and ’1’, rises one chip later than a “High” bit, the PLL locks later in this case
(see Figure 20). The real needed RUNIN time can be shorter than the configured
RUNIN length in the x_CDRRI register by up to two chips. This should be considered
when setting the TSI pattern and/or TSI length. See also Chapter 2.4.8.6 Frame
Synchronization.
first edge
RUNIN
1
0
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
4 bits detected
first edge
RUNIN
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
4 bits detected
Figure 20
RUNIN Generation Principle
Data Sheet
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TDA5235
Functional Description
Number of Required RUNIN Bits
The number of RUNIN bits specified in x_CDRRI register should always be 3.0. This
setting defines the duration of the internal synchronization. Because of internal
processing delays, the pattern length that must be reserved for RUNIN is longer.
The ideal RUNIN pattern is a series of either Manchester 1’s or Manchester 0’s. This
pattern includes the highest number of edges that can be used for synchronization. In
this case, the number of physically sent RUNIN bits is 4.
For any other RUNIN pattern, 5.5 bits should be reserved for RUNIN.
TVWIN (Timing Violation WINdow length)
The PLL unlocks if the reference signal is lost for more than the time defined in the
x_TVWIN register. During the TSI Gap (see TSI Gap Mode in Chapter 2.4.8.6 Frame
Synchronization), the PLL and the TVWIN are frozen.
TVWIN time is the time during which the Digital Baseband Receiver should stay locked
without any incoming signal edges detected. The time resolution is T/16.
Calculation of TVWIN can be seen at the end of subsection TSI Gap Mode in
Chapter 2.4.8.6 Frame Synchronization.
Data Sheet
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TDA5235
Functional Description
Duty Cycle Variation
Ideally, the input signal to the Clock and Data Recovery (CDR) would have a chip width
of 8 samples and a bit width of 16 samples and the CDR would not lock onto any input
that violates this. However, due to variations in the duty cycle this stringent assumption
for the pulse widths will in general not be true. Therefore it is necessary to loosen this
requirement by using tolerance windows.
TOLCHIPH
TOLBITH
TOLCHIPL
TOLBITL
1
t
lim_chip_low = 8 - TOLCHIPL
lim_bit_low = 16 - TOLBITL
lim_chip_high = 8 + TOLCHIPH
Figure 21
lim_bit_high = 16 + TOLBITH
Definition of Tolerance Windows for the CDR
There exist now two registers - x_CDRTOLC for the chip width tolerance and
x_CDRTOLB for the bit width tolerance - that can be used to tighten or loosen the
windows around the ideal pulse widths. As it can easily be seen from Figure 21, tighter
windows will result in more stringent requirements for the input data to have a 50% duty
cycle and bigger windows will allow the duty cycle to vary more. Figure 21 also depicts
the meaning of the bits in the registers x_CDRTOLC and x_CDRTOLB.
Data Sheet
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TDA5235
Functional Description
Data Rate Acceptance Limitation
The Clock and Data Recovery is able to accept data rate errors of more than +/-15% with
a certain loss of performance. There exist Multi-Configuration applications where the
data rate of both configurations are within this range. So the adjacent data rates of these
configurations are disturbing each other. The limitation of the data rate acceptance can
be activated in this case.
clock recovery
slicer
CLOCK RECOVERY
symbol synchronization
Data Rate
Acceptance
Limitation
&
preset value correlator
cdr_lock
Clock Recovery PLL
Figure 22
cdr_clock
Data Rate Acceptance Limitation
The clock and data recovery (CDR) regenerates the clock based on the input data
delivered from the clock recovery (CR) slicer. Symbol synchronization (cdr_lock) is
achieved when a specified number of chips (can be set via register x_CDRRI.RUNLEN)
has a valid pulse width. In parallel the preset value correlator estimates a preset value
for the clock recovery PLL so that a shorter settling time is achieved. This preset value
is also proportional to the data rate and is therefore used in the data rate acceptance
limitation block. If the preset value is outside a certain range (positive and negative
threshold configurable via registers CDRDRTHRP and CDRDRTHRN), the CDR does
not go into lock and no symbol synchronization is generated.
For each configuration there exists one bit (register x_CDRRI.DRLIMEN) to switch the
data rate acceptance limitation functionality on or off. Data rate acceptance limitation is
disabled by default. All configurations share the same threshold registers, the default
Data Sheet
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TDA5235
Functional Description
thresholds are set so that almost all packets with a data rate error of +/-10% and larger
are rejected.
The following statements summarize some important aspects that need to be kept in
mind when using the described functionality:
•
•
•
•
•
The output of the estimator must be described on statistical terms - this means that
it can not be guaranteed that all packets with a certain data rate outside the allowed
range will be rejected
The quality of the estimated data rate value is mainly influenced by the setting of the
signal and noise detectors
Reducing the RUNIN length in register x_CDRRI reduces the quality of the data rate
estimation, resulting in a degradation of the performance of the data rate acceptance
limitation block
The same threshold can be used for FSK and ASK
If the thresholds are too small it may happen that also packets with a valid data rate
are rejected
2.4.8.4
Data Slicer and Line Decoding
The output signal of the matched filter within the internal data processing path is in the
range of +x to -x (x is the maximum value of the internal bit width). If Code Violations
within a Manchester encoded bitstream have to be detected, the data slicer has to
recover the underlying chipstream instead of the bitstream. In this case zero values at
the matched filter output lead to an additional slicing threshold and an implicit sensitivity
loss. To provide the full reachable sensitivity for applications which do not need the
symbols S (space) and M (mark), the data slicer has two different operating modes:
•
•
Chip mode (Code Violations are allowed)
Bit mode (without Code Violations)
The chip mode introduces an implicit sensitivity loss compared to the bit mode, because
a zero-crossing in the 2-chip matched filter signal must be detectable. This is only
possible when an additional slicing level is introduced in the data slicer.
The data slicer internally maps a positive value to a 1 and a negative value to a -1.
Everything inside the zero thresholds (zero-tube) becomes a 0. After that, the decoding
to the chip-level representation is done by mapping the -1 to a "0" chip and the 1 to a "1"
chip. A zero out of the data slicer is decoded to chip-level by referencing to the previous
chip value.
Data Sheet
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TDA5235
Functional Description
In bit mode the data slicer has only one threshold (zero) to distinguish between the two
levels of the matched filter output. The data slicer internally maps a positive value to a 1
and a negative value to a -1. After that, the selected line decoding is applied.
Summary of data slicer modes in the TDA5235:
Data Slicer Chip mode:
•
•
•
Code violations detectable (TSI, or EOM)
Performance loss compared to bit mode
Activation via setting register x_SLCCFG to a value of
+ 0x90 (Chip Mode EOM-CV: For patterns with code violations in data packet and
optimized for activated EOM code violation criterion (and optional EOM data
length criterion))
+ 0x94 (Chip Mode EOM-Data length: For patterns with code violations in data
packet and optimized for activated EOM data length criterion only)
+ 0x95 (Chip Mode Transparent: When Framer is not used, but CH_DATA /
CH_STR are used for data processing)
Data Slicer Bit mode:
•
•
•
•
No code violations detectable
Full performance
In case of Bi-phase mark and Bi-phase space an additional bit must be sent to ensure
correct decoding of the last bit
Activation via setting register x_SLCCFG to a value of 0x75
In Data Slicer Bit mode an even number of TSI chips needs to be used.
When Data Slicer Bit mode is selected, then the the last chip of RUNIN must be different
from first chip of TSI (e.g. Runin-bit sequence 000000 and TSI bit sequence 0xx...xxx is
OK). Otherwise the TSI will not be detected correctly.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied.
A line decoder decodes the incoming data chips according to the encoding scheme (see
Chapter 2.4.8.2).
Data Sheet
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TDA5235
Functional Description
2.4.8.5
Wake-Up Generator
A wake-up generation unit is used only in the Self Polling Mode for the detection of a
predefined wake-up criterion in the received pattern.
There are two groups of configurable wake-up criteria:
•
•
Wake-up on Level criteria
Wake-up on Data criteria
The search for the wake-up data criterion is started if data chip synchronization has
occurred within the predefined number of symbols, otherwise the wake-up search is
aborted. Several different wake-up patterns, like random bit, equal bit, bit pattern or bit
synchronization, are programmable.
Additional level criterion fulfilment for RSSI or Signal Recognition can lead to a fast
wake-up and to a change to Run Mode Self Polling. Whenever one of these Wake-up
Level criteria is enabled and exceeds a programmable threshold, a wake-up has been
detected.
The Wake-up Level criterion can be used very effectively in combination with the
Ultrafast Fall Back to SLEEP Mode (see Chapter 2.6.2.3) for further decreasing the
needed active time of the autonomous receive mode. A configurable observation time
for Wake-up on Level can be set in the x_WULOT register. The Wake-up on Level
criterion can be handled very quickly for FSK modulation, while in case of ASK the nature
of this modulation type has to be kept in mind.
Data Sheet
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TDA5235
Functional Description
RSSI Level
x_WURSSIBH1
Exceeding Threshold
Compare
x_WURSSIBL1
x_WURSSITH1
WU Level
Criterion
Data
x_NDCONFIG
x_SIGDET1
Wake-up on Signal
Recognition
Exceeding Threshold(s)
x_NDTHRES
x_SIGDETLO
Sync Search Time Elapsed
Sync
WU
x_WUBCNT
WUW Chip Counter
Elapsed
Wake-up Window
Chip Counter
Code Violation Detector
Bit Change Detector
Wake-up
Generation
FSM
No WU
Code Violation Detected
Bit Change Detected
3
Chip Data Clock
16-chips Shift Register
Chip Data
0
2
15
16
x_WUPAT0
Pattern Detector
Pattern Detected
x_WUPAT1
RSSI
WU on Level Criteria
Signal
Recognition
Sync
Selection
Random Bits
WU on Data Criteria
Equal Bits
Pattern
x_WUC
Figure 23
Wake-Up Generation Unit
Wake-Up on RSSI
The threshold x_WURSSITH1 is used to decide whether the actual signal is a wanted
signal or just noise. Any kind of interfering RSSI level can be blocked by using an RSSI
blocking window. This window is determined by the thresholds x_WURSSIBL1 and
Data Sheet
51
V1.0, 2010-02-19
TDA5235
Functional Description
x_WURSSIBH1. These two thresholds can be evaluated during normal operation of the
application to handle the actual interferer environment.
RSSI magnitude
The blocking window can be disabled by setting x_WURSSIBH1 to the minimum value
and x_WURSSIBL1 to the maximum value.
wanted signal
x_WURSSIBH1
interferer
x_WURSSIBL1
wanted signal
x_WURSSITH1
noise floor
Figure 24
RSSI Blocking Thresholds
Threshold evaluation procedure
A statistical noise floor evaluation using read register RSSIPMF (RMS operation) leads
to the threshold x_WURSSITH1. The interferer thresholds x_WURSSIBL1 and
x_WURSSIBH1 are disabled when they are set to their default values.
For evaluation of the interferer thresholds, either use register RSSIPMF for RMS
operation or during SPM and WU (Wake-Up) on RSSI use register RSSIPWU to
statistically evaluate the interferer band. Finally the thresholds x_WURSSIBL1 and
x_WURSSIBH1 can be set.
Wake-Up on RSSI can also be applied as additional criterion when already using a
Wake-Up on Data criterion in Constant On-Off (COO) Mode.
Further details can be seen in Figure 10, Chapter 2.4.7 RSSI Peak Detector,
Chapter 2.6.2.2 Constant On-Off Time (COO) and Chapter 2.6.2.3 Fast Fall Back to
SLEEP (FFB).
NOTE: If e.g. an interferer ends/starts too close after/to the beginning/end of the
observation time, then a decision level error can arise. This is due to the filter dynamics
(settling time). Further, for interferer thresholds evaluation in SPM this changes interferer
statistics. Several interferer measurements are recommended to suppress this, what
makes sense anyway for a better distribution.
Data Sheet
52
V1.0, 2010-02-19
TDA5235
Functional Description
Wake-Up on Signal Recognition
Instead of the previously mentioned RSSI criterion, the Signal Recognition criterion (see
Chapter 2.4.8.1) can be applied for Wake-Up search. So the x_SIGDET1, x_SIGDETLO
and x_NDTHRES threshold registers can be used.
The observation time has to be specified in the register x_WULOT. This observation time
has to contain the delay in the signal path (12.5 µs + 2.25*Tbit) and the duration for the
comparison of the Signal Recognition criterion.
The number of consecutive valid Signal Recognition samples/levels is compared vs. a
threshold defined in x_WURSSIBH1 register. Please note that x_WURSSIBH1 register
is used for both Wake-Up on RSSI and Wake-Up on Signal Recognition function. This
threshold has an influence on the false alarm rate. So x_WURSSIBH1 defines the
minimum needed consecutive T/16 samples of the Signal Recognition output to be at
high level for a positive Wake-Up event generation.
Wake-Up on Data Criterion
All SFRs configuring the Wake-up Generation Unit support the Multi-Configuration
capability. The search for a wake-up data criterion is started if symbol synchronization is
given within a certain duration (see Chapter 2.4.8.8 RUNIN, Synchronization Search
Time and Inter-Frame Time); otherwise the wake-up search is aborted. During the
observation period, the wake-up data search is aborted immediately if symbol
synchronization is lost. If this is not the case, the wake-up search will last for the number
of chips/bits defined in the register x_WUBCNT.
The Wake-up Window (WUW) Chip/Bit Counter counts the number of received chips/bits
and compares this number vs. the number of chips/bits defined in the register
x_WUBCNT.
The Code Violation Detector checks the incoming chip data stream for being Bi-Phase
coded. A Code Violation is given if three consecutive chips are ’One’ or ’Zero’.
The Bit Change Detector checks the incoming Bi-phase coded bit data stream for
changes from 'Zero' to 'One' or 'One' to 'Zero'.
The Pattern Detector searches for a pattern with 16 chips/bits length within the Wake-up
Window. The pattern is configurable via the registers x_WUPAT0 and x_WUPAT1.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied. Further details can be seen at the end of Chapter 2.4.8.4.
The selection of 1 out of 4 wake-up data criteria is done via the x_WUC register.
Data Sheet
53
V1.0, 2010-02-19
TDA5235
Functional Description
Details on the four wake-up data criteria
Pattern Detection
The incoming signal must match a dedicated pattern of up to 8 bits or 16 chips in WakeUp Pattern Chip Mode. When the WUW chip counter elapses, the search is stopped. The
higher the setting of WUBCNT the longer it is possible to search for the wake-up pattern.
The minimum for the WUBCNT is 0x11!
The pattern detection is stopped either when WUW elapses, or when symbol
synchronization is lost.
The Wake-Up pattern can be extended from 16 chips to 16 bits on activation of
WUPMSEL bit (Wake-Up Pattern Bit Mode). In this Bit Mode no Code Violations (CV)
are allowed and thus Pattern Detection is aborted, when a CV is detected.
Equal Bits Detection
Wake-up condition is fulfilled if all received bits inside of WUW are either 0 or 1.
WUBCNT holds the number of required equal bits. The higher the setting of WUBCNT
the lower the number of wrong wake-ups.
Equal bits detection is stopped if a bit change or a CV has been detected, or symbol
synchronization is lost.
Random Bits Detection
Wake-up condition is fulfilled if there is no code violation inside of WUW. WUBCNT holds
the number of required Bi-phase coded bits. The higher the setting of WUBCNT, the
lower the number of wrong wake-ups.
Random bits detection is stopped if a code violation has been detected, or symbol
synchronization is lost.
Valid Data Rate Detection
Wake-up condition is fulfilled if symbol synchronization is possible inside of Sync Search
Time out (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and InterFrame Time). WUBCNT is not used.
This is the weakest wake-up data criterion, and should be avoided.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
SSync Search Time Elapsed = 1
Reset
Init Wakeup Unit
SSync =0
Idle
WU=0
No WU=0
SSync=1
Wakeup Criteria=Pattern Detection
SSync =0
SSync=1
Wakeup Criteria=Random Bits Detection
SSync=1
Wakeup Criteria=Equal Bits Detection
WUW Chip Counter <
WUBCNT
WUW Chip Counter <
WUBCNT
Pattern Detection
Random Bits Detection
WU=0
No WU=0
WU=0
No WU=0
WUW Chip
Counter 22kBit/s) OR (EOM2SPM = 0) )
If the condition above is not fulfilled, then the chip internal state machine can set
PLDLEN to 0 and a correct function of PLDLEN cannot be guaranteed.
2.5.3
Digital Output Pins
As long as the P_ON pin is high, all digital output pins operate as described. If the P_ON
pin is low, all digital output pins are switched to high impedance mode.
The digital outputs PP0, PP1, PP2 and PP3 are configurable, where each of the signals
CLK_OUT, RX_RUN, NINT, a LOW level (GND) and a HIGH level, DATA,
DATA_MATCHFIL, CH_DATA, CH_STR, RXD and RXSTR can be routed to any of the
four output pins. There is only one exception, CLK_OUT is not available on PP3. The
default configuration for these four output pins can be seen in Table 1.
Each port pin can be inverted by usage of PPCFG2 register.
The RX_RUN signal is active high for all Configurations by default. It can be deactivated
for every Configuration separately. Every PPx can be configured with an individual
RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers.
Interfacing to 3.3V Logic:
The TDA5235 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V
environment.
Interfacing to 5V Logic:
The TDA5235 is able to interface directly to a 5V logic, when chip is operated in 5V
environment.
Data Sheet
85
V1.0, 2010-02-19
TDA5235
Functional Description
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.
2.5.4
Interrupt Generation Unit
The TDA5235 is able to signal interrupts (NINT signal) to the external Application
Controller on one of the PPx port pins (for further details see Chapter 2.5.3 Digital
Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the
NINT signal based on the configuration of the Interrupt Mask register IM0. The Interrupt
Status register IS0 is set from the Interrupt Generation Unit, depending on which
interrupt occurred. The polarity of the interrupt can be changed in the PPCFG2 register.
Please note that during power up and brownout reset, the polarity of NINT signal is
always as described in Chapter 2.4.9.2 Chip Reset.
A Reset event has the highest priority. It sets all bits in the Status register to “1” and sets
the interrupt signal to “0”. The first interrupt after the Reset event will clear the Status
register and will set the interrupt signal to “1”, even if this interrupt is masked.
A Wake-up interrupt clears the FsyncA, FsyncB and the complementary Wake-up flag.
An Fsync interrupt clears the EOMA, EOMB, MIDA, MIDB and the complementary Fsync
flag.
The Interrupt Status register is always cleared after read out via SPI.
It is not possible to disable the Power On Reset Indicator Interrupt using the Interrupt
Mask register.
Some interrupts are not usable depending on the selected receive mode, which is
described in Chapter 2.5.1.2 Data Interface.
Interrupts for WU can be used in all receive modes.
Interrupts for FSync, MID and EOM can only be used in the receive modes POTP and
POF.
Data Sheet
86
V1.0, 2010-02-19
TDA5235
Wake-up Cfg A
WUA
FSync Cfg A
FSyncA
Message ID Cfg A
MIDA
EOM Cfg A
EOMA
Wake-up Cfg B
WUB
FSyncB
FSync Cfg B
Message ID Cfg B
MIDB
EOMB
EOM Cfg B
Power-Up / Brownout
Functional Description
IS0
IM0
Interrupt-Mask
NINT
Reset
Interrupt-Signalling
NINT signal
Figure 56
Interrupt Generation Unit
RESET
PP2_select=NINT
PP2INV
SPI READ IS0
IS0
X
FF
01
03
07
0F
1C
30
70
F0
00
PP2(NINT)
WU(A,B)
FSYNC(A,B)
MID(A,B)
EOM(A,B)
ConfigA
Figure 57
Data Sheet
ConfigB
Interrupt Generation Waveform (Example for Configuration A+B)
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TDA5235
Functional Description
The following handling mechanism for read-clear registers was chosen due to
implementation of the Burst Read command:
•
•
the current Interrupt Status (ISx) register 8-bit content is latched into the SPI shift
register after the last address bit is clocked-in (point A in Figure 58)
the IS register is then cleared after last IS register bit is clocked out of the SPI
interface (point B in Figure 58)
Consequence: any interrupt event occurring in the window-time between points A and B
is cleared at point B and not stored/shown in an later readout of ISx.
(However: NINT signal is toggling in any case, if occurring interrupt is not masked in IMx
register)
A
B
8-bit @2MHz = 4us
irq1 (masked?)
irq2 (masked?)
nint
ncs
SPI IF
inst
addr
read /readb data = IS(t+0)
read/capture IS*
content
SFR IS* IS(t-1)
IS(t+0)
SFR IS* read clear
@end of data frame
IS(t+1) 0x00
NOTE:
SFR IS(j) status flag is cleared
before it can be read if an IRQ
occurs during SPI data frame
Figure 58
ISx Readout Set Clear Collision
Please see also the IMPORTANT NOTE in the Burst Read section !
Data Sheet
88
V1.0, 2010-02-19
TDA5235
Functional Description
2.5.5
Digital Control (4-wire SPI Bus)
The control interface used for device control and data transmission is a 4-wire SPI
interface.
•
•
•
•
NCS - select input, active low
SDI
- data input
SDO - data output
SCK - clock input: Data bits on SDI are read in at rising SCK edges and written out
on SDO at falling SCK edges.
Level definition:
logic 0 = low voltage level
logic 1 = high voltage level
Note for non-Burst modes: It is possible to send multiple frames while the device is
selected. It is also possible to change the access mode while the device is selected by
sending a different instruction.
Note: In all bus transfers MSB is sent first, except for the received data read from the
FIFO. There the bit order is given as first bit received is first bit transferred via the bus.
To read from the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
data byte at this address is then shifted out on SDO. After completing the read operation,
the master sets the NCS line to high.
NCS
Frame
1
8
1
Frame
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Address
Instruction
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
high impedance Z
Figure 59
Data Sheet
Register Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
Data Out
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Read Register
89
V1.0, 2010-02-19
TDA5235
Functional Description
To read from the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first), the slave unit
will respond by transferring the register contents beginning from the given start address
(MSB first). Driving the NCS line to high will end the Burst frame.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
Register Start Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out (i)
SDO
high impedance Z
Figure 60
Data Out (i+1)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
Data Out (i+x)
D0 D7 D6 D5 D4 D3 D2 D1 D0
Burst Read Registers
IMPORTANT NOTE - for being upwards compatible with further versions of the
product, we give following strong recommendation:
For read-clear registers at address (N), no read-burst access stopping at address
(N-1) is allowed, because read-clear register will be cleared without being read out.
Use single read command to read out the register at address (N-1) or extend the
burst read to include the read-clear register at address (N).
To write to the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
following data byte is then stored at this address.
After completing the writing operation, the master sets the NCS line to high.
Additionally the received address byte is stored into the register SPIAT and the received
data byte is stored into the register SPIDT. These two trace registers are readable.
Therefore, an external controller is able to check the correct address and data
transmission by reading out these two registers after each write instruction. The trace
registers are updated at every write instruction, so only the last transmission can be
checked by a read out of these two registers.
Data Sheet
90
V1.0, 2010-02-19
TDA5235
Functional Description
NCS
Frame
1
8
1
Frame
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Address
Data Byte
Instruction
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Register Address
Data Byte
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
Figure 61
Write Register
To write to the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first) the successive
data bytes will be stored into the automatically addressed registers.
To verify the SPI Burst Write transfer, the current address (start address, start address
+ 1, etc.) is stored in register SPIAT and the current data field of the frame is stored in
register SPIDT. At the end of the Burst Write frame the latest address as well as the
latest data field can be read out to verify the transfer. Note that some error in one of the
intermediate data bytes can not be detected by reading SPIDT.
Driving the NCS line to high will end the Burst frame.
A single SPI Burst Write command can be applied very efficiently for data transfer either
within a register block of configuration dependent registers or within the block of
configuration independent registers.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Start Address
Data Byte (i)
Data Byte (i+1)
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte (i+x)
D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
Figure 62
Data Sheet
Burst Write Registers
91
V1.0, 2010-02-19
TDA5235
Functional Description
The SPI also includes a safety feature by which the checksum is calculated with an
XOR operation from the address and the data when writing SFR registers. The
checksum is in fact an XOR of the data 8-bitwise after every 8 bits of the SPI write
command. The calculated checksum value is automatically written in the SPICHKSUM
register and can be compared with the expected value. After the SPICHKSUM register
is read, its value is cleared.
In case of an SPI Burst Write frame, a checksum is calculated from the SPI start address
and consecutive data fields.
enable every 8 bit
SPI shift register
Figure 63
Checksum SFR
XOR
read/clear
SPI Checksum Generation
To read the FIFO, the SPI master has to select the SPI slave unit first. Therefore, the
master must set the NCS line to low. After this, the instruction byte is shifted in on SDI
and stored in the internal instruction register. The data bits of the FIFO are then shifted
out on SDO. The following byte is a status word that contains the number of valid bits in
the data packet. After completing the read operation, the master sets the NCS line to
high.
NCS
Frame
1
8
Frame
1
32
1
8
1
8
1
32
1
8
SCK
Instruction
SDI
I7
I6
Instruction
I1
I0
I7
32 FIFO Bits
SDO
high impedance Z
D0
D1
D30
I6
I1
I0
Status Word
D31
S7
Figure 64
Read FIFO
Table 4
Instruction Set
S6
S1
32 FIFO Bits
S0
D0
D1
D30
Status Word
D31
S7
S6
S1
S0
Instruction
Description
Instruction Format
WR
Write to chip
0000 0010
RD
Read from chip
0000 0011
RDF
Read FIFO from chip
0000 0100
WRB
Write to chip in Burst mode
0000 0001
RDB
Read from chip in Burst mode 0000 0101
Data Sheet
92
V1.0, 2010-02-19
TDA5235
Functional Description
2.5.5.1
Timing Diagrams
tDeselect
NCS
tnot_hold
tSetup
tCLK_H
thold
tnot_setup
SCK
tSDI_setup
tSDI_hold
tCLK_L
SDI
high impedance Z
SDO
Figure 65
Serial Input Timing
NCS
tCLK_H
SCK
tCLK_SDO
tCLK_SDO
tCLK_L
tSDO_r
tSDO_disable
tSDO_f
Z
SDO
SDI
Z
ADDR LSB
Figure 66
Data Sheet
Serial Output Timing
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TDA5235
Functional Description
Table 5
SPI Bus Timing Parameter
Symbol
Parameter
fclock
Clock frequency
tCLK_H
Clock High time
tCLK_L
Clock Low time
tsetup
Active setup time
tnot_setup
Not active setup time
thold
Active hold time
tnot_hold
Not active hold time
tDeselect
Deselect time
tSDI_setup
SDI setup time
tSDI_hold
SDI hold time
tCLK_SDO
Clock low to SDO valid
tSDO_r
SDO rise time
tSDO_f
SDO fall time
tSDO_disable
SDO disable time
2.5.6
Chip Serial Number
Every device contains a unique, preprogrammed 32-bit wide serial number. This number
can be read out from SN3, SN2, SN1 and SN0 registers via the SPI interface. The
TDA5235 always has SN0.6 set to 1 and SN0.5 set to 0.
SN0
......
......
Fuses
FuseReadoutInterface
SN1
SN2
SN3
Figure 67
Data Sheet
Chip Serial Number
94
V1.0, 2010-02-19
TDA5235
Functional Description
2.6
System Management Unit (SMU)
The System Management Unit consists of two main units:
•
•
Master Control Unit, where the various operating modes can be configured.
Polling Timer Unit, where the receiver’s On and Off times and modes are defined.
The Polling Timer Unit is only working in the Self Polling Mode.
2.6.1
Master Control Unit (MCU)
2.6.1.1
Overview
The Master Control Unit controls the operation modes, the global states, and is generally
responsible for automating data reception, verification, identification, extraction, and
storage into the FIFO. The payload data without RUNIN, TSI and optional EOM can be
read from the FIFO via SPI by the external microcontroller.
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
The following operation modes and the behavior of the Master Control Unit are fully
automatic and only influenced by SFR settings and by incoming RF data streams.
The TDA5235 has two major operation modes, which are switched by SFR bit MSEL.
In Slave Mode the device is controlled via SPI by the external microcontroller. This mode
supports:
•
•
•
Run Mode Slave (RMS), where the receiver is continuously active
SLEEP Mode, where the receiver is switched off for power saving. This mode can
also be used to change register settings
HOLD Mode, allows register settings to be changed. The change to HOLD Mode and
back to RMS is faster than changing to SLEEP Mode and back to RMS.
In Slave Mode, switching between configurations, as well as between Run and SLEEP
Mode must be initiated by the microcontroller.
In Self Polling Mode, TDA5235 autonomously polls for incoming RF signals. The
receiver switches automatically between up to two configurations (Configuration A and
B). Further information can be found in Chapter 2.6.2.
Between the RF signal scans, the receiver is automatically switched to Low Power Mode
for reducing the average power consumption. If an incoming signal fulfills the selected
wake-up criterion an interrupt can be generated and Run Mode Self Polling will be
entered. If the following received data matches to the TSI pattern, and passes the
optional message ID screening, the payload is loaded into the FIFO, and, if not masked,
an interrupt is generated. Then the payload data can be read via SPI.
Data Sheet
95
V1.0, 2010-02-19
TDA5235
Functional Description
Init
Reset
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Sleep Mode
Initialize RX-Part
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Chip is idle
Bit:SLRXEN == 1
Bit:MSEL == 0
Run Mode
Slave
Bit:SLRXEN == 1
Bit:MSEL == 0
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout == X
Self Polling
Mode
Bit:SLRXEN == X
Bit:MSEL == 1
EOM2SPM == 1
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 1
Run Mode
Self Polling
Chip is permanently
active
Figure 68
2.6.1.2
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Global State Diagram
Run Mode Slave (RMS)
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake-up criterion are not performed, but RUNIN and TSI
are required.
Recognition of TSI and validation of the optional MID (Message IDentification) are done
automatically. The data payload is extracted from the data stream, and moved to the
FIFO.
The various recognition steps are communicated by interrupts. Interrupts can be
generated at frame-start (when a valid TSI has been detected), when a valid MID has
been found and at EOM (End of Message).
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Data Sheet
96
V1.0, 2010-02-19
TDA5235
Functional Description
Configurations are switched via SFR bit MCS in the CMC0 register. The RF channel can
be selected by SFRs x_PLLINTC1, x_PLLFRAC0C1, x_PLLFRAC1C1,
x_PLLFRAC2C1, where x = A or B.
The configuration may be changed only in SLEEP or in HOLD Mode before returning to
the previously selected operation mode. This is necessary to restart the state machine
with defined settings at a defined state. Otherwise the state machine may hang up.
Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence.
The following flowchart and explanation show and help to understand the internal
behavior of the Finite State Machine (FSM) in Run Mode Slave.
Data Sheet
97
V1.0, 2010-02-19
TDA5235
Functional Description
0
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
Startup Finished == 1
4
1
FIFO locked
Wait Till FIFO Read Out
INIT
fifolk == 1
EXTPROC==00 Init FIFO=Init FIFO@Cyc.
Symbol Sync ==0
INITDRXES==1
fifolk == 0
2
fifolk == 1
INIT
fifolk == 0
INITDRXES==1
Init Digital Receiver
Symbol Sync ==0
INITDRXES==0
3
fifolk == 0
INITDRXES==0
Symbol Sync == 0
Generating A Frame Start
Interrupt If Not Masked
Symbol Sync == 1
EXTPROC10
Hold == 0
12
5
Hold
Ready for
reconfiguration
Wait
Wait Till Symbol
Synchronization
Is Found
Wait
Frame Sync == 0
Hold == 1
Wait Till Frame Start
Is Found
Frame Sync == 1
EXTPROC==00
6
INIT FIFO
Init FIFO =
Init FIFO@FSYNC
7
Check
MID Setup
MID Screening enable == 0
Check The MID Setup
Register
MID Screening enable == 1
8
Init MID
Scanning Unit
Initialize The MID
Scanning Unit
9
MID Scanning Finished == 0
Wait
Store RX Data Into FIFO
Wait For Scan Finish
MID Scanning Finished == 1
10
MID Found == 0
Generating A MID Found
Interrupt If Not Masked
Checking ID
Scanning Result
Store RX Data Into FIFO
Analyze The Scanning
Result
Generating A EOM Interrupt If
Not Masked
MID Found=1
11
EOM Check
EOM Found == 1
Store RX Data Into FIFO
Check For EOM
EOM Found == 0
Figure 69
Data Sheet
Run Mode Slave
98
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.1.3
HOLD Mode
This state (item 12 in Figure 69) is used for fast reconfiguration of the chip in Run Mode
Slave. This state can be reached after the Start-Up Sequencer and Initialization of the
chip have been completed from any state from 3 to 11. To reconfigure the chip the SFR
control bit HOLD must be set. After reconfiguration in this state the SFR control bit HOLD
must be cleared again. After leaving the HOLD state, the INIT state is entered and the
receiver can work with the new settings. Be aware that the time between changing the
configuration and reinitialization of the chip has to be at least 40us. Take note that one
SPI command for clearing the SFR control bit HOLD needs 24 bits or 12μs at an SPI
data rate of 2.0Mbit/s. The remaining 28μs must be guaranteed by the application.
FSM State
EOM-Check
SPI Command
Instruction Address
Write
CMC0
0x02
HOLD
Data
HOLD=1
Instruction Address
Write
x_PLL...
0x02
INIT
Data
(sel. other
channel)
Instruction Address
Write
CMC0
0x02
Wait till
SSync
Data
HOLD=0
12us @ 2.0MHz
40us
Figure 70
HOLD State Behavior (INITPLLHOLD disabled)
In case of large frequency steps, an additional VAC routine (VCO Automatic Calibration)
has to be activated when recovering from HOLD Mode (INITPLLHOLD bit). The
maximum allowed frequency step in HOLD Mode without activation of VAC routine is
depending on the selected frequency band. The limits are +/- 1 MHz for the 315 MHz
band, +/- 1.5 MHz for the 434 MHz band and +/- 3 MHz for the 868/915 MHz band.
When this additional VAC routine is enabled, the TDA5235 starts initialization of the
Digital Receiver block after release from HOLD and an additional Channel Hop time.
FSM State
SPI Command
EOM-Check
Instruction Address
Write
CMC0
0x02
HOLD
Data
HOLD=1
Instruction Address
Write
x_PLL...
0x02
Data
(sel. other
channel)
VAC
Instruction Address
Write
CMC0
0x02
VAC
INIT
Wait till
SSync
Data
HOLD=0
12us @ 2.0MHz
tC _Hop
40us
Figure 71
HOLD State Behavior (INITPLLHOLD enabled)
HOLD Mode is only available in Run Mode Slave. Configuration changes in Self Polling
Mode have to be done by switching to SLEEP Mode and returning to Self Polling Mode
after reconfiguration.
Data Sheet
99
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.1.4
SLEEP Mode
The SLEEP Mode is a power save mode. The complete RF part is switched off and the
oscillator is in Low Power Mode. As in HOLD Mode, the chip can be reconfigured. When
switching from SLEEP to Run Mode Slave, the state machine starts with the internal
Start-Up Sequence.
2.6.1.5
Self Polling Mode (SPM)
In Self Polling Mode TDA5235 autonomously polls for incoming RF wake-up data
streams. There is no processing load on the host microcontroller. When a wake-up
criterion has been found, an interrupt can be generated and the TDA5235 mode is
changed to Run Mode Self Polling for automatic verification of TSI, optional MIDs and
for transfer of payload data into the FIFO.
A general overview on a typically transmitted protocol and the behaviour of the TDA5235
is given in Figure 72.
TX - RX interaction in RX - Self Polling Mode
TX Telegram:
Wake-up Frame
Wake-up Frame continued or Gap
RUNIN + Wake-up sequence
1)
Data Frame
(RUNIN)
TSI
PAYLOAD
EOM
RX Mode:
On time 2)
Self Polling Mode
On time 2)
Self Polling Mode
a
b
Run Mode Self Polling
Legend:
1) There can either be a Wake -up Frame directly followed by a Data Frame or the Wake -up Frame is separated from the Data Frame by a Gap in -between .
2) The position of the O n time can vary (a, b, ...) as there is no synchronization between transmitted telegram and start of the receiver’s On time.
Figure 72
SPM - TX-RX Interaction
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Self Polling Mode is entered by setting the MSEL register bit to 1.
Configuration changes are allowed only by switching to SLEEP Mode, and returning to
Self Polling Mode after reconfiguration.
Data Sheet
100
V1.0, 2010-02-19
TDA5235
Functional Description
The Polling Timer Unit controls the timing for scanning (On time) and sleeping (Off
time, SPM_OFF). Up to two independent configuration sets (A and B) can automatically
be processed, thus enabling scanning from different transmit sources. See also
Chapter 2.6.2 Polling Timer Unit.
The Wake-Up Generation Unit identifies, whether an incoming data stream matches
the configurable wake-up criterion.
After fulfillment of the wake-up criterion, modulation can be switched automatically.
See also Chapter 2.6.1.6 Automatic Modulation Switching, Chapter 2.4.8.5 WakeUp Generator and Chapter 2.5.1.2 Data Interface (in Subsection TMRDS).
The following state diagrams and explanations help to illustrate the behavior during Self
Polling Mode. First there is a search for a wake-up criterion according to Configuration
A. Then, there is an optional search for a wake-up criterion according to Configuration B.
In applications using only Single-Configuration, settings are always taken from
Configuration A.
Data Sheet
101
V1.0, 2010-02-19
TDA5235
Functional Description
RX_RUN=0
RX_RUN == 0
1
IDLE
Permanent WU Search Mode Enable == 0
Chip is idle
RX_RUN == 1
2
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
From Run Mode Self Polling
Startup Finished == 1
Init
Loop Counter
3
Permanent WU Search Mode Enable == 1
CfgLoopCounter
is Initialized
WU Search With
Configuration A
Modulation
Switching CFG A
4
Modulation Selection
Depending On Register
Setting
Init With
CFG A
5
Initialize RX- Part
Configuration A
Permanent WU Search Mode Enable == 0
Const On Time
Fast Fall Back To Sleep
7
ON Time elapsed == 0
WU Found == 0
Permanent WU Search Mode Enable == 1
7
WU Search
CFG A FFTS
WU Search
CFG A COOT
Search For A Configurated
Wake Up Criteria
Fast Fall Back
Search For A Configurated
Wake Up Criteria
Const On Off
ON Time elapsed == 1
WU Found == 0
WU Search Finished == 1
WU Found == 1
ON Time elapsed == X
WU Found == 1
WU Search Finished == 0
WU Search Finished == 1
WU Found == 0
9
Compare
Compare Loop Counter
Against Number Of
Configs
CfgLoopCounter CfgNr
CfgLoopCounter == CfgNr
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
12
Generating WU CFG A
Interrupt If Not Masked
Run Mode
Self Polling
Chip is permanently
active
To Init Loop Counter
of Config B
Figure 73
Data Sheet
From Compare of
Config B
Wake-up Search with Configuration A
102
V1.0, 2010-02-19
TDA5235
Functional Description
To Init Loop
Counter / Idle of
Config A
From Compare of
Config A
WU Search With
Configuration B
4
Modulation
Switching CFG B
Modulation Selection
Depending On Register
Setting
5
Init With
CFG B
Initialize RX-Part
Configuration B
Permanent WU Search Mode Enable == 0
Const On Time
Fast Fall Back To Sleep
7
ON Time elapsed == 0
WU Found == 0
Permanent WU Search Mode Enable == 1
7
WU Search
CFG B COOT
WU Search
CFG B FFTS
Search For A Configurated
Wake Up Criteria
Const On Off
Search For A Configurated
Wake Up Criteria
Fast Fall Back
ON Time elapsed == X
WU Found == 1
ON Time elapsed == 1
WU Found == 0
WU Search Finished == 1
WU Found == 1
WU Search Finished == 0
WU Search Finished == 1
WU Found == 0
9
Compare
Compare Loop Counter
Against Number Of
Configs
(CfgLoopCounter == CfgNr)
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
12
Generating WU CFG B
Interrupt If Not Masked
Run Mode
Self Polling
Chip is permanently
active
Figure 74
Data Sheet
Wake-up Search with Configuration B
103
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.1.6
Automatic Modulation Switching
In Self Polling Mode, the chip is able to automatically change the type of modulation
after a wake-up criterion was fulfilled in a received data stream. The type of modulation
used in the different operational modes is selected by the SFR control bit MT.
2.6.1.7
Multi-Channel in Self Polling Mode
A simple Multi-Channel behavior can be realized when the same application parameters
are programmed in both Configuration sets and only the RF PLL frequency differs.
Channel frequencies are defined in registers x_PLLINTC1, x_PLLFRAC0C1,
x_PLLFRAC1C1, x_PLLFRAC2C1, where x = A or B.
See also Chapter 2.4.5 Sigma-Delta Fractional-N PLL Block.
2.6.1.8
Run Mode Self Polling (RMSP)
The chip enters Run Mode Self Polling after a successful fulfillment of a wake-up
criterion in Self Polling Mode.
When Wake-Up criterion for RSSI or Signal Recognition (see Chapter 2.4.8.1) is
selected and fulfilled, this leads to a change to Run Mode Self Polling. This will be
interesting especially in case of a transparent data stream being processed externally by
the Application Controller (see Chapter 2.5.1.2 Data Interface).
The following steps are performed automatically, depending on register settings:
•
•
•
•
Modulation switching (see Chapter 2.6.1.6 Automatic Modulation Switching)
Wait for valid TSI (see Chapter 2.4.8.6 Frame Synchronization)
Initialize FIFO (see Chapter 2.5.2 Receive FIFO) and write data to FIFO
Scan for MIDs (see Chapter 2.4.8.7 Message ID Scanning)
Depending on interrupt masking, the host microcontroller is alerted when
•
•
•
a data frame has started,
an MID has been found, (if enabled) or
EOM (End of Message) has been detected.
See also Chapter 2.5.4 Interrupt Generation Unit
Run Mode Self Polling is left, when synchronization is lost and the timeout timer for loss
of synchronization (TOTIM_SYNC) has elapsed, or when one of the other timeout timers
(TOTIM_TSI, TOTIM_EOM) for each configuration (A, B) has elapsed, or when an EOM
occurred and the SFR bit EOM2SPM is activated, or when the operating mode is
switched to SLEEP or Run Mode Slave by the host microcontroller.
Data Sheet
104
V1.0, 2010-02-19
TDA5235
Functional Description
Timeout timers for getting no TSI or getting no EOM within a certain time period can be
used to avoid a deadlock situation, e.g. TOTIM_TSI can be used in case an interfering
transmit signal fulfilled the wake-up criterion and keeps on transmitting, but no TSI can
be found in this data stream within a certain programmable time period. TOTIM_EOM
might be used in case EOM criterion “EOM by payload data length” cannot be applied.
The timeout timer functionality in the absence/presence of an interfering signal is shown
in Figure 75 and Figure 76.
Without interfering signal:
Wake-up
RI TSI Payload1
RI TSI Payload2
EOM
TX signal
EOM
WU frame and Payload frame have the same modulation type
e.g. TOTIM_TSI is set to 15ms
RX_RUN
WU-data Interrupt
RunMode SelfPolling
SelfPolling / Sleep
Init TOTIMs
TOTIM_SYNC
counter activity
TOTIM_TSI
counter activity
9.5ms
5ms
5ms
TOTIM_EOM
counter activity
Figure 75
Data Sheet
TOTIM Behavior without Presence of Interferer
105
V1.0, 2010-02-19
TDA5235
Functional Description
With interfering signal (interferer signal has same data rate as wanted wake-up signal):
WU frame and Payload frame have the same modulation type
e.g. TOTIM_TSI is set to 15ms
RI TSI Payload1
Wake-up
RI TSI Payload2
EOM
TX signal
EOM
TX interferer
RX_RUN
WU-data Interrupt
RunMode SelfPolling
SelfPolling / Sleep
*)
Init TOTIMs
TOTIM_SYNC
counter activity
TOTIM_TSI
counter activity
15ms
TOTIM_EOM
counter activity
*) Chip proceeds with Self Polling Mode
Figure 76
TOTIM Behavior in Presence of Interferer
On expiring of one of the timeout timers, the receiver proceeds with Self Polling Mode
and with searching for a suitable wake-up criterion on the next configuration or a search
for a wake-up criterion in Configuration A is initiated.
As long as the chip is in Run Mode Self Polling, incoming data frames (including a
RUNIN sequence and TSI, but without necessity of additional wake-up patterns) can be
received and stored.
The data FIFO can be initialized and cleared either at
• Cycle Start, that means whenever Run Mode Self Polling is entered or
• Frame Start, when a TSI has been successfully identified (and Receive FIFO is not
locked).
Further information about the Receive FIFO can be found in the Chapter 2.5.2 Receive
FIFO.
After an EOM was found, the information about the RF channel and the configuration of
the actual payload data is saved in the RFPLLACC register.
Data Sheet
106
V1.0, 2010-02-19
TDA5235
Functional Description
After detection of EOM the TDA5235 can either proceed with a search for a wake-up
criterion in the next configuration or a search for wake-up in Configuration A can follow
or the TOTIMs of the current configuration are reloaded for being prepared to receive
another (redundant) payload data frame within the same configuration.
Alternatively, a transparent data stream can also be processed externally by the
Application Controller. Therefore the external controller needs the possibility to send
following commands, which would normally be generated by the TDA5235 itself (see
Figure 77 and EXTPCMD register as well):
•
•
EXTTOTIM: So the TDA5235 can proceed with Self Polling Mode (either with the
next configuration or with Configuration A).
EXTEOM found: In this case the TDA5235 can either proceed with Self Polling Mode
(either with the next configuration or with Configuration A) or stay in Run Mode Self
Polling.
EXTTOTIM and EXTEOM are only available, when the external processing mode is
deactivating functional blocks (see bit group x_CHCFG.EXTPROC).
When the actual processed configuration is right before the Off time and the Application
Controller sends one of the above mentioned commands, then the TDA5235 can
proceed with the Off time (in case next configuration is selected).
If the autonomous Wake-up Search with Configuration A follows a TOTIM or EOM event,
then also the Polling Timer is initialized, this means a new On period is started. In case
the Wake-up Search gets started with Next Configuration (after a TOTIM or EOM event),
then the Polling Timer is not initialized. This means that the On time counter proceeds
with the old value from leaving the previous Wake-up search period successfully. This is
the case for Fast Fall Back to SLEEP Mode.
In Constant On-Off Time Mode the Polling Timer is always initialized after a TOTIM or
EOM event.
Data Sheet
107
V1.0, 2010-02-19
TDA5235
Functional Description
0
All Operations Are Done With
The Wake Up Configuration
Modulation
Switching
Modulation Selection
Depending On Register
Setting
1
INIT
If PWUF == 0 then
{ Init FIFO =
Init FIFO@Cycle Start }
PWUF = 0
To Self Polling Mode
(WU Search With Next
Configuration )
To Self Polling Mode
(WU Search With
Configuration A )
1.1
17
INIT
INIT
Generating WU
CFG X Interrupt
If Not Masked
Goto SP Next
Configuration
If INITFRCS== 1 then
Init Framer
Init Digital Receiver
EXTTOTIM
(from external controller)
INITDRXES==1
2
3
Init TOTIMs
Symbol Sync ==0
Wait Till FIFO Read Out
INITDRXES==0
16
3.1
fifolk == 0
Parallel Wake-Up
Found
To Self Polling Mode
(WU Search With
Configuration A)
Wait
ToTim Timeout TSI == 0
Frame Sync == 1
EXTPROC==00
Start ToTimEOM (If Enab.)
Init FIFO=
InitFIFO@FSYNC
Check
MID Setup
MID Screening
enable == 0
Check The MID Setup
Register
13
It Is Possible To Disable
The Timeout Feature
Generating A Frame Start
Interrupt If Not Masked
INIT FIFO
6
7
INITDRXES==1
ToTim Timeout TSI == 1
Frame Sync == X
EXTPROC == 00
Start ToTim TSI (If Enabl.)
Wait Till Frame Start
Is Found
EOM2SPM == 0
Symbol Sync ==0
ToTim Timeout TSI == 0
Frame Sync == 0
5
EOM2nCfg == 1
EOM2SPM == 1
ToTim Timeout SYNC == 0
Symbol Sync == 0
ToTim Timeout SYNC == 0
Symbol Sync == 1
EXTPROC 10
ToTim Timeout SYNC == 1
Symbol Sync == X
ToTim Timeout SYNC == 1
Symbol Sync == X
EXTPROC 10
(If Enabled)
EOM2nCfg == 0
Goto Next
Config After EOM
fifolk == 0
Wait
WU Found == 1
PWUF == 1
Start ToTim Timer SYNC
To Self Polling Mode
(WU Search With
Next Configuration)
14
INIT
Init
Digital Receiver
4
WU Found == 1
PWUF == 1
ToTim Timeout == 1
EXTPROC==00
fifolk == 1
FIFO locked
Initialize TOTIM timers
MID Screening
enable == 1
Goto SelfPolling
After EOM
8
Init MID
Scanning Unit
ToTim Timeout
EOM == 1
Initialize The MID
Scanning Unit
9
Wait
Store RX Data Into FIFO
Wait For Scan Finish
Save
Channel and
Configuration
Information
MID Scanning
Finished == 0
Generating A MID Found
Interrupt If Not Masked
MID Scanning
Finished == 1
MID Found == 0
Checking ID 10
Scanning Result
Store RX Data Into FIFO
Analyze The Scanning
Result
Generating A EOM
Interrupt If Not Masked
MID Found == 1
11
EOM Found == 1
EXTEOM found
EOM Check
Store RX Data Into FIFO
Check For EOM
PWUF = PWUEN bit
(from external controller)
Figure 77
Data Sheet
15
TOTIM2nCh == 0
INITDRXES==0
12
TOTIM2nCh == 1
ToTim Timeout EOM == 1
EOM Found == X
ToTim Timeout EOM == 0
EOM Found == 0
Run Mode Self Polling
108
V1.0, 2010-02-19
TDA5235
Functional Description
While the TDA5235 is in Run Mode Self Polling, further Wake-ups would normally not be
detected by the receiver. If the functionality of a parallel Wake-up search during the
search for a TSI is desired, this can be activated by the PWUEN bit. In this case the
Wake-up search is not active during a recognized payload and is only active after the
first received payload frame, as can be seen from Figure 77. This feature can only be
used, when modulation type is the same for SPM and RMSP.
So after a reception of the EOM from the current payload, the parallel WU search can
take place in this mode. The WU search will be active after Symbol Sync has been
detected. The WU search will be active until the Synchronization gets lost or wake-up is
generated. After the Synchronization gets lost the WU search will be finished and wakeup can not be detected any more (the TSI search continues as usual).
Following procedure can be applied with help of 3 SPI Write command sequences.
The idea is to generate external EOM every time the Symbol Sync goes to inactive state
and no interrupt (TSI or WU) has been detected. This will bring the MCU to the cycle start
and reinitialize the WU search.
Configuration:
Write x_WUC.PWUEN = 1
// Enable Parallel Wake-up search
Write x_WURSSITH1 0xFF
// Set RSSI threshold to max value (avoid WU during the reinitialization procedure)
Write x_WULOT 0xFF
// Set WULOT to max value (avoid WU during the reinitialization procedure)
Data Sheet
109
V1.0, 2010-02-19
TDA5235
Functional Description
Wait for Wake-up interrupt
TIMEOUT -> SLEEP -> SPM
or (dependent on application )
EXT_TOTIM:
* Select external processing (for ext. TOTIM)
(Write x_CHCFG.EXTROC = 0x2)
* Generate external TOTIM
(Write EXTPCMD 0x02)
* Disable external processing
(Write x_CHCFG.EXTROC = 0x0)
WU IRQ
WU IRQ
Wait for TSI interrupt
TSI IRQ
TSI IRQ
Wait for EOM interrupt
EOM IRQ
Only necessary if other PPx signals needed during self -polling
otherwise configure PPx once at the beginning
Activate Symbol Sync on PPx
(example for PP 0;
for other PPx see notes below )
Write 0xF4 0x07
Write PPCFG0.PP0CFG = 0xE
Deactivate Symbol Sync on PPx
(example for PP 0 = RX_RUN)
Write PPCFG0.PP0CFG = 0x1
1. Force Symbol Sync for MCU to 0
Write 0xED 0x40
2. Select external processing (for ext. EOM)
Write x_CHCFG.EXTPROC = 0x2
3. Generate external EOM
Write EXTPCMD 0x01
4. Disable external processing
Write x_CHCFG.EXTPROC = 0x0
5. Unforce Symbol Sync
Write 0xED 0x00
Wait for Symbol Sync
(on PPx)
(if no ISR impl.)
Symbol Sync = 1
Interrupt
Wait for interrupt
Wait for SW Timeout
Symbol Sync = 0
EOM generation
- must be faster than
RUNIN duration
SW Timeout
Figure 78
Parallel Wake-up Search
Notes:
- Symbol Sync can be activated on any PPx port
PP0: Write 0xF4 0x07 & Write PPCFG0 0x0E
PP1: Write 0xF4 0x70 & Write PPCFG0 0xE0
PP2: Write 0xF5 0x01 & Write PPCFG1 0x0E
PP3: Write 0xF5 0x10 & Write PPCFG1 0xE0
- Symbol Sync monitoring necessary only in run mode between frames and WU pattern
or till software timeout generated
Data Sheet
110
V1.0, 2010-02-19
TDA5235
Functional Description
- generation of external EOM will reinitialize also the TOTIM timers
- external EOM generation period should be smaller than the RUNIN length
(7 chips RUNIN = ~62 us @ 112 kchip/s , 5 SPI write commands = ~ 60 us @ 2 Mbit)
- minimal Symbol Sync active period = TVWIN, minimal Symbol Sync inactive period =
RUNIN
For protocols where no ASK/FSK switching is required between the Wake-up and
payload frame, the Wake-up and TSI pattern can share the same bits (e.g. Wake-up
pattern = ..00000, TSI = 000001, all bits Manchester encoded). This function can be
activated by the INITFRCS bit, so then there is no reset of the framer compare shift
register after a Wake-up event, which can shorten the required processing time.
Data Sheet
111
V1.0, 2010-02-19
TDA5235
Functional Description
SPMIP
Timer-Status
Timer-Status
SPM
Active-Idle Period Timer
(5 / 8 Bit)
Timer-Control
fOnOff
Receiver-Enable
Self-Polling-Mode (SPM)
FSM
No WU
SPMC
Polling Mode
Figure 79
SPMAP
SPMOFFT1
SPMOFFT0
SPM
On-Off-Timer
(14 Bit)
fRT
Timer-Control
SPM
Reference-Timer
(8 Bit)
Timer-Control
f sys / 64
SPMONTx1
SPMONTx0
Polling Timer Unit
SPMRT
2.6.2
to
Master-Control-Unit
Polling Timer Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (fsys/64) into the slower
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5235 is able to handle up to two different sets of configurations automatically.
Data Sheet
112
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.2.1
Self Polling Modes
Four polling modes are available to fit the polling behavior to the expected wake-up
patterns and to optimize power consumption in Self Polling Mode.
The following 4 Polling Modes are available and can be configured via 2 bits in the
configuration register SPMC:
•
•
•
•
Constant On-Off (COO)
Fast Fall Back to SLEEP (FFB)
Mixed Mode (MM)
Permanent Wake-Up Search (PWUS)
A detected wake-up data sequence or an actual value for RSSI or Signal Recognition (a
combination of Signal Detector and Noise Detector, see Chapter 2.4.8.1) exceeding a
certain adjustable threshold forces the TDA5235 into Run Mode Self Polling.
In all modes the timing resolution is defined by the Reference Timer, which scales the
incoming frequency (fsys/64) corresponding to the value, which is defined in the Self
Polling Mode Reference Timer (SPMRT) register. Changing values of SPMRT helps to
fit the final On-Off timing to the calculated ideal timing.
2.6.2.2
Constant On-Off Time (COO)
In this mode there is a constant On and a constant Off time. Therefore also the resulting
master period time is constant. The On and Off time are set in the SPMONTA0,
SPMONTA1, SPMONTB0, SPMONTB1, SPMOFFT0 and SPMOFFT1 registers. The
On time configuration is done separately for Configuration A and B.
When Single-Configuration is selected then only Configuration A is used. MultiConfiguration Mode allows reception of up to 2 different transmit sources. The diagram
below shows possible scenarios.
All receive modes described in Chapter 2.5.1.2 Data Interface can be used.
Data Sheet
113
V1.0, 2010-02-19
TDA5235
Functional Description
Single Config
run mode
RX polling
sleep mode
A
TAON
TMasterPeriod = TAON + TOFF
TOFF
TMasterPeriod
Multi Config
run mode
RX polling
sleep mode
A
B
TAON TBON
TMasterPeriod = TAON + TBON + T OFF
TOFF
TMasterPeriod
Figure 80
Constant On-Off Time
Calculation of the On time:
The On time must be long enough to ensure proper detection of a specified wake-up
criterion. Therefore the On time depends on the wake-up pattern, and the wake-up
criterion. It has to include transmitter data rate tolerances.
A widely used wake-up pattern is a sequence of equal Bi-phase encoded bits or a certain
Bi-phase encoded bit pattern.
TON also must include the relevant start-up times. In case of the first configuration after
TOFF, this is the Receiver Start-Up Time. In case of the following Configuration B (RF
Receiver is already on, there is only a change of the configuration), e.g. if Configuration
B is used, this is the Configuration Change Latency Time. In addition, it has to be
considered that some data bits are required for synchronization and internal latency, see
Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame Time.
There are other wake-up patterns in use as well, which have several (up to 10 and more)
short wake-up sequences (a few byte each) that are separated by a certain pause (again
a few byte each). In this case the On time has to be set, so that a possible wake-up can
be found within two wake-up sequences including the pause in-between.
Calculation of the Off time:
The longer the Off time, the lower the average power consumption in Self Polling Mode.
On the other hand, the Off time has to be short enough that no transmitted wake-up
Data Sheet
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TDA5235
Functional Description
pattern is missed. Therefore the Off time depends mainly on the duration of the expected
wake-up pattern.
For basic timing of WU on RSSI in COO mode, please see Figure 81.
RF signal
e.g . ASK
t
RX ON
SLEEP
t
t WULOT t WULOT
t Startup
1
t WULOT t WULOT_part
n-1
2
npartially
last observation time
window is forced to end by
end of t ON
latest decision here !
tON
Figure 81
COO Polling in WU on RSSI Mode
Always check at the end of the current observation time window, if there is a WU (WakeUp) event or NOT. This means, in algorithmic description (see also Figure 10,
Chapter 2.4.7 RSSI Peak Detector and Chapter 2.4.8.5 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITH1) and (RSSIPWU_value > x_WURSSIBH1)
then WU
else NOT
Here, ‘NOT‘ means to keep on evaluating and move on to the next observation time
window, also keep on peak value tracking of RSSIPWU signal. Keep on walking through
the observation time windows until there is a WU event from the algorithm above or
finally decide at the end of the On time with the following algorithm:
if (RSSIPWU_value > x_WURSSITH1) and (RSSIPWU_value < x_WURSSIBL1 or
RSSIPWU_value > x_WURSSIBH1)
then WU
else NOT
If there is a WU event at the end of an observation time window while walking through
the observation time windows, freeze/hold this decision/peak value in register RSSIPWU
for optional read out and switch to run mode self polling.
Instead of the single RSSI criterion also the Signal Recognition criterion can be
activated.
Data Sheet
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TDA5235
Functional Description
Combined Level and Data criterion in COO mode
On using the Wake-Up on Data criterion in COO mode, the RSSI criterion (including the
RSSI blocking window) can be applied additionally by setting the bit
x_WUC.UFFBLCOO. This means that a Wake-Up interrupt will not be generated, when
a blocking RSSI level (e.g. an interfering signal) is detected even when the Data criterion
is fulfilled.
The behavior of the additional RSSI criterion is similar to the behavior in Ultrafast Fall
Back Mode.
After the level observation time the receiver checks, if the RSSI level is within a valid
range. If RSSI is within a valid range, the state machine will go on to check the Data
criterion. If the RSSI is within a forbidden range, a new level observation time is started
(Note that no parts of the Wake-Up pattern are lost in this case, when the RSSI criterion
succeeds within the following observation time).
This will be done as long as the RSSI value is within a forbidden range and the On time
is not elapsed.
If the receiver loses synchronization within the search for the Data criterion (e.g. pattern
detection), the WU unit will be initialized and checks again for the RSSI criterion.
Instead of the additional RSSI criterion also Signal Recognition criterion can be applied.
When the Signal Recognition threshold (x_WURSSIBH1) is not exceeded at
Observation Time, the Wake-Up on Level FSM (finite state machine) and Wake-Up on
Data FSM are initialized.
If the threshold is exceeded, then the Wake-Up on Level FSM enters the READY state
and has no further impact on Wake-up search until the Wake-up unit is initialized again.
When afterwards a Data Criterion is found to be OK (e.g. pattern matches, number of
equal bits or random bits is reached), the Wake-up search is completed positively.
When a Data Criterion is found to be not OK, the Wake-up search is terminated
independent of the state of the Wake-Up on Level FSM. Therefore both FSMs are
initialized.
Data Sheet
116
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TDA5235
Functional Description
2.6.2.3
Fast Fall Back to SLEEP (FFB)
This mode is used to switch off the receiver, if there is no RF signal, as quickly as
possible to reduce power consumption.
During the search for wake-up data, there is a check for a bit stream, to which the system
can be synchronized. If there is no synchronization to a bit stream within the so-called
Sync Search Time Out (SYSRCTO), the wake-up search for this channel is stopped. If
synchronization to a bit stream is possible (and not lost again), the TDA5235 waits if the
wake-up criterion is fulfilled. If the wake-up criterion is not fulfilled (in worst case, if the
last bit of an expected wake-up data pattern is wrong), the wake-up procedure for this
configuration is stopped, and the TDA5235 tries to synchronize on the next
configuration, or falls back to sleep. That means that the effective search time and,
consequently, the receiver active time is significantly shorter, and power consumption is
reduced, when no input signal is present. Calculation of Sync Search Time Out can be
found in Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame
Time.
The needed time for detecting that no relevant transmission took place can be further
reduced by using Ultrafast Fall Back to SLEEP (UFFB). When there was no Wake-up on
Level criterion fulfilled in UFFB Mode during the Observation Time (TWULOT, see
Chapter 2.4.8.5), then the system goes back to SLEEP (or to next config). This can
further reduce the receiver active time, when no data is available. When Wake-up on
Level criterion was fulfilled, then the system proceeds with normal FFB functionality
(SYSRCTO, optional Wake-up data criterion).
Note: UFFB and FFB start working at the same time!
Ultrafast Fall Back to SLEEP is working, when a Wake-up on Data criterion is selected,
the UFFBLCOO bit is enabled and FFB or PWUS mode is selected. The UFFB level
criterion can be selected in the x_WUC register.
RF signal
e.g. ASK
t
RX ON
UFFB
FFB
FFB
SLEEP
t
t WULOT
t Startup
t SYSRCTO
tWU-data-pattern
tON
Figure 82
Ultrafast Fall Back to SLEEP
Data Sheet
117
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TDA5235
Functional Description
At the end of the observation time the RSSI peak tracking value of RSSIPWU signal is
compared to the 3 thresholds. Then the decision is made. The algorithmic description is
as follows (see also Figure 10, Chapter 2.4.7 RSSI Peak Detector and
Chapter 2.4.8.5 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITH1) and (RSSIPWU_value < x_WURSSIBL1 or
RSSIPWU_value > x_WURSSIBH1)
then WU
else NOT
Instead of the RSSI criterion also Signal Recognition criterion can be applied. When the
Signal Recognition threshold (x_WURSSIBH1) is not exceeded at Observation Time,
then the system goes back to SLEEP or the Wake-Up on Level FSM (finite state
machine) is initialized and a Wake-up search is performed on the next specified
configuration.
WULCUFFB
0
1
RSSI
&
UFFB criterion
4
WU on Level Criterion
Signal
Recognition
5
Sync
3
Random Bits
1
Equal Bits
2
Pattern
0
WU criterion
WU on Data Criterion
Wake-up
Generation
FSM
WUCRT
WUCRT (2)
WUCRT (1)
WUCRT (0)
&
&
UFFBLCOO
FFB is selected
Figure 83
Data Sheet
UFFB activation
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TDA5235
Functional Description
The On and Off time setting is different from the Constant On-Off Time Mode. The entire
On time is defined in the SPMONTA0 and SPMONTA1 registers. Regardless of the
numbers of Configurations, the On time is defined with the Configuration A On-Timer.
The deactivation of the receiver can happen at different times, but this event does not
influence the timer stage, because the On time is still the same. So the master period is
constant. The following scenarios are the same as before, but with Fast Fall Back to
SLEEP.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Single Config
run mode
RX polling A
sleep mode
TAON
TOFF
TMasterPeriod = TAON + TOFF
TMasterPeriod
Multi Config
run mode
RX polling A
TMasterPeriod = TAON + TOFF
B
sleep mode
TAON
TOFF
TMasterPeriod
Figure 84
Fast Fall Back to SLEEP
Calculation of the On time:
The On time, which is now a sum for all of the configurations used, must include enough
time to ensure proper detection of the specified wake-up pattern on all configurations. To
cover the worst case scenario, the maximum time is required on all configurations as in
Constant On-Off.
TON must also include the relevant start-up times. In case of the first configuration after
TOFF, this is the Receiver Start-Up Time. In case of the following Configuration B (RF
Receiver is already on, there is only a change of the configuration), e.g. if Configuration
B is used, this is the Configuration Change Latency Time.
Data Sheet
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TDA5235
Functional Description
In addition, it has to be considered that some data bits are required for synchronization
and internal latency (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and
Inter-Frame Time).
Calculation of the Off time:
The same general rules apply as for Constant On-Off Time. The Off time has to be short
enough that no wake-up pattern reception is missed.
2.6.2.4
Mixed Mode (MM, Const On-Off & Fast Fall Back to SLEEP)
This mode combines Constant-On Time and Fast Fall Back to SLEEP within different
configuration sets: Cfg.A: COO; Cfg.B: FFB
TON for Configuration A is always calculated according to Const On-Off rules.
TON for Configuration B is always calculated according to Fast Fall Back to SLEEP rules.
In Mixed Mode the On time of Configuration B is used for the FFB group. Below there
are shown the same scenarios as before, but now for Mixed Mode. Note that SingleConfiguration can be set, but is not recommended in Mixed Mode.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Single Config
run mode
RX polling
sleep mode
A
T AON
TBON
T MasterPeriod = TAON + T BON + TOFF
TOFF
TMasterPeriod
Multi Config
run mode
RX polling
sleep mode
A
TAON
B
TBON
TOFF
T MasterPeriod = TAON + T BON + TOFF
TMasterPeriod
Figure 85
Data Sheet
Mixed Mode
120
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TDA5235
Functional Description
2.6.2.5
Permanent Wake-Up Search (PWUS)
In this mode the receiver will work in Fast Fall Back Mode, but it will not go back to the
SLEEP state after the last configuration has been searched. Instead, it will start again
from the beginning (Configuration A) until the On time has elapsed. The timing
calculation can be seen in Figure 86. Ultrafast Fall Back to SLEEP functionality can be
used as well.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Single Config
run mode
RX polling A A A A AA
sleep mode
TAO N
TMasterPeriod = TAON + TOFF
TOFF
TMasterPeriod
Multi Config
run mode
RX polling A B A
B
A
TMasterPeriod = TAO N + TOFF
sleep mode
TAON
TOFF
TMasterPeriod
Figure 86
Data Sheet
Permanent Wake-Up Search
121
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TDA5235
Functional Description
2.6.2.6
Active Idle Period Selection
This mode is used to deactivate some polling periods and can additionally be applied to
each of the above mentioned Polling Modes.
Normally, polling starts again after the TMasterPeriod. With this Active Idle Period selection
some of the polling periods can be deactivated, independent from the Polling Mode. The
active and the idle sequence is set with the SPMAP and the SPMIP registers. The values
of these registers determine the factor M and N.
run mode
RX polling
sleep mode
TOn
TOff
TMasterPeriod
Figure 87
Data Sheet
M*TMasterPeriod
N*TMasterPeriod
Active
Idle
Active Idle Period
122
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TDA5235
Functional Description
2.7
Definitions
2.7.1
Definition of Bit Rate
The definition for the bit rate in the following description is:
symbols
bitrate = ---------------------s
If a symbol contains n chips (for Manchester n=2; for NRZ n=1) the chip rate is n times
the bit rate:
chiprate = n × bitrate
2.7.2
Definition of Manchester Duty Cycle
Several different definitions for the Manchester duty cycle (MDC) are in place. To avoid
wrong interpretation some of the definitions are given below.
Level-based Definition
MDC = Duration of H-level / Symbol period
bit = 1
1
0
0
1
0
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50%
1
1
0
TH
ΔT
TH
Tb it
Tc hip
Tb it
MDC > 50%
ΔT
Tc hip
Figure 88
TH
TH
Tb it
Tb it
Definition A: Level-based definition
This definition determinates the duty cycle to be the ratio of the high pulse width and the
ideal symbol period. The DC content is constant and directly proportional to the specified
duty cycle.
For ΔT > 0 the high period is longer than the chip-period and for ΔT < 0 the high period
is shorter than the chip-period.
Data Sheet
123
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TDA5235
Functional Description
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
With this definition the Manchester duty cycle is calculated to
T chip + ΔT
TH
MDC A = --------- = --------------------------T bit
T bit
Chip-based Definition
MDC = Duration of the first chip / Symbol period
bit = 1
1
0
0
1
0
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50%
1
1
ΔT
0
T1 .ch ip
T1.ch ip
Tb it
Tc hip
Tbit
MDC > 50%
ΔT
Tc hip
Figure 89
T1.ch ip
T1 .chip
Tb it
Tbit
Definition B: Chip-based definition
This definition determinates the duty cycle to be the ratio of the first symbol chip and the
ideal symbol period independently of the information bit content. The DC content
depends on the information bit and it is balanced only if the message itself is balanced.
For ΔT > 0 the first chip-period is longer than the ideal chip-period and for ΔT < 0 the first
chip-period is shorter than the ideal chip-period.
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
Data Sheet
124
V1.0, 2010-02-19
TDA5235
Functional Description
With this definition the Manchester duty cycle is calculated to
T chip + ΔT
T 1.chip
MDC B = ---------------- = -------------------------T bit
T bit
Edge delay Definition
MDC = Duration delayed edge / Symbol period
bit = 1
1
0
0
1
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50% Tf = 0
1
Tr
ΔT
1
0
0
Tb it
Tbit
Tb it
TH
Tc hip
Tr
TH
MDC > 50% Tr = 0
1
1
ΔT
Tc hip
Figure 90
0
0
Tf
1
Tf
TH
TH
Tb it
Tbit
Tb it
Definition C: Edge delay definition
This definition determinates the duty cycle to be the ratio of the duration of the delayed
high-chip and the ideal symbol period independently of the information bit content. The
position of the high-chip is determined by the delayed rising edge and/or the delayed
falling edge. For ΔT = Tfall -Trise the Manchester duty cycle is calculated to
T chip + ΔT
T chip + T fall – T rise
T delayedHighchip
MDC C = ---------------------------------------- = -------------------------- = -----------------------------------------------T bit
T bit
T bit
Independent on the bit content, the same type of edge (rising edge and/or falling edge)
is shifted.
Data Sheet
125
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TDA5235
Functional Description
2.7.3
Definition of Power Level
The reference plane for the power level is the input of the receiver board. This means,
the power level at this point (Pr) is corrected for all offsets in the signal path (e.g.
attenuation of cables, power combiners etc.).
The specification value of power levels in terms of sensitivity is related to the peak power
of Pr in case of On-Off Keying (OOK). This is noted by the unit dBm peak.
Specification value of power levels is related to a Manchester encoded signal with a
Manchester duty cycle of 50% in case of ASK modulation.
An RF signal generator usually displays the level of the unmodulated carrier (Pcarrier).
This has following consequences for the different modulation types:
Table 6
Power Level
Modulation
scheme
Realization with RF signal
generator
Power level specification
value
ASK
AM 100%
Pr = Pcarrier + 6dB
ASK
Pulse modulation (=OOK)
Pr = Pcarrier
FSK
FM with deviation Δf:
f1 = fcarrier - Δf
f2 = fcarrier + Δf
Pr = Pcarrier
For power levels in sensitivity parameters given as average power, this is noted by the
unit dBm. Peak power can be calculated by adding 3 dB to the average power level in
case of ASK modulation and a Manchester duty cycle of 50%.
2.7.4
Figure 91
Data Sheet
Symbols of SFR Registers and Control Bits
CONTROL
Symbolizes unique SFR registers or SFR control bit(s),
which are common for all configuration sets .
CONTROL
Symbolizes SFR registers or SFR control bit (s) with
Multi-Configuration capability (protocol specific).
In case of SFR register, the name starts with A _ or B_,
depending on the selected configuration. This is
generally noted by the prefix „x _“.
SFR Symbols
126
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TDA5235
Functional Description
2.8
Digital Control (SFR Registers)
2.8.1
SFR Address Paging
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure 92).
logical address space
0x000
Configuration A 1) - Page 0
physical address space
0
d
Reserved 2)
0x080
0x0FF
0x100
Common Registers 3)
Reserved
4)
Configuration B 1) - Page 1
Reserved 2)
128 d
255 d
256 d
Reserved 2)
0x180
0x1FF
1)
2), 4)
3)
Figure 92
2.8.2
Configuration A 1) - Page 0
Common Registers 3)
Reserved
4)
Configuration B 1) - Page 1
Reserved 2)
Common Registers 3)
384 d
Reserved 4)
511 d
Configuration dependent register block (2 protocol specific sets)
page switch via SFRPAGE register
Reserved – Forbidden area
Configuration independent registers (common for all configurations )
map (“mirror“ ) to the same physical address space
SFR Address Paging
SFR Register List and Detailed SFR Description
The register list is attached in the Appendix at the end of the document.
Registers for Configuration B are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B having the prefix “B_”.
Data Sheet
127
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TDA5235
Functional Description
Data Sheet
128
V1.0, 2010-02-19
TDA5235
Applications
3
Applications
RF in
SAW
filter
to µC
SPI Bus
SDI 18
SCK 17
NCS 16
XTAL2 15
11 PP1
12 PP2
13 P_ON
14 XTAL1
SDO 19
T1 20
T2 21
LNA_INN 22
LNA_INP 23
GNDRF 24
PP3 25
RSSI 26
IFMIX_INP
IFMIX_INN
VDD5V
VDDD
VDDD1V5
GNDD
4
5
6
7
8
9
10 PP0
GNDA
TDA5235
3
IFBUF_OUT
2
VDDA 27
IFBUF_IN
1
IF CER
filter
(opt.)
IF_OUT 28
VS
IF CER
filter
(opt.)
VS
to/from µC
Figure 93
Typical Application Schematic
Note: As a good practice in any RF design, shielding around sensitive nodes can
improve the EMC performance of the application.
For achieving the best sensitivity results the following has to be kept in mind. Every
digital system generates certain frequencies (fSRC, e.g. the crystal frequency or a
microcontroller clock) and harmonics (N * fSRC) of it, which can act as interferer (EMI
source) and therefore sensitivity can be reduced.
Data Sheet
129
V1.0, 2010-02-19
TDA5235
Applications
There are two different cases, which need to be checked for the desired receive
channel(s):
Elimination of in-band EMI mixing with (2*M + 1) * fLO, where M > 0:
A square wave is used as LO (Local Oscillator) for the switching-type mixer, which also
has odd harmonics. When the harmonics of the EMI source are exactly the IF frequency
away from the harmonics of the LO, these spurs will be down-converted to the IF
frequency and act as a co-channel interferer within the receiver’s channel bandwidth
mainly in the 315 MHz band.
In this case a change of the LO injection side (high side or low side injection) can be
applied.
Example (Low Side LO-injection):
Wanted channel fRF = 314.233MHz ==> fLO = 303.533MHz ==> 3*fLO = 910.599MHz
fXOSC = 21.948717 MHz ==> 41 * fXOSC = 899.8974 MHz
Resulting IF = 910.599 - 899.8974 MHz = 10.702 MHz ==> co-channel interferer
within the receiver’s channel bandwidth ==> change LO injection side
Example (High Side LO-injection):
Wanted channel fRF = 314.233 MHz ==> fLO = 324.933 MHz ==> 3*fLO = 974.799 MHz
fXOSC = 21.948717 MHz ==> 44 * fXOSC = 965.744 MHz; 45 * fXOSC = 987.692 MHz
==> both XOSC harmonics are not generating a co-channel interferer at 10.7 MHz
A final sensitivity measurement on the application hardware is recommended.
Elimination of in-band EMI mixing with 1 * fLO:
Assuming a harmonic (N * fSRC) is falling within the BW of the wanted channel and has
an impact on the sensitivity there. In this case another XTAL frequency shall be selected,
e.g. 10 kHz away
| N * fSRC - fLocalOscillator | < BWChannel
Example (e.g. EMI source TDA5235 XOSC):
fXOSC = 21.948717 MHz ==> 42 * fXOSC = 921.846114 MHz
For further details please refer to the corresponding application note or to the latest
configuration software.
3.1
Configuration Example
Please see configuration files supplied with the Explorer tool.
Data Sheet
130
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TDA5235
Reference
4
Reference
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
may result.
Table 7
#
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
A1
Supply Voltage at VDD5V pin
Vsmax
-0.3
+6
V
A2
Supply Voltage at VDDD,
VDDA pin
Vsmax
-0.3
+4
V
A3
Voltage between VDD5V vs
VDDD and VDD5V vs VDDA
Vsmax
-0.3
+4
V
A4
Junction Temperature
Tj
-40
+125
°C
A5
Storage Temperature
Ts
-40
+150
°C
A6
Thermal resistance junction to
air
Rth(ja)
140
K/W
A7
Total power dissipation at
Tamb = 105°C
Ptot
100
mW
A8
ESD HBM integrity
VHBMRF
-2
2
KV
A9
ESD SDM integrity (All pins
except corner pins)
VSDM
-500
500
V
A10
ESD SDM integrity (All corner
pins)
VSDM
-750
750
V
A11
Latch up
ILU
100
A12
Maximum input voltage at
digital input pins
Vinmax
-0.3
A13
Maximum current into digital
input and output pins
IIOmax
Data Sheet
131
According to ESD
Standard JEDEC EIA /
JESD22-A114-B
mA
AEC-Q100 (transient
current)
VDD5V+0.5
or 6.0
V
whichever is lower
4
mA
V1.0, 2010-02-19
TDA5235
Reference
4.1.2
Operating Range
Table 8
#
Supply Operating Range and Ambient Temperature
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
B1
Supply voltage at pin VDD5V
VDD5V
4.5
5.5
V
Supply voltage range 1
B2
Supply voltage at pin
VDD5V=VDDD=VDDA
VDD3V3
3.0
3.6
V
Supply voltage range 2
B3
Ambient temperature
Tamb
-40
105
°C
Data Sheet
132
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TDA5235
Reference
4.1.3
AC/DC Characteristics
Supply voltage VDD5V = 4.5 to 5.5 Volt or VDD5V = VDDA = VDDD = 3.0 to 3.6 Volt
Ambient temperature Tamb = -40...105oC; Tamb = +25oC and VDD5V = 5.0V or VDD5V =
VDDA = VDDD = 3.3V for typical parameters, unless otherwise specified.
■ not subject to production test - verified by characterization/design
Table 9
#
AC/DC Characteristics
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
General DC Characteristics
C1.1
Supply Current
in Run Mode and
Double Down
Conversion Mode
IRun, Double
12
15
mA
ASK or FSK mode
Pin < -50dBm
C1.2
Supply Current
in Run Mode and
Single Down
Conversion Mode
IRun, Single
10.5
14
mA
ASK or FSK mode
Pin < -50dBm
C2
Supply current
in Sleep Mode
Isleep_low
crystal oscillator in Low
Power Mode;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
Tamb = 25 °C
40
50
µA
Tamb = 85 °C
60
110
µA
Tamb = 105 °C
90
160
µA
115
350
µA
Tamb = 25 °C
0.8
1.5
µA
Tamb = 85 °C
3.7
13
µA
■
Tamb = 105 °C
9.0
27
µA
■
C3
Supply current
in Sleep Mode
Isleep_high
C4
Supply current
IPDN
in Power Down Mode
■
■
crystal oscillator in High
Precision Mode
Cload = 25 pF;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
C5
Supply current
clock generator
Iclock
23
27
µA
fclockout = 1 kHz
Cload = 10 pF
■
C6
Supply current
IF-Buffer
IBuffer
0.5
0.7
mA
fIF_1 = 10.7 MHz
Rload = 330 Ω
no AC signal
■
Data Sheet
133
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Supply current
during RF-FE startup
/ BPF calibration
IRF-FE-
C8
Brownout detector
threshold
VBOR
2.3
C9
Receiver reset time
tReset
1.0
C10
Receiver startup
time
tRXstartup
455
C11
RF Channel Hop
Latency Time and
Configuration (Hop)
Change Latency
Time (e.g. Cfg A to
Cfg B)
tC_Hop
C12
RF Frontend startup
delay
C13
C7
Unit
Test Conditions
Remarks
max.
■
2.2
2.9
mA
2.45
2.6
V
3.0
ms
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
455
455
µs
Time to startup RF
frontend (comprises time
required to switch crystal
oscillator from Low Power
Mode to High Precision
Mode
■
111
111
111
µs
Time to switch RF PLL
between different RF
Channels (does not
include settling of Data
Clock Recovery) and time
to change Configuration
■
tRFstartdelay
350
350
350
µs
Delay of startup of RF
frontend
■
P_ON pulse width
tP_ON
15
µs
Minimal pulse width to
reset the chip
■
C14
NINT pulse length
tNINT_Pulse
µs
Pulse width of interrupt
■
C15
Accuracy of Temperature Sensor
startup,BPFcal
12
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
C15.1 uncalibrated
TError, uncal
+/- 23
°C
uncalibrated (3 sigma)
value
■
C15.2 calibrated
TError, cal
+/- 4.5
°C
after 1-point calibration at
room temperature (3
sigma)
■
C16
Accuracy of VDDD readout
C16.1 uncalibrated
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
VDDD, Error,
+/- 200
mV
uncalibrated (3 sigma)
value
■
+/- 25
mV
after 1-point calibration at
room temperature (3
sigma)
■
uncal
C16.2 calibrated
VDDD, Error,
cal
Data Sheet
134
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
1st Local Oscillator
Low Side LO-injection
and High Side LOinjection allowed;
See also Chapter 3
max.
General RF Characteristics (overall)
D1
Frequency
Range 1
fband_1
300
320
MHz
Range 2
fband_2
425
450
MHz
Range 3
fband_3
863
870
MHz
Range 4
fband_4
902
928
MHz
D2
Frequency step of
Sigma-Delta PLL
fstep
10.5
D3
ASK Demodulation
Data Rate
Rdata
0.5
40
kchip/s
■
Data rate tol.
Rdata_tol
-10
+10
%
■
Modulation index
mASK
50
100
%
ASK
■
mOOK
99
100
%
ON-OFF keying
■
Data Rate
Rdata
0.5
112
kchip/s
including tolerance
■
Data rate tol.
Rdata_tol
-10
+10
%
Frequency deviation
Δf
1
64
kHz
Modulation index
mFSK
1.0
D4
D5
Hz
fstep = fXTAL / 221
■
FSK Demodulation
■
frequency deviation
zero-peak
■
m = frequency_
deviationzero-peak /
maximum_occuring_data
_frequency;
m >= 1.25 is
recommended at small
frequency deviation
■
Decoding schemes
Manchester, differential Manchester,
Bi-phase Mark / Bi-phase Space
D6
Duty cycle ASK
Tchip/
Tdata
35
55
%
see Chapter 2.7.2
Definition C
■
Duty cycle FSK
Tchip/
Tdata
45
55
%
see Chapter 2.7.2
Definition B
■
Overall noise figure
Noise figure
Data Sheet
NF
6
135
8
dB
RF input matched to 50 Ω
@ Tamb = 25 °C
■
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D7
Unit
Test Conditions
Remarks
max.
BER Sensitivity (FSK)
Manchester coding;
for additional test conditions see right after this
table
BER = 2*10-3
RF input matched to 50 Ω
@ Tamb = 25 °C;
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D7.1
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK1BER
-119
-116
dBm
2nd IF BW = 50 kHz
PDF = 33 kHz, AFC off,
IFATT=0
■
D7.2
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK2BER
-114
-111
dBm
2nd IF BW = 50 kHz
PDF = 65 kHz, AFC off,
IFATT=0
■
D7.3
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK3BER
-112
-109
dBm
2nd IF BW = 125 kHz
PDF = 132 kHz, AFC off,
IFATT=0
■
D7.4
Data Rate 50 kBit/s;
Δf = 50 kHz
SFSK4BER
-105
-102
dBm
2nd IF BW = 300 kHz
PDF = 239 kHz, AFC off,
IFATT=0
■
D7.5
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK5BER
-110
-107
dBm
2nd IF BW = 300 kHz
■
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.6
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK6BER
-106
-103
dBm
2nd IF BW = 300 kHz
■
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.7
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK7BER
-110
-107
dBm
2nd IF BW = 300 kHz
■
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Sheet
136
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D8
Unit
Test Conditions
Remarks
max.
BER Sensitivity (OOK)
Manchester coding;
for additional test conditions see right after this
table
BER = 2*10-3
RF input matched to 50 Ω
@ Tamb = 25 °C,
peak power level (see
Chapter 2.7.3);
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D8.1
Data Rate 0.5 kBit/s
SASK1BER
-120
-117
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.2
Data Rate 2 kBit/s
SASK2BER
-116
-113
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.3
Data Rate 10 kBit/s
SASK3BER
-111
-108
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.4
Data Rate 16 kBit/s
SASK4BER
-109
-106
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 80 kHz
■
D8.5
Data Rate 0.5 kBit/s
SASK5BER
-115
-112
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D8.6
Data Rate 2 kBit/s
SASK6BER
-112
-109
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D8.7
Data Rate 10 kBit/s
SASK7BER
-106
-103
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D8.8
Data Rate 16 kBit/s
SASK8BER
-104
-101
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D9.1
Sensitivity increase
for Single Down
Conversion mode
ΔSSDC
0.5
1
dB
■
D9.2
Double Down
Conversion sensitivity
decrease for higher
blocking performance
(IFATT=0 => IFATT=7)
1
2
dB
■
Data Sheet
ΔSDDC,
0
IFATT7
137
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D9.3
Single Down Conversion
sensitivity decrease for
higher blocking
performance
(IFATT=4 => IFATT=7)
ΔSSDC,
0.5
Unit
Test Conditions
Remarks
max.
1
dB
■
IFATT7
D10.1 Sensitivity variation
due to temperature
(-40...+105°C)
ΔPin
2
dB
relative to Tamb = 25 °C;
temperature drift of crystal
not considered
■
D10.2 Sensitivity variation
due to frequency
offset 1)
ΔPin
3
dB
AFC inactive;
For Sensitivity Bandwidth
see Table 11
■
D10.3 Sensitivity variation
due to frequency
offset
ΔPin
3
dB
AFC active, slow AFC;
For Sensitivity Bandwidth
see Table 11 and applied
AFCLIMIT
■
D10.4 Sensitivity loss when
AFC active at center
frequency
ΔPin
1
dB
AFC active;
center frequency - no
AFC wander (see
Chapter 2.4.6.3)
■
D11
3rd order intercept
IIP3
PIIP3
-16
-14
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
■
D12
1 dB compression
point CP1dB
PCP1dB
-27
-25
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
■
D13
1st IF image rejection dimage1
30
40
dB
1st IF = 10.7 MHz
without front end SAW
filter;
valid for Double Down
Conversion Mode
D14
2nd IF image
rejection
30
34
dB
2nd IF = 274 kHz
without 1st IF CER filter;
valid for Single and
Double Down Conversion
Mode
Data Sheet
dimage2
138
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
RF Front End Characteristics
(Unless otherwise noted, all values apply for the specified frequency ranges)
E1
LNA input impedance
E1.1
fRF = 315 MHz
E1.2
E1.3
E1.4
E1.5
E1.6
E1.7
E1.8
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
fRF = 315 MHz
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
Rin_p,diff
680
Ω
Cin_p,diff
1.05
pF
Rin_p,diff
570
Ω
■
Cin_p,diff
0.87
pF
■
Rin_p,diff
550
Ω
■
Cin_p,diff
0.63
pF
■
Rin_p,diff
540
Ω
■
Cin_p,diff
0.63
pF
■
Rin_p, SE
500
Ω
Cin_p, SE
1.87
pF
Rin_p, SE
400
Ω
Cin_p, SE
1.63
pF
■
Rin_p, SE
322
Ω
■
Cin_p, SE
1.59
pF
■
Rin_p, SE
312
Ω
■
Cin_p, SE
1.56
pF
■
differential parallel
equivalent input between
LNA_INP and LNA_INN
single-ended parallel
equivalent input between
LNA_INP and GNDRF /
LNA_INN and GNDRF
E2
FE output
impedance
Rout_IF
290
330
380
Ω
fIF = 10.7 MHz
E3
FE voltage
conversion gain
AVFE, max
34
36
38
dB
min. IF attenuation
(IFATT = 0);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
E4
FE voltage
conversion gain
AVFE_7
29
31
33
dB
IF attenuation
(IFATT = 7);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
Data Sheet
139
■
■
■
■
■
■
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
E5
FE voltage
conversion gain
E6
FE voltage
conversion gain step
Symbol
AVFE, min
Limit Values
min. typ.
max.
22
26
24
0.8
Unit
Test Conditions
Remarks
dB
max. IF attenuation
(IFATT = 15);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
dB
12dB / 15 = 0.8dB/step
■
Double Down
Conversion: 16 gain
settings (4 bit)
Single Down Conversion:
7 gain settings
E7
1st Local Oscillator SSB Noise
E7.1
PLL loop Bandwidth
BW
E7.2
fin_R1 = 315MHz
dSSB_LO
E7.3
E7.4
E7.5
fin_R2 = 434MHz
fin_R3 = 868MHz
fin_R4 = 915MHz
dSSB_LO
dSSB_LO
dSSB_LO
closed loop
100
BW and its tolerances
■
150
200
kHz
-81
-76
dBc/Hz @ foffset = 1 kHz
-85
-80
@ foffset = 10 kHz
■
-82
-77
@ foffset = 100 kHz
■
-120
-115
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-78
-73
-83
-78
@ foffset = 10 kHz
■
-82
-77
@ foffset = 100 kHz
■
-117
-112
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-75
-70
-79
-74
@ foffset = 10 kHz
■
-77
-72
@ foffset = 100 kHz
■
-114
-109
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-71
-66
-79
-74
@ foffset = 10 kHz
■
-77
-72
@ foffset = 100 kHz
■
-116
-111
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
dBc/Hz @ foffset = 1 kHz
dBc/Hz @ foffset = 1 kHz
dBc/Hz @ foffset = 1 kHz
■
■
■
■
E8.1
Spurious emission < 1 GHz
-57
dBm
■
E8.2
Spurious emission > 1 GHz
-47
dBm
■
Data Sheet
140
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
E9
Inband fractional spur
E10
3dB Overall Analog
Frontend Bandwidth
Test Conditions
Remarks
max.
-40
■
dBc
230
BWANA
Unit
kHz
LNA input to Limiter
output, excluding external
CER filter
■
1st IF Buffer Characteristics
F1
Input impedance
Rin_IF
290
330
370
Ω
fIF = 10...12 MHz
■
F2
Output impedance
Rout_IF
290
330
370
Ω
fIF = 10...12 MHz
■
F3
Voltage gain
AVBuffer
3
4
5
dB
fIF = 10...12 MHz
Zsource = 330 Ω
Zload = 330 Ω
F4
Buffer switch
disolation
isolation (CERFSEL)
dB
fIF = 10...12 MHz
see Figure 6
■
Ω
fIF = 10...12 MHz
■
60
2nd IF Mixer, RSSI and Filter Characteristics
G1
Mixer input
impedance
G2
RSSI
G2.1
Dynamic range
(Linearity +/- 2 dB)
Rin_IF
290
330
390
Related to RF input
matched to 50 Ω
DRRSSI
-110
-30
dBm
applies for digital RSSI;
AGC on
■
-115
-60
dBm
applies for analog RSSI
@ 50kHz BPF, AGC off
■
-110
-50
dBm
applies for analog RSSI
@ 300kHz BPF, AGC off
■
G2.2
Linearity
DRLIN
-1
+1
dB
-95 dBm...-35 dBm;
applies for digital RSSI
■
G2.3
Temperature drift
within linear dynamic
range
DRTEMP
-2.5
+1.5
dB
-95 dBm...-35 dBm;
applies for digital RSSI
■
G2.4
Output dynamic
range
VRSSI+
0.8
2.0
V
G2.5
analog RSSI error,
untrimmed
DRSSIana
-4
+2
dB
at RSSI pin
G2.6
analog RSSI slope,
untrimmed
dVRSSI/
dVmix_in
8
12
mV/dB
at RSSI pin;
typical 600 mV/60 dB =
10 mV/dB
G2.7
digital RSSI error,
untrimmed
DRSSIdig_u -4
+2
dB
RSSI register readout
Data Sheet
10
141
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
Unit
Test Conditions
Remarks
min. typ.
max.
+1
dB
RSSI register readout
G2.8
digital RSSI error,
user trimmed via
SFRs RSSISLOPE
and RSSIOFFS
DRSSIdig_t
-1
G2.9
digital RSSI slope,
untrimmed
dVRSSI/
dVmix_in
2
2.5
3
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.10 digital RSSI slope,
user trimmed via
SFRs RSSISLOPE
and RSSIOFFS
dVRSSI/
dVmix_in
2.35
2.5
2.65
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.11 Resistive load at
RSSI pin
RL,RSSImax
100
G2.12 Capacitive load at
RSSI pin
CL,RSSI
■
■
kΩ
■
20
pF
■
288
kHz
G3
2nd IF Filter (3rd order Bandpass Filter)
G3.1
Center frequency
fcenter
G3.2
-3 dB BW
BW-3dB
G3.3
-3 dB BW tolerance
tol_BW-3dB -5
+5
%
For BW = 125, 200, 300
kHz
■
G3.4
-3 dB BW tolerance
tol_BW-3dB -6
+6
%
For BW = 50, 80 kHz
■
Data Sheet
262
274
■
kHz
50
80
125
200
300
142
Asymmetric BPF corners:
f_center=sqrt(flow * fhigh);
Use AFC for more
symmetry
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Crystal Oscillator Characteristics
H1
Frequency range
fXTAL
H2
Crystal parameters
H2.1
Motional
capacitance
C1
H2.2
Motional resistance
H2.3
MHz
21.948
717
6
10
fF
■
R1
18
80
Ω
■
Shunt capacitance
C0
2
4
pF
■
H2.4
Load capacitance
CLoad
12
H2.5
Initial frequency
tolerance
fXTAL_Tol
-30
H2.6
Frequency trimming
range
ΔfXTAL
-50
H2.7
Trimming step
ΔfX_step
H3
Clock output
fclock_out
frequency at PPx pin
H4
Crystal oscillator
settling time
(switching from Low
Power to High
Precision Mode)
tCOSCsettle
H5
Start up time
tstart_up
Data Sheet
3
pF
nominal value
■
+30
ppm
oscillator untrimmed (trim
capacitor default settings,
usage of recommended
crystal);
not including crystal
tolerances
■
+50
ppm
larger trimming range
possible via SD PLL
4
ppm
see also step size of
SD PLL
5.5M
Hz
10pF load
292
292
µs
0.45
1
ms
1
11
292
143
■
■
crystal type:
NDK NX5032SD;
See also BOM for ext.
load caps;
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Digital Inputs/Outputs Characteristics
I1
High level input
voltage
VIn_High
I2
High level input
leakage current
IIn_High
I3
Low level input
voltage (except
P_ON pin)
VIn_Low
I4
0.7*
VDDD
VDD5V V
+0.1
5
µA
0
0.8
V
Low level input
voltage (at P_ON
pin)
VIn_Low_PON 0
0.5
V
I5
Low level input
leakage current
IIn_Low
-5
I6
High level output
voltage 1
VOut_High1
VDD5V
-0.4
VDD5V V
IOH=-500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I7
Low level output
voltage 1
VOut_Low1
0
0.4
IOL=500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I8
High level output
voltage 2
VOut_High2
VDD5V
-0.8
VDD5V V
IOH=-4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
I9
Low level output
voltage 2
VOut_Low2
0
0.8
IOL=4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
Data Sheet
µA
144
V
V
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
MHz
Note: A high SPI clock
rate during data reception
can reduce sensitivity
max.
Timing SPI-Bus Characteristics
J1
Clock frequency
fclock
2.2
J2
Clock High time
tCLK_H
200
ns
■
J3
Clock Low time
tCLK_L
200
ns
■
J4
Active setup time
tsetup
200
ns
■
J5
Not active setup time tnot_setup
200
ns
■
J6
Active hold time
thold
200
ns
■
J7
Not active hold time
tnot_hold
200
ns
■
J8
Deselect time
tDeselect
200
ns
■
J9
SDI setup time
tSDI_setup
100
ns
■
J10
SDI hold time
tSDI_hold
100
ns
■
J11
Clock low to SDO
valid
tCLK_SDO
145
ns
@ Cload = 80 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J12
Clock low to SDO
valid
tCLK_SDO
40
ns
@ Cload = 10 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J13
SDO rise time
tSDO_r
90
ns
@ Cload = 80 pF
■
J14
SDO fall time
tSDO_f
90
ns
@ Cload = 80 pF
■
J15
SDO rise time
tSDO_r
15
ns
@ Cload = 10 pF
■
J16
SDO fall time
tSDO_f
15
ns
@ Cload = 10 pF
■
J17
SDO disable time
tSDO_disable
25
ns
■
■
1) Please note that the system bandwidth is smaller than the smallest bandwidth in the signal path.
Data Sheet
145
V1.0, 2010-02-19
TDA5235
Reference
Unless explicitly otherwise noted, the following test conditions apply to the given
specification values in Table 10 and items D7 and D8:
* Hardware: TDA5240 Platform Testboard V1.0
* Single-Ended Matching for 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz
* RF input matched to 50 Ω; Insertion loss of input matching network = 1dB
* Receive Frequency 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz; Lo-Side LO-Injection
* Reference Clock: XTAL=21.948717 MHz
* IF-Gain: Attenuation set to default value (IFATT = 7)
* Double Down Conversion
* 1 IF-Filter: Center=10.7MHz; BW=330kHz; Connected between IF_OUT and IFBUF_IN
* 2nd IF Filter BW: Depending on Data Rate and FSK Deviation
* Received Signal at zero Offset to IF Center Frequency
* RSSI trimmed
* FSK Pre-Demodulation Filter (PDF) BW: Depending on Data Rate and FSK Deviation
* No SPI-traffic during telegram reception, CLK_OUT disabled
* AFC and AGC are OFF, unless otherwise noted
* Specification values are in respect to Manchester-coded Infineon-Reference Pattern 1
(7 Bits '0', 1 Bit ’1', 1 Bits '0', 1 Bit ’1', 1 Bits '0', 1 Bit ’1', PRBS5 (31 Bit), 1 Bit 'M') according to Figure 18
However a Code Violation is not used as EOM criterion
BER sensitivity measurements use Receive Mode TMMF (sampled with ideal data clock)
MER sensitivity measurements use Receive Mode POF
* DRE ... Data Date Error of received telegram vs. adjusted Data Rate
* DC ... Duty Cycle
* MER ... Message Error Rate
[MER = 1 - (number_of_correctly_received_messages / number_of_transmitted messages)]
* FAR ... False Alarm Rate
[FAR = number_of_mistakenly_wake_ups / number_of_periods_searching_for_data_on_channel]
* MMR ... Missed Message Rate
[MMR = number_of_mistakenly_missed_wake_up_patterns /
number_of_periods_with_wake_up_pattern_transmitted_and_searching_for_wake_up_pattern]
* BER ... Bit Error Rate (using a PRBS9 Pseudo-Random Binary Sequence)
[BER = 1 - (number_of_correctly_received_bits / number_of_transmitted bits)]
Data Sheet
146
V1.0, 2010-02-19
TDA5235
Reference
Table 10
#
MER Characteristics (Receive Mode = POF)
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Characteristics of Digital Data Filter and Data Clock Recovery
Acceptance Criterion is: MER = 50 kBit/s
■
tolManch_DefC
35
55
%
According to Definition C
in Chapter 2.7.2
including
DRE of -10% to +10%
Data Rate >= 10 kBit/s
Note:
If BPF_BW / Bitrate < 12,
the selected data rate in
the configuration tool
needs to be set 5%
higher.
■
K1
Db
Data Rate Error of
received Telegram
Sensitivity loss < 1dB
K2
Duty Cycle Error of Manchester coding of received Telegram
K2.1
Sensitivity loss < 1dB
tolManch_DefB
45
K2.2
Sensitivity loss <
3.5dB
tolManch_DefC
K2.3
Sensitivity loss <
1.5dB
K2.4
Sensitivity loss < 4dB
Data Sheet
-10
10
147
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Sensitivity of Receiver
Acceptance Criterion is: MER
