TDA7200XUMA1

D at a Sh ee t , V 1. 0 , Ma y 20 0 7 TDA7200 ASK/ FS K Sin gle Co nve rsio n Re ceiver Ver s i on 1 .0 W i re l e s s C o n t r o l Co mpo ne nts N e v e r s t o p t h i n k i n g . Edition 2007-05-02 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany © Infineon Technologies AG 2007-05-02. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D at a Sh ee t , V 1. 0 , Ma y 20 0 7 TDA7200 ASK/ FS K Sin gle Co nve rsio n Re ceiver Ver s i on 1 .0 W i re l e s s C o n t r o l Co mpo ne nts N e v e r s t o p t h i n k i n g . TDA7200 Revision History: 2007-05-02 Previous Version: none Page V 1.0 Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com TDA7200 Table of Contents Page 1 1.1 1.2 1.3 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASK/FSK-Data Path Functional Description . . . . . . . . . . . . . . . . . . . . . . . FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 21 22 22 23 25 26 28 28 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics at TAMB= -20°C ... +70°C . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 32 32 33 38 42 43 44 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Data Sheet 5 6 6 6 6 V 1.0, 2007-05-02 TDA7200 Product Description 1 Product Description 1.1 Overview The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency band 400 to 440 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, an advanced data comparator (slicer) with selection between two threshold modes and a peak detector. Additionally there is a power down feature to save current and extend battery life, and two selectable alternatives of generating the data slicer threshold. 1.2 • • • • • • • • • • Low supply current (Is = 5.7 mA typ. in FSK mode, Is = 5.0 mA typ. in ASK mode) Supply voltage range 5V ±10% Power down mode with very low supply current (50nA typ.) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser ASK sensitivity better than -106 dBm over specified temperature range (-20 to +70°C) FSK sensitivity better than -100 dBm over specified temperature range (-20 to +70°C) Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with selection between two threshold modes (see Section 2.4.8) 1.3 • • • Features Application Remote Control Systems Alarm Systems Low Bitrate Communication Systems Table 1 Type TDA7200 Data Sheet Order Information Ordering Code Package SP000296473 PG-TSSOP-28 6 V 1.0, 2007-05-02 TDA7200 Functional Description 2 Functional Description 2.1 Pin Configuration Figure 1 Data Sheet CRST1 1 28 CRST2 VCC 2 27 PDWN LNI 3 26 PDO TAGC 4 25 DATA AGND 5 24 3VOUT LNO 6 23 THRES VCC 7 22 FFB MI 8 21 OPP MIX 9 20 SLN AGND 10 19 SLP PTST 11 18 LIMX IFO 12 17 LIM DGND 13 16 SSEL VDD 14 15 MSEL TDA 7200 Pin Configuration 7 V 1.0, 2007-05-02 TDA7200 Functional Description 2.2 Pin Definition and Functions Table 2 Pin Defintion and Function Pin No. Symbol 1 CRST1 Equivalent I/O Schematic Function External Crystal Connector 1 4.15V 1 50uA 2 VCC 5V Supply 3 LNI LNA Input 57uA 3 500uA 4k 1k Data Sheet 8 V 1.0, 2007-05-02 TDA7200 Functional Description Pin No. Symbol 4 TAGC Equivalent I/O Schematic Function AGC Time Constant Control 4.3V 4.2uA 4 1k 1.5uA 1.7V 5 AGND 6 LNO Analogue Ground Return LNA Output 5V 1k 6 7 VCC Data Sheet 5V Supply 9 V 1.0, 2007-05-02 TDA7200 Functional Description Pin No. Symbol 8 MI 9 Equivalent I/O Schematic Function Mixer Input 1.7V MIX 2k Complementary Mixer Input 2k 8 9 400uA 10 AGND Analogue Ground Return 11 PTST has to be left open 12 IFO 10.7 MHz IF Mixer Output 300uA 2.2V 60 12 4.5k 13 DGND Digital Ground Return 14 VDD 5V Supply (PLL Counter Circuity) Data Sheet 10 V 1.0, 2007-05-02 TDA7200 Functional Description Pin No. Symbol 15 MSEL Equivalent I/O Schematic Function ASK/FSK Modulation Format Sector 1.2V 40k 15 16 SSEL Data Slicer Reference Level Sector 1.2V 40k 16 17 18 LIM Limiter Input 2.4V LIMX Complementary Limiter Input 15k 17 330 75uA 18 15k Data Sheet 11 V 1.0, 2007-05-02 TDA7200 Functional Description Pin No. Symbol 19 SLP Equivalent I/O Schematic Function Data Slicer Positive Input 15uA 100 3k 19 80µA 20 SLN Data Slicer Negative Input 5uA 10k 20 21 OPP OpAmp Noninverting Input 5uA 200 21 22 FFB Data Filter Feedback Pin 5uA 100k 22 Data Sheet 12 V 1.0, 2007-05-02 TDA7200 Functional Description Pin No. Symbol 23 THRES Equivalent I/O Schematic Function AGC Threshold Input 5uA 10k 23 24 3VOUT 3V Reference Output 24 20kΩ 3.1V 25 DATA Data Output 500 25 40k 26 PDO Peak Detector Output 26 446k Data Sheet 13 V 1.0, 2007-05-02 TDA7200 Functional Description Pin No. Symbol 27 PDWN Equivalent I/O Schematic Function Power Down Input 27 220k 220k 28 CRST2 External Crystal Connector 2 4.15V 28 50uA Data Sheet 14 V 1.0, 2007-05-02 TDA7200 Functional Description 2.3 Functional Block Diagram VCC IF Filter MSEL H=ASK L=FSK MI LNO 6 9 IFO LIM 12 17 FFB 18 SLP 21 19 SLN 20 Logic + CM LNA + FSK - ASK + TDA 7200 4 16 SSEL 25 DATA + CP - - FSK PLL Demod LIMITER TAGC OPP 22 15 DATASLICER OP - RF 3 8 LIM X + LNI MI X PEAK DETECTOR PDO 26 OTA :2 VCC VCO : 64 Φ DET U REF CRYSTAL OSC 14 13 2,7 5,10 VCC AGND THRES 24 3VOUT Bandgap Reference Loop Filter DGND AGC Reference 23 1 28 11 PTST 27 PDWN Crystal Figure 2 Block Diagram 2.4 Functional Block Description 2.4.1 Low Noise Amplifier (LNA) The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current consumption is 500µA. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 3.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 3.1. Data Sheet 15 V 1.0, 2007-05-02 TDA7200 Functional Description 2.4.2 Mixer The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400440MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced only single-ended, the unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330Ω to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry. 2.4.3 PLL Synthesizer The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. The frequency range of the VCO guaranteed over production spread and the specified temperature range is 820 to 860MHz. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. The VCO signal is divided by two before it is fed to the Mixer. Depending on whether high- or low-side injection of the local oscillator is used, the receiving frequency range is 400 to 420MHz and 420 to 440MHz - see also Section 3.4. 2.4.4 Crystal Oscillator The calculation of the value of the necessary crystal load capacitance is shown in Section 3.3, the crystal frequency calculation is explained in Section 3.4. 2.4.5 Limiter The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It has a typical input impedance of 330 Ω to allow for easy interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4. This signal is used to demodulate ASKmodulated receive signals in the subsequent baseband circuitry. The RSSI output is applied to the modulation format switch, to the Peak Detector input and to the AGC circuitry. In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state as described in the next chapter. Data Sheet 16 V 1.0, 2007-05-02 TDA7200 Functional Description 2.4.6 FSK Demodulator To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain is typically 200µV/kHz. The passive loop filter output that is comprised fully on chip is fed to both the VCO and the modulation format switch described in more detail below. This signal is representing the demodulated signal with low frequencies applied to the demodulator demodulated to logic zero and high frequencies demodulated to logic ones. However this is only valid in case the local oscillator is low-side injected to the mixer which is applicable to receive frequencies above 420MHz. In case of receive frequencies below 420MHz high frequencies are demodulated as logical zeroes due to a sign inversion in the downconversion mixing process as the L0 is high-side injected to the mixer. See also Section 3.4. The modulation format switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset produced by the demodulator in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle of operation of the switch are described in Section 3.6. Table 3 MSEL Pin Operating States MSEL Modulation Format Open ASK Shorted to ground FSK The demodulator circuit is switched off in case of reception of ASK signals. 2.4.7 Data Filter The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100kΩ on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 3.2. Data Sheet 17 V 1.0, 2007-05-02 TDA7200 Functional Description 2.4.8 Data Slicer The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of up to 100kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RCterm. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx. 87%) can be used as the slicer-threshold as shown in Table 4. The data slicer threshold generation alternatives are described in more detail in Section 3.5. Table 4 SSEL Pin Operating States SSEL MSEL Selected Slicing Level (SL) X Low external SL on Pin 20 (RC-term, e.g.) High High external SL on Pin 20 (RC-term, e.g.) Low High 87% of PDO-output (approx.) 2.4.9 Peak Detector The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. A capacitor is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ASK mode. Note that the RSSI level is also output in case of FSK mode. 2.4.10 Bandgap Reference Circuitry A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA. Table 5 PDWN Pin Operating States PDWN Operating State Open or tied to ground Powerdown Mode Tied to Vs Receiver On Data Sheet 18 V 1.0, 2007-05-02 TDA7200 Applications 3 Applications 3.1 Application Circuit C18 R4 R5 Uthreshold 3VOUT THRES 24 23 RSSI (0.8 - 2.8V) 20kΩ OTA +3.1 V Iload Gain control voltage RSSI > Uthreshold: Iload=4.2µA RSSI < Uthreshold: Iload= -1.5µA UC Figure 3 LNA 4 TAGC C5 VCC Uc:< 2.6V : Gain high Uc:> 2.6V : Gain low Ucmax= VCC - 0.7V Ucmin = 1.67V LNA Automatic Gain Control Circuity The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8V to provide a switching point within the receive signal dynamic range. This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the Data Sheet 19 V 1.0, 2007-05-02 TDA7200 Applications AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage. LNA always in high gain mode 3 2 RSSI Level Range UTHRES Voltage Range 2.5 RSSI Level 1.5 1 LNA always in low gain mode 0.5 0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 Input Level at LNA Input [dBm] Figure 4 RSSI Level and Permissive AGC Threshold Levels The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50µA, but that the THRES pin input current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. The sum of R1 and R2 has to be 600kΩ in order to yield 3V at the 3VOUT pin. R1 can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT output current of 5µA1) and a threshold voltage of 1.8V Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operation THRES has to be connected to GND. As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF. 1) note the 20kΩ resistor in series with the 3.1V internal voltage source Data Sheet 20 V 1.0, 2007-05-02 TDA7200 Applications 3.2 Data Filter Design Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1). C14 C12 FFB RF1 int OPP 22 100k Figure 5 SLP 21 RF2 int 19 100k Data Filter Design with RF1int=RF2int=R C14 = 2Q b R2πf 3dB C12 = b 4QRπf 3dB with Q= b a Q is the qualify factor of the poles where, in case of a Bessel filter a=1.3617, b=0.618 and thus Q=0.577 and in case of a Butter worth filter a=1.414, b=1 and thus Q=0.71 Example: Butter worth filter with f3dB=5kHz and R=100kΩ: C14=450pF, C12=225pF 1) taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999 Data Sheet 21 V 1.0, 2007-05-02 TDA7200 Applications 3.3 Crystal Load Capacitance Calculation The value of the capacitor necessary to achieve that the crystal oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 4.1.3 and by the crystal specifications given by the crystal manufacturer. CS CRST2 Crystal 28 Input impedance Z1-28 TDA7200 1 CRST1 Figure 6 Determination of Series Capacitance Vale for the Quartz Oscillator The required series capacitor for a crystal with specified load capacitance CL can be calculated as CS = 1 1 + 2π f X L CL CL is the nominal load capacitance specified by the crystal manufacturer. Example: 13.4 MHz: CL = 12 pF XL=1010 Ω CS = 5.9 pF This value may be obtained by putting two capacitors in series to the crystal, such as 22pF and 8.2pF for 13.4MHz. But please note that the calculated CS-value includes all parasitic. 3.4 Crystal Frequency Calculation As described in Section 2.4.3 the operating range of the on-chip VCO is wide enough to guarantee a receive frequency range between 400 and 440MHz. The VCO signal is divided by 2 before applied to the mixer. This local oscillator signal can be used to downconvert the RF signals both with high- or low-side injection at the mixer. High-side Data Sheet 22 V 1.0, 2007-05-02 TDA7200 Applications injection of the local oscillator has to be used for receive frequencies between 400 and 420MHz. In this case the local oscillator frequency is calculated by adding the IF frequency (10.7 MHz) to the RF frequency. Thus the higher frequency of a FSKmodulated signal is demodulated as a logical zero (low). Low-side injection has to be used for receive frequencies above 420 MHz. The local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency then. In this case no sign-inversion occurs and the higher frequency of a FSKmodulated signal is demodulated as a logical one (high). The overall division ratio in the PLL is 32. Therefore the crystal frequency may be calculated by using the following formula: f QU = with f RF ± 10.7 32 ƒRF receive frequency ƒLO local oscillator (PLL) frequency (ƒRF ± 10.7) ƒQU quartz crystal oscillator frequency 32 ratio of local oscillator (PLL) frequency and crystal frequency. This yields the following example: f QU = 3.5 434 . 2 MHz − 10 .7 MHz = 13 .234375 MHz 32 Data Slicer Threshold Generation The threshold of the data slicer can be generated using an external R-C integrator as shown in Figure 7. The time constant TA of this circuit including also the internal resistors RF3int and RF4int (see Figure 9) has to be significantly larger than the longest period of no signal change TL within the data sequence. In order to keep distortion low, the minimum value for R is 20kΩ. Data Sheet 23 V 1.0, 2007-05-02 TDA7200 Applications TA has to be calculated as TA = R1⋅ ( RF 3int + RF 4 int ) R1 + RF 3int + RF 4 int ⋅ C13 = R1II ( RF 3 int + RF 4 int ) ⋅ C13 ⋅ C13 = ... for ASK and TA = R1⋅ RF 4 int R1 + RF 3 int + RF 4 int R1II ( RF 3int + RF 4 int ) v ⋅ C13 ... for FSK R1, RF3 int, RF4 int and C13 see also Figure 7 and Figure 9 19 20 Uthreshold 25 CM data filter data slicer Figure 7 Data Slicer Threshold Generation with External R-C Integrator In case of ASK operation another possibility for threshold generation is to use the peak detector in connection with an internal resistive divider and one capacitor as shown in Figure 8. For selecting the peak detector as reference for the slicing level a logic low as to be applied on the SSEL pin. In case of MSEL is high (or open), which means that ASK-Mode is selected, a logic low on the SSEL pin yields a logic high on the AND-output and thus the peak-detector is selected (see Figure 9). In case of FSK the MSEL-pin and furthermore the one input of the AND-gate is low, so the peak detector can not be selected. The capacitor value is depending on the coding scheme and the protocol used. Data Sheet 24 V 1.0, 2007-05-02 TDA7200 Applications C Pins: 26 25 peak detector 390k 56k Uthreshold data slicer CP Figure 8 3.6 Data Slicer Threshold Generation Utilising the Peak Detector ASK/FSK-Data Path Functional Description The TDA7200 is containing an ASK/FSK switch which can be controlled via Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case of the FSK PLL demodulator there is a feedback connection between the threshold voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK switch amplifier. In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-reference level. The slicing reference level is generated by an internal voltage divider (RT1int, RT2int), which is applied on the peak detector output. The selection between these modes is controlled by Pin 16 (SSEL), as described in Section 3.5. This is shown in Figure 9. Data Sheet 25 V 1.0, 2007-05-02 TDA7200 Applications MSEL 15 H=ASK L=FSK PDO PEAK DETECTOR from RSSI Gen (ASK signal) 26 RT1 int ASK/FSK Switch 56k C15 100nF RT2 390k Data Filter + FSK PLL Demodulator 100k 100k 25 DATA Out 300k 1 RF4 int Comp + CP + CM H=CP L=CM v=1 DC typ. 2 V 1.5 V......2.5 V AC 0.18 mV/kHz ASK + FSK RF3 int RF2 int RF1 int 30k ASK mode: v=1 FSK mode: v=11 22 21 FFB 19 OOP C14 20 SLP 16 SLN SSEL R1 C12 C13 Figure 9 3.7 ASK/FSK mode datapath FSK Mode The FSK datapath has a bandpass characterisitc due to the feedback shown above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by the external RC-combination. The upper cutoff frequency f3 is determined by the data filter bandwidth. The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic gain of this circuit is 2.2mV/kHz within the bandpass. The gain for the DC content of FSK signal remains at 200µV/kHz. The cut-off frequencies of the bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount. In case that the user data is containing long sequences of logical zeroes the effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (Pin20) is used. The comparator has no hysteresis built in. This offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20nA) running over the external resistor R. This voltage raises the voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain benefit of this Data Sheet 26 V 1.0, 2007-05-02 TDA7200 Applications asymmetrical offset for the demodulation of long zeros the lower of the two FSK frequencies should be chosen in the transmitter as the zero-symbol frequency. In the following figure the shape of the above mentioned bandpass is shown. gain (pin19) v v-3dB 20dB/dec -40dB/dec 3dB 0dB f DC f1 f2 0.18mV/kHz Figure 10 f3 2mV/kHz Frequency characteristic in case of FSK mode The cutoff frequencies are calculated with the following formulas: f1 = 1 R1× 330kΩ 2π × C13 R1 + 330kΩ f 2 = v × f1 = 11× f1 f 3 = f 3dB f3 is the 3dB cutoff frequency of the data filter - see Section 3.2. Example: R1 = 100kΩ, C13 = 47nF This leads tof1 = 44Hz and f2 = 485Hz Data Sheet 27 V 1.0, 2007-05-02 TDA7200 Applications 3.8 ASK Mode In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped. The cutoff frequency is determined by the external capacitors C12 and C14 and the internal 100k resistors as described in Section 3.2 0dB -3dB -40dB/dec f f3dB Figure 11 3.9 Frequency characteristic in case of ASK mode Principle of the Precharge Circuit In case the data slicer threshold shall be generated with an external RC network as described in Section 3.5 it is necessary to use large values for the capacitor C attached to the SLN pin (pin 20) in order to achieve long time constants. This results also from the fact that the choice of the value for R1 connected between the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appearing in parallel to R1 as can be seen in Figure 9. Apart from this a resistor value of 100kΩ leads to a voltage offset of 1mV at the comparator input. The resulting startup time constant τ1 can be calculated with: τ1 = (R1 || 330kΩ) × C13 In case R1 is chosen to be 100kΩ and C13 is chosen as 47nF this leads to τ 1 = (100kΩ || 330kΩ ) × 47 nF = 77 kΩ × 47 nF = 3.6ms When the device is turned on this time constant dominates the time necessary for the device to be able to demodulate data properly. In the powerdown mode the capacitor is only discharged by leakage currents. Data Sheet 28 V 1.0, 2007-05-02 TDA7200 Applications In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA7200 as shown in the following figure. C18 R4+R5=600k R5 R4 C13 R1 Uthreshold 24 23 Uc>Us Uc2.8V, high gain mode 1 Average Power Level at BER = 2E-3 (Sensitivity) RFin -110 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth ■ 2 Average Power Level at BER = 2E-3 (Sensitivity) FSK RFin -103 dBm Manchester enc. datarate 4kBit, 280kHz IF Bandw., ± 50kHz pk. dev. ■ 3 Input impedance fRF = 434 MHz S11 LNA 4 Input level @ 1dB compression P1dBLNA 5 Input 3rd order intercept IIP3LNA point fRF = 434 MHz 6 LO signal feedthrough at antenna port 0.873 / -34.7 deg ■ -15 dBm ■ -10 dBm matched input ■ dBm ■ LOLNI -73 Signal Output LNO (PIN 6), VTHRES>2.8V, high gain mode 1 Gain fRF = 434 MHz S21 LNA 1.509/ 138.2 deg ■ 2 Output impedance, fRF = 434 MHz S22 LNA 0.886 / -12.9 deg ■ 3 Voltage Gain Antenna to IFO fRF = 434 MHz GAntMixer-Out 42 Data Sheet 34 dB V 1.0, 2007-05-02 TDA7200 Reference # Parameter Symbol Limit Values min. typ. max. Unit Test Conditions/ L Notes Signal Input LNI, VTHRES=GND, lwo gain mode S11 LNA 1 Input impedance, fRF = 434 MHz 0.873 / -34.7 deg 2 Input level @ 1dB C. P. P1dBLNA fRF = 434 MHz -18 dBm matched input ■ 3 Input 3rd order intercept IIP3LNA point fRF = 434 MHz -10 dBm matched input ■ ■ Signal Output LNO, VTHRES=GND, lwo gain mode 1 Gain fRF = 434 MHz S21 LNA 0.183 / 140.6 deg ■ 2 Output impedance, fRF = 434 MHz S22 LNA 0.897 / -13.6 deg ■ 3 Voltage Gain Antenna to IFO fRF = 434 MHz GAntMixer-Out 22 dB Signal 3VOUT (PIN 24) 1 Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open 2 Current out I3VOUT -3 -5 -10 µA see Section 4.1 V see Section 4.1 Signal THRES (PIN 23) 1 Input Voltage range VTHRES 0 2 LNA low gain mode VTHRES 0 VS-1 3 LNA high gain mode VTHRES 3 4 Current in ITHRES_in 5 V VS-1 V or shorted to Pin 24 nA ■ Signal TAGC (PIN 4) 1 Current out, LNA low gain state ITAGC_out -3.6 -4.2 -5.5 µA RSSI > VTHRES 2 Current in, LNA high gain state ITAGC_in 1 1.5 2.2 µA RSSI < VTHRES MIXER Signal Input MI/MIX (PINS 8/9) 1 Input impedance, fRF = 434 MHz 2 Input 3rd order intercept IIP3MIX point fRF = 434 MHz Data Sheet S11 MIX 0.942 / -14.4 deg -28 35 ■ dBm ■ V 1.0, 2007-05-02 TDA7200 Reference # Parameter Symbol Limit Values min. typ. max. Unit Test Conditions/ L Notes Signal Output IFO (PIN 12) 1 Output impedance ZIFO 330 Ω 2 Conversion Voltage Gain fRF = 434 MHz GMIX 19 dB ■ LIMITER Signal Input LIM/X (PINS 17/18) 1 Input Impedance ZLIM 2 RSSI dynamic range DRRSSI 3 RSSI linearity LINRSSI 4 Operating frequency (3dB points) fLIM 264 330 5 396 Ω ■ 70 dB ±1 dB ■ 23 MHz ■ 100 kHz 10.7 DATA FILTER 1 Useable bandwidth BWBB FILT 2 RSSI Level at Data Filter Output SLP, RFIN=-103dBm RSSIlow 1.1 V LNA in high gain mode at 868 MHz 3 RSSI Level at Data Filter Output SLP, RFIN=-30dBm RSSIhigh 2.65 V LNA in high gain mode at 868 MHz ■ SLICER Signal Output DATA (PIN 25) 1 Maximum Datarate DRmax 2 LOW output voltage VSLIC_L 3 HIGH output voltage VSLIC_H 100 kBps NRZ, 20pF capacitive loading 0 0.1 V VS-1.3 VS-1 VS-0.7 V output current=200µA -100 -300 see Section 4.2. ■ Slicer, Negative Input (PIN 20) 1 Precharge Current Out IPCH_SLN Data Sheet 36 -220 µA V 1.0, 2007-05-02 TDA7200 Reference # Parameter Symbol Limit Values min. typ. max. Unit Test Conditions/ L Notes PEAK DETECTOR Signal Output PDO (PIN 26) 1 Load current Iload -500 2 Internal resistive load R 357 µA 446 static load current must not exceed -500µA 535 kΩ 14 MHz fundamental mode, series resonance CRYSTAL OSCILLATOR Signals CRSTL 1, CRSTL 2 (PINS 1/28) 1 Operating frequency fCRSTL 2 Input Impedance @ ~13MHz Z1-28 3 Load Capacitance @ ~13MHz CCRSTmax =C1 6 Ω ■ 5.9 pF ■ 4 V 0.2 V 19 µA -600 + j 1010 ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 ASK Mode VMSEL 1.4 2 FSK Mode VMSEL 0 3 Input Bias Current MSEL IMSEL -11 200 or open MSEL tied to GND FSK DEMODULATOR 1 Demodulation Gain GFMDEM 2 Useable IF Bandwidth BWIFPLL 10.2 10.7 µV/ kHz 11.2 MHz POWER DOWN MODE Signal PDWN (PIN 27) 1 Powerdown Mode On PWDNON 2.8 VS V 2 Powerdown Mode Off PWDNOff 0 0.8 V Data Sheet 37 V 1.0, 2007-05-02 TDA7200 Reference # Parameter Symbol Limit Values min. typ. max. Unit Test Conditions/ L Notes 3 Input bias current PDWN IPDWN 19 µA Power On Mode 4 Start-up Time until valid IF signal is detected TSU VTHRES 2 Current in, LNA high gain state ITAGC_in 0.5 1.5 5 µA RSSI < VTHRES MIXER 1 Conversion Voltage Gain fRF = 434 MHz GMIX +19 dB 2 Conversion Voltage Gain fRF = 868 MHz GMIX +18 dB DRRSSI 70 dB LIMITER Signal Input LIM/X (PINS 17/18) 1 RSSI dynamic range DATA FILTER 1 RSSI Level at Data Filter Output SLP, RFIN= -103dBm RSSIlow 1.1 V LNA in high gain mode at 868 MHz 2 RSSI Level at Data Filter Output SLP, RFIN= -30dBm RSSIhigh 2.65 V LNA in high gain mode at 868 MHz Data Sheet 39 V 1.0, 2007-05-02 TDA7200 Reference # Parameter Symbol Limit Values min. typ. Unit Test Conditions/ Notes ■ 100 kBps NRZ, 20pF capacitive loading ■ max. SLICER Slicer, Signal Output DATA (PIN 25) 1 Maximum Datarate DRmax 2 LOW output voltage VSLIC_L 0 0.1 V 3 HIGH output voltage VSLIC_H VS1.5 VS-1 VS0.5 V output current=200µA -100 -220 -300 µA see Section 4.2 µA static load current must not exceed -500µA Slicer, Negative Input (PIN 20) 1 Precharge Current Out IPCH_SLN PEAK DETECTOR Signal Output PDO (PIN 26) 1 Load current Iload 2 Internal resistive load R -400 356 446 575 kΩ CRYSTAL OSCILLATOR Signals CRSTL 1, CRSTL 2 (PINS 1/28) 1 Operating frequency fCRSTL 6 14 MHz 4 V fundamental mode, series resonance ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 ASK Mode VMSEL 1.4 2 FSK Mode VMSEL 0 3 Input bias current MSEL IMSEL Data Sheet -11 40 0.2 V -20 µA or open MSEL tied to GND V 1.0, 2007-05-02 TDA7200 Reference # Parameter Symbol Limit Values min. typ. Unit max. Test Conditions/ Notes ■ FSK DEMODULATOR 1 Demodulation Gain GFMDEM 2 Useable IF Bandwidth BWIFPLL 200 10.2 10.7 µV/ kHz 11.2 MHz VS V 0.8 V POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 Powerdown Mode On PWDNON 2.8 Powerdown Mode Off PWDNOff 0 Start-up Time until valid signal is detected at IF TSU