TDA7255V
ASK/FSK 434 MHz Wireless Transceiver
Data Sheet
Revision 1.1, 2010-11-10
Wireless Sense & Control
Edition 2010-11-10
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TDA7255V
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 1.1, 2010-11-10
Just minor changes
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™,
CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™,
EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™,
PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™,
SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™,
XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™,
REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership.
Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation
Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation.
FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of
Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of
INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of
Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP.
MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2010-06-09
Data Sheet
3
Revision 1.1, 2010-11-10
TDA7255V
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
1.1
1.2
1.3
1.4
1.5
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10
2.4.11
2.4.12
2.4.13
2.4.14
2.4.15
2.4.15.1
2.4.15.2
2.4.15.3
2.4.15.4
2.4.15.5
2.4.16
2.4.16.1
2.4.17
2.4.18
2.4.19
2.4.20
2.4.21
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bandgap Reference Circuitry and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I2C Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bus Data Format in I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3-Wire Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bus Data Format 3-Wire Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.1.1
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX/TX-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch in RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch in TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesizer Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Possible Crystal Oscillator Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
4
6
6
6
7
7
7
56
56
56
57
60
61
67
70
70
Revision 1.1, 2010-11-10
TDA7255V
Table of Contents
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
3.7.1
3.7.2
3.8
3.9
3.10
Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSK-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASK-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of the External Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSK-Switch Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fine-tuning and FSK Modulation Relevant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Slicer - Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Detector - Analog Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Detector – Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RSSI Threshold Voltage - RF Input Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.3
4.4
Reference Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Data Sheet
5
70
70
72
73
74
75
75
76
77
79
80
82
82
84
86
87
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Revision 1.1, 2010-11-10
TDA7255V
Product Description
1
Product Description
1.1
Overview
The TDA7255V is an ASK/FSK single-channel transceiver for 433 - 435 MHz frequency band in a tiny VQFN-40
package. Due to the very high level of integration the device requires only a few external components. The
extreme low current consumption in receive, transmit and especially in power down mode and the wide supply
voltage range make TDA7255V the ideal choice for small, battery driven applications.
The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL
synthesizer, a crystal oscillator with FSK modulator, a limiter with RSSI generator, a FSK demodulator, a data filter,
a data comparator (slicer), a positive and a negative data peak detector, a highly efficient power amplifier and a
complex digital timing and control unit with I2C/3-wire microcontroller interface. Additionally there is a power down
feature to save battery power.
The transmit section uses direct ASK modulation by switching the power amplifier, and crystal oscillator detuning
for FSK modulation. The necessary detuning load capacitors are external. The capacitors for fine tuning are
integrated. The receive section is using a novel single-conversion/direct-conversion scheme that is combining the
advantages of both receive topologies. The IF is contained on the chip, no RF channel filters are necessary as the
channel filter is also on the chip.
The self-polling logic can be used to let the device operate autonomously as a master for a decoding
microcontroller.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
Features
FSK and ASK modulation and demodulation capability without external circuitry changes, FM demodulation
capability
Frequency range: 433 to 435 MHz
Sensitivity FSK typically -115 dBm at 4 kbit/s data rate
Sensitivity ASK typically -112 dBm at 4 kbit/s data rate
Transmit power up to +13 dBm
Low supply current (Is = 9 mA typ. in receive mode, Is = 13,5 mA typ. in transmit mode (both at 3 V supply
voltage, 25°C)
Very low supply current in power down mode (5 nA typ.)
Supply voltage range: 2.1 V to 5.5 V
Data rates up to 100 kbit/s Manchester encoded
Fully integrated PLL synthesizer including VCO and loop filter on-chip with on-chip crystal oscillator tuning
Differential receive signal path completely on-chip, therefore no external filters are necessary
On-chip low pass channel select and data filter with tuneable bandwidth
Data slicer with self-adjusting threshold and 2 peak detectors
Self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode providing
periodical interrupt
Adjustable LNA gain
Digital RSSI and battery voltage readout
Clock Out Pin for external microcontroller
I2C/3-wire microcontroller interface, working at max. 400 kbit/s
Operating temperature range -40°C to +85°C
5.5 x 6.5 mm small VQFN-40 package
Data Sheet
6
Revision 1.1, 2010-11-10
TDA7255V
Product Description
1.3
Application
The TDA7255V is targeted specifically at highly size-sensitive industrial and consumer applications such as small
home automation or security and alarm systems.
Main applications:
•
•
•
•
•
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•
Bi-directional remote control systems
Home automation systems
Lighting control
Security and alarm systems
Industrial control
Remote keyless entry systems
Low bit-rate communication systems
1.4
Ordering Information
Type
Ordering Code
Package
TDA7255V
SP000698114
PG-VQFN-40-8
1.5
Package Outlines
Figure 1
Package PG-VQFN-40-8
Figure 2
PG-VQFN-40-8 Package Outlines
Data Sheet
7
Revision 1.1, 2010-11-10
TDA7255V
32 31
Figure 3
Data Sheet
30 29 28
27 26 25 24 23
EN
RESET
CLKDIV
PWDDD
DATA
GNDRF3
RSSI
CQ2x
Pin Configuration
CQ2
2.1
CI2x
Functional Description
CI2
2
GND
Functional Description
22 21
CQ1x
33
20
XGND
CQ1
34
19
XSWA
CI1x
35
18
XIN
CI1
36
17
XSWF
VCC
37
16
XOUT
BUSMODE
38
15
VSS
LF
39
14
BUSCLK
GNDRF1
40
13
GNDRF2
4
5
6
7
8
9
RXTX
LIN
LINX
GND-PA
PA
VCC1
PDN
PDP
10 11 12
BUSDTA
3
VDD
2
SLC
1
ASKFSK
TDA7255V
Pin Configuration TDA7255V
8
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TDA7255V
Functional Description
2.2
Pin Definitions and Functions
Table 1
Pin Definition and Function
Ball Name
No.
1
Pin Buffer Type
Type
Function
ASKFSK
ASK/FSK-Mode Switch Input
High = ASK
Low = FSK
350
1
2
RXTX
RX/TX-Mode Switch
Input/Output
High = RX
Low = TX
350
2
TX
3
LNI
RF Input to Differential Low
Noise Amplifier (LNA)
5k
3
1.1V 5k
180
180
PWDN
4
LNIX
5
GND-PA
4
PWDN
See Pin 3
Complementary RF Input to
Differential LNA
28
26
and also 13, 40
Ground Return for Power
Amplifier (PA) Driver Stage
15
5
Data Sheet
9
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TDA7255V
Functional Description
Table 1
Ball Name
No.
6
Pin Definition and Function (cont’d)
Pin Buffer Type
Type
Function
PA
PA Output Stage
10 Ω
6
5
GND-PA
7
VCC1
Supply for LNA and PA
37
7
11
8
PDN
50k
PWDN
350
50k
Output of the Negative Peak
Detector
3k
8
9
PDP
50k
350
50k
Output of the Positive Peak
Detector
3k
9
PWDN
Data Sheet
10
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TDA7255V
Functional Description
Table 1
Pin Definition and Function (cont’d)
Ball Name
No.
10
Pin Buffer Type
Type
Function
SLC
Slicer Level for the Data Slicer
1.2uA
350
50k
50k
50k
50k
50k
50k
10
1.2uA
11
VDD
12
BUSDTA
See Pin 7
Digital Supply
A 10 Ω serial resistor in the VDD
supply line is strongly
recommended; see also
Chapter 4.4
Bus Data In/Output
15k
350
12
13
GNDRF2
14
BUSCLK
See Pin 5
Ground Return for RF Except
PA
Bus Clock Input
350
14
15
VSS
Data Sheet
See Pin 5
Ground for Digital Section
11
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TDA7255V
Functional Description
Table 1
Ball Name
No.
16
Pin Definition and Function (cont’d)
Pin Buffer Type
Type
Function
XOUT
4k
16
Vcc
Crystal Oscillator Output
Can also be used as external
reference frequency input
Vcc-860m V
150μA
17
XSWF
FSK Modulation Switch
18
4pF .....
125pF
8pF .....
250fF
17
20
18
XIN
19
XSWA
See Pin 17
Ground for Digital Section
ASK Modulation/FSK Center
Frequency Switch
19
17
20
20
XGND
21
EN
See Pin 19
Crystal Oscillator Ground
Return
3-Wire Bus Enable Input, Active
Low
350
21
Data Sheet
12
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TDA7255V
Functional Description
Table 1
Pin Definition and Function (cont’d)
Ball Name
No.
22
Pin Buffer Type
Type
Function
RESET
Reset of the Entire System (to
Default Values) Active Low
110k
350
22
10p
23
CLKDIV
Clock Output
350
23
24
PWDDD
Power Down Input (Active High),
Data Detect Output (Active Low)
30k
350
24
25
DATA
TX Data Input, RX Data Output
(RX Powerdown: Pin 25 @
GND)
350
25
26
GNDRF3
Data Sheet
See Pin 5
Ground Return for RF except PA
13
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TDA7255V
Functional Description
Table 1
Ball Name
No.
27
Pin Definition and Function (cont’d)
Pin Buffer Type
Type
Function
RSSI
RSSI Output
S&H
350
27
16p
37k
28
GND
29
CQ2x
See Pin 5
Analog Ground
Pin for External Capacitor
Q-channel, stage 2
Stage1:Vcc-630mV
Stage2: Vcc-560mV
29
30
CQ2
See Pin 29
Pin for External Capacitor
Q-channel, stage 2
31
CI2x
See Pin 29
Pin for External Capacitor
I-channel, stage 2
32
CI2
See Pin 29
Pin for External Capacitor
I-channel, stage 2
33
CQ1x
See Pin 29
Pin for External Capacitor
Q-channel, stage 1
34
CQ1
See Pin 29
Pin for External Capacitor
Q-channel, stage 1
35
CI1x
See Pin 29
Pin for External Capacitor
I-channel, stage 1
36
CI1
See Pin 29
Pin for External Capacitor
I-channel, stage 1
37
VCC
See Pin 7
Analog Supply
Antiparallel diodes between
VCC, VCC1, VDD
Data Sheet
14
Revision 1.1, 2010-11-10
TDA7255V
Functional Description
Table 1
Pin Definition and Function (cont’d)
Ball Name
No.
38
Pin Buffer Type
Type
Function
BUSMODE
Bus Mode Selection
I2C/3 wire bus mode selection
350
38
39
LF
Loop Filter and VCO Control
Voltage
200
39
40
GNDRF1
Data Sheet
See Pin 5
Ground Return for LNA
15
Revision 1.1, 2010-11-10
Figure 4
Data Sheet
(LNA/PA)
16
PA
VCC1
ANT
(analog)
GNDRF1
VCC
6
GND-PA
5
PA
high/low
Gain
40 (LNA)
4
(digital)
:2
fRX= 578.85MHz
fTX= 434.15MHz
MIXER
VCO
:4
90°
0°
f = 144.7MHz
39
LF
LOOP
FILTER
MIXER
TX/RX
:6/8
Channel
Filter
Q
PHASE
DET.
Charge P.
TX/RX
RSSI
XIN
18
100k
6-bit
SAR-ADC
-Peak
Det
+Peak
Det
19
XSWA
17
XSWF
CRYSTAL Osc, FSKMod, Finetuning
ASK/FSK
fQ= 18.0896MHz
XOUT
16
ASK DATA
LIMITER
ASK
20
XGND
32
31
30
29
LNA
QUADRI
CORRELATOR
CI2
CI2x
CQ2
CQ2x
I
Data
FILTER
36
35
34
33
FSK DATA
CLK
Bandgap
Reference
100k
100k
ASK/FSK
-
SLICER
+
GNDRF3
26
21
38
GNDRF2
13
WAKEUP
LOGIC
CONTROLLER
INTERFACE
BUSDTA
LP
FILTER
fIF= 144.7MHz
FSK
CI1
CI1x
CQ1
CQ1x
LIMITER
14
EN
LINX
3
Channel
Filter
12
BUSCLK
LIN
fRF= 434.15MHz
MIXER
SLC
10
VSS
15
(digital)
BUSMODE
single ended to
differential conv.
ANT
15
VDD
1
27
22
8
9
1
2
24
23
25
VCC
RSSI
RESET
PDN
PDP
ASKFSK
RXTX
PWDDD
CLKDIV
Data (RX/TX
2.3
11
TDA7255V
Functional Description
Functional Block Diagram
Main Block Diagram
Revision 1.1, 2010-11-10
TDA7255V
Functional Description
2.4
Functional Block Description
2.4.1
Power Amplifier (PA)
The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode
the transmit power is approximately +13 dBm into 50 Ω at 5 V and +6 dBm at 2.1 V supply voltage. In low power
mode the transmit power is approximately +11 dBm at 5 V and -32 dBm at 2.1 V supply voltage using the same
matching network. The transmit power is controlled by the D0-bit of the CONFIG register (sub-address 00H) as
shown in the following Table 2. The default output power mode is high power mode.
Table 2
Sub Address 00H: CONFIG
Bit
Function
Description
Default
D0
PA_PWR
0 = Low TX Power, 1 = High TX Power
1
In case of ASK modulation the power amplifier is turned fully on and off by the transmit baseband data, i.e. 100%
On-Off-Keying.
2.4.2
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20 dB and symmetrical inputs. It is possible
to reduce the gain to 0 dB via logic.
Table 3
Sub Address 00H: CONFIG
Bit
Function
Description
Default
D4
LNA_GAIN
0 = Low Gain, 1 = High Gain
1
2.4.3
Downconverter 1st Mixer
The Double Balanced 1st Mixer converts the input frequency (RF) in the range of 434-435 MHz down to the
intermediate frequency (IF) at approximately 144 MHz. The local oscillator frequency is generated by the PLL
synthesizer that is fully implemented on-chip as described in Chapter 2.4.5. This local oscillator operates at
approximately 578 MHz in receive mode providing the above mentioned IF frequency of 144 MHz. The mixer is
followed by a low pass filter with a corner frequency of approximately 175 MHz in order to prevent RF and LO
signals from appearing in the 144 MHz IF signal.
2.4.4
Downconverter 2nd I/Q Mixers
The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 144 MHz IF signal down
to zero-IF. These two mixers are driven by a signal that is generated by dividing the local oscillator signal by 4,
thus equalling the IF frequency.
Data Sheet
17
Revision 1.1, 2010-11-10
TDA7255V
Functional Description
2.4.5
PLL Synthesizer
The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider by 4, an
asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a loop
filter and is fully implemented on-chip. The VCOs are including spiral inductors and varactor diodes. The center
frequency of the transmit VCO is 868 MHz, the center frequency of the receive VCO is 1156 MHz.
Generally in receive mode the relationship between local oscillator frequency fosc, the receive RF frequency f fRF
and the IF frequency f fIF and thus the frequency that is applied to the I/Q Mixers is given in the following formula:
f osc
= 4/3 f RF = 4 f IF
2
(1)
The VCO signal is applied to a divider by 2 and afterwards by 4 which is producing approximately 144 MHz signals
in quadrature. The overall division ratio of the divider chain following the divider by 2 and 4 is 6 in transmit mode
and 8 in receive mode as the nominal crystal oscillator frequency is 18.083 MHz. The division ratio is controlled
by the RxTx pin (pin 2) and the D10 bit in the CONFIG register.
2.4.6
I/Q Filters
The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters that are used for RF-channel
filtering.
OP
INTERNAL BUS
Figure 5
One I/Q Filter Stage
The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and
350 kHz in 50 kHz steps via the bits D1 to D3 of the LPF register (sub-address 03H).
2.4.7
I/Q Limiters
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall
gain of approximately 80 dB each in the frequency range of 100 Hz up to 350 kHz. Receive Signal Strength
Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional
to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to
the nominal RSSI signal.
Data Sheet
18
Revision 1.1, 2010-11-10
TDA7255V
Functional Description
2.4.8
FSK Demodulator
The output differential signals of the I/Q limiters are fed to a quadrature correlator circuit that is used to demodulate
frequency shift keyed (FSK) signals. The demodulator gain is 2.4 mV/kHz, the maximum frequency deviation is
±300 kHz as shown in Figure 6 below.
The demodulated signal is applied to the ASK/FSK mode switch which is connected to the input of the data filter.
The switch can be controlled by the ASKFSK pin (pin 1) and via the D11 bit in the CONFIG register.
The modulation index m must be significantly larger than 2 and the deviation at least larger than 25 kHz for correct
demodulation of the signal.
1.5
1.4
1.3
U /V
1.2
1.1
1
0.9
0.8
0.7
0.6
-500
-400
-300
-200
-100
0
100
200
300
400
500
f /kHz
Figure 6
Data Sheet
Quadricorrelator Demodulation Characteristic
19
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TDA7255V
Functional Description
2.4.9
Data Filter
The 2-pole data filter has a Sallen-Key architecture and is implemented fully on-chip. The bandwidth can be
adjusted between approximately 5 kHz and 102 kHz via the bits D4 to D7 of the LPF register as shown in
Table 29.
ASK / FSK
OTA
INTERNAL BUS
Figure 7
Data Filter Architecture
2.4.10
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. The self-adjusting threshold is generated by a
RC-network (LPF) or by use of one or both peak detectors depending on the baseband coding scheme as
described in Chapter 3.6. This can be controlled by the D15 bit of the CONFIG register as shown in the following
table.
Table 4
Sub Address 00H: CONFIG
Bit
Function
Description
Default
D15
SLICER
0 = Lowpass Filter, 1 = Peak Detector
0
2.4.11
Peak Detectors
Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and slow-release
manner that are proportional to the positive and negative peak voltages appearing in the data signal. These
voltages may be used to generate a threshold voltage for non-Manchester encoded signals, for example. The
time-constant of the fast-attack/slow-release action is determined by the RC network with external capacitor.
2.4.12
Crystal Oscillator
The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal operating in serial
resonance. The nominal operating frequency of 18.089583 MHz and the frequencies for FSK modulation can be
adjusted via 3 external capacitors. Via microcontroller and bus interface the chip-internal capacitors can be used
for fine-tuning of the nominal and the FSK modulation frequencies. This fine-tuning of the crystal oscillator allows
to eliminate frequency errors due to crystal or component tolerances.
Data Sheet
20
Revision 1.1, 2010-11-10
TDA7255V
Functional Description
2.4.13
Bandgap Reference Circuitry and Powerdown
A Bandgap Reference Circuit provides a temperature stable 1.2 V reference voltage for the device. A power down
mode is available to switch off all subcircuits that are controlled by the bidirectional Powerdown & DataDetect
PWDDD pin (pin 24) as shown in the following table. Power down mode can either be activated by pin 24 or bit
D14 in Register 00h. In power down mode also pin 25 (DATA) is affected (see Chapter 2.4.18).
Table 5
PWDDD Pin Operating States
PWDDD
Operating State
VDD
Powerdown Mode
Ground/VSS
Device On
Data Sheet
21
Revision 1.1, 2010-11-10
TDA7255V
Functional Description
2.4.14
Timing and Data Control Unit
BUSMODE
EN
BUSCLK
BUSDTA
The timing and data control unit contains a wake-up logic unit, an I2C/3-wire microcontroller interface, a “data valid”
detection unit and a set of configuration registers as shown in the subsequent figure.
REGISTERS
I2C / 3Wire
INTERFACE
INTERNAL BUS
DATA VALID
DETECTOR
6 Bit
ADC
FSK DATA
ASK DATA
BLOCK ENABLE
CONTROL
LOGIC
CLKDiv
PWDDD
DATA
ASK / FSK
RX / TX
32kHz
RC-Osc.
DATA
VALID
FREQUENCY
window
TH1
<
C0 >
<
<
-
Frequency of quartz >
>>>
>
>>
>
-
CL >
>
<
-
The crystal oscillator in the TDA7255V is a NIC (negative impedance converter) oscillator type. The input
impedance of this oscillator is a negative impedance in series to an inductance. Therefore the load capacitance
of the crystal CL (specified by the crystal supplier) is transformed to the capacitance CV as shown in Equation (18).
-R
LOSC
f, CL
CV
TDA7255V
Figure 33
CL =
Crystal Oscillator
1
1
− ω 2 LOSC
CV
↔ CV =
1
1
+ ω 2 LOSC
CL
(18)
CL
Crystal load capacitance for nominal frequency
ω
Angular frequency
LOSC
Inductivity of the crystal oscillator - typ: 2.7 mH with pad of board, 2.45 μH without pad
Data Sheet
68
Revision 1.1, 2010-11-10
TDA7255V
Application
With the aid of this formula it becomes obvious that the higher the serial capacitance Cv is, the higher is the
influence of LOSC.
The tolerance of the internal oscillator inductivity is much higher, so the inductivity is the dominating value for the
tolerance.
FSK modulation and tuning are achieved by a variation of Cv.
In case of small frequency deviations (up to +/- 1000 ppm), the desired load capacitances for FSK modulation are
frequency depending and can be calculated with the formula below.
CL ± =
⎛ 2 ⋅ (C0 + C L ) ⎞
⎟⎟
⋅ ⎜⎜1 +
C1
⎠
⎝
Δf ⎛ 2 ⋅ (C0 + C L ) ⎞
⎟⎟
⎜1 +
1±
N ⋅ f ⎜⎝
C1
⎠
C L m C0 ⋅
Δf
N⋅ f
(19)
CL
Crystal load capacitance for nominal frequency
C0
Shunt capacitance of the crystal
C1
Motional capacitance of the crystal
f
Crystal oscillator frequency
N
Division ratio of the PLL
Δf
Peak frequency deviation
With CL+ and CL- the necessary Cv+ for FSK HIGH and Cv- for FSK LOW can be calculated.
Alternatively, an external AC coupled (10 nF in series to 1 kΩ) signal can be applied at pin 16 (XOUT). The drive
level should be approximately 100 mVpp.
Data Sheet
69
Revision 1.1, 2010-11-10
TDA7255V
Application
3.2.1
Synthesizer Frequency Setting
Generating ASK and FSK modulation 3 settable frequencies are necessary.
3.2.1.1
Possible Crystal Oscillator Frequencies
The resulting possible crystal oscillator frequencies are shown in the following Figure 34
RX:
TX:
FSK-
FSK
ASK
Deviation
f1
ASK
FSK+
Deviation
f0
f2
Nominal
Frequency
Figure 34
Possible Crystal Oscillator Frequencies
In ASK receive mode the crystal oscillator is set to frequency f2 to realize the necessary frequency offset to receive
the ASK signal at f0*N (N: division ratio of the PLL).
To set the 3 different frequencies 3 different Cv are necessary. Via internal switches 3 external capacitors can be
combined to generate the necessary Cv in case of ASK- or FSK-modulation. Internal banks of switchable
capacitors allow the fine-tuning of these frequencies.
3.2.2
Transmit/Receive ASK/FSK Frequency Assignment
Depending on whether the device operates in transmit or receive mode or whether it operates in ASK or FSK the
following cases can be distinguished:
3.2.2.1
FSK-Mode
In transmit mode the two frequencies representing logical HIGH and LOW data states have to be adjusted
depending on the intended frequency deviation and separately according to the following formulas:
fCOSC HI = ( fRF + fDEV) / 24
(20)
fCOSC LOW = ( fRF - fDEV) / 24
(21)
e.g.
fCOSC HI = (434,16E6 + 35E3) / 24 = 18.09146 MHz
fCOSC LOW = (434,16E6 - 35E3) / 24 = 18.08854 MHz
with a frequency deviation of 35 kHz.
Data Sheet
70
Revision 1.1, 2010-11-10
TDA7255V
Application
Figure 35 shows the configuration of the switches and the capacitors to achieve the 2 desired frequencies. Gray
parts of the schematics indicate inactive parts. For FSK modulation the ASK-switch is always open.
For FSK LOW the FSK-switch is closed and Cv2 and Ctune2 are bypassed. The effective Cv- is given by:
CV − = Cv1 + Ctune1
(22)
For fine-tuning Ctune1 can be varied over a range of 8 pF in steps of 125 fF. The switches of this C-bank are
controlled by the bits D0 to D5 in the FSK register (sub-address 01H, see Table 25).
For FSK HIGH the FSK-switch is open. So the effective Cv+ is given by:
CV + =
(CV 1 + Ctune1 ) ⋅ (CV 2 + Ctune 2 )
CV 1 + Ctune1 + CV 2 + Ctune 2
(23)
The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250 fF for fine-tuning of the
FSK HIGH frequency. The switches of this C-bank are controlled by the bits D8 to D13 in the FSK register (subaddress 01H, see Table 25).
XOUT
16
X IN
18
L
-R
f, C L
16
X IN
18
XSW F
17
-R
f, C L
C V1
C V1
17
C tu ne 1
X S W A 19
XSW A 19
C V3
C V2
C tu n e2
C tu n e2
20
ASKswitch
FSK LO W
Figure 35
C V3
XGND
FSKswitch
20
ASKswitch
XGND
C tu ne 1
FSKswitch
XSW F
C V2
L
XOUT
F S K H IG H
FSK Modulation
In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. Thus
the frequency may be calculated as
fCOSC = fRF / 24,
(24)
e.g.
fCOSC = 434,15E6 / 24= 18.089583 MHz
which is identical to the ASK transmit case.
Data Sheet
71
Revision 1.1, 2010-11-10
TDA7255V
Application
XOUT
16
X IN
18
L
-R
f, C L
C V1
XSW F
C tu n e 1
17
XSW A 19
C V3
Figure 36
switch
FSK-
C tu n e 2
20
ASK-
XGND
switch
C V2
FSK Receive
In this case the ASK-switch is closed. The necessary Cvm is given by:
CV + =
(CV 1 + Ctune1 ) ⋅ (CV 2 + CV 3 + Ctune 2 )
CV 1 + Ctune1 + CV 2 + CV 3 + Ctune 2
(25)
The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250 fF for fine-tuning of the FSK receive
frequency. In this case the switches of the C-bank are controlled by the bits D0 to D5 of the XTAL_TUNING register
(sub-address 02H, see Table 24).
3.2.2.2
ASK-Mode
In transmit mode the crystal oscillator frequency is the same as in the FSK receive case, Figure 36.
In receive mode a receive frequency offset is necessary as the limiters feedback is AC-coupled. This offset is
achieved by setting the oscillator frequency to the FSK HIGH transmit frequency, Figure 35.
Data Sheet
72
Revision 1.1, 2010-11-10
TDA7255V
Application
3.2.3
Parasitics
For the correct calculation of the external capacitors the parasitic capacitances of the pins and the switches (C20,
C21, C22) have to be taken into account.
XOUT
L
16
-R
f, CL
XIN
18
CV1
C21
XSWF
Ctune1
17
XSWA 19
CV2
CV3
C22
XGND
20
Figure 37
Parasitics of the Switching Network
Table 22
Typical Values of Parasitic Capacitances
C20
Ctune2
Name
Value
C20
4,6 pF
C21
FSK_Low: 2,8 pF / FSK_High & ASK: 2.2 pF
C22
1 pF
With the given parasitics the actual Cv can be calculated:
CV − = CV 1 + Ctune1 + C21
CV + =
Cvm =
(CV 1 + Ctune1 )⋅ (CV 2 + C20 + Ctune2 ) + C
CV 1 + Ctune1 + CV 2 + C20 + Ctune 2
(26)
21
(CV 1 + Ctune1 )⋅ (CV 2 + C20 + CV 3 + C22 + Ctune2 ) + C
CV 1 + Ctune1 + CV 2 + C20 + CV 3 + C22 + Ctune2
(27)
21
(28)
Note: Please keep in mind also to include the Pad parasitics of the circuit board.
Data Sheet
73
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TDA7255V
Application
3.2.4
•
Calculation of the External Capacitors
Determination of necessary crystal frequency using Equation (20)
e.g. fFSK- = fCOSC LOW
Determine corresponding CLoad applying Equation (19)
e.g. CL FSK- = CL ±
Necessary Cv using Equation (18)
e.g.
•
•
CV − =
1
1
2
+ (2πf FSK − ) ⋅ LOSC
C L , FSK −
(29)
When the necessary Cv for the 3 frequencies (Cv for FSK LOW, Cv+ for FSK HIGH and Cvm for FSK-receive)
are known the external capacitors and the internal tuning caps can be calculated using the following formulas:
•
-FSK:
C
v1
+ C t une1 = C v- – C21
(30)
-FSK:
CV 2 + Ctune2 =
(CV 1 + Ctune1 ) ⋅ (CV + − C21 ) − C
(CV 1 + Ctune1 ) − (CV + − C21 ) 20
(31)
FSK_RX:
CV 3 + Ctune2 =
(CV 1 + Ctune1 ) ⋅ (CVm − C21 ) − C − C − C
20
V2
22
(CV 1 + Ctune1 ) − (CVm − C21 )
(32)
To compensate frequency errors due to crystal and component tolerance Cv1, Cv2 and Cv3 have to be varied. To
enable this correction, half of the necessary capacitance variation has to be realized with the internal C-banks.
If no fine-tuning is intended it is recommended to leave XIN (Pin 18) open. So the parasitic capacitance of Pin 18
has no effect.
Please keep in mind also to include the Pad parasitics of the circuit board.
In the suitable range for the serial capacitor, either capacitors with a tolerance of 0.1 pF or 1% are available.
A spreadsheet, which can be used to predict the total frequency error by simply entering the crystal specification,
may be obtained from Infineon.
Data Sheet
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Application
3.2.5
FSK-Switch Modes
The FSK-switch can be used either in a bipolar or in a FET mode. The mode of this switch is controlled by bit D0
of the XTAL_CONFIG register (sub-address 0EH).
In the bipolar mode the FSK-switch can be controlled by a ramp function. This ramp function is set by the bits D1
and D2 of the XTAL_CONFIG register (sub-address 0EH). With these modes of the FSK-switch the bandwidth of
the FSK spectrum can be influenced.
When working in the FET mode the power consumption can be reduced by about 200 μA.
The default mode is bipolar switch with no ramp function (D0 = 1, D1 = D2 = 0), which is suitable for all bitrates.
Sub Address 0EH: XTAL_CONFIG
Table 23
D0
D1
D2
Switch mode
Ramp time
Max. Bitrate
0
N.a.
N.a.
FET
< 0.2 μs
> 32 kBit/s NRZ
1
0
0
Bipolar (default)
< 0.2 μs
> 32 kBit/s NRZ
1
1
0
Bipolar
4 μs
32 kBit/s NRZ
1
0
1
Bipolar
8 μs
16 kBit/s NRZ
1
1
1
Bipolar
12 μs
12 kBit/s NRZ
3.2.6
Fine-tuning and FSK Modulation Relevant Registers
Case FSK-RX or ASK-TX (Ctune2):
Table 24
Sub Address 02H: XTAL_TUNING
Bit
Function
Value
Description
Default
D5
Nominal_Frequ_5
8 pF
0
D4
Nominal_Frequ_4
4 pF
D3
Nominal_Frequ_3
2 pF
Setting for nominal
frequency ASK-TX
FSK-RX (Ctune2)
D2
Nominal_Frequ_2
1 pF
0
D1
Nominal_Frequ_1
500 fF
1
D0
Nominal_Frequ_0
250 fF
0
1
0
Case FSK-TX or ASK-RX (Ctune1 and Ctune2)
Table 25
Sub Address 01H: FSK
Bit
Function
Value
Description
Default
D13
FSK_High_5
8 pF
0
D12
FSK_High_4
4 pF
D11
FSK_High_3
2 pF
Setting for positive
frequency shift: ASK-RX or
FSK_High (Ctune2)
D10
FSK_High_2
1 pF
0
D9
FSK_High_1
500 fF
1
D8
FSK_High_0
250 fF
0
Data Sheet
75
0
1
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Application
Table 25
Sub Address 01H: FSK (cont’d)
Bit
Function
Value
Description
Default
D5
FSK_Low_5
4 pF
0
D4
FSK_Low_4
2 pF
D3
FSK_Low_3
1 pF
Setting for negative
frequency shift:
FSK_Low (Ctune2)
D2
FSK_Low_2
500 fF
1
D1
FSK_Low_1
250 fF
0
D0
FSK_Low_0
125 fF
0
0
1
Default Values
In case of using the evaluation board, the crystal with its typical parameters (fp’ = fs’ = 18.089583 MHz, C1 = 8 fF,
C0 = 2,1 pF, CL = 20 pF) and external capacitors with Cv1 = 12 pF, Cv2 = 3.3 pF, Cv3 = 15 pF each are used the
following default states are set in the device.
Table 26
Default Oscillator Settings
Operating State
Frequency
ASK-TX / FSK-RX
434.15 MHz
FSK_High-TX / ASK-RX
+35 kHz
FSK_Low-TX
-35 kHz
3.2.7
Chip and System Tolerances
Quartz: fp’ = fs’ = 18.089583 MHz; C1 = 8 fF; C0 = 2,1 pF; CL = 20 pF (typical values)
Cv1 = 12 pF, Cv2 = 3.3 pF, Cv3 = 15 pF
Table 27
Internal Tuning
Part
Frequency Tlerance @ 434 MHz
Rel. Tolerance
Frequency set accuracy
+/- 1.3 kHz
+/- 3 ppm
Temperature (-40...+85 C)
+/- 3.5 kHz
+/- 8 ppm
Supply Voltage(2.1...5.5 V)
+/- 0.9 kHz
+/- 2 ppm
Total
+/- 5.7 kHz
+/- 13 ppm
Table 28
Default Setup (without Internal Tuning & without Pin21 Usage)
Part
Frequency Tolerance @ 434 MHz
Rel. Tolerance
Internal capacitors (+/- 10%)
+/- 3.5 kHz
+/- 8 ppm
Inductivity of the crystal oscillator +/- 11.4 kHz
+/- 26 ppm
Temperature (-40...+85°C)
+/- 3.5 kHz
+/- 8 ppm
Supply Voltage (2.1...5.5 V)
+/- 0.9 kHz
+/- 2 ppm
Total
+/- 19.3 kHz
+/- 44 ppm
Tolerance values in Table 27 are valid, if pin 21 is not connected. Establishing the connection to pin 21 the
tolerances increase by +/- 27 ppm (internal capacitors), if internal tuning is not used.
Concerning the frequency tolerances of the whole system also crystal tolerances (tuning tolerances, temperature
stability, tolerance of CL) have to be considered.
Data Sheet
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Application
In addition to the chip tolerances also the crystal and external component tolerances have to be considered in the
tuning and non-tuning case.
In case of internal tuning: The crystal on the evaluation board has a temperature stability of +/- 20 ppm (or +/8.7 kHz), which must be added to the total tolerances in worst case. It’s possible to choose a crystal compensating
the oscillators temperature drift in a certain range and thus the overall temperature tolerances are minimized.
In case of default setup (without internal tuning and without usage of pin 18) the temperature stability and tuning
tolerance of the crystal as well as the tolerance of the external capacitors (+/- 0.1 pF) have to be added. The crystal
on the evaluation board has a temperature stability of +/- 20 ppm (or +/- 8.7 kHz) and a tuning tolerance of
+/- 10 ppm (or +/- 4.4 kHz). The external capacitors add a tolerance of +/- 3.5 ppm (or +/- 1.5 kHz). Here also the
overall temperature tolerances can be reduced when applying an appropriate temperature drift of the crystal.
The frequency stabilities of both the receiver and the transmitter and the modulation bandwidth set the limit for the
bandwidth of the IQ filter. To achieve a high receiver sensitivity and efficient suppression of adjacent interference
signals, the narrowest possible IQ bandwidth should be realized (see Chapter 3.3).
3.3
IQ-Filter
The IQ-Filter should be set to values corresponding to the RF-bandwidth of the received RF signal via the D1 to
D3 bits of the LPF register (sub-address 03H).
Table 29
3dB Cutoff Frequencies I/Q Filter
D3
D2
D1
Nominal f-3dB in kHz (programmable)
0
0
0
Not used
0
0
1
350
700
0
1
0
250
500
0
1
1
200
400
1
0
0
150 (default)
300
1
0
1
100
200
1
1
0
50
100
1
1
1
Not used
Data Sheet
77
Resulting effective channel bandwidth in kHz
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Application
10
50kHz
100kHz
0
150kHz
- 10
200kHz
250kHz
-20
350kHz
-30
-40
-50
-60
-70
-80
10
10 0
10 0 0
10 0 0 0
f [ kHz]
Figure 38
I/Q Filter Characteristics
effective channel bandwidth
-f
Figure 39
Data Sheet
-f
f
3dB
IQ Filter
3dB
IQ Filter
f
IQ Filter and Frequency Characteristics of the Receive System
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3.4
Data Filter
The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the D4
to D7 bits of the LPF register (sub-address 03H).
Table 30
3 dB Cutoff Frequencies Data Filter
D7
D6
D5
D4
Nominal f-3dB in kHz
0
0
0
0
5
0
0
0
1
7 (default)
0
0
1
0
9
0
0
1
1
11
0
1
0
0
14
0
1
0
1
18
0
1
1
0
23
0
1
1
1
28
1
0
0
0
32
1
0
0
1
39
1
0
1
0
49
1
0
1
1
55
1
1
0
0
64
1
1
0
1
73
1
1
1
0
86
1
1
1
1
102
Data Sheet
79
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Application
3.5
Limiter and RSSI
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall
gain of approximately 80 dB each in the frequency range of 100 Hz up to 350 kHz. Receive Signal Strength
Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional
to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to
the nominal RSSI signal.
I- Filter
fg
Q- Filter
fg
Figure 40
31
C
RSSI
30
CQ2x
32
CQ2
33
CI2x
34
CQ1x
35
CQ1
CI1x
36
Cc
CI2
Cc
Cc
CI1
Cc
I
Limiter
27 RSSI
29
Quadr.
Corr.
37k
Σ
Q
Limiter
Quadr.
Corr.
Limiter and Pinning
The DC offset compensation needs 2.2 ms after Power On or Tx/Rx switch. This time is hard wired and
independent from external capacitors CC on pins 29 to 36. The maximum value for this capacitors is 47 nF.
RSSI accuracy settling time = 2.2 ms + 5*RC = 2.2 ms + 5*37k*2.2 nF = 2.6 ms
R - Internal resistor
C - External capacitor at Pin 27
Table 31
Limiter Bandwidth
Cc [nF]
f3dB Lower Limit [Hz]
f3dB Upper Limit
Comment
220
100
IQ Filter
Setup time not guaranteed
100
220
- ll -
Setup time not guaranteed
47
470
- ll -
Eval Board
22
1000
- ll -
10
2200
- ll -
Data Sheet
80
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Application
v [dB]
80
0
f3dB
lower limit
Figure 41
Data Sheet
f3dB
f3dB
IQ Filter
Limiter
f
Limiter Frequency Characteristics
81
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ADC
1300
1200
1100
1000
900
RSSI /mV
800
700
600
500
high gain
400
low gain
300
200
100
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
RF /dBm
Figure 42
Typ. RSSI Level (Eval Board) @ 3 V
3.6
Data Slicer - Slicing Level
The data slicer is an analog-to-digital converter. It is necessary to generate a threshold value for the negative
comparator input (data slicer). The TDA7255V offers an RC integrator and a peak detector which can be selected
via logic. Independent of the choice, the peak detector outputs are always active.
3.6.1
RC Integrator
Table 32
Sub Address 00H: CONFIG
Bit
Function
Description
Default
SET
D15
SLICER
0 = LP, 1 = Peak Detector
0
0
Necessary External Component (Pin10): CSLC
This integrator generates the mean value of the data filter output. For a stable threshold value, the cut-off
frequency has to be lower than the lowest signal frequency. The cutoff frequency results from the internal
resistance R = 100 kΩ and the external capacitor CSLC on Pin10.
Data Sheet
82
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Application
Cut-off frequency:
f
cut − off
=
1
< Min {f
2 π ⋅100 kΩ ⋅ C SLC
Signal
}
(33)
Component calculation: (rule of thumb)
TL – longest period of no signal change
C
SLC
≥
3 ⋅TL
100 kΩ
(34)
DataSlicer
+
Contr .
Logic
-
DATA
25
Slicer Threshold
+ Peak
Detector
PDP
9
100 k
Data
Filter
Signal
100k
SLC
10
R
CSLC
100 k
- Peak
Detector
PDN
8
VDD
Figure 43
Data Sheet
Slicer Level using RC Integrator
83
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3.6.2
Peak Detectors
Table 33
Sub Address 00H: CONFIG
Bit
Function
Description
Default
SET
D15
SLICER
0 = LP, 1 = Peak Detector
0
1
The TDA7255V has two peak detectors built in, one for positive peaks in the data stream and the other for the
negative ones.
Necessary External Components
Pin 8: CN
Pin 9: CP
DataSlicer
+
Contr.
Logic
DATA
25
Slicer Threshold
+ Peak
Detector
PDP
9
Data
Filter
Signal
CP
R1 100k
100 k
SLC
R
R2 100k
10
VDD
CN
- Peak
Detector
PDN
8
VDD
Figure 44
Slicer Level using Peak Detector
For applications requiring fast attack and slow release from the threshold value it is reasonable to use the peak
detectors. The threshold value is generated by an internal voltage divider. The release time is defined by the
internal resistance values and the external capacitors
τ
posPkD
=100 k Ω ⋅ C p
τ
negPkD
=100 k Ω ⋅ C
Data Sheet
(35)
n
(36)
84
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Application
Signal
τ posPkD
Signal
Pos. Peak Detector (pin13)
Threshold SLC(pin14)
Neg. Peak Detector (pin12)
τ negPkD
t
Figure 45
Peak Detector Timing
Component calculation: (rule of thumb)
Cp ≥
2 ⋅ TL1
100kΩ
(37)
TL1 – longest period of no signal change (LOW signal)
Cn ≥
2 ⋅ TL 2
100kΩ
(38)
TL2 – longest period of no signal change (HIGH signal)
Data Sheet
85
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Application
3.6.3
Peak Detector - Analog Output Signal
The TDA7255V data output can be digital (pin 25) or in analog form by using the peak detector output and
changing some settings.
To get an analog data output the slicer must be set to lowpass mode (Reg. 0, D15 = LP = 0) and the peak
detector capacitor at pin 8 or 9 has to be changed to a resistor of about 47 kΩ.
DataSlicer
+
Contr .
Logic
-
DATA
25
Slicer Threshold
+ Peak
Detector
PDP
9
47k
100 k
Data
Filter
Signal
100k
SLC
10
R
CSLC
100 k
- Peak
Detector
PDN
8
VDD
Figure 46
Data Sheet
Peak Detector as analog Buffer (v = 1)
86
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3.6.4
Peak Detector – Power Down Mode
For a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit
(Chapter 2.4.18) only after the entire receiving path is active.
In the off state the output of the positive peak detector is tied down to GND and the output of the negative peak
detector is pulled up to VCC.
Logic
Power Down Mode
0V
+ Peak
Detector
PDP
9
off
CP
Data
Filter
R1
100 k
R2
100 k
SLC
10
CN
- Peak
Detector
PDN
8
off
VDD
Figure 47
VDD
VDD
Peak Detector - Power Down Mode
Signal
Data Signal
Vcc
Neg. Peak Detector (pin 8)
Threshold (pin 10)
Power ON
Figure 48
Data Sheet
2,2ms
Pos. Peak Detector (pin 9)
0
Power Down
Power ON
Peak Detector Power ON
t
Power Down Mode
87
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3.7
Data Valid Detection
In order to detect valid data two criteria must be fulfilled.
One criteria is the data rate, which can be set in register 06h and 07h. The other one is the received RF power
level, which can be set in register 08h in form of the RSSI threshold voltage. Thus for using the data valid detection
FSK modulation is recommended.
Timing for data detection looks like the following. Two settings are possible: „Continuous“ and „Single Shot“, which
can be set by D5 and D6 in register 00H.
Data
t
Sequencer enables
data detection
t
Counter Reset
reset
reset
t
Gate time
Compare with single
TH and latch result
count
count
t
comp.
comp.
t
Compare with double
TH and latch result
comp.
t
(Frequency) Window
Count Complete
start of conversion
Figure 49
ready*
t
possible start of next conversion
Frequency Detection Timing in Continuous Mode
Note:
1. Chip internal signal „Sequencer enables data detection“ has a LOW to HIGH transition about 2.6 ms after RX
is activated (see Figure 17).
2. The positive edge of the „Window Count Complete“ signal latches the result of comparison of the analog to
digital converted RSSI voltage with TH3 (register 08H). A logic combination of this output and the result of the
comparison with single/double THx defines the internal signal „data_valid“.
Figure 49 shows that the logic is ready for the next conversion after 3 periods of the data signal.
Timing in Single Shot mode can be seen in the subsequent figure:
Data Sheet
88
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TDA7255V
Application
Data
t
Sequencer enables
data detection
t
Counter Reset
reset
t
Gate time
count
t
Compare with single
TH and latch result
comp.
t
Compare with double
TH and latch result
comp.
t
(Frequency) Window
Count Complete
ready*
t
no possible start of next conversion
because of Single Shot Mode
start of conversion
Figure 50
Frequency Detection Timing in Single Shot Mode
3.7.1
Frequency Window for Data Rate Detection
The high time of data is used to measure the frequency of the data signal. For Manchester coding either the data
frequency or half of the data frequency have to be detected corresponding to one high time or twice the high time
of data signal.
A time period of 3*2*T is necessary to decide about valid or invalid data.
T
2*T
DATA
t
0
0
1
0
T2
T1
possible
GATE 1
t
0
2*T2
2*T1
possible
GATE 2
t
0
Figure 51
Data Sheet
1
Window Counter Timing
89
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Application
Example to calculate the Thresholds for a given Data Rate
•
•
•
Data signal Manchester coded
Data Rate: 2 kbit/s
fclk = 18,089583 MHz
Then the period equals to
2⋅T =
1
= 0,5ms
2kbit/s
(39)
respectively the high time is 0,25 ms.
We set the thresholds to +-10% and get: T1 = 0,225 ms and T2 = 0,275 ms
The thresholds TH1 and TH2 are calculated with following formulas
TH1 = T1 ⋅
f clk
4
TH2 = T2 ⋅
(40)
f clk
4
(41)
This Yields the following Results
TH1~ 1017 = 001111111001b
TH2~ 1243 = 010011011011b
which have to be programmed into the D0 to D11 bits of the COUNT_TH1 and COUNT_TH2 registers
(sub-addresses 06H and 07H), respectively.
Default Values (window counter inactive)
TH1 = 000000000000b
TH2 = 000000000001b
Note: The timing window of +/-10% of a given high time T in general does not correspond to a frequency window
+/-10% of the calculated data frequency.
3.7.2
RSSI Threshold Voltage - RF Input Power
The RF input power level is corresponding to a certain RSSI voltage, which can be seen in Chapter 3.5. The
threshold TH3 of this RSSI voltage can be calculated with the following formula:
TH 3 =
desired RSSI threshold voltage
⋅ (2 6 − 1)
1.2V
(42)
As an example a desired RSSI threshold voltage of 500 mV results in TH3~26 = 011010b, which has to be written
into D0 to D5 of the RSSI_TH3 register (sub address 08H).
Default Value (RSSI detection inactive)
TH3 = 111111b
Data Sheet
90
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Application
3.8
Calculation of ON_TIME and OFF_TIME
ON = (216-1) - (fRC*tON)
(43)
OFF = (216-1) - (fRC*tOFF)
(44)
fRC = Frequency of internal RC-Oscillator
Example: tON = 0,005 s, tOFF = 0,055s, fRC = 32300 Hz
ON = 65535-(32300*0,005) ~ 65373 = 1111111101011101b
OFF = 65535-(32300*0,055) ~ 63758 = 1111100100001110b
The values have to be written into the D0 to D15 bits of the ON_TIME and OFF_TIME registers (sub-addresses
04H and 05H).
Default Values
ON = 65215 = 1111111011000000b
OFF = 62335 = 1111001110000000b
tON ~10 ms @ fRC = 32 kHz
tOFF ~100 ms @ fRC = 32 kHz
Data Sheet
91
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Application
3.9
Example for Self Polling Mode
The settings for Self Polling Mode depend very much on the timing of the transmitted Signal. To create an example
we consider following data structure transmitted in FSK.
4 Frames
Data
Data
Data
Data
t [ms]
50ms 50ms
400ms
Framedetails
t [ms]
Preamble
Data
Sync
t [ms]
Synchronisation Preamble
Figure 52
Example for transmitted Data-Structure
According to existing synchronization techniques there are some synchronization bursts in front of the data added
(code violation!). A minimum of 4 Frames is transmitted. Data are preferably Manchester encoded to get fastest
respond out of the Data Rate Detection.
Target Application
•
•
•
Received Signal has code violation as described before
Total mean current consumption below 1 mA
Data reception within max. 400 ms after first transmitted frame
One possible Solution
tON = 15 ms, tOFF = 135 ms
This gives 15 ms ON time of a total period of 150 ms which results in max. 0.9 mA mean current consumption in
Self Polling Mode. The resulting worst case timing is shown in the following figure:
Data Sheet
92
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Application
Case A:
Data
Data
50ms 15ms
Data
135ms
Data
t [ms]
µP enables Receiver
until Data completed
Interrupt
due PWDDD
Case B:
Data
50ms
Data
15ms
Data
135ms
Data
t [ms]
µP enables Receiver
until Data completed
Interrupt
due PWDDD
Case C:
Data
50ms
Data
15ms
Data
135ms
t [ms]
µP enables Receiver
until Data completed
Interrupt
due PWDDD
... Receiver enabled
Figure 53
Data
3 Possible Timings
Description
Assumption: the ON time comes right after the first frame (Case A). If OFF time is 135 ms the receiver turns on
during Sync-pulses and the PWDDD- pulse wakes up the μP.
If the ON time is in the center of the 50 ms gap of transmission (Case B), the Data Detect Logic will wake up the
μP 135 ms later.
If ON time is over just before Sync-pulses (Case C), next ON time is during Data transmission and Data Detect
Logic will trigger a PWDDD- pulse to wake up the μP.
Note: In this example it is recommended to use the Peak Detector for slicer threshold generation, because of its
fast attack and slow release characteristic. To overcome the data zero gap of 50 ms larger external
capacitors than noted in Chapter 4.4 at pin12 and 13 are recommended. Further information on calculating
these components can be taken from Chapter 3.6.2.
Data Sheet
93
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Application
3.10
Default Setup
Default setup is hard wired on chip and effective after a reset or return of power supply.
Table 34
Default Setup
Parameter
Value
IQ-Filter Bandwidth
150 kHz
Data Filter Bandwidth
7 kHz
Limiter lower fg
470 Hz
47 nF
Slicing Level Generation
RC
10 nF
Nom. Frequency Capacity intern (ASK TX, FSK RX)
4.5 pF
434.16 MHz
FSK_High Frequency Capacity intern (FSK_High, ASK RX)
2.5 pF
+35 kHz
FSK_Low Frequency Capacity intern (FSK_Low)
1.5 pF
-35 kHz
LNA Gain
HIGH
Power Amplifier
HIGH
+10 dBm
RSSI accuracy settling time
2.6 ms
2.2 nF
ADC measurement
RSSI
ON-Time
10 ms
OFF-Time
100 ms
Clock out RX PowerON
1 MHz
Clock out TX PowerON
1 MHz
Clock out RX PowerDOWN
-
Clock out TX PowerDOWN
-
XTAL modulation switch
Bipolar
XTAL modulation shaping
Off
RX/TX
-
Jumper
ASK/FSK
-
Jumper
PWDDD
PWDN
Jumper removed
Operating Mode
Slave
Data Sheet
94
IFX-Board
Comment
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
4
Reference Data
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Table 35
WARNING
TDA7255V is intended for use in general electronic equipment (AV equipment, telecommunication
equipment, home appliances, amusement equipment, computer equipment, personal equipment, office
equipment, measurement equipment) under a normal operation and use condition.
Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum
ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the
integrated circuit.
Table 36
Absolute Maximum Ratings
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Note /
Test Condition
Test Number
Supply Voltage
VCC/VDD
-0.3
5.8
V
■
1.1
Junction
Temperature
Tj
-40
+125
°C
■
1.2
Storage
Temperature
Ts
-40
+125
°C
■
1.3
Thermal
Resistance
RthJA
■
die pad not
soldered, no vias
1.4
50
K/W
die pad soldered,
and vias
30
ESD HBM integrity
(all pins)
4.1.2
VESD-HBM
-1.0
+1.0
kV
AEC Q100-002
EIA/JESD22A114
■
1.5
Operating Range
Within the operational range the IC operates as explained in the circuit description.
Table 37
Operating Range
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Note /
Test Condition
Test Number
Supply voltage
VCC/VDD
2.1
5.5
V
■
2.1
Ambient
temperature
TA
-40
+85
°C
■
2.2
Data Sheet
95
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Table 37
Operating Range (cont’d)
Parameter
Symbol
Values
Min.
Receive frequency
Typ.
Unit
Max.
Note /
Test Condition
Test Number
fRX
433
435
MHz
■
2.3
Transmit frequency fTX
433
435
MHz
■
2.4
Data Sheet
96
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
4.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production.
Table 38
AC/DC Characteristics with TAMB = 25 °C, VCC = 2.1 ... 5.5 V
Parameter
Symbol
Values
Min.
Typ.
Unit
Note / Test Condition Test Number
Max.
RECEIVER Characteristics
Supply current RX FSK
IRX_FSK
9
mA
3 V, FSK, Default
3.1
Supply current RX FSK
IRX_FSK
9.5
mA
5 V, FSK, Default
3.2
Supply current RX ASK
IRX_ASK
8.6
mA
3 V, ASK, Default
3.3
Supply current RX ASK
IRX_ASK
9.1
mA
5 V, ASK, Default
3.4
Sensitivity FSK
10-3 BER
RFsens
-115
dBm
■
FSK @ 35 kHz,
4 kBit/s Manch. Data,
Default
5 kHz datafilter, 50 kHz
IQ filter
3.5
Sensitivity ASK
10-3 BER
RFsens
-112
dBm
ASK, 4 kBit/s Manch.
data, Default setup
5 kHz datafilter,
50 kHz IQ filter
3.6
Input reflection
coefficient (S11)
fRF = 868 MHz
S11
0.958 /
-20 deg
Power down current
IPWDN_RX
5
System setup time
(1st power on or reset)
tSYSSU
Clock Out setup time
tCLKSU
Receiver setup time
tRXSU
1.54
2.2
Data detection setup
time
tDDSU
1.82
RSSI stable time
tRSSI
1.82
Data valid time
tData_Valid
Input P1dB, high gain
4
3.7
nA
8
■
12
0.5
5.5 V, all power down
3.8
ms
3.9
ms
Stable CLKDIV output
signal
3.10
2.86
ms
DATA out (valid or
invalid)
3.11
2.6
3.38
ms
Begin of Data detection
3.12
2.6
3.38
ms
RFin -100 dBm
see Chapter 4.5
3.13
3.35
ms
4 kBit/s Manch.
detected (valid)
3.14
P1dB
-63dBm
dBm
3 V, Default, high gain
■
3.15
Input P1dB, low gain
P1dB_low
-42dBm
dBm
3 V, Default, low gain
■
3.16
Selectivity
VBL_1MHz
-55
dB
tRF+/-1 MHz, Default,
■
3.17
■
3.18
RFsens+3 dB
LO leakage
PLO
-108
dBm
578,9 MHz
10,7
mA
2.1 V, high power
TRANSMITTER Characteristics
Supply current TX, FSK ITX
Data Sheet
97
3.19
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Table 38
AC/DC Characteristics with TAMB = 25 °C, VCC = 2.1 ... 5.5 V (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Unit
Note / Test Condition Test Number
Max.
Supply current TX, FSK ITX
13,5
mA
3 V, high power
3.20
Supply current TX, FSK ITX
18,3
mA
5 V, high power
3.21
Output power
Pout
+6
dBm
2.1 V, high power
■
3.22
Output power
Pout
9
dBm
3 V, high power
■
3.23
Output power
Pout
13
dBm
5 V, high power
■
3.24
Supply current TX, FSK ITX
5
mA
2.1 V, low power
3.25
Supply current TX, FSK ITX
7.5
mA
3 V, low power
3.26
Supply current TX, FSK ITX
15
mA
5 V, low power
3.27
Output power
Pout_low
-32
dBm
2.1 V, low power
■
3.28
Output power
Pout_low
-1
dBm
3 V, low power
■
3.29
Output power
Pout_low
11
dBm
5 V, low power
■
3.30
Power down current
IPWDN_TX
5
nA
5.5 V, all power down
3.31
Clock-Out setup time
tCLKSU
0.5
ms
Stable CLKDIV output
signal
3.32
Transmitter setup time
tTXSU
ms
PWDN-->PON or
RX-->TX
■
3.33
Spurious fRF+/-fclock
Pclock
-59
dBm
3 V, 50 Ω Board,
Default (1 MHz)
■
3.34
Spurious fRF+/-fXTAL
P1st
-74
dBm
3 V, 50 Ω Board
■
3.35
harmonic
P2nd
-43
dBm
3 V, 50 Ω Board
■
3.36
Spurious 3rd harmonic
P3rd
-43
dBm
3 V, 50 Ω Board
■
3.37
Spurious 2
nd
0.77
1.1
1.43
1: including pin diode current (RX/TX-switch)
130 uA @ 2.1 V; 310 uA @ 3 V; 720 uA @ 5 V
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
Data Sheet
98
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Table 39
AC/DC Characteristics with TAMB = 25 °C, VCC = 2.1 ... 5.5 V
Parameter
Symbol
Values
Min.
Typ.
Unit
Note /
Test Condition
Max.
Test Num
ber
GENERAL Characteristics
Power down current
timer mode (standby)
IPWDN_32k
9
uA
3 V, 32 kHz clock on
4.1
Power down current
timer mode (standby)
IPWDN_32k
11
uA
5 V, 32 kHz clock on
4.2
Power down current
with XTAL ON
IPWDN_Xtl
750
uA
3 V, CONFIG9 = 1
4.3
Power down current
with XTAL ON
IPWDN_Xtl
860
uA
5 V, CONFIG9 = 1
4.4
32 kHz oscillator freq. f32 kHz
24
32
40
kHz
XTAL startup time
tXTAL
0.3
ms
Load capacitance
CC0max
5
Serial resistance of the Rmax
crystal
100
4.5
■
4.6
pF
■
4.7
Ω
■
4.8
IFX Board with
Crystal Q1 as
specified in
Chapter 4.4
Input inductance
XOUT
LOSC
2.7
uH
With pad on
evaluation board
■
4.9
Input inductance
XOUT
LOSC
2.45
uH
Without pad on
evaluation board
■
4.10
FSK demodulator gain GFSK
2.4
mV/k
Hz
RSSI @ -120 dBm
U-120 dBm
0.4
V
Default setup
■
4.12
RSS I@ -100 dBm
U-100 dBm
0.6
V
Default setup
■
4.13
RSSI @ -70 dBm
U-70 dBm
0.96
V
Default setup
■
4.14
RSSI @ -50 dBm
U-50 dBm
1.1
V
Default setup
■
4.15
RSSI Gradient
GRSSI
12
mV/d
B
Default setup
■
4.16
IQ-Filter bandwidth
f3dB_IQ
115
150
185
kHz
Default setup
■
4.17
Data-Filter bandwidth
f3dB_LP
5.3
7
8.7
kHz
Default setup
■
4.18
VCC-Vtune RX, Pin3
Vcc-tune,RX
0.5
1
1.6
V
fRef = 18.08956 MHz
4.19
VCC-Vtune TX, Pin3
Vcc-tune,TX
0.5
1.1
1.6
V
fRef = 18.08956 MHz
4.20
4.11
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
Data Sheet
99
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
4.1.4
Digital Characteristics
BusMode = LOW
t BUF
BusData
tR
tLOW
tHD.ST
BusCLK
tHD.DA
A
tHD.ST
tF
tHIGH
T
t SU.DA
tSU.ST
T
A
tSP
tSU.ST
O
A
tHIGH
EN
pulsed or
mandatory low
tSU.ENASDA
tSU.ENASDA
t SU.ENASDA
Figure 54
I2C Bus Timing
BUS_MODE = HIGH
SDA
tLOW
SCL
tSU.ST
tR
A
t SP
tF
tHD.DA
T
tHIGH
tSU.DA
T
tSU.ST
O
BUS_ENA
t WHEN
Figure 55
Data Sheet
3-Wire Bus Timing
100
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Table 40
Digital Characteristics with TAMB = 25 °C, VDD = 2.1 ... 5.5 V
Parameter
Symbol
Values
Min.
Unit
Note /
Test Condition
Test Number
Typ.
Max.
fTX.ASK
10
100
kBaud
PRBS9, Manch.
@+9 dBm
■
5.1
Data rate TX FSK1)
fTX.FSK
10
32
kBaud
PRBS9, Manch.
@+9 dBm
@35 kHz dev.
■
5.2
Data rate RX ASK
fRX.ASK
10
50
kBaud
PRBS9, Manch.
■
5.3
Data rate RX FSK
fRX.FSK
10
64
kBaud
PRBS9, Manch.
@100 kHz dev.
■
5.4
Data rate RX FSK
fRX.FSK
10
28.8
kBaud
PRBS9, Manch.
@35 kHz dev.
■
5.5
Digital inputs
High-level input voltage
Low-level input voltage
■
5.6
VIH
VIL
VDD-0.2
VDD
0
0.2
V
V
@VDD = 3 V
Isink = 800 uA
Isink = 3 mA
■
5.7
■
5.8
Data rate TX ASK
1)
RXTX Pin 5
TX operation
int. controlled
VOL
0.4
1.15
V
V
35
30
ns
ns
VDD-0.4
V
V
@VDD = 3 V
Load 10 pF
Load 10 pF
Isource = 350 uA
Isink = 400 uA
50
ns
VDD = 5 V
■
5.9
0.4
V
3 mA sink current
VDD = 5V
■
5.11
400
kHz
VDD=5 V
■
5.12
■
5.13
CLKDIV Pin 26
trise (0.1*VDDto 0.9*VDD) tr
tfall (0.9*VDD to 0.1*VDD) tf
Output High Voltage
VOH
Output Low Voltage
VOL
0.4
Bus Interface Characteristics
Pulse width of spikes
tSP
which must be
suppressed by the input
filter
LOW level output
voltage at BusData
VOL
SLC clock frequency
fSLC
0
0
2
Bus free time between
STOP and START
condition
fBUF
1.3
Hold time (repeated)
START condition.
tHO.STA
0.6
μs
■
After this period,
the first clock pulse
is generated, only
I2C
5.14
LOW period of BusCLK
clock
tLOW
1.3
μs
VDD = 5 V
■
5.15
HIGH period of BusCLK tHIGH
clock
0.6
μs
VDD = 5 V
■
5.16
Data Sheet
μs
Only I C mode
VDD = 5 V
101
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Table 40
Digital Characteristics with TAMB = 25 °C, VDD = 2.1 ... 5.5 V (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Unit
Note /
Test Condition
Test Number
Max.
Setup time for a
repeated START
condition
tSU.STA
0.6
μs
Only I2C mode
■
5.17
Data hold time
tHD.DAT
0
ns
VDD = 5 V
■
5.18
Data setup time
tSU.DAT
100
ns
VDD = 5 V
■
5.19
Rise, fall time of both
BusData and BusCLK
signals2)
tR, tF
20+
0.1Cb
ns
VDD = 5 V
■
5.20
Setup time for STOP
condition
tSU.STO
0.6
μs
Only I2C mode
VDD = 5 V
■
5.21
pF
VDD = 5 V
■
5.22
Capacitive load for each Cb
bus line
300
400
Setup time for BusCLK
to EN
tSU.SCLEN
0.6
μs
Only 3-wire mode
VDD = 5 V
■
5.23
H-pulsewidth (EN)
tWHEN
0.6
μs
VDD = 5 V
■
5.24
1) Limited by transmission channel bandwidth and depending on transmit power level; ETSI regulation EN 300 220 fulfilled,
see Chapter 3.1
2) Cb = capacitance of one bus line
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
Data Sheet
102
Revision 1.1, 2010-11-10
X8
3
2
1
C4
R22
C5
L1
R2
X1
C8
C3
C26
C2
L3
C7
R1
1 X7
2
3
C10
R23
C24
R3
C12
C29
C14
C13
C27
ASKFSK
RXTX
LIN
LINX
GND_RF
PA
VCC1
PDN
PDP
SLC
VDD
BUSDATA
C16
D1
L2
1
2
3
4
5
6
7
8
9
10
11
12
CI2
CI2X
CQ2
CQ2X
GND
RSSI
GND2
DATA
PWDDD
CLKDIV
RESET
EN
TDA7255V
C15
C11
C28
40
39
38
37
36
35
34
33
GND3
LF
BUSMODE
VCC
CI1
CI1X
CQ1
CQ1X
GND1
BUSCLK
VSS
XOUT
XSWF
XIN
XSWA
XGND
Q1
13
14
15
16
17
18
19
20
C6
C1
C9
32
31
30
29
28
27
26
25
24
23
22
21
R18
D2
C17
C21
C22
C19
C20
R7
1 X2
2
R20
C23
C31
R21
EN
BUSCLK
BUSDATA
R19
1 X16
2
RSSI
JP2
C18
BUSMODE
R24
JP5
2
1
JP1
X14
1 X15
2
1 X3
2
DATA-MC
JP3
RESET
S1
PWDDD
5
3
1
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
2
4
6
8
BUSMODE
10
12
SCK
14
SDI
16
SDO
18
DATA-MC
PWDDDNACHJUMPER 20
EN
CS_E
CS_E
SDI
SCK
P$1 P$20
P$2 P$19
P$3 P$18
P$4 P$17
P$5 P$16
P$6 P$15
P$7 P$14
P$8 P$13
P$9 P$12
P$10 P$11
U$1
CS
SI
SCK
IC2
P$21
P$1 P$20
P$2 P$19
P$3 P$18
P$4 P$17
P$5 P$16
P$6 P$15
P$7 P$14
P$8 P$13
P$9 P$12
P$10 P$11
U$2
G1
P$21
P$1 P$20
P$2 P$19
P$3 P$18
P$4 P$17
P$5 P$16
P$6 P$15
P$7 P$14
P$8 P$13
P$9 P$12
P$10 P$11
U$3
G1
P$21
103
G1
GND
SO
VCC
6
1
3
5
7
9
11
13
15
17
19
1
3
5
7
9
11
13
15
17
19
1
3
5
7
9
11
13
15
17
19
2
EEPROM
Array
P$22
G2
P$22
Data Sheet
G2
Figure 56
P$22
4
RESET
BUSCLK
BUSDATA
RSSI
SDO
4.2
G2
JP4
TDA7255V
Reference Data
Test Circuit
The device performance parameters marked with X in Chapter 4.1.3 were measured on an Infineon evaluation
board (IFX board).
Schematic of the Evaluation Board
Revision 1.1, 2010-11-10
C25
C30
TDA7255V
Reference Data
4.3
Test Board Layout
Gerber-files for this Testboard are available on request.
1
3
1
2
2
1
3
Figure 57
Top Layer of the Customer Board TDA7255V
Figure 58
Bottom Layer of the Customer Board TDA7255V
Data Sheet
104
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Notes
1. The LNA and PA matching network was designed for minimum required space and maximum performance
and thus via holes were deliberately placed into solder pads.
In case of reproduction please bear in mind that this may not be suitable for all automatic soldering processes.
2. Please keep in mind not to layout the CLKDIV line directly in the neighborhood of the crystal and the associated
components.
3. Difference in supply voltage especially between pin 1 and pin 15 is recommended to be lower than 30 mV,
therefore a serial resistor in the VDD supply line, as mentioned on page 15 and in Chapter 4.4, is strongly
recommended.
Figure 59
Data Sheet
Placement of connectors and jumpers (axial)
105
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Figure 60
Placement of connectors and jumpers (SMD)
Initially JP2 (Data to UWLink), JP3 (RESET via UWLink), JP4 (Supply via UWLink) and JP5 (PWDDD via UWLink)
are open. Closing JP2 enables to apply a PRBS9 data sequence from 200 bit/s up to 80kbit/s to the data input
(DATA) in case of transmit mode by the TDA7255V Explorer. Closing JP5 enables to control the PDWDDD-pin via
the TDA7255V Explorer. A supply voltage of ~3.3 V for the TDA7255V Extension Board can be provided from the
UWLink board when closing JP4. But don’t forget to remove the external supply in that case.
Opening JP1 and closing JP3 enables the facility to RESET the TDA7255V by clicking the reset button at the
TDA7255V Explorer.
Data Sheet
106
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
4.4
Bill of Materials
Table 41
Bill of Materials
Reference
Value
Specification
Tolerance
R1
4 k7
0402
+/-5%
R2
0
0402
+/-5%
R3
---
0402
+/-5%
R6
---
0402
+/-5%
R7
4 k7
0402
+/-5%
R18
1M
0402
+/-5%
R19
560
0402
+/-5%
R20
1k
0402
+/-5%
R21
0
0402
+/-5%
R22
0
0402
+/-5%
R23
10
0402
+/-5%
R24
180
0402
+/-5%
C1
33 pF
0402
+/-5%
C2
1,8 pF
0402
+/-0,1 pF
C3
27 pF
0402
+/-1%
C4
12 pF
0402
+/-0,1 pF
C5
1 nF
0402
+/-5%
C6
1 nF
0402
+/-5%
C7
10 pF
0402
+/-0,1 pF
C8
---
0402
+/-0,1 pF
C9
27 pF
0402
+/-1%
C10
100 pF
0402
+/-5%
C11
---
0402
+/-5%
C12
10 nF
0402
+/-10%
C13
10 nF
0402
+/-10%
C14
10 nF
0402
+/-10%
C15
12 pF
0402
+/-0,1 pF
C16
3.3 pF
0402
+/-0,1 pF
C17
15 pF
0402
+/-1%
C18
10 nF
0402
+/-10%
C19
2,2 nF
0402
+/-10%
C20
47 nF
0402
+/-10%
C21
47 nF
0402
+/-10%
C22
47nF
0402
+/-10%
C23
47 nF
0402
+/-10%
C24
100 nF
0402
+/-10%
Data Sheet
107
Revision 1.1, 2010-11-10
TDA7255V
Reference Data
Table 41
Bill of Materials (cont’d)
Reference
Value
Specification
Tolerance
C25
100 nF
0402
+/-10%
C26
100 nF
0402
+/-10%
C27
100 nF
0402
+/-10%
C28
100 nF
0402
+/-10%
C29
100 nF
0402
+/-10%
C30
100 nF
0402
+/-10%
C31
100 nF
0402
+/-10%
L1
100 nH
Coilcraft SIMID 0402HP, + 2%
+/-2%
L2
12 nH
Coilcraft SIMID 0402HP, + 2%
+/-2%
L3
36 nH
Coilcraft SIMID 0402HP, + 2%
+/-2%
IC1
TDA7255V
PG-VQFN-40
IC2
25AA040AT
EEPROM 4KB (MICROCHIP)
Q1
18.089583 MHz
Hertz: TSS-6035
Spec.-Nr.: 1053-935
S1
1-pol. push-button
MULTICOMP
MCTAEF-25N-V
D1, D2
BAR63-02W
SCD-80 (Infineon)
X1
SMA-socket
X2, X3, X14, X15, X16
2-pol.
2-pole pin connector 2,54 mm
X7, X8
3-pol.
3-pole pin connector 2,54 mm
JP1
Solder bridge
Solder bridge closed
JP2, JP3, JP4, JP5
Solder bridge
Solder bridge open
U$1, U$2, U$3
20-pol. connector
Hirose: DF12(3.5)-20DS-0.5 V
C1 = 8 fF,
C0 = 2.1 pF,
CL = 20 pF
Note: Serial resistors in supply lines (R21, R22, R23) should be equipped as shown in the table above.
Data Sheet
108
Revision 1.1, 2010-11-10
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