TDK5100XUMA1

Wireless Components ASK/FSK Transmitter 868/433 MHz TDK 5100 Version 1.1 Specification May 2012 Preliminary Revision History Current Version: Version 1.1 as of 09.05.2012 Previous Version: Version 1.0 as of 31.10.2002 Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) Product Info Product Info Package Info corrected to PG-TSSOP-16 Ordering Code corrected to SP000014557 ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. Edition 09.05.2012 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg © Infineon Technologies AG 2012. All Rights Reserved. Attention please! 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Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. TDK 5100 Product Info Product Info General Description Features Package The TDK 5100 is a single chip ASK/ FSK transmitter for the frequency bands 433-435 and 868-870 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additionally features like a power down mode, a low power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation. - Applications Ordering Information - fully integrated frequency synthesizer VCO without external components ASK and FSK modulation switchable frequency range 433-435 MHz / 868-870 MHz high efficiency power amplifier (typically 5 dBm / 2 dBm) low supply current (typically 7mA) - temperature range -40 ... +125°C power down mode low voltage sensor selectable crystal oscillator 6.78 MHz / 13.56 MHz - programmable divided clock output - for µC low external component count voltage supply range 2.1 - 4 V Keyless entry systems Remote control systems - Alarm systems Communication systems Type Ordering Code Package TDK 5100 SP000014557 PG-TSSOP-16 available on tape and reel Wireless Components Product Info Specification, May 2012 1 Product Description Contents of this Chapter 1.1 1.2 1.3 1.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 TDK 5100 1.1 Overview The TDK 5100 is a single chip ASK/FSK transmitter for the frequency bands 433-435 MHz and 868-870 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features like a power down mode, a low power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation. 1.2 Applications - Keyless entry systems Remote control systems Alarm systems Communication systems 1.3 Features - Wireless Components fully integrated frequency synthesizer VCO without external components ASK and FSK modulation switchable frequency range 433-435 MHz / 868-870 MHz high efficiency power amplifier (typically 5 dBm / 2 dBm) low supply current (typically 7 mA) voltage supply range 2.1 - 4 V temperature range -40°C ... 125°C power down mode low voltage sensor selectable crystal oscillator 6.78 MHz / 13.56 MHz programmable divided clock output for µC low external component count 1-2 Specification, May 2012 TDK 5100 1.4 Package Outlines Figure 1-1 Wireless Components PG-TSSOP-16 1-3 Specification, May 2012 2 Functional Description Contents of this Chapter 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Recommended timing diagrams for ASK- and FSK-Modulation . . 2-12 TDK 5100 2.1 Pin Configuration PDWN 1 16 CSEL LPD 2 15 FSEL VS 3 14 PAOUT LF 4 13 PAGND GND 5 12 FSKGND ASKDTA 6 11 FSKOUT FSKDTA 7 10 COSC CLKOUT 8 9 TDK 5100 CLKDIV Pin_config.wmf Figure 2-1 IC Pin Configuration Table 2-1 Wireless Components Pin No. Symbol Function 1 PDWN Power Down Mode Control 2 LPD Low Power Detect Output 3 VS Voltage Supply 4 LF Loop Filter 5 GND 6 ASKDTA Amplitude Shift Keying Data Input 7 FSKDTA Frequency Shift Keying Data Input 8 CLKOUT Clock Driver Output 9 CLKDIV Clock Divider Control (847.5 kHz or 3.34 MHz) 10 COSC 11 FSKOUT Frequency Shift Keying Switch Output 12 FSKGND Frequency Shift Keying Ground 13 PAGND Power Amplifier Ground 14 PAOUT Power Amplifier Output 15 FSEL Frequency Range Selection (433 or 868 MHz) 16 CSEL Crystal Frequency Selection (6.78 or 13.56 MHz) Ground Crystal Oscillator Input 2-2 Specification, May 2012 TDK 5100 2.2 Pin Definitions and Functions Table 2-2 Pin No. Symbol 1 PDWN Function Interface Schematic*) Disable pin for the complete transmitter circuit. VS 40 μA ∗ (ASKDTA+FSKDTA) A logic low (PDWN < 0.7 V) turns off all transmitter functions. 5 kΩ A logic high (PDWN > 1.5 V) gives access to all transmitter functions. 1 "ON" 150 kΩ PDWN input will be pulled up by 40 µA internally by either setting FSKDTA or ASKDTA to a logic high-state. 250 kΩ 2 LPD This pin provides an output indicating the low-voltage state of the supply voltage VS. VS VS < 2.15 V will set LPD to the low-state. 40 µA 2 300 Ω 3 VS Wireless Components An internal pull-up current of 40 µA gives the output a high-state at supply voltages above 2.15 V. This pin is the positive supply of the transmitter electronics. An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 5) as short as possible. 2-3 Specification, May 2012 TDK 5100 4 LF Output of the charge pump and input of the VCO control voltage. The loop bandwidth of the PLL is 150 kHz when only the internal loop filter is used. The loop bandwidth may be reduced by applying an external RC network referencing to the positive supply VS (pin 3). VS 140 pF 15 pF 35 kΩ 10 kΩ VS 4 5 GND 6 ASKDTA General ground connection. VS Digital amplitude modulation can be imparted to the Power Amplifier through this pin. +1.2 V 60 kΩ 6 +1.1 V 90 kΩ 50 pF 7 FSKDTA VS 30 μA A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier. A logic low (ASKDTA < 0.5 V) disables the Power Amplifier. Digital frequency modulation can be imparted to the Xtal Oscillator by this pin. The VCO-frequency varies in accordance to the frequency of the reference oscillator. +1.2 V 60 kΩ 7 +1.1 V 90 kΩ 30 μA A logic high (FSKDTA > 1.5V or open) sets the FSK switch to a high impedance state. A logic low (FSKDTA < 0.5 V) closes the FSK switch from FSKOUT (pin 11) to FSKGND (pin 12). A capacitor can be switched to the reference crystal network this way. The Xtal Oscillator frequency will be shifted giving the designed FSK frequency deviation. Wireless Components 2-4 Specification, May 2012 TDK 5100 8 CLKOUT Clock output to supply an external device. An external pull-up resistor has to be added in accordance to the driving requirements of the external device. A clock frequency of 3.39 MHz is selected by a logic low at CLKDIV input (pin9). A clock frequency of 847.5 kHz is selected by a logic high at CLKDIV input (pin9). VS 8 300 Ω 9 CLKDIV VS +1.2 V VS 5 μA 60 kΩ 9 +0.8 V 60 kΩ 10 COSC VS VS 6 kΩ 10 This pin is used to select the desired clock division rate for the CLKOUT signal. A logic low (CLKDIV < 0.2 V) applied to this pin selects the 3.39 MHz output signal at CLKOUT (pin 8). A logic high (CLKDIV open) applied to this pin selects the 847.5 kHz output signal at CLKOUT (pin 8). This pin is connected to the reference oscillator circuit. The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin. 100 μA 11 FSKOUT This pin is connected to a switch to FSKGND (pin 12). VS VS The switch is closed when the signal at FSKDTA (pin 7) is in a logic low state. The switch is open when the signal at FSKDTA (pin 7) is in a logic high state. 200 µA 1.5 kΩ 11 FSKOUT can switch an additional capacitor to the reference crystal network to pull the crystal frequency by an amount resulting in the desired FSK frequency shift of the transmitter output frequency. 12 12 FSKGND Wireless Components Ground connection for FSK modulation output FSKOUT. 2-5 Specification, May 2012 TDK 5100 13 PAGND Ground connection of the power amplifier. The RF ground return path of the power amplifier output PAOUT (pin 14) has to be concentrated to this pin. PAOUT 14 RF output pin of the transmitter. 14 A DC path to the positive supply VS has to be supplied by the antenna matching network. 13 FSEL 15 This pin is used to select the desired transmitter frequency. +1.2 V VS A logic low (FSEL < 0.5 V) applied to this pin sets the transmitter to the 433 MHz frequency range. 30 kΩ 15 +1.1 V 90 kΩ 30 μA CSEL 16 VS +1.2 V 60 kΩ 16 60 kΩ *) A logic high (FSEL open) applied to this pin sets the transmitter to the 868 MHz frequency range. This pin is used to select the desired reference frequency. VS 5 μA A logic low (CSEL < 0.2 V) applied to this pin sets the internal frequency divider to accept a reference frequency of 6.78 MHz. +0.8 V A logic high (CSEL open) applied to this pin sets the internal frequency divider to accept a reference frequency of 13.56 MHz. Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode. In Power Down Mode, the values are zero or high-ohmic. Wireless Components 2-6 Specification, May 2012 Wireless Components Figure 2-2 2-7 Clock Output Frequency Select 0.85/3.39 MHz Crystal 6.78/13.56 MHz FSK Switch FSK Ground 9 10 11 12 XTAL Osc Clock Output 8 :2/8 :4/16 PFD 7 FSK Data Input OR 1 Power Down Control Crystal Select 6.78/13.56 MHz 16 :128/64 6 ASK Data Input Loop Filter 4 LF VCO 15 :1/2 On Ground 5 Power AMP Low Voltage Sensor 2.2V 2 Low Power Detect Output Frequency Select 434/868 MHz Power Supply 3 Positive Supply VS Power Amplifier Output Power Amplifier Ground 14 13 TDK 5100 2.3 Functional Block diagram Block_diagram.wmf Functional Block diagram Specification, May 2012 TDK 5100 2.4 Functional Blocks 2.4.1 PLL Synthesizer The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 869 MHz. The oscillator signal is fed both, to the synthesizer divider chain and to the power amplifier. The overall division ratio of the asynchronous divider chain is 128 in case of a 6.78 MHz crystal or 64 in case of a 13.56 MHz crystal and can be selected via CSEL (pin 16). The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip. 2.4.2 Crystal Oscillator The crystal oscillator operates either at 6.78 MHz or at 13.56 MHz. The reference frequency can be chosen by the signal at CSEL (pin 16). Table 2-3 CSEL (pin 16) *) Low Open†) *) Low: †) Open: Crystal Frequency 6.78 MHz 13.56 MHz Voltage at pin < 0.2 V Pin open For both quartz frequency options, 847.5 kHz or 3.39 MHz are available as output frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a micro controller. The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9) Table 2-4 CLKDIV (pin 9) *) Low Open†) *) Low: †) Open: Wireless Components CLKOUT Frequency 3.39 MHz 847.5 kHz Voltage at pin < 0.2 V Pin open 2-8 Specification, May 2012 TDK 5100 To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount by switching an external capacitor via FSKOUT (pin 11). The condition of the switch is controlled by the signal at FSKDTA (pin 7). Table 2-5 FSKDTA (pin7) FSK Switch *) Low Open†), High‡) *) Low: †) Open: ‡) High: CLOSED OPEN Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V 2.4.3 Power Amplifier In case of operation in the 868-870 MHz band, the power amplifier is fed directly from the voltage controlled oscillator. In case of operation in the 433-435 MHz band, the VCO frequency is divided by 2. This is controlled by FSEL (pin 15) as described in the table below. Table 2-6 FSEL (pin 15) Radiated Frequency Band *) Low Open†) *) Low: †) Open: 433 MHz 868 MHz Voltage at pin < 0.5 V Pin open The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6). Table 2-7 ASKDTA (pin 6) *) Low Open†), High‡) *) Low: †) Open: ‡) High: Power Amplifier OFF ON Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V The Power Amplifier has an Open Collector output at PAOUT (pin 14) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 14) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 13) in order to reduce the amount of coupling to the other circuits. Wireless Components 2-9 Specification, May 2012 TDK 5100 2.4.4 Low Power Detect The supply voltage is sensed by a low power detector. When the supply voltage drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To minimize the external component count, an internal pull-up current of 40 µA gives the output a high-state at supply voltages above 2.15 V. The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off the PA as soon as the supply voltage drops below 2.15 V or it can be used to inform a micro-controller to stop the transmission after the current data packet. 2.4.5 Power Modes The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE MODE and the TRANSMIT MODE. 2.4.5.1 Power Down Mode In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.3 nA at 3 V 25°C. This current doubles every 8°C. The values for higher temperatures are typically 14 nA at 85°C and typically 600 nA at 125°C. 2.4.5.2 PLL Enable Mode In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is less than 1 msec when the specified crystal is used. The current consumption is typically 3.5 mA. 2.4.5.3 Transmit Mode In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 7 mA when using a proper transforming network at PAOUT, see Figure 3-1. 2.4.5.4 Power mode control The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1). When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up internally. Forcing the voltage at the pins low overrides the internally set state. Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open. Wireless Components 2 - 10 Specification, May 2012 TDK 5100 The principle schematic of the power mode control circuitry is shown in Figure 3-5. PDWN ASKDTA OR FSKDTA On Bias Source Bias Voltage 120 kΩ 120 kΩ On PLL 868 MHz FSKOUT FSK PA PAOUT IC Power_Mode.wmf Figure 2-5 Power mode control circuitry Table 3-8 provides a listing of how to get into the different power modes Table 2-8 PDWN FSKDTA ASKDTA Low*) Low, Open Low, Open Open†) Low Low High‡) Low, Open, High Low Open High Low High Low, Open, High Open, High Open High Open, High Open Low, Open, High High *) Low: †) Open: ‡) High: MODE POWER DOWN PLL ENABLE TRANSMIT Voltage at pin < 0.7 V (PDWN) Voltage at pin < 0.5 V (FSKDTA, ASKDTA) Pin open Voltage at pin > 1.5 V Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not recommended. Wireless Components 2 - 11 Specification, May 2012 TDK 5100 2.4.6 Recommended timing diagrams for ASK- and FSK-Modulation ASK Modulation using FSKDTA and ASKDTA, PDWN not connected Modes: Power Down PLL Enable Transmit High FSKDTA Low to t DATA Open, High ASKDTA Low to t min. 1 msec. ASK_mod.wmf Figure 2-6 ASK Modulation FSK Modulation using FSKDTA and ASKDTA, PDWN not connected Modes: Power Down PLL Enable Transmit DATA High FSKDTA Low to t to t High ASKDTA Low min. 1 msec. FSK_mod.wmf Figure 2-7 Wireless Components FSK Modulation 2 - 12 Specification, May 2012 TDK 5100 Alternative ASK Modulation, FSKDTA not connected. Modes: Power Down PLL Enable Transmit High PDWN Low to t DATA Open, High ASKDTA Low to t min. 1 msec. Alt_ASK_mod.wmf Figure 2-8 Alternative ASK Modulation Alternative FSK Modulation Modes: Power Down PLL Enable Transmit High PDWN Low to t to t Open, High ASKDTA Low DATA Open, High FSKDTA Low to t min. 1 msec. Alt_FSK_mod.wmf Figure 2-9 Wireless Components Alternative FSK Modulation 2 - 13 Specification, May 2012 3 Applications Contents of this Chapter 3.1 3.2 3.3 3.4 3.5 3.6 3.7 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 3-2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 3-4 50 Ohm-Output Testboard: Measurement results . . . . . . . . . . . . . . . 3-5 Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 3-7 Design Hints on the Clock Output (CLKOUT). . . . . . . . . . . . . . . . . . . 3-9 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . 3-10 TDK 5100 3.1 50 Ohm-Output Testboard Schematic X2SMA C8 C2 C4 L2 L1 VCC C7 433 (868) MHz C3 C6 10 9 8 11 7 12 13 14 15 6.78 (13.56) MHz 16 Q1 0.85 (3.4) MHz VCC T1 6 5 4 3 2 VCC 1 TDK 5100 C1 R3A R3F R4 R2 FSK ASK R1 C5 X1SMA 50ohm_test_v5.wmf Figure 3-1 Wireless Components 50 Ω - output testboard schematic 3-2 Specification, May 2012 TDK 5100 3.2 50 Ohm-Output Testboard Layout Wireless Components Figure 3-2 Top Side of TDK 5100-Testboard with 50 Ω - Output Figure 3-3 Bottom Side of TDK 5100-Testboard with 50 Ω - Output 3-3 Specification, May 2012 TDK 5100 3.3 Bill of material (50 Ohm-Output Testboard) Table 3-1 Bill of material Part Value R1 4.7 kΩ 434 MHz 869 MHz ASK FSK Specification 0805, ± 5% R2 12 kΩ R3A 15 kΩ R3F 0805, ± 5% 0805, ± 5% 15 kΩ 0805, ± 5% R4 open 0805, ± 5% C1 47 nF 0805, X7R, ± 10% C2 39 pF 47 pF 0805, COG, ± 5% C3 3.9 pF 1.8 pF 0805, COG, ± 0.1 pF C4 330 pF 100 pF 0805, COG, ± 5% C5 1 nF 0805, X7R, ± 10% C6 8.2 pF 0805, COG, ± 0.1 pF C7 0Ω Jumper 434MHz: 22 pF 868MHz: 47pF 0805, COG, ± 5% 0805, 0Ω Jumper C8 15 pF 8.2 pF 0805, COG, ± 5% L1 100 nH 33 nH TOKO LL2012-J L2 39 nH 15 nH 39 nH: TOKO LL2012-J 15 nH: TOKO LL1608-J Q1 13.56875 MHz, CL=20pF IC1 TDK5100 T1 Push-button replaced by a short X1 SMA-S SMA standing X2 SMA-S SMA standing Wireless Components Tokyo Denpa TSS-3B 13568.75 kHz Spec.No. 10-50205 3-4 Specification, May 2012 TDK 5100 3.4 50 Ohm-Output Testboard: Measurement results Note the specified operating range: 2.1 V to 4.0 V and -40°C to +125°C. Pout over temperature TD K 5100 434 MH z 8,00 7,00 6,00 Pout [dBm] 5,00 4,0V 4,00 3,0V 3,00 2,1V 2,0V 2,00 1,9V 1,00 0,00 -1,00 -2,00 -50 0 50 100 150 T [°C] pout_over_temp_434.wmf Output power over temperature of the 50 Ω - testboard with TDK 5100 at 434 MHz Figure 3-4 Is o ver temperatu re TD K 5100 434 MH z 8,00 7,50 Is [mA] 7,00 4,0V 3,0V 2,1V 6,50 2,0V 1,9V 6,00 5,50 5,00 -50 0 50 100 150 T [°C] Is_over_temp_434.wmf Figure 3-5 Wireless Components Supply current over temperature of the 50 Ω - testboard with TDK 5100 at 434 MHz 3-5 Specification, May 2012 TDK 5100 Note the specified operating range: 2.1 V to 4.0 V and -40°C to +125°C. Pout over temperature TD K5100 868 MH z 6,00 5,00 4,00 Pout [dBm] 3,00 4,0V 2,00 3,0V 1,00 2,1V 0,00 2,0V 1,9V -1,00 -2,00 -3,00 -4,00 -50 0 50 100 150 T [°C] pout_over_temp_868.wmf Figure 3-6 Output power over temperature of the 50 Ω - testboard with TDK 5100 at 868 MHz Is over temperature TD K5100 868 MHz 8,00 7,50 Is [mA] 7,00 4,0V 3,0V 2,1V 6,50 2,0V 1,9V 6,00 5,50 5,00 -50 0 50 100 150 T [°C] is_over_temp_868.wmf Figure 3-7 Wireless Components Supply current over temperature of the 50 Ω - testboard with TDK 5100 at 868 MHz 3-6 Specification, May 2012 TDK 5100 3.5 Application Hints on the Crystal Oscillator 1. Application Hints on the crystal oscillator The crystal oscillator achieves a turn on time less than 1 msec when the specified crystal is used. To achieve this, a NIC oscillator type is implemented in the TDK 5100. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv. -R L f, CL Cv IC Cv = 1 1 +ω2L CL Formula 1) CL: crystal load capacitance for nominal frequency ω: angular frequency L: inductance of the crystal oscillator Example for the ASK-Mode: Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced by a short to ground. Assume a crystal frequency of 13.56 MHz and a crystal load capacitance of CL = 20 pF. The inductance L at 13.5 MHz is about 4.6 mH. Therefore C6 is calculated to 12 pF. Cv = Wireless Components 3-7 1 1 +ω 2L CL = C6 Specification, May 2012 TDK 5100 Example for the FSK-Mode: FSK modulation is achieved by switching the load capacitance of the crystal as shown below. FSKDTA FSKOUT Csw -R L f, CL Cv1 Cv2 COSC IC The frequency deviation of the crystal oscillator is multiplied with the divider factor N of the Phase Locked Loop to the output of the power amplifier. In case of small frequency deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated with the formula below. CL ± = C L: C 0: f: ω: N: df: 2(C 0 + CL ) Δf (1 + ) N * f1 C1 Δf 2(C 0 + CL ) 1± (1 + ) N * f1 C1 CL m C 0 crystal load capacitance for nominal frequency shunt capacitance of the crystal frequency ω = 2πf: angular frequency division ratio of the PLL peak frequency deviation Because of the inductive part of the TDK 5100, these values must be corrected by Formula 1). The value of Cv± can be calculated. Cv± = Wireless Components 3-8 1 1 + ω 2L CL ± Specification, May 2012 TDK 5100 If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram). If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated. Cv 2 = C 7 = Csw ∗ Cv1 − (Cv + ) ∗ (Cv1 + Csw) (Cv + ) − Cv1 Csw: parallel capacitance of the FSK switch (3 pF incl. layout parasitics) Remark: These calculations are only approximations. The necessary values depend on the layout also and must be adapted for the specific application board. 3.6 Design Hints on the Clock Output (CLKOUT) The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the microcontroller). RL can be calculated to: RL = 1 fCLKOUT * 8 * CLD Table 3-2 fCLKOUT= 847 kHz CL[pF] fCLKOUT= 3.39 MHz RL[kOhm] CL[pF] RL[kOhm] 5 27 5 6.8 10 12 10 3.3 20 6.8 20 1.8 Remark: To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen. Even harmonics of the signal at CLKOUT can interact with the crystal oscillator input COSC preventing the start-up of oscillation. Care must be taken in layout by sufficient separation of the signal lines to ensure sufficiently small coupling. Wireless Components 3-9 Specification, May 2012 TDK 5100 3.7 Application Hints on the Power-Amplifier The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of θ Minimum Tamb + 5°C Maximum fVCO + 1 MHz => Maximum Tamb - 5°C Maximum fVCO + 1 MHz => Minimum VS + 25 mV, max. + 40 MHz. †) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA ‡) Matching circuitry as used in the 50 Ohm-Output Testboard for 434 MHz operation. Tolerances of the passive elements not taken into account. Range @ 2.1 V, +25°C: 2.4 dBm +/- 0.7 dBm Typ. temperature dependency at 2.1 V: +0.4 dBm@-40°C and -1.4 dBm@+125°C, reference +25°C Range @ 3.0 V, +25°C: 5.0 dBm +/- 1.0 dBm Typ. temperature dependency at 3.0 V: +0.5 dBm@-40°C and -1.9 dBm@+125°C, reference +25°C Range @ 4.0 V, +25°C: 6.6 dBm +/- 2.0 dBm Typ. temperature dependency at 4.0 V: +0.6 dBm@-40°C and -3.1 dBm@+125°C, reference +25°C **) Matching circuitry as used in the 50 Ohm-Output Testboard for 868 MHz operation. Tolerances of the passive elements not taken into account. Range @ 2.1 V, +25°C: 0.0 dBm +/- 1.0 dBm Typ. temperature dependency at 2.1 V: +0.6 dBm@-40°C and -2.5 dBm@+125°C, reference +25°C Range @ 3.0 V, +25°C: 2.0 dBm +/- 2.0 dBm Typ. temperature dependency at 3.0 V: +0.9 dBm@-40°C and -3.6 dBm@+125°C, reference +25°C Range @ 4.0 V, +25°C: 3.2 dBm +/- 2.7 dBm Typ. temperature dependency at 4.0 V: +1.3 dBm@-40°C and -4.0 dBm@+125°C, reference +25°C A smaller load impedance reduces the supply-voltage dependency. A higher load impedance reduces the temperature dependency. Wireless Components 4-8 Specification, May 2012