LITIX™ Basic
TLD1326EL
3 Channel High-Side Current Source
1
Package
PG-SSOP-14
Marking
TLD1326
Overview
Applications
Exterior LED lighting applications such as tail/brake light, turn indicator,
position light, side marker,...
•
Interior LED lighting applications such as ambient lighting, interior
illumination and dash board lighting.
GND
DC/DC
controller
EN
Internal
supply
Thermal
protection
IN_SET
OUT3
Output
control
Current
adjustment
OUT1
PWMI
RSET
OUT2
N-1
CFB
TLD1326EL
RFB
FB
CN-1
DC/DC
control
GND
VBATT
VS
10kΩ
DC/DC Converter
CVS =4.7nF
•
Application Diagram with TLD1326EL
Data Sheet
www.infineon.com
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Overview
Basic Features
•
3 Channel device with integrated output stages (current sources), optimized to drive LEDs with output
current up to 120 mA per channel
•
Low current consumption in sleep mode
•
PWM-operation supported via VS- and EN-pin
•
Integrated PWM dimming engine to provide two LED brightness levels without external logic (e.g. µC)
•
Output current adjustable via external low power resistor and possibility to connect PTC resistor for LED
protection during over temperature conditions
•
Dynamic overhead control
•
Reverse polarity protection and overload protection
•
Undervoltage detection
•
N-1 detection, latched function
•
Wide temperature range: -40°C < Tj < 150°C
•
PG-SSOP-14 package with exposed heatslug
Description
The LITIX™ Basic TLD1326EL is a three channel high side driver IC with integrated output stages. It is designed
to control LEDs with a current up to 120 mA. In typical automotive applications the device is capable to drive
i.e. 3 red LEDs per chain (total 9 LEDs) with a current up to 60 mA, which is limited by thermal cooling aspects.
The output current is controlled practically independent of load and supply voltage changes.
Table 1
Product Summary
Parameter
Symbol
Value
Operating voltage range
VS(nom)
5.5 V ... 40 V
Maximum voltage
VS(max)
VOUTx(max)
40 V
Nominal output (load) current
IOUTx(nom)
60 mA when using a supply voltage range of 8 V - 18 V (e.g.
Automotive car battery). Currents up to IOUT(max) possible in
applications with low thermal resistance RthJA
Maximum output (load) current
IOUTx(max)
120 mA; depending on thermal resistance RthJA
Output current accuracy at RSET = 12 kΩ
kLT
750 ± 7%
Current consumption in sleep mode IS(sleep,typ)
0.1 µA
Protective Functions
•
ESD protection
•
Under voltage lock out
•
Over Load protection
•
Over Temperature protection
•
Reverse Polarity protection
Diagnostic Functions
•
N-1 detection, latched function
•
SC to Vs (indicated by N-1 diagnosis)
Data Sheet
2
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Block Diagram
Block Diagram
VS
2
EN
Internal
supply
Thermal
protection
IN_SET
OUT3
Output
control
Current
adjustment
OUT2
OUT1
PWMI
TLD1326EL
Figure 1
Data Sheet
FB
DC/DC
control
GND
N-1
Basic Block Diagram
3
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
Figure 2
Data Sheet
VS
1
VS
2
EN
3
NC
4
PWMI
14
NC
13
OUT3
12
OUT2
11
OUT1
5
10
FB
IN_SET
6
9
GND
N-1
7
8
NC
TLD1326EL
EP
Pin Configuration
4
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Input/
Output
Function
1, 2
VS
–
Supply Voltage; battery supply, connect a decoupling capacitor (100 nF - 1 µF)
to GND
3
EN
I
Enable pin
4
NC
–
Pin not connected
5
PWMI
I/O
PWM Input
6
IN_SET
I/O
Input / SET pin; Connect a low power resistor to adjust the output current
7
N-1
I/O
N-1 pin
8
NC
–
Pin not connected
–
1)
9
GND
Ground
10
FB
O
Feedback Output
11
OUT1
O
Output 1
12
OUT2
O
Output 2
13
OUT3
O
Output 3
14
NC
–
Pin not connected
–
1)
Exposed
Pad
GND
Exposed Pad; connect to GND in application
1) Connect all GND-pins together.
Data Sheet
5
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin for input pins (I),
positive currents flowing out of the I/O and output pins (O) (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Conditions
Voltages
4.1.1
Supply voltage
VS
-16
40
V
–
4.1.2
Input voltage EN
VEN
-16
40
V
–
4.1.3
Input voltage EN related to VS
VEN(VS)
VS - 40
VS + 16
V
–
4.1.4
Input voltage EN related to VOUTx
VEN - VOUTx
VEN VOUTx
-16
40
V
–
4.1.5
Output voltage
VOUTx
-1
40
V
–
4.1.6
Power stage voltage
VPS = VS - VOUTx
VPS
-16
40
V
–
4.1.7
Input voltage PWMI
VPWMI
-0.3
6
V
–
4.1.8
IN_SET voltage
VIN_SET
-0.3
6
V
–
4.1.9
N-1 voltage
VN-1
-0.3
6
V
–
4.1.10
Feedback voltage
VFB
-0.3
40
V
–
4.1.11
IN_SET current
IIN_SET
–
–
2
8
mA
–
Diagnosis output
4.1.12
N-1 current
IN-1
-0.5
0.5
mA
–
4.1.13
Feedback current
IFB
–
0.5
mA
–
4.1.14
Output current
IOUTx
–
130
mA
–
Currents
Temperatures
4.1.15
Junction temperature
Tj
-40
150
°C
–
4.1.16
Storage temperature
Tstg
-55
150
°C
–
ESD Susceptibility
4.1.17
ESD resistivity to GND
VESD
-2
2
kV
Human Body
Model (100 pF via
1.5 kΩ)2)
4.1.18
ESD resistivity all pins to GND
VESD
-500
500
V
CDM3)
4.1.19
ESD resistivity corner pins to GND
VESD
-750
750
V
CDM3)
1) Not subject to production test, specified by design
2) ESD susceptibility, Human Body Model “HBM” according to ANSI/ESDA/JEDEC JS-001-2011
3) ESD susceptibility, Charged Device Model “CDM” according to JESD22-C101E
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Data Sheet
6
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
General Product Characteristics
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions
are not designed for continuous repetitive operation.
Functional Range
4.2
Pos.
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Conditions
4.2.20
Supply voltage range for
normal operation
VS(nom)
5.5
40
V
–
4.2.21
Power on reset threshold
VS(POR)
–
5
V
VEN = VS
RSET = 12 kΩ
IOUTx = 80% IOUTx(nom)
VOUTx = 2.5 V
4.2.22
Junction temperature
Tj
-40
150
°C
–
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Thermal Resistance
4.3
Pos.
Parameter
Symbol
4.3.1
Junction to Case
RthJC
4.3.2
Junction to Ambient 1s0p board
RthJA1
4.3.3
1)
2)
3)
4)
Junction to Ambient 2s2p board
Limit Values
Min.
Typ.
Max.
–
8
10
–
–
61
56
Unit
Conditions
K/W
1) 2)
K/W
1) 3)
–
–
Ta = 85 °C
Ta = 135 °C
K/W
RthJA2
1) 4)
–
45
–
Ta = 85 °C
–
43
–
Ta = 135 °C
Not subject to production test, specified by design. Based on simulation results.
Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed Pad
are fixed to ambient temperature). Ta = 85°C, Total power dissipation 1.5 W.
The RthJA values are according to Jedec JESD51-3 at natural convection on 1s0p FR4 board. The product
(chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 70 µm Cu, 300 mm2 cooling area.
Total power dissipation 1.5 W distributed statically and homogenously over all power stages.
The RthJA values are according to Jedec JESD51-5,-7 at natural convection on 2s2p FR4 board. The product
(chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (outside 2 x
70 µm Cu, inner 2 x 35 µm Cu). Where applicable, a thermal via array under the exposed pad contacted the
first inner copper layer. Total power dissipation 1.5 W distributed statically and homogenously over all
power stages.
Data Sheet
7
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
EN Pin
5
EN Pin
The EN pin is a dual function pin:
Internal Supply
Output Control
EN
V EN
Figure 3
Block Diagram EN pin
Note: The current consumption at the EN-pin IEN needs to be added to the total device current consumption. The
total current consumption is the sum of the currents at the VS-pin IS and the EN-pin IEN.
5.1
EN Function
If the voltage at the pin EN is below a threshold of VEN(off) the LITIX™ Basic IC will enter Sleep mode. In this state
all internal functions are switched off, the current consumption is reduced to IS(sleep). A voltage above VEN(on) at
this pin enables the device after the Power on reset time tPOR.
VS
V EN
IOU T
t
t
tPOR
100%
80%
t
Figure 4
Data Sheet
Power on reset
8
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
EN Pin
5.2
Internal Supply Pin
The EN pin can be used to supply the internal logic. There are two typical application conditions, where this
feature can be used:
1) In “DC/DC control Buck” configurations, where the voltage Vs can be below 5.5V (see Figure 20 for details).
2) In configurations, where a PWM signal is applied at the Vbatt pin of a light module. The buffer capacitor CBUF
is used to supply the LITIX™ Basic IC during Vbatt low (Vs low) periods. This feature can be used to minimize
the turn-on time to the values specified in Pos. 10.2.13. Otherwise, the power-on reset delay time tPOR
(Pos. 6.3.6) has to be considered.
The capacitor can be calculated using the following formula:
I EN ( LS )
C BUF = tLOW ( max ) ⋅ -------------------------------------------------V S – V D1 – V S ( POR )
(1)
See also a typical application drawing in Chapter 11.
VBATT
VS
D1
GND
CBUF
EN
Internal
supply
Thermal
protection
Current
adjustment
OUT2
OUT1
LITIX™ Basic
Figure 5
Data Sheet
GND
R SET
IN_SET
OUT3
Output
control
External circuit when applying a fast PWM signal on VBATT
9
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
EN Pin
V EN
t
V BATT
IOU T
t
tON (VS)
100%
80%
Switch off behavior depends on
V BATT and load characteristics
20%
t
Figure 6
Typical waveforms when applying a fast PWM signal on VBATT
The parameter tON(VS) is defined at Pos. 10.2.13. The parameter tOFF(VS) depends on the load and supply voltage
VBATT characteristics.
5.3
EN Unused
In case of an unused EN pin, there are two different ways to connect it:
5.3.1
EN - Pull Up to VS
The EN pin can be connected with a pull up resistor (e.g. 10 kΩ) to Vs potential. In this configuration the
LITIX™ Basic IC is always enabled.
5.3.2
EN - Direct Connection to VS
The EN pin can be connected directly to the VS pin (IC always enabled). This configuration has the advantage
(compared to the configuration described in Chapter 5.3.1) that no additional external component is
required.
Data Sheet
10
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
PWMI Pin
6
PWMI Pin
The PWMI pin is designed as a dual function pin.
IPWMI(L)
Output Control
PWMI
VPWMI
Figure 7
Block Diagram PWMI pin
The pin can be used for PWM-dimming via a push-pull stage of a micro controller, which is connecting the
PWMI-pin to a low or high potential.
Note: The micro controller’s push-pull stage has to able to sink currents according to Pos. 6.3.16 to activate the
device.
Furthermore, the device offers also an internal PWM unit by connecting an external-RC network according to
Figure 10.
6.1
PWM Dimming
A PWM signal can be applied at the PWMI pin for LED brightness regulation. The dimming frequency can be
adjusted in a very wide range (e.g. 400 Hz). The PWMI pin is low active. Turn on/off thresholds VPWMI(L) and
VPWMI(H) are specified in parameters Pos. 6.3.13 and Pos. 6.3.14.
V PWMI
IOU T
tON (PWMI )
tOFF(PWMI )
t
100%
80%
20%
t
Figure 8
Data Sheet
Turn on and Turn off time for PWMI pin usage
11
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
PWMI Pin
6.2
Internal PWM Unit
Connecting a resistor and a capacitor in parallel on the PWMI pin enables the internal pulse width modulation
unit. The following figure shows the charging and discharging defined by the RC-network according to and the
internal PWM unit.
VPWMI
Outputs OFF
VPWMI(H)
Internal PWM
VPWMI(L)
Outputs ON
t
OUTON
Figure 9
OUT - OFF
OUTON
OUT - OFF
OUTON
OUT - OFF
OUTON
OUT - OFF
PWMI operating voltages
The PWM Duty cycle (DC) and the PWM frequency can be adjusted using the formulas below. Please use only
typical values of VPWMI(L), VPWMI(H) and IPWMI(on) for the calculation of tPWMI(on) and tPWMI(off) (as described in
Pos. 6.3.13 to Pos. 6.3.16).
⎛ V PWMI ( H ) – I PWMI ( on ) ⋅ R PWMI⎞
-⎟
t PWMI ( on ) = –R PWMI ⋅ C PWMI ⋅ LN ⎜ ------------------------------------------------------------------------------⎝ V PWMI ( L ) – I PWMI ( on ) ⋅ R PWMI ⎠
(2)
⎛ V PWMI ( H )⎞
-⎟
t PWMI ( off ) = R PWMI ⋅ C PWMI ⋅ LN ⎜ ------------------------⎝ V PWMI ( L ) ⎠
(3)
1
f PWMI = --------------------------------------------------------t PWMI ( on ) + tPWMI ( off )
(4)
DC = tPWMI ( on ) ⋅ f PWMI
(5)
Out of this equations the required CPWMI and RPWMI can be calculated:
t
⎞ tPWMI ( off )
PWMI ( on )
------------------------
⎛ V PWMI ( L )
– I PWMI ( on ) ⋅ t PWMI ( off ) ⋅ ⎜ --------------------------⎟
⎝ V PWMI ( H )⎠
–1
C PWMI = ------------------------------------------------------------------------------------------------------------------------------------------------------------------tPWMI ( on )
-----------------------t
⎛ V PWMI ( L ) ⎞
⎛ V PWMI ( L ) ⎞ PWMI ( off )
LN ⎜ --------------------------⎟ ⋅ V PWMI ( L ) ⋅ ⎜ --------------------------⎟
– V PWMI ( H )
⎝ V PWMI ( H )⎠
⎝ V PWMI ( H )⎠
t PWMI ( off )
RPWMI = --------------------------------------------------------------⎛ V PWMI ( H )⎞
-⎟
C PWMI ⋅ LN ⎜ ------------------------⎝ V PWMI ( L ) ⎠
(6)
(7)
See Figure 10 for a typical external circuitry.
Data Sheet
12
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
PWMI Pin
Note: In case of junction temperatures above Tj(CRT) (Pos. 10.2.14) the device provides a temperature dependent
current reduction feature as descirbed in Chapter 10.1.1. In case of output current reduction IIN_SET is
reduced as well, which leads to increased turn on-times tPWMI(on), because the CPWMI is charged slower. The
turn off-time tPWMI(off) remains the same.
VBATT
VS
10 kΩ
GND
EN
PWMI
Internal
supply
OUT3
Thermal
protection
Output
control
OUT2
Current
adjustment
OUT1
RSET
CN-1
IN_SET
FB
DC/DC
control
LITIX™ Basic
GND
CPWM I
RPWM I
N-1
Figure 10
Typical circuit using internal PWM unit
6.3
Electrical Characteristics Internal Supply / EN / PWMI Pin
Electrical Characteristics Internal Supply / EN / PWMI pin
Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40°C to +150°C, RSET = 12 kΩ all voltages with respect to
ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output
pins (O) (unless otherwise specified)
Pos.
Parameter
Symbol
6.3.1
Current consumption,
sleep mode
IS(sleep)
6.3.2
Current consumption,
active mode
IS(on)
Limit Values
Min.
Typ.
Max.
–
0.1
2
–
–
–
Data Sheet
–
–
–
13
1.7
1.0
1.75
Unit
Conditions
µA
1)
VEN = 0.5 V
Tj < 85 °C
VS = 18 V
VOUTx = 3.6 V
mA
2)
VPWMI= 0.5 V
IIN_SET = 0 µA
Tj < 105 °C
VS = 18 V
VOUTx = 3.6V
VEN = 5.5 V
VEN = 18 V
1)
REN = 10 kΩ between
VS and EN-pin
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
PWMI Pin
Electrical Characteristics Internal Supply / EN / PWMI pin (cont’d)
Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40°C to +150°C, RSET = 12 kΩ all voltages with respect to
ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output
pins (O) (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
6.3.3
Current consumption,
device disabled via PWMI
–
–
–
6.3.5
–
–
–
mA
2)
VS = 18 V
Tj < 105 °C
VIN_SET = 5 V
VEN = 5.5 V
VEN = 18 V
1)
REN = 10 kΩ between
VS and EN-pin
mA
2)
VS = 18 V
Tj < 105 °C
VPWMI= 3.4 V
VEN = 5.5 V
VEN = 18 V
1)
REN = 10 kΩ between
VS and EN-pin
mA
2)
VS = 18 V
Tj < 105 °C
RSET = 12 kΩ
VPWMI= 0.5 V
VOUTx = 18 V
VEN = 5.5 V
VEN = 18 V
1)
REN = 10 kΩ between
VS and EN-pin
1)
1.65
0.9
1.7
IS(dis,PWMI)
–
–
–
Conditions
Max.
Current consumption,
IS(dis,IN_SET)
device disabled via IN_SET
–
–
–
6.3.4
Typ.
Unit
1.9
1.0
2.0
Current consumption,
IS(fault)
active mode in single fault
detection condition
–
–
–
–
–
–
6.0
4.9
5.9
Power-on reset delay time tPOR
–
–
25
µs
VS = VEN = 0 →13.5 V
VOUTx(nom) = 3.6 ± 0.3V
IOUTx = 80% IOUTx(nom)
6.3.7
Required supply voltage
for output activation
VS(on)
–
–
4
V
VEN = 5.5 V
VOUTx = 3 V
IOUTx = 50% IOUTx(nom)
6.3.8
Required supply voltage
for current control
VS(CC)
–
–
5.2
V
VEN = 5.5 V
VOUTx = 3.6 V
IOUTx ≥ 90% IOUTx(nom)
6.3.9
EN turn on threshold
VEN(on)
–
–
2.5
V
–
6.3.10
EN turn off threshold
VEN(off)
0.8
–
–
V
–
mA
1)
6.3.6
6.3.11
Data Sheet
3)
EN input current during
low supply voltage
IEN(LS)
–
–
14
1.8
VS = 4.5 V
Tj < 105 °C
VEN = 5.5 V
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
PWMI Pin
Electrical Characteristics Internal Supply / EN / PWMI pin (cont’d)
Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40°C to +150°C, RSET = 12 kΩ all voltages with respect to
ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output
pins (O) (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
6.3.12
EN high input current
IEN(H)
Typ.
Unit
Conditions
mA
Tj < 105 °C
VS = 13.5 V, VEN = 5.5 V
VS = 18 V, VEN = 5.5 V
VS = VEN = 18 V
1)
VS = 18 V, REN = 10 kΩ
between VS and EN-pin
Max.
–
–
–
–
–
–
–
–
0.1
0.1
1.65
0.45
6.3.13
PWMI (active low)
Switching low threshold
(outputs on)
VPWMI(L)
1.5
1.85
2.3
V
1)4)
6.3.14
PWMI(active low)
Switching high threshold
(outputs off)
VPWMI(H)
2.45
2.85
3.2
V
1)4)5)
VS = 8...18 V
6.3.15
PWMI
∆VPWMI
Switching threshold
difference VPWMI(H) - VPWMI(L)
0.75
1
1.10
V
1)4)5)
VS = 8...18 V
6.3.16
PWMI (active low)
Low input current with
active channels (voltage
1
2
( V IN_SET(max) ) ⋅ R SET(max)
VPWMI ( H, max )
R PWMI(min) = --------------------------------------------------------------------------------VPWMI ( H, max ) + VF
I IN_SET(OL,min) – -----------------------------------------------RSET(max)
(14)
V PWMI ( H, min )
R PWMI(max) = --------------------------------------------------VIN_SET(max)
n N – 1 ⋅ 4 ⋅ ------------------------------R SET(min)
(15)
VF represents the voltage drop across the diode between the IN_SET- and the PWMI-pin.
Note: If one channel of the device should not be used, the according output needs to be connected to GND, which
leads to a disabling of this output.
Note: In case of a double fault, where the loads of two channels are faulty at the same time, the device operates
as in normal operation. This feature is implemented to avoid any unwanted switch off during significant
supply voltage drops. Please refer to Chapter 9.2.
9.2
Double Fault Conditions
The TLD1326EL has an integrated double fault detection feature. This feature is implemented to detect
significant supply voltage drops. During such supply voltage drops close to the forward voltage of the LEDs the
drivers outputs remain active. In case of load faults on two or more outputs within the time period tN-1 the
device disables the diagnosis to avoid any uncorrect open load diagnosis during low supply voltages close to
the forward voltages of the connected LED chains. If the faults between two or three channels happen with a
delay of longer than tOL the double fault detection feature is not active, i.e. the device is not turned on.
9.3
Electrical Characteristics IN_SET Pin and Load Diagnosis
Electrical Characteristics IN_SET pin and Load Diagnosis
Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40°C to +150°C, RSET = 12 kΩ, all voltages with respect to ground,
positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output pins (O) (unless
otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
1)
9.3.1
IN_SET reference
voltage
VIN_SET(ref)
1.19
1.23
1.27
V
VOUTx = 3.6 V
Tj = 25...115 °C
9.3.2
IN_SET N_1 voltage
VIN_SET(N-1)
4
–
5.5
V
1)
Data Sheet
23
VS > 8 V
Tj = 25...150 °C
VS = VOUTx (OL) x
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Load Diagnosis
Electrical Characteristics IN_SET pin and Load Diagnosis (cont’d)
Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40°C to +150°C, RSET = 12 kΩ, all voltages with respect to ground,
positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output pins (O) (unless
otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
1)
9.3.3
IN_SET N_1 voltage
VIN_SET(N-1)
3.2
–
5.5
V
9.3.4
IN_SET N_1 current
IIN_SET(N-1)
1.5
–
7.4
mA
VS > 8 V
Tj = 25...150 °C
VIN_SET = 4 V
VS = VOUTx (OL)
9.3.5
N-1 high threshold
VN-1(th)
2.45
2.85
3.2
V
VS > 8 V
9.3.6
N-1 output current
IN-1
12
20
28
µA
VS > 8 V
VN-1 = 2 V
9.3.7
N-1 detection voltage
VPS(N-1) = VS - VOUTx
VPS(N-1)
0.2
–
0.4
V
VS > 8 V
–
15
µA
See Figure 15
2
IN_SET activation
IIN_SET(act)
current without turn on
of output stages
1) Not subject to production test, specified by design
9.3.8
Data Sheet
24
VS = 5.5 V
Tj = 25...150 °C
VS = VOUTx (OL)
x
1)
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Power Stage
10
Power Stage
The output stages are realized as high side current sources with a current of 120 mA. During off state the
leakage current at the output stage is minimized in order to prevent a slightly glowing LED.
The maximum current of each channel is limited by the power dissipation and used PCB cooling areas (which
results in the applications RthJA).
For an operating current control loop the supply and output voltages according to the following parameters
have to be considered:
•
•
•
Required supply voltage for current control VS(CC), Pos. 6.3.8
Voltage drop over output stage during current control VPS(CC), Pos. 10.2.6
Required output voltage for current control VOUTx(CC), Pos. 10.2.7
10.1
Protection
The device provides embedded protective functions, which are designed to prevent IC destruction under fault
conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range.
Protective functions are neither designed for continuous nor for repetitive operation.
10.1.1
Over Load Behavior
An over load detection circuit is integrated in the LITIX™ Basic IC. It is realized by a temperature monitoring of
the output stages (OUTx).
As soon as the junction temperature exceeds the current reduction temperature threshold Tj(CRT) the output
current will be reduced by the device by reducing the IN_SET reference voltage VIN_SET(ref). This feature avoids
LED’s flickering during static output overload conditions. Furthermore, it protects LEDs against over
temperature, which are mounted thermally close to the device. If the device temperature still increases, the
three output currents decrease close to 0 A. As soon as the device cools down the output currents rise again.
IOU T
V IN_ SET
Tj (C R T)
Figure 19
Tj
Output current reduction at high temperature
Note: This high temperature output current reduction is realized by reducing the IN_SET reference voltage
voltage (Pos. 9.3.1). In case of very high power loss applied to the device and very high junction
temperature the output current may drop down to IOUTx = 0 mA, after a slight cooling down the current
increases again.
10.1.2
Reverse Battery Protection
The TLD1326EL has an integrated reverse battery protection feature. This feature protects the driver IC itself,
but also connected LEDs. The output reverse current is limited to IOUTx(rev) by the reverse battery protection.
Data Sheet
25
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Power Stage
Note: Due to the reverse battery protection a reverse protection diode for the light module may be obsolete. In
case of high ISO-pulse requirements and only minor protecting components like capacitors a reverse
protection diode may be reasonable. The external protection circuit needs to be verified in the application.
10.2
Electrical Characteristics Power Stage
Electrical Characteristics Power Stage
Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40°C to +150°C, VOUTx = 3.6 V, all voltages with respect to
ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output
pins (O) (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
10.2.1
Output leakage current
Typ.
Unit
Conditions
µA
VEN = 5.5 V
IIN_SET = 0 µA
VOUTx = 2.5 V
Tj = 150 °C
1)
Tj = 85 °C
1)
Max.
IOUTx(leak)
–
–
–
–
7
3
10.2.2
Output leakage current in
boost over battery setup
–
IOUTx(leak,B2B)
–
50
µA
10.2.3
Reverse output current
-IOUTx(rev)
–
1
µA
10.2.4
Output current accuracy
kLT
limited temperature range
–
Output current accuracy
over temperature
1)
VS = -16 V
Output load: LED with
break down voltage
< - 0.6 V
1)
697
645
10.2.5
VEN = 5.5 V
IIN_SET = 0 µA
VOUTx = VS = 40 V
750
750
Tj = 25...115 °C
VS = 8...18 V
VPS = 2 V
RSET = 6...12 kΩ
RSET = 30 kΩ
803
855
1)
kALL
697
645
750
750
803
855
Tj = -40...115 °C
VS = 8...18 V
VPS = 2 V
RSET = 6...12 kΩ
RSET = 30 kΩ
10.2.6
Voltage drop over power
stage during current
control VPS(CC) = VS - VOUTx
VPS(CC)
0.75
–
–
V
1)
10.2.7
Required output voltage
for current control
VOUTx(CC)
2.3
–
–
V
1)
Data Sheet
26
VS = 13.5 V
RSET = 12 kΩ
IOUTx ≥ 90% of
(kLT(typ)/RSET)
VS = 13.5 V
RSET = 12 kΩ
IOUTx ≥ 90% of
(kLT(typ)/RSET)
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Power Stage
Electrical Characteristics Power Stage (cont’d)
Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40°C to +150°C, VOUTx = 3.6 V, all voltages with respect to
ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output
pins (O) (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
10.2.8
Maximum output current
IOUT(max)
120
–
–
mA
RSET = 4.7 kΩ
The maximum output
current is limited by the
thermal conditions.
Please refer to
Pos. 4.3.1 - Pos. 4.3.3
10.2.9
PWMI turn on time
tON(PWMI)
–
–
15
µs
2)
VS = 13.5 V
RSET = 12 kΩ
PWMI → L
IOUTx = 80% of
(kLT(typ)/RSET)
10.2.10 PWMI turn off time
tOFF(PWMI)
–
–
10
µs
2)
VS = 13.5 V
RSET = 12 kΩ
PWMI→ H
IOUTx = 20% of
(kLT(typ)/RSET)
10.2.11 IN_SET turn on time
tON(IN_SET)
–
–
15
µs
VS = 13.5 V
IIN_SET = 0 → 100 µA
IOUTx = 80% of
(kLT(typ)/RSET)
10.2.12 IN_SET turn off time
tOFF(IN_SET)
–
–
10
µs
VS = 13.5 V
IIN_SET = 100 → 0 µA
IOUTx = 20% of
(kLT(typ)/RSET)
10.2.13 VS turn on time
tON(VS)
–
–
20
µs
1) 3)
10.2.14 Current reduction
temperature threshold
Tj(CRT)
–
140
–
°C
1)
IOUTx = 95% of
(kLT(typ)/RSET)
–
A
1)
10.2.15 Output current during
IOUT(CRT)
85% of –
current reduction at high
(kLT(typ)
temperature
/RSET)
1) Not subject to production test, specified by design
2) see also Figure 8
3) see also Figure 6
Data Sheet
27
VEN = 5.5 V
RSET = 12 kΩ
VS = 0 → 13.5 V
IOUTx = 80% of
(kLT(typ)/RSET)
RSET = 12 kΩ
Tj = 150 °C
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Application Information
11
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
DBO
VBO
RFB1
ROV1
L2
CBO
CIN
CSEPIC
CVS = 4.7 nF
L1
VBATT
EN
IN
SWO
ROV2
SWCS
Output
control
4 .7 nF ** 4. 7 nF** 4. 7 nF**
OUT 3
PWMI
OUT 2
N- 1
CN-1
VIVCC
Thermal
protection
RSWCS
TLD5097
RSET
SGND
1 nF
RFB2
OUT 1
IN _ SET
Current
adjust
DC / DC
control
LITIX™ Basic
FB
GND
RFB(PD)
1
OVFB
RSET
VS
Internal
supply
EN / PWMI
CVS = 4.7 nF
ST
FBL
CIN
DPOL
RPOL
IVCC
GND
CIVCC
CCOMP
RCOMP
COMP
VBO
RFB3
2
FBH
FREQ / SYNC
RFREQ
RSET
SET
VS
Internal
supply
EN
Thermal
protection
Output
control
4 . 7 nF ** 4 .7 nF ** 4. 7 nF**
OUT 3
PWMI
OUT 2
OUT 1
CN-1
N- 1
RSET
IN _ SET
LITIX™ Basic
**
Figure 20
Data Sheet
Current
adjust
DC / DC
control
FB
GND
For EMI improvement , if required .
System diagram DC/DC control SEPIC + N-1 detection
28
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Application Information
DRV
LBO
VIN
VBATT
DBO
CIN
VBO
CBO
IN
SWCS
TLD5095
SGND
RFB1
CVS =4.7nF
TSW
SWO
EN
RCS
ROVH
CN-1
ROVL
COMP
CCOMP
PWMI
OUT2
OUT1
IN_SET Current
DC/ DC
control
FB
GND
FBH
VIN
RFB2
FBL
VBO
RPWMI
RFB3
PWMO
RCOMP
4.7nF** 4.7nF** 4.7nF**
OUT3
N-1
adjust
IVCC
CVS =4.7nF
VS
10kΩ
GND
RFREQ
Output
control
LITIX™ Basic
RSET
ST
FREQ / SYNC
Internal
supply
Thermal
protection
OVFB
EN / PWMI
VS
10kΩ
CIVCC
EN
Internal
supply
Thermal
protection
1nF
RFB( PD)
CN-1
4.7nF** 4.7nF** 4.7nF**
OUT3
PWMI
OUT2
N-1
OUT1
IN_SET Current
adjust
RSET
Output
control
LITIX™ Basic
DC/ DC
control
FB
GND
VIN
* For EMI improvement, if required, ≈10nF
Figure 21
System diagram DC/DC control Boost + N-1 detection
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.
11.1
•
Further Application Information
For further information you may contact http://www.infineon.com/
Data Sheet
29
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Package Outlines
12
Package Outlines
0.19 +0.06
0.08 C
0.15 M C A-B D 14x
0.64 ±0.25
1
8
1
7
0.2
M
D 8x
Bottom View
3 ±0.2
A
14
6 ±0.2
D
Exposed
Diepad
B
0.1 C A-B 2x
14
7
8
2.65 ±0.2
0.25 ±0.05 2)
0.1 C D
8˚ MAX.
C
0.65
3.9 ±0.11)
1.7 MAX.
Stand Off
(1.45)
0 ... 0.1
0.35 x 45˚
4.9 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
Dimensions in mm
PG-SSOP-14-1,-2,-3-PO V02
Figure 22
PG-SSOP-14
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
30
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Revision History
13
Revision History
Revision
Date
Changes
1.0
2013-08-08
Inital revision of data sheet
1.1
2015-03-19
Updated parameters KLT and KALL in the chapter Power Stage
1.2
2018-04-26
Updated to latest template
1.2
2018-04-26
Updated application drawing
1.2
2018-04-26
Updated package marking
1.2
2018-04-26
Updated package figure
1.2
2018-04-26
Updated Chapter 7.1
1.2
2018-04-26
Updated Figure 20
Data Sheet
31
Rev. 1.2
2018-04-26
LITIX™ Basic
TLD1326EL
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
4.1
4.2
4.3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
5.3
5.3.1
5.3.2
EN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EN Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
EN Unused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EN - Pull Up to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EN - Direct Connection to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
6.1
6.2
6.3
PWMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal PWM Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Internal Supply / EN / PWMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7.1
7.2
FB Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC/DC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics FB Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
8.1
8.2
IN_SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Current Adjustment via RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Smart Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
9.1
9.2
9.3
Load Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N-1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Double Fault Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics IN_SET Pin and Load Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
23
23
10
10.1
10.1.1
10.1.2
10.2
Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Load Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Battery Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
26
11
11.1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
6
7
7
11
11
12
13
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data Sheet
32
Rev. 1.2
2018-04-26
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-04-26
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
TLD1326EL
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
For further information on technology, delivery terms
and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
工商网监
湘ICP备2023018690号
