TLE42672GATMA2

TLE 4267-2 5-V Low Drop Voltage Regulator Data Sheet Rev. 1.0, 2012-04-03 Automotive Power 5-V Low Drop Voltage Regulator TLE 4267-2 Features • • • • • • • • • • • • • • • • • Output voltage tolerance ≤ ±2% 400 mA output current capability Low-drop voltage Very low standby current consumption Input voltage up to 40 V Overvoltage protection up to 60 V (≤ 400 ms) Reset function down to 1 V output voltage ESD protection up to 2000 V Adjustable reset time On/off logic Overtemperature protection Reverse polarity protection Short-circuit proof Wide temperature range Suitable for use in automotive electronics Green Product (RoHS compliant) AEC Qualified P TO263 7 1 Functional Description The TLE 4267-2 G is a 5-V low drop voltage regulator for automotive applications in a PG-TO220-7-4 package. It supplies an output current of > 400 mA. The IC is shortcircuitproof and has an overtemperature protection circuit. Type Package TLE 4267-2 G PG-TO220-7-4 TLE 4267-2 G PG-TO263-7-1 Data Sheet 1 Rev. 1.0, 2012-04-03 TLE 4267-2 Application The IC regulates an input voltage VI in the range of 5.5 V < VI < 40 V to a nominal output voltage of VQ = 5.0 V. A reset signal is generated for an output voltage of VQ < VRT. The reset delay can be set with an external capacitor. The device has two logic inputs. A voltage of VE2 > 4.0 V given to the E2-pin (e.g. by ignition) turns the device on. Depending on the voltage on pin E6 the IC may be hold in active-state even if VE2 goes to low level. This makes it simple to implement a self-holding circuit without external components. When the device is turned off, the output voltage drops to 0 V and current consumption tends towards 0 μA. Design Notes for External Components The input capacitor CI is necessary for compensation of line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 Ω in series with CI. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values of ≥ 22 μF and an ESR of ≤ 3 Ω within the operating temperature range. Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturating of the power element. The reset output RO is in high-state if the voltage on the delay capacitor CD is greater or equal VUD. The delay capacitance CD is charged with the current ID for output voltages greater than the reset threshold VRT. If the output voltage gets lower than VRT a fast discharge of the delay capacitor CD sets in and as soon as VCD gets lower than VLD the reset output RO is set to low-level (see Figure 5). The reset delay can be set within wide range by dimensioning the capacitance of the external capacitor. Data Sheet 2 Rev. 1.0, 2012-04-03 TLE 4267-2 Table 1 Truth Table for Turn-ON/Turn-OFF Logic E2, Inhibit E6, Hold VQ Remarks L X OFF Initial state H X ON Regulator switched on via Inhibit, by ignition for example H L ON Hold clamped active to ground by controller while Inhibit is still high X L ON Previous state remains, even ignition is shut off: self-holding state L L ON Ignition shut off while regulator is in self-holding state L H OFF Regulator shut down by releasing of Hold while Inhibit remains Low, final state. No active clamping required by external selfholding circuit (μC) to keep regulator in off-state. Inhibit: E2 Enable function, active High Hold: E6 Hold and release function, active Low Data Sheet 3 Rev. 1.0, 2012-04-03 TLE 4267-2 PG-TO263-7-1 PG-TO220-7-4 1 2 3 4 5 6 7 Ι RO D Q E2 GND E6 AEP01724 Figure 1 Pin Configuration (top view) Table 2 Pin Definitions and Functions Pin Symbol Function 1 I Input; block to ground directly at the IC by a ceramic capacitor 2 E2 Inhibit; device is turned on by High signal on this pin; internal pull-down resistor of 100 kΩ 3 RO Reset Output; open-collector output internally connected to the output via a resistor of 30 kΩ 4 GND Ground; connected to rear of chip 5 D Reset Delay; connect via capacitor to GND 6 E6 Hold; see Table 1 for function; this input is connected to output voltage via a pull-up resistor of 50 kΩ 7 Q 5-V Output; block to GND with 22-μF capacitor, ESR < 3 Ω Data Sheet 4 Rev. 1.0, 2012-04-03 TLE 4267-2 Saturation Control and Protection Circuit Temperature Sensor Input I Q 5V Output Control Amplifier Adjustment D Reset Delay Buffer Bandgap Reference Reset Generator RO Reset Output Turn-ON/Turn-OFF Logic E2 Inhibit Figure 2 Data Sheet E6 Hold GND Ground BLOCKDIAGRAM Block Diagram 5 Rev. 1.0, 2012-04-03 TLE 4267-2 Table 3 Absolute Maximum Ratings TJ = -40 to 150 °C Parameter Symbol Limit Values Unit Notes Min. Max. VI VI II -42 42 V – – 60 V t ≤ 400 ms – – – internally limited VRO IRO -0.3 7 V – – – – internally limited VD ID -0.3 42 V – – – – – VQ IQ -0.3 7 V – – – – internally limited VE2 IE2 -42 42 V – -5 5 mA t ≤ 400 ms VE6 IE6 -0.3 7 V – – – mA internally limited IGND -0.5 – A – TJ Tstg – 150 °C – -50 150 °C – Input Voltage Voltage Current Reset Output Voltage Current Reset Delay Voltage Current Output Voltage Current Inhibit Voltage Current Hold Voltage Current GND Current Temperatures Junction temperature Storage temperature Data Sheet 6 Rev. 1.0, 2012-04-03 TLE 4267-2 Table 4 Operating Range Parameter Symbol Limit Values Unit Notes Min. Max. VI TJ 5.5 40 V see diagram -40 150 °C – Junction ambient Rthja – 65 K/W PG-TO220-7-4 package Junction-case Rthjc – 6 K/W PG-TO220-7-4 package Junction-case Zthjc – 2 K/W T < 1 ms Input voltage Junction temperature Thermal Resistance PG-TO220-7-4 package Junction ambient Rthja – 70 K/W PG-TO263-7-1 (SMD) package Junction-case Rthjc – 6 K/W PG-TO263-7-1 (SMD) package Junction-case Zthjc – 2 K/W T < 1 ms PG-TO263-7-1 (SMD) package Data Sheet 7 Rev. 1.0, 2012-04-03 TLE 4267-2 Table 5 Characteristics VI = 13.5 V; -40 °C < TJ < 125 °C; VE2 > 4 V (unless specified otherwise) Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Output voltage VQ 4.9 5 5.1 V 5 mA ≤ IQ ≤ 400 mA 6 V ≤ VI ≤ 26 V Output voltage VQ 4.9 5 5.1 V 5 mA ≤ IQ ≤ 150 mA 6 V ≤ VI ≤ 40 V Output current limiting IQ Iq 500 – – mA TJ = 25 °C – – 50 μA IC turned off Iq – 1.0 10 μA TJ = 25 °C Current consumption Iq = II - IQ Iq – 1.3 4 mA IQ = 5 mA Current consumption Iq – – 60 mA IQ = 400 mA Iq – – 80 mA VDr ΔVQ ΔVQ – 0.3 0.6 V – – 50 mV – 15 25 mV Supply-voltage rejection SVR – 54 – dB IQ = 400 mA VI = 5 V IQ = 400 mA1) 5 mA ≤ IQ ≤ 400 mA VI = 6 to 36 V; IQ = 5 mA fr = 100 Hz; Vr = 0.5 Vpp Longterm stability ΔVQ – 0 – mV 1000 h Current consumption Iq = II - IQ Current consumption Iq = II - IQ IC turned off IC turned on Iq = II - IQ Current consumption Iq = II - IQ Drop voltage Load regulation Supply-voltage regulation Reset Generator Switching threshold VRT 4.5 4.65 4.8 V Reset High level – 4.5 – – V Saturation voltage VRO,SAT RRO VD,SAT ID VUD – 0.1 0.4 V VQ decreasing Rext = ∞ RR = 4.7 kΩ 2) – 30 – kΩ – – 50 100 mV Internal Pull-up resistor Saturation voltage Charge current Upper delay switching threshold Data Sheet 8 15 25 μA VQ < VRT VD = 1.5 V 2.6 3 3.3 V – 8 Rev. 1.0, 2012-04-03 TLE 4267-2 Table 5 Characteristics (cont’d) VI = 13.5 V; -40 °C < TJ < 125 °C; VE2 > 4 V (unless specified otherwise) Parameter Delay time Lower delay switching threshold Reset reaction time Symbol Limit Values Unit Test Condition Min. Typ. Max. tD VLD – 20 – ms Cd = 100 nF – 0.43 – V – tRR – 2 – μs Cd = 100 nF VU,INH VL,INH RINH ΔVINH IINH VU,HOLD VL,HOLD RHOLD – 3 4 V IC turned on 2 – – V IC turned off 50 100 200 kΩ – 0.2 0.5 0.8 V – – 35 100 μA VINH = 4 V 30 35 40 % Referred to VQ 60 70 80 % Referred to VQ 20 50 100 kΩ – VI,OV VI,turn on 42 44 46 V 36 – – V VI increasing VI decreasing Inhibit Turn on voltage Turn off voltage Pull-down resistor Hysteresis Input current Hold voltage Turn off voltage Pull-up resistor Overvoltage Protection Turn off voltage Turn on voltage after turn off 1) Drop voltage = VI - VQ (measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V) 2) The reset output is Low for 1 V < VQ < VRT Data Sheet 9 Rev. 1.0, 2012-04-03 TLE 4267-2 Figure 3 Test Circuit Input Inhibit; e.g. from Terminal 15 Reset to µC I e.g. 470nF E2 Q D TLE4267-2 100nF RO GND Data Sheet + 22µF E6 Hold from µC Figure 4 5V Output APPLICATIONDIAGRAM Application Circuit 10 Rev. 1.0, 2012-04-03 TLE 4267-2 VΙ t VINH VU, INH VL, INH t < t RR VQ VRT VD VUD t t RR dV Ι D = dt C D VLD VD, SAT VRO t tD VRO, SAT t Power on Thermal Reset Shutdown Figure 5 Data Sheet Voltage Drop at Input Undervoltage at Output Secondary Load Spike Bounce Shutdown AET01985 Time Response 11 Rev. 1.0, 2012-04-03 TLE 4267-2 VΙ t VE2 VU, INH 1) 5) VL, INH VE6, rel for more than 4 μs AET01986 Enable and Hold Behavior 12 Rev. 1.0, 2012-04-03 TLE 4267-2 Output Voltage VQ versus Temperature Tj AED01486 5.10 VQ Drop Voltage VDr versus Output Current IQ V AED01488 700 VDr V Ι = 13.5 V mV 5.00 500 400 T j = 125 C 4.90 300 T j = 25 C 200 4.80 100 4.70 -40 0 40 80 0 160 C 0 100 200 300 400 mA Charge Current ID versus Temperature Tj Delay Switching Threshold VUD versus Temperature Tj AED01485 22 AED01487 4.0 ΙD VUD μA V Ι = 13.5 V V 3.0 V Ι = 13.5 V 18 600 ΙQ Tj VUD VC = 0 V 2.5 16 ΙD 2.0 14 1.5 12 1.0 10 -40 0.5 0 40 80 0 -40 160 C Data Sheet 0 40 80 160 C Tj Tj 13 Rev. 1.0, 2012-04-03 TLE 4267-2 Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Input Voltage VI AED01490 70 AED01491 15 Ιq Ιq mA R L = 25 Ω mA V Ι = 13.5 V 50 10 40 30 5 20 10 0 0 100 200 300 400 mA 0 600 0 20 10 30 ΙQ VΙ Output Current Limiting IQ versus Temperature Tj Output Current Limiting IQ versus Input Voltage VI AED01489 700 AED01987 700 mA Ι Q mA 600 500 500 ΙQ Tj = 25 C Tj = 125 C V Ι = 13.5 V 400 400 300 300 200 200 100 100 0 -40 0 40 80 0 160 C Tj Data Sheet 50 V 14 0 10 20 30 40 V 50 Vi Rev. 1.0, 2012-04-03 TLE 4267-2 Output Voltage VQ versus Inhibit Voltage VINH AED01988 6 VQ Inhibit Current IINH versus Inhibit Voltage VINH AED01989 50 Ι INH μA V 5 40 4 30 3 20 2 10 1 0 0 1 2 3 4 0 5 V 6 VINH Data Sheet 15 0 1 2 3 4 5 V 6 V INH Rev. 1.0, 2012-04-03 TLE 4267-2 Package Outlines 4.4 10 ±0.2 1.27 ±0.1 0...0.3 B 0.05 2.4 0.1 3.6 ±0.3 2.1±0.3 7.551) 1±0.3 9.25 ±0.2 (13.85) A 8.5 1) 0...0.15 7 x 0.6 ±0.1 6 x 1.27 1) 0.5 ±0.1 0.25 M A B 8˚MAX. 0.1 B Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut. gpt09465 Figure 7 PG-TO220-7-4 (Plastic Transistor Single Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/packages. Dimensions in mm SMD = Surface Mounted Device Data Sheet 16 Rev. 1.0, 2012-04-03 TLE 4267-2 4.4 10 ±0.2 1.27 ±0.1 0...0.3 B 0.05 2.4 0.1 4.7 ±0.5 2.7 ±0.3 7.551) 1±0.3 9.25 ±0.2 (15) A 8.5 1) 0...0.15 7 x 0.6 ±0.1 6 x 1.27 0.5 ±0.1 0.25 M A B 8˚ MAX. 1) Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut. Figure 8 0.1 B GPT09114 PG-TO263-7-1 (Plastic Transistor Single Outline) Green Product (RoHS compliant) [1] To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/packages. Dimensions in mm SMD = Surface Mounted Device Data Sheet 17 Rev. 1.0, 2012-04-03 TLE 4267-2 Revision History Version Date Rev. 1.0 2012-04-03 Initial datasheet for TLE4267-2 Data Sheet Changes 18 Rev. 1.0, 2012-04-03 Edition 2012-04-03 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. 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