OPTIREG™ Linear TLE42694
5V low drop fixed voltag e regulator
Features
•
Output Voltage 5 V ±2%
•
Output Current up to 150 mA
•
Very Low Current Consumption
•
Early Warning
•
Power-on and Undervoltage Reset with Programmable Delay Time
•
Reset Low Down to VQ = 1 V
•
Adjustable Reset Threshold
•
Very Low Dropout Voltage
•
Output Current Limitation
•
Reverse Polarity Protection
•
Overtemperature Protection
•
Suitable for Use in Automotive Electronics
•
Wide Temperature Range from -40°C up to 150°C
•
Input Voltage Range from -42 V to 45 V
•
Integrated Pull-Up Resistors at Logic Outputs
•
Green Product (RoHS compliant)
Applications
General automotive applications.
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
The OPTIREG™ Linear TLE42694 is a monolithic integrated low dropout voltage regulator, especially designed
for automotive applications. An input voltage up to 45 V is regulated to an output voltage of 5.0 V. The
component is able to drive loads up to 150 mA. It is short-circuit proof by the implemented output current
limitation and has an integrated overtemperature shutdown. A reset signal is generated for an output voltage
VQ,rt of typically 4.65 V. This threshold can be decreased by an external resistor divider. The power-on reset
delay time can be programmed by the external delay capacitor. The additional sense comparator provides an
early warning function: Any voltage (e.g. the input voltage) can be monitored, an undervoltage condition is
indicated by setting the comparator’s output to low. The reset and sense output are internally connected to
Data Sheet
www.infineon.com/OPTIREG-Linear
1
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
the output Q via a pull-up resistor. If these integrated resistors are not desired, the TLE42794 can be used
instead of the TLE42694.
Dimensioning information on external components
The input capacitor CI is recommended for compensation of line influences. The output capacitor CQ is
necessary for the stability of the control loop.
Circuit description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and
drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents
any oversaturation of the power element. The TLE42694 also has a number of internal circuits for protection
against:
•
Overload
•
Overtemperature
•
Reverse polarity
Type
Package
Marking
TLE42694G
PG-DSO-8
42694G
TLE42694GM
PG-DSO-14
42694GM
TLE42694E
PG-SSOP-14 exposed pad
42694E
Data Sheet
2
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block diagram
1
Block diagram
Ι
Q
Error
Amplifier
20 kΩ
20 kΩ
Current and
Saturation
Control
Reference
Trimming
D
RO
&
Reference
SO
RADJ
SI
GND
Figure 1
Data Sheet
AEB01669
Block diagram
3
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Pin configuration
2
Pin configuration
2.1
Pin assignment PG-DSO-8
PG-DSO-8
Ι
SΙ
RADJ
D
1
2
3
4
8
7
6
5
Q
SO
RO
GND
AEP01668
Figure 1
Pin configuration (top view)
2.2
Pin definitions and functions PG-DSO-8
Table 1
Pin definitions and functions PG-DSO-8
Pin
Symbol
Function
1
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2
SI
Sense input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
3
RADJ
Reset threshold adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
4
D
Reset delay timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5
GND
Ground
6
RO
Reset output
the open collector output is connected to the 5 V output via an integrated 20 kΩ
pull-up resistor;
leave open if the reset function is not needed
7
SO
Sense output
the open collector output is connected to the 5 V output via an integrated 20 kΩ
pull-up resistor;
leave open if the sense comparator is not needed
8
Q
Output
connect a capacitor to GND close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in “Functional range” on Page 9
Data Sheet
4
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Pin configuration
2.3
Pin assignment PG-DSO-14
PG-DSO-14
RADJ
D
GND
GND
GND
GND
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SI
Ι
GND
GND
GND
Q
SO
AEP02248
Figure 2
Pin configuration (top view)
2.4
Pin definitions and functions PG-DSO-14
Table 2
Pin definitions and functions PG-DSO-14
Pin
Symbol
Function
1
RADJ
Reset threshold adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2
D
Reset delay timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
3, 4, 5, 6, GND
10, 11, 12
Ground
Connect all pins to GND and to the heatsink area for improved cooling
7
RO
Reset output
the open collector output is connected to the 5 V output via an integrated 20 kΩ
pull-up resistor;
leave open if the reset function is not needed
8
SO
Sense Output
the open collector output is connected to the 5 V output via an integrated 20 kΩ
pull-up resistor;
leave open if the sense comparator is not needed
9
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values
given for its capacitance CQ and ESR in the table “Functional range” on Page 9
13
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
14
SI
Sense input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
Data Sheet
5
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Pin configuration
2.5
Pin assignment PG-SSOP-14 exposed pad
RADJ
n.c.
D
GND
n.c.
n.c.
RO
14
13
12
11
10
9
8
1
2
3
4
5
6
7
SI
I
n.c.
Q
n.c.
n.c.
SO
PinConfig_SSOP-14.vsd
Figure 3
Pin configuration (top view)
2.6
Pin definitions and functions PG-SSOP-14 exposed pad
Table 3
Pin definitions and functions PG-SSOP-14 exposed pad
Pin
Symbol
Function
1
RADJ
Reset threshold adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2, 5, 6
n.c.
Not connected
3
D
Reset delay timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
4
GND
Ground
Connect to GND
7
RO
Reset output
the open collector output is connected to the 5 V output via an integrated 20 kΩ
pull-up resistor;
leave open if the reset function is not needed
8
SO
Sense output
the open collector output is connected to the 5 V output via an integrated 20 kΩ
pull-up resistor;
leave open if the sense comparator is not needed
9, 10, 12
n.c.
Not connected
11
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values
given for its capacitance CQ and ESR in the table “Functional range” on Page 9
13
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
Data Sheet
6
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Pin configuration
Pin definitions and functions PG-SSOP-14 exposed pad (cont’d)
Table 3
Pin
Symbol
Function
14
SI
Sense input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
Pad
-
Exposed pad
connect to heatsink area;
connect to GND
Data Sheet
7
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 4
Absolute maximum ratings1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
-40
–
45
V
–
P_4.1.1
Input, sense input
VI, VSI
Voltage
Output, reset output, sense output, reset delay
VQ, VRO,
VSO, VD
-0.3
–
7
V
–
P_4.1.2
Voltage
VRADJ
-0.3
–
7
V
–
P_4.1.3
Current
IRADJ
-10
–
10
mA
–
P_4.1.4
Junction Temperature
Tj
-40
–
150
°C
–
P_4.1.5
Storage Temperature
Tstg
-50
–
150
°C
–
P_4.1.6
Voltage
-2
–
2
kV
–
P_4.1.7
Voltage
-1
–
1
kV
–
P_4.1.8
Voltage
Reset threshold
Temperature
ESD susceptibility
Human Body Model (HBM)2)
3)
Charged Device Model (CDM)
1) not subject to production test, specified by design
2) ESD HBM Test according to AEC-Q100-002 - JESD22-A114
3) ESD CDM Test according to ESDA ESD-STM5.3.1
Note:
Data Sheet
Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible
damage to the integrated circuit. Integrated protection functions are designed to prevent IC
destruction under fault conditions. Fault conditions are considered as outside normal operating
range. Protections functions are not designed for continuous repetitive operation.
8
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
General product characteristics
3.2
Functional range
Table 5
Functional range
Parameter
Symbol
Input Voltage
VI
Values
Min.
Typ. Max.
5.5
–
45
Unit
Note or
Test Condition
Number
V
–
P_4.2.1
Output capacitor’s requirements CQ
for stability
10
–
–
µF
–
Output capacitor’s requirements ESR(CQ)
for stability
–
–
3
Ω
–2)
P_4.2.3
-40
–
150
°C
–
P_4.2.4
Junction temperature
Tj
1)
P_4.2.2
1) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) Relevant ESR value at f = 10 kHz
Note:
Data Sheet
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
9
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
General product characteristics
3.3
Thermal resistance
Table 6
Thermal resistance
Parameter
Symbol
Values
Min.
Typ. Max.
–
80
Unit
Note or
Test Condition
Number
K/W
measured to pin 5
P_4.3.1
TLE42694G (PG-DSO-8)
Junction to soldering point1)
RthJSP
–
Junction to ambient
1)
RthJA
–
113
–
K/W
FR4 2s2p board
Junction to ambient
1)
RthJA
–
170
–
K/W
FR4 1s0p board,
footprint only3)
Junction to ambient1)
RthJA
–
142
–
K/W
FR4 1s0p board,
P_4.3.4
2
300 mm heatsink area
on PCB3)
Junction to ambient1)
RthJA
–
136
–
K/W
FR4 1s0p board,
P_4.3.5
600 mm2 heatsink area
on PCB3)
Junction to soldering point1)
RthJSP
–
27
–
K/W
measured to group of
pins 3, 4, 5, 10, 11, 12
P_4.3.6
Junction to ambient1)
RthJA
–
63
–
K/W
FR4 2s2p board2)
P_4.3.7
1)
RthJA
–
104
–
K/W
FR4 1s0p board,
footprint only3)
P_4.3.8
Junction to ambient1)
RthJA
–
73
–
K/W
FR4 1s0p board,
P_4.3.9
2
300 mm heatsink area
on PCB3)
Junction to ambient1)
RthJA
–
65
–
K/W
FR4 1s0p board,
P_4.3.10
600 mm2 heatsink area
on PCB3)
–
10
–
K/W
measured to pin 5
2)
P_4.3.2
P_4.3.3
TLE42694GM (PG-DSO-14)
Junction to ambient
TLE42694E (PG-SSOP-14 exposed pad)
Junction to soldering point1)
RthJSP
P_4.3.11
Junction to ambient
1)
RthJA
–
47
–
Junction to ambient
1)
RthJA
–
145
–
K/W
FR4 1s0p board,
Footprint only3)
Junction to ambient1)
RthJA
–
63
–
K/W
FR4 1s0p board,
P_4.3.14
2
300 mm heatsink area
on PCB3)
Junction to ambient1)
RthJA
–
53
–
K/W
FR4 1s0p board,
P_4.3.15
600 mm2 heatsink area
on PCB3)
FR4 2s2p board
2)
P_4.3.12
P_4.3.13
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
10
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
4
Block description and electrical characteristics
4.1
Voltage regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the
chip temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the
output capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table
“Functional range” on Page 9 have to be maintained. For details see also the typical performance graph
“Output capacitor series resistor ESR(CQ) versus output current IQ” on Page 14. As the output capacitor
also has to buffer load steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to
the component’s terminals.
A protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal
shutdown in case of overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the
package, the maximum output current is decreased at input voltages above VI = 22 V.
The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output
continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed. However,
junction temperatures above 150°C are outside the maximum ratings and therefore significantly reduce the
IC’s lifetime.
The TLE42694 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the
thermal protection circuit is not operating during reverse polarity conditions.
Supply
II
I
Q
IQ
Regulated
Output Voltage
Saturation Control
Current Limitation
CQ
CI
Temperature
Shutdown
Blo c k Dia gra m _Vo lta ge Re gu la tor.v s d
Figure 4
Data Sheet
LOAD
Bandgap
Reference
GND
Voltage regulator
11
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Table 7
Electrical characteristics voltage regulator
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or Test Condition Number
Output voltage
VQ
4.9
5.0
5.1
V
100 µA < IQ < 100 mA
6 V < VI < 18 V
P_5.1.1
Output current limitation
IQ,max
150
200
500
mA
VQ = 4.8V
P_5.1.2
Load regulation
steady-state
ΔVQ, load
-30
-15
–
mV
IQ = 5 mA to 100 mA
VI = 6 V
P_5.1.3
Line regulation
steady-state
ΔVQ,line
–
10
40
mV
VI = 6 V to 32 V
IQ = 5 mA
P_5.1.4
Dropout voltage1)
Vdr = VI - VQ
Vdr
–
250
500
mV
IQ = 100 mA
P_5.1.5
Overtemperature shutdown
threshold
Tj,sd
151
–
200
°C
Tj increasing2)
P_5.1.6
Overtemperature shutdown
threshold hysteresis
Tj,sdh
–
15
–
°C
Tj decreasing2)
P_5.1.7
Power supply ripple rejection
PSRR
–
70
–
dB
fripple = 100 Hz
Vripple = 0.5 Vpp
P_5.1.8
1) Measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V
2) Not subject to production test, specified by design
Data Sheet
12
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Typical Performance Characteristics Voltage Regulator
Output current IQ versus
input voltage VI
Output voltage VQ versus
junction temperature Tj
01_VQ_TJ.VSD
5,2
02_IQ_VI.VSD
300
V Q = 4.8 V
I Q = 5 mA
V I = 13.5 V
5,1
250
I Q,max [mA]
4,9
V
Q
[V]
5
4,8
200
150
100
4,7
50
4,6
0
-40
0
40
80
120
T j = 150 °C
0
160
10
Power supply ripple rejection PSRR versus
ripple frequency fr
03_PSRR_FR.VSD
3,5
T j = 25 °C
I Q = 10 mA
C Q = 10 µF ceramic
ΔV Q,line [mV]
PSRR [dB]
70
40
T j = 25 °C
2,5
2
1,5
20
1
10
0,5
T j = -40 °C
0
0,1
1
10
100
0
1000
10
20
30
40
V I [V]
f [kHz]
Data Sheet
T j = 150 °C
I Q = 5 mA
3
30
0
0,01
40
04_DVQ_DVI.VSD
4,5
4
50
30
Line regulation ΔVQ,line versus
input voltage change ΔVI
80
60
20
V I [V]
T j [°C]
90
T j = -40 °C
T j = 25 °C
13
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Output capacitor series resistor ESR(CQ) versus
output current IQ
Load regulation ΔVQ,load versus
output current change ΔIQ
05_DVQ_DIQ.VSD
0
06_ESR_IQ.VSD
100
C Q = 10 µF
V I = 13.5 V
VI = 13.5 V
-2
10
-6
ESR(C Q ) [Ω ]
ΔVQ,load [mV]
-4
T j = -40 °C
T j = 25 °C
-8
T j = 150 °C
-10
Unstable
Region
1
Stable
Region
0,1
-12
0,01
-14
0
20
40
60
80
100
0
50
I Q [mA]
100
150
IQ [mA]
Dropout voltage Vdr versus
junction temperature Tj
Dropout voltage Vdr versus
output current IQ
07_VDR_IQ.VSD
300
08_VDR_TJ.VSD
300
I Q = 100 mA
250
T j = 25 °C
200
200
T j = -40 °C
V DR [mV]
V DR [mV]
250
T j = 150 °C
150
150
100
100
50
50
I Q = 25 mA
I Q = 5 mA
I Q = 100 µA
0
0
0
20
40
60
80
-40
100
40
80
120
160
T j [°C]
I Q [mA]
Data Sheet
0
14
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
4.2
Current consumption
Table 8
Electrical characteristics current consumption
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or Test Condition
Number
Current consumption
Iq = II - IQ
Iq
–
210
280
µA
IQ = 100 µA
Tj = 25°C
P_5.2.1
Current consumption
Iq = II - IQ
Iq
–
240
300
µA
IQ = 100 µA
Tj ≤ 85°C
P_5.2.2
Current consumption
Iq = II - IQ
Iq
–
0.7
1
mA
IQ = 10 mA
P_5.2.3
Current consumption
Iq = II - IQ
Iq
–
3.5
8
mA
IQ = 50 mA
P_5.2.4
Data Sheet
15
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Typical performance characteristics current consumption
Current consumption Iq versus
output current IQ (IQ low)
Current consumption Iq versus
output current IQ
09_IQ_IQ_IQLOW.VSD
1,6
V I = 13.5 V
T j = 25 °C
1,4
V I = 13.5 V
T j = 25 °C
10
8
1
I q [mA]
I q [mA]
1,2
10_IQ_IQ.VSD
12
0,8
0,6
6
4
0,4
2
0,2
0
0
0
5
10
15
20
25
0
I Q [mA]
20
40
60
80
100
120
I Q [mA]
Current consumption Iq versus
input voltage VI
11_IQ_VI.VSD
6
5
I q [mA]
4
R LOAD = 100 Ω
3
2
1
R LOAD = 50 k Ω
0
0
10
20
30
40
V I [V]
Data Sheet
16
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
4.3
Reset function
The reset function provides several features:
Output undervoltage reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be
used to reset a microcontroller during low supply voltage.
Power-on reset delay time:
The power-on reset delay time trd allows a microcontroller and oscillator to start up. This delay time is the time
frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output
“RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD
connected to pin D charged by the delay capacitor charge current ID,ch starting from VD = 0 V.
If the application needs a power-on reset delay time trd different from the value given in Power-on reset delay
time, the delay capacitor’s value can be derived from the specified values in Power-on reset delay time and
the desired power-on delay time:
(4.1)
CD
t rd, new
= ---------------- × 100nF
t rd
with
•
CD: capacitance of the delay capacitor to be chosen
•
trd,new: desired power-on reset delay time
•
trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset reaction time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The
reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the
external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time
becomes:
(4.2)
t rr = t rd, int + t rr, d
with
•
trr: reset reaction time
•
trr,int: internal reset reaction time
•
trr,d: reset discharge
Optional reset output pull-up resistor RRO,ext:
The Reset Output RO is an open collector output with an integrated pull-up resistor. To improve the EMC
behavior of the component, an external pull-up resistor to the output VQ can be added. In Table 9 “Electrical
characteristics reset function” on Page 19 a minimum value for the external resistor RRO,ext is given.
Data Sheet
17
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Reset adjust function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by
connecting an external voltage divider (RADJ1, RADJ2) at pin RADJ. For selecting the default threshold connect
pin RADJ to GND.
When dimensioning the voltage divider, take into consideration that there will be an additional current
constantly flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows:
(4.3)
R ADJ, 1 + R ADJ, 2
V RT, new = ------------------------------------------ × V RADJ, th
R ADJ, 2
with
•
VRT,new: the desired new reset switching threshold
•
RADJ1, RADJ2: resistors of the external voltage divider
•
VRADJ,th: reset adjust switching threshold given in Table 9 “Electrical characteristics reset function” on
Page 19
I
Q
RRO
Int.
Supply
Control
CQ
RO
ID,ch
RRO,ext
Reset
I RO
VDST
VRADJ,th
VDD
optional
Supply
OR
RADJ,1
MicroController
RADJ
I RADJ
GND
optional
ID,dch
D
BlockDiagram_ResetAdjust.vsd
RADJ,2
GND
CD
Figure 5
Data Sheet
Block diagram reset function
18
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
VI
t
t < trr,total
VQ
VRT
1V
t
t rd
VD
V DU
V DRL
t
t rd
VRO
V RO,low
trr,total
trd
t rr,total
t rd
t rr,total
1V
t
Thermal
Shutdown
Input
Voltage Dip
Undervoltage
Figure 6
Timing diagram reset
Table 9
Electrical characteristics reset function
Spike at
output
Overload
T i mi n g Di a g ra m_ Re se t . vs
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
4.5
4.65
4.8
V
VQ decreasing
P_5.3.1
1.35
1.44
V
3.5 V ≤ VQ < 5 V
P_5.3.2
Output undervoltage reset
Default output undervoltage
Reset switching thresholds
VRT
Output undervoltage reset threshold adjustment
Reset adjust
Switching threshold
Data Sheet
VRADJ,th
1.26
19
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Table 9
Electrical characteristics reset function (cont’d)
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
VRT,range
3.50
–
4.65
V
–
P_5.3.3
Reset output low voltage
VRO,low
–
0.1
0.4
V
1 V ≤ VQ ≤ VRT
no external RRO,ext
P_5.3.4
Reset output internal pull-up
resistor to VQ
RRO
10
20
40
kΩ
–
P_5.3.5
Optional reset output external
pull-up resistor to VQ
RRO,ext
20
–
–
kΩ
1 V ≤ VQ ≤ VRT ; VRO ≤
0.4 V
P_5.3.6
Delay pin output voltage
VD
–
–
5
V
–
P_5.3.7
Power-on reset delay time
trd
17
28
39
ms
CD = 100 nF
P_5.3.8
Upper delay
switching threshold
VDU
–
1.8
–
V
–
P_5.3.9
Lower delay
switching threshold
VDL
–
0.45
–
V
–
P_5.3.10
Delay capacitor
charge current
ID,ch
–
6.5
–
µA
VD= 1 V
P_5.3.11
Delay capacitor
reset discharge current
ID,dch
–
70
–
mA
VD= 1 V
P_5.3.12
Delay capacitor
discharge time
trr,d
–
1.9
3
µs
Calculated value:
trr,d = CD*(VDU - VDL)/
ID,dch
CD = 100 nF
P_5.3.13
Internal reset reaction time
trr,int
–
3
7
µs
CD = 0 nF 2)
P_5.3.14
Reset reaction time
trr,total
–
4.9
10
µs
Calculated value:
trr,total = trr,int + trr,d
CD = 100 nF
P_5.3.15
1)
Reset adjustment range
Reset output RO
Reset delay timing
1) VRT is scaled linearly, in case the reset switching threshold is modified
2) Parameter not subject to production test; specified by design
Data Sheet
20
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Typical performance characteristics reset function
Power-on reset delay time trd
versus capacitance CD
Power-on reset delay time trd
versus junction temperature Tj
12_TRD_TJ.VSD
35
13_trd_CD.vsd
70
T j = 25 °C
30
60
25
50
20
40
t r d [m s]
t rd [ms]
C D = 100 nF
15
30
10
20
5
10
0
-40
0
40
80
120
0
160
0
T j [°C]
Data Sheet
50
100
150
200
250
C D [nF]
21
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
4.4
Early warning function
The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can
be monitored, an undervoltage condition is indicated by setting the comparator’s output to low.
Sense
Input
Voltage
VSI, High
VSI, Low
t
Sense
Output
High
Low
t
AED03049
Figure 7
Sense timing diagram
Table 10
Electrical characteristics early warning function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Test Condition
Number
Sense comparator input
Sense threshold high
VSI,high
1.24
1.31
1.38
V
–
P_5.4.1
Sense threshold low
VSI,low
1.16
1.22
1.28
V
–
P_5.4.2
Sense switching hysteresis
VSI,hy
20
90
160
mV
–
P_5.4.3
Sense input current
ISI
-1
-0.1
1
µA
–
P_5.4.4
Data Sheet
22
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Block description and electrical characteristics
Table 10
Electrical characteristics early warning function (cont’d)
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Test Condition
Number
Sense comparator output
Sense output low voltage
VSO,low
–
0.1
0.4
V
VSI < VSI,low
VI > 5.5 V
no external RSO,ext
P_5.4.5
Sense output internal pull-up
resistor to VQ
RSO,int
10
20
40
kΩ
–
P_5.4.7
Optional sense output external RSO,ext
pull-up resistor to VQ
20
–
–
kΩ
Vl > 5.5 V
VSO ≤ 0.4 V
P_5.4.8
Data Sheet
23
Rev. 1.41
2019-04-30
OPTIREG™ Linear TLE42694
5V low drop fixed voltage regulator
Application information
5
Application information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
5.1
Application diagram
II
Supply
RSI1
CI1
10μF
100nF
IQ
Regulated
Output Voltage
CQ
10μF
SI
RSO
(ESR
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