TLE4470G

Dual Low-Drop Voltage Regulator TLE 4470 Features • • • • • • • • • • • • • • • Stand-by output 180 mA; 5 V ± 2% Adjustable reset switching threshold Main output 350 mA; tracked to the stand-by output Low quiescent current consumption in standby mode Disable function for main output Wide operation range: up to 45 V Very low dropout Power-On-Reset circuit sensing the stand-by voltage Early warning comparator for supply undervoltage Output protected against short circuit Wide temperature range: -40 °C to 150 °C Overtemperature protection Overload protection Green Product (RoHS compliant) AEC Qualified P-DSO-14-1, -4, -7 PG-DSO-14 P/PG-DSO-20-1,-6,-7,-9,-14,-1 PG-DSO-20 Functional Description The TLE 4470 is a monolithic integrated voltage regulator with two very low-drop outputs, a main output Q2 for loads up to 350 mA and a stand by output Q1 providing a maximum of 180 mA. The device is available in two packages the PG-DSO-14 and PG-DSO-20. It is designed to supply microprocessor systems under the severe conditions of automotive applications and is therefore equipped with additional protection functions against overload, short circuit and overtemperature. Of course the TLE 4470 can also be used in other applications where two stabilized voltages are required. The device operates in the wide junction temperature range of -40 °C to 150 °C. The stand-by regulator transforms an input voltage VI in the range of 5.6 V ≤ VI ≤ 45 V to VQ1,nom = 5 V within an accuracy of 2%, whereas the main regulator is adjustable. By Type Package TLE 4470 GS PG-DSO-14 TLE 4470 G PG-DSO-20 Data Sheet 1 Rev. 1.2, 2008-03-20 TLE 4470 use of an external voltage divider the main output voltage can be set to VQ2 ≥ 5 V for the TLE 4470 G type (PG-DSO-20 package). VQ1 is compared to the voltage at pin ADJ2, which is proportional to the output voltage VQ2. A control amplifier drives the base of the series PNP transistor via a buffer. The main output voltage VQ2 is tracked to the accuracy of the stand-by output. For the TLE 4470 GS (PG-DSO-14 package) the output voltage is fixed to 5 V. To save energy e.g. in battery powered body electronic applications, the main regulator can be switched off via the disable input, which causes the current consumption to drop to 180 µA typical. Two additional features of the TLE 4470 are an early warning comparator (can be used e.g. to monitor the supply voltage VI) and reset generator with an adjustable reset delay time. The TLE 4470 G (PG-DSO-20 package) has in addition an adjustable reset switching threshold. This feature is useful with microprocessors which guarantee a safe operation down to voltages below the internally set reset threshold of 4.65 V typical. Two functions are included in the reset generator, a power-on-reset and an undervoltage reset. The power-on-reset feature is necessary for a defined start of the microprocessor when switching on the application. The reset signal is kept low for a certain delay time after the output voltage VQ1 of the regulator has surpassed the reset threshold. An external delay capacitor sets this delay time. The under voltage reset circuit supervises the stand-by output voltage. In case VQ1 falls below the reset switching threshold the reset output is set LOW after a short reaction time. The reset LOW signal is generated down to an output voltage VQ1 of 1 V. PG-DSO-20 PG-DSO-14 D DIS GND GND GND RQ SQ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 RADJ D DIS GND GND GND GND RQ SQ Q1 SI Ι GND GND GND Q2 Q1 AEP02152 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SI Ι1 Ι2 GND GND GND GND Q2 Q2 ADJ2 AEP02151 Figure 1 Data Sheet Pin Configuration (top view) 2 Rev. 1.2, 2008-03-20 TLE 4470 Pin Definitions and Functions Table 1 PG-DSO-20 Pin No. Symbol Function 1 RADJ Reset switching threshold adjust; for setting the reset switching threshold connect to a voltage divider from Q1 to GND. If this input is connected to GND, the reset is triggered at the internal threshold. 2 D Reset delay; connect a capacitor CD to GND for delay time adjustment 3 DIS Disable input main regulator; Q2 disabled with high signal 4, 5, 6, 7 GND Ground 8 RQ Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 9 SQ Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 10 Q1 Stand-by regulator output voltage; block to GND with a capacitor CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz 11 ADJ2 Main regulator adjust input; Q2 can be set to higher values than 5 V by an external voltage divider from Q2 to GND 12, 13 Q2 Main regulator output voltage; block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz 14, 15, 16, 17 GND Ground 18 I2 Main regulator input voltage; block to GND directly at the IC with a ceramic capacitor 19 I1 Stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor 20 SI Sense comparator input Data Sheet 3 Rev. 1.2, 2008-03-20 TLE 4470 Table 2 PG-DSO-14 Pin No. Symbol Function 1 D Reset delay; connect a capacitor CD to GND for delay time adjustment 2 DIS Disable input main regulator; Q2 disabled with high signal 3, 4, 5 GND Ground 6 RQ Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 7 SQ Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 8 Q1 Stand-by regulator output voltage; block to GND with a capacitor, CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz 9 Q2 Main regulator output voltage; 5 V output tracking to Q1, block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz 10, 11, 12 GND Ground 13 I Main and stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor 14 SI Sense comparator input RADJ: Adjustable reset switching threshold is not available in the PG-DSO-14 package. Reset is always triggered at the internal threshold. ADJ2: Main regulator adjust input is internally connected to VQ2. Data Sheet 4 Rev. 1.2, 2008-03-20 TLE 4470 Ι1 19 10 Reference Ι2 DIS 18 Q1 Stand-by-Regulator 12, 13 V REF 11 3 Q2 ADJ2 Main Regulator 2 V REF 8 Ιd = V RADJTH Reset SI 30 k Ω 9 Sense RADJ SQ 4-7 14-17 GND V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) Data Sheet RQ 20 = Figure 2 30 k Ω V Q1 1 D AEB02153 Block Diagram 5 Rev. 1.2, 2008-03-20 TLE 4470 Table 3 Absolute Maximum Ratings -40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks Min. Max. VI1 II1 -42 45 V – – – mA Internally limited VI2 II2 -42 45 V – – – mA Internally limited VQ1 IQ1 -1 7 V – – – mA Internally limited VQ2 IQ2 -1 36 V – – – mA Internally limited VADJ2 IADJ2 -0.3 18 V – – – mA Internally limited VSQ ISQ -0.3 25 V – -5 5 mA – VRQ IRQ -0.3 25 V – -5 5 mA – VDIS IDIS -42 45 V – -2 2 mA – VSI ISI -25 18 V – -2 2 mA – Stand-by Regulator Input I1 Voltage Current Main Regulator Input I2 Voltage Current Stand-by Output Q1 Voltage Current Main Output Q2 Voltage Current Main Regulator Adjust Input ADJ2 Voltage Current Sense Output SQ Voltage Current Reset Output RQ Voltage Current Disable Input DIS Voltage Current Sense Input SI Voltage Current Data Sheet 6 Rev. 1.2, 2008-03-20 TLE 4470 Table 3 Absolute Maximum Ratings (cont’d) -40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks Min. Max. -0.3 7 V – -2 2 mA – Reset Delay D Voltage Current VD ID Reset Switching Threshold Adjust RADJ Voltage Current VRADJ IRADJ -0.3 7 V – – – mA Internally limited Tj Tstg -50 150 °C – -50 150 °C – Temperatures Junction temperature Storage temperature Note: ESD-Protection according to MIL Std. 883: ±2 kV. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Data Sheet 7 Rev. 1.2, 2008-03-20 TLE 4470 Table 4 Operating Range Parameter Symbol Limit Values Min. Max. Unit Remarks Stand-by regulator input voltage VI1 5.6 45 V – Main regulator input voltage VI2 VQ2,nom 45 V – Stand-by regulator output current IQ1 0 180 mA – Main regulator output current IQ2 0 350 mA – Disable input voltage VDIS VSI Tj -0.3 45 V – -0.3 17 V – -40 150 °C – – 32 K/W Measured to pin 4 – 112 K/W 1) – 23 K/W Measured to pin 4 – 100 K/W 1) Sense input voltage Junction temperature + 0.6 V Thermal Resistances PG-DSO-14 Junction pin Junction ambient Rthj-pin Rthj-a Thermal Resistances PG-DSO-20 Junction pin Junction ambient Rthj-pin Rthj-a 1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35 µ Cu; 5 µ Sn; Footprint only; zero airflow. Note: In the operating range the functions given in the circuit description are fulfilled. Data Sheet 8 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. 4.90 5.0 5.10 V 1 mA < IQ1 < 100 mA 180 280 – mA 1) – 300 500 mV IQ1 = 100 mA1) – 180 250 µA – 180 300 µA – 4 6 mA IQ1 = 300 µA; Tj = 25 °C VDIS > VDISH (Q2 = OFF) IQ1 = 300 µA; VDIS > VDISH (Q2 = OFF) IQ1 = 100 mA; VDIS > VDISH (Q2 = OFF) Stand-by Regulator Output 1 Output voltage Output current limitation VQ1 IQ1 Output drop voltage; VDRQ1 VDRQ1 = VI1 - VQ1 Current Consumption Quiescent current; stand-by Iq = II1 - IQ1 Iq Quiescent current Iq = II1 - IQ1 Iq Regulator Performance Load regulation ∆VQ1,Lo – 15 50 mV 1 mA < IQ1 < 150 mA Load regulation ∆VQ1,Lo – 5 25 mV 1 mA < IQ1 < 100 mA Line regulation ∆VQ1,Li – 5 20 mV – 60 – dB IQ1 = 1 mA; 6 V < VI1 < 28 V 20 Hz < fr < 20 kHz; Vr = 5 Vpp Power Supply Ripple PSRR Rejection Temperature output voltage drift ∆VQ1/∆T – 0.3 – mV/ K – dVI1/dt stability VQ1 CQ1 4.5 – 5.5 V no reset occurs2) 6 – – µF – ESRCQ1 – – 10 Ω at 10 kHz Value of output capacitance ESR of output capacitance Data Sheet 9 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Main-Regulator Output 2 Output voltage tracking accuracy ∆VQ2 = -25 VQ2 - VQ1 5 25 mV 5 mA < IQ2 < 100 mA; 6 V < VI2 < 40 V3) Output voltage tracking accuracy -25 ∆VQ2 = VQ2 - VQ1 5 25 mV 5 mA < IQ2 < 250 mA; 7 V < VI2 < 28 V3) Adjust input current IADJ2 IQ2 -1 – 1 µA – 350 500 – mA 1) VDRQ2 – 300 600 mV IQ2 = 200 mA1) IQ2 = 200 mA; IQ1 = 300 µA IQ2 = IQ1 = 300 µA; Tj = 25 °C Output current limitation Output drop voltage VDRQ2 = VI2 - VQ2 Current Consumption Quiescent current; Iq = II - IQ Iq – 7 15 mA Quiescent current; Iq = II - IQ Iq – 250 500 µA Regulator Performance Load regulation ∆VQ2,Lo – 5 25 mV 5 mA < IQ2 < 200 mA; Line regulation ∆VQ2,Li – 5 20 mV – 60 – dB IQ2 = 5 mA; 6 V < VI2 < 28 V 20 Hz < fr < 20 kHz; Vr = 5 Vpp Power Supply Ripple PSRR Rejection Temperature output voltage drift ∆VQ2/∆T – 0.5 – mV/ K – dVI2/dt stability VQ2 CQ2 4.5 – 5.5 V no reset occurs3) 10 – – µF – ESRCQ2 – – 10 Ω at 10 kHz Value of output capacitance ESR of output capacitance Data Sheet 10 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Disable Input DIS H-input voltage threshold VDISH 2.3 – – V – L-input voltage threshold VDISL – – 1.4 V Output 2 active H-input current IDISH IDISL -2 -1 1 µA 2.3 V < VDIS < 7 V -6 -2 -0.5 µA 0 V < VDIS < 1.4 V L-input current Reset Timing D and Output RQ Reset switching threshold VQ, rt 4.5 4.65 4.8 V RADJ connected to GND Reset adjust threshold VRADJTH 1.25 1.35 1.45 V VQ1 > 3.5 V Reset output low voltage VRQL – 0.15 0.3 V RRQ = 10 kΩ externally Reset high voltage VRQH RRQ 4.5 – – V – 20 30 45 kΩ Internally connected to Q1 Reset charging current ID,c 3 5 9 µA VD = 1 V Upper timing threshold VDU 1.5 1.8 2.2 V – Lower timing threshold VDL 0.3 0.4 0.55 V – Reset delay time trd trr 12 15 20 ms – 0.5 2.0 µs CD = 47 nF CD = 47 nF Reset pull-up resistor Reset reaction time Data Sheet connected to Q1; VQ1 ≥ 1 V 11 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Sense Input SI and Output SQ Sense threshold voltage VSITH 1.28 1.35 1.45 V VSI decreasing Sense threshold hysteresis VSIHY 25 60 100 mV – Sense output low voltage VSQL – 0.15 0.4 V RSQ = 10 kΩ externally Sense output high voltage VSQH 4.5 – – V – Sense pull-up resistor RSQ 20 30 45 kΩ Internally connected to Q1 connected to Q1; VSI < 1.1 V; VI1 > 4.5 V 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value. 2) Square wave at VI: 8 V to 18 V; f = 10 kHz; tr = tf ≤ 100 ns. 3) VQ2 connected to ADJ2. Data Sheet 12 Rev. 1.2, 2008-03-20 TLE 4470 Application Information D1 1N4004 VBatt Ι 1 19 5V 10 Q1 C Q1 10 µF ZD1 C Ι 36 V 100 nF ( R 1= R 2 ) 10 V Reference Ι 2 18 Control C Q2 22 µF Stand-by-Regulator 12, 13 Q2 V REF R1 DIS 3 11 ADJ2 R SI1 330 k Ω R2 Main Regulator V REF 2 D 8 RQ Ιd = V RADJTH Reset 30 k Ω V Q1 1 CD 100 nF RADJ 30 k Ω 9 SQ SI 20 R SI2 100 kΩ C SI 10 nF = Sense V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) Figure 3 Data Sheet 4-7 14-17 GND AES02154 Application Circuit 13 Rev. 1.2, 2008-03-20 TLE 4470 Input, Output The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors CQ1 and CQ2 are necessary. Stability is guaranteed at values CQ1 ≥ 6 µF and CQ2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range. For the TLE 4470 G (PG-DSO-20) the output voltage VQ2 of the main regulator can be adjusted to 5 V ≤ VQ2,nom ≤ 20 V by connecting an external voltage divider to the voltage adjust pin ADJ2. For VQ2 = 5 V the voltage adjust pin has to be connected directly to the main output. For calculating VQ2 or R1 and R2 respectively the following equations can be used: VQ2 = VQ1 × (1 + R1 / R2) (1) or R1 = R2 × (VQ2 / VQ1 - 1) (2) Disable The main regulator of the TLE 4470 can be switched OFF by a voltage above 2.3 V at pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows: CD = (∆t × ID,c) / ∆V (3) Definitions: CD = delay capacitor ∆t = reset delay time ID,c = charge current, typical 5 µA ∆V = VDU, typical 1.8 V VDU = upper delay switching threshold at CD for reset delay time The reset reaction time trr is the time it takes the voltage regulator to set the reset out • • • • • LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated using the following equation: trr ≈ 20 s/F × CD Data Sheet (4) 14 Rev. 1.2, 2008-03-20 TLE 4470 VΙ t < t rr VQ V Q, rt d V Ι D,c = dt CD VD t V DU V DL VRO t rr t rd t t Power-on-Reset Figure 4 Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03010_4470 Reset Timing Reset Switching Threshold The internally set reset threshold is 4.65 V. When using the TLE 4470 G (PG-DSO-20) this threshold can be adjusted to 3.5 V < VQ, rt < 4.6 V by connecting an external voltage divider to pin RADJ. If this pin is not needed, it can be left open or even better connected to GND. R1 = R2 × (VQ, rt - Vref) / Vref or VQ, rt = Vref (1 + R1 / R2) (5) Definitions: • • VQ, rt = Reset threshold Vref = comparator reference voltage, typical 1.35 V (Reset adjust input current ≈ 50 nA) The reset output pin is internally connected to the stand-by output Q1 via a 30 kΩ pull-up resistor. The reset LOW signal at pin RQ is guaranteed down to an output voltage VQ1 of 1 V typical. Data Sheet 15 Rev. 1.2, 2008-03-20 TLE 4470 VQ1 V I1 30 k Ω Band-Gap Reference 1.35 V RO Band-Gap Reference 1.35 V