Data Sheet, Rev. 1.01, October 2019
TLE4966K
High Precision Hall-Effect Switch with
Direction Detection
Sensors
Edition 2019-10-25
Published by
Infineon Technologies AG
81726 München, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
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of any third party.
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TLE4966K
Revision History:
2019-10-25
Previous Version:
2007-09
Page
Rev. 1.01
Subjects (major changes since last revision)
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TLE4966K
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Electrical and Magnetic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Field Direction Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Timing Diagrams for the Speed and Direction Outputs . . . . . . . . . . . . 13
7
7.1
7.2
7.3
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Distance between Chip and Package Surface . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Footprint for PG-TSOP6-6-5 . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
4
6
6
6
7
15
15
15
16
16
Rev. 1.01, 2019-10-25
TLE4966K
Data Sheet
5
Rev. 1.01, 2019-10-25
High Precision Hall-Effect Switch with Direction
Detection
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TLE4966K
2.7 V to 24 V supply voltage operation
Operation from unregulated power supply
High sensitivity and high stability
of the magnetic switching points
High resistance to mechanical stress
by Active Error Compensation
Reverse battery protection (-18 V)
Superior temperature stability
Peak temperatures up to 195°C without damage
Low jitter (typ. 1 μs)
Digital output signals
Bipolar version
Excellent matching between the 2 Hall probes
Hall plate distance 1.45 mm
Direction & speed information
Direction signal switches before the speed signal
SMD package PG-TSOP6-6-5
1.2
Functional Description
The TLE4966K is an integrated circuit double Hall-effect sensor designed specifically for
highly accurate applications. Precise magnetic switching points and high temperature
stability are achieved by active compensation circuits and chopper techniques on chip.
They provide a speed signal at Q2 for every magnetic pole pair and a direction
information at Q1, which is provided before the speed signal.
Type
Ordering Code
Package
TLE4966K
SP000392740
PG-TSOP6-6-5
Data Sheet
6
Rev. 1.01, 2019-10-25
TLE4966K
Overview
1.3
Pin Configuration (top view)
Center of
Sensitive Area
0.73 ± 0.15
1.45
0.8
± 0.15
4
s 66
speed
1
ym
5
6
direction
2
Year (y) = 0...9
Month (m) = 1...9,
O - October
N - November
D - December
3
AEA03645
Figure 1
Pin Definition and Center of Sensitive Area
Table 1
Pin Definitions and Functions PG-TSOP6-6-5
Pin No.
Symbol
Function
1
Q2
Speed
2
GND
Recommended connection to GND
3
Q1
Direction
4
VS
Supply voltage
5
GND
Recommended connection to GND
6
GND
Ground
Data Sheet
7
Rev. 1.01, 2019-10-25
TLE4966K
General
2
General
2.1
Block Diagram
VS
Voltage Regulator
(reverse polarity protected)
Oscillator
& Sequencer
ESD
Bias and
Compensation
Circuits
GND
Q2
Chopped
Hall
Probe
Chopped
Hall
Probe
Figure 2
2.2
Amplifier
Amplifier
Filter
Comparator
with
Hysteresis
Filter
Q1
Direction
Detection
Block Diagram
Circuit Description
The chopped Double Hall Switch comprises two Hall probes, bias generator,
compensation circuits, oscillator, and output transistors.
The bias generator provides currents for the Hall probes and the active circuits.
Compensation circuits stabilize the temperature behavior and reduce technology variations.
The Active Error Compensation rejects offsets in signal stages and the influence of
mechanical stress to the Hall probes caused by molding and soldering processes and
other thermal stresses in the package. This chopper technique together with the threshold
generator and the comparator ensures high accurate magnetic switching points.
Data Sheet
8
Rev. 1.01, 2019-10-25
TLE4966K
Maximum Ratings
3
Maximum Ratings
Table 2
Absolute Maximum Ratings
Tj = -40°C to 150°C
Parameter
Symbol
Supply voltage
VS
Limit Values
Unit
min.
max.
-18
-18
-18
18
24
26
V
-50
50
mA
VQ
-0.7
-0.7
18
26
V
Continuous
output current
IQ
-50
50
mA
Junction
temperature
Tj
–
–
–
–
155
165
175
195
°C
Storage
temperature
TS
-40
150
°C
Magnetic flux
density
B
–
unlimited
mT
Supply current
IS
through
protection device
Output voltage
Conditions
for 1 h, RS ≥ 200 Ω
for 5 min, RS ≥ 200 Ω
for 5 min @ 1.2 kΩ pull up
for 2000 h (not additive)
for 1000 h (not additive)
for 168 h (not additive)
for 3 x 1 h (additive)
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 3
ESD Protection 1)
Parameter
Symbol
ESD voltage
VESD
Limit Values
min.
max.
–
±4
Unit
Notes
kV
HBM, R = 1.5 kΩ,
C = 100 pF
TA = 25°C
1) Human Body Model (HBM) tests according to: EOS/ESD Association Standard S5.1-1993 and
Mil. Std. 883D method 3015.7
Data Sheet
9
Rev. 1.01, 2019-10-25
TLE4966K
Operating Range
4
Operating Range
Table 4
Operating Range
Parameter
Symbol
min.
typ.
max.
Supply voltage
VS
2.7
–
–
–
–
–
18
24
26
V
VQ
Tj
-0.7
–
18
V
-40
–
–
–
150
175
°C
IQ
0
–
10
mA
Output voltage
Junction
temperature
Output current
Data Sheet
Limit Values
10
Unit
Conditions
1 h with RS ≥ 200 Ω
for 5 min RS ≥ 200 Ω
for 168 h
Rev. 1.01, 2019-10-25
TLE4966K
Electrical and Magnetic Parameters
5
Electrical and Magnetic Parameters
Table 5
Electrical Characteristics
Parameter
Symbol
1)
Limit Values
Unit
Conditions
min.
typ.
max.
IS
ISR
VQSAT
4
5.2
7
mA
0
0.2
1
mA
–
0.3
0.6
V
VS = 2.7 V ... 18 V
VS = -18 V
IQ = 10 mA
Output leakage
current
IQLEAK
–
0.05
10
μA
for VQ = 18 V
Output fall time
tf
tr
–
0.2
1
μs
RL = 1.2 kΩ; CL < 50 pF
–
0.2
1
μs
fOSC
fSW
td
tdc
tQJ
–
320
–
kHz
0
–
15 2)
kHz
–
13
–
μs
50
200
1000
ns
–
1
–
μsRMS Typ. value for squarewave signal 1 kHz
BREP
Repeatability of
magnetic thresholds 5)
–
40
–
μTRMS Typ. value for
ΔB/Δt > 12 mT/ms
Power-on time 6)
–
13
–
μs
–
1.45
–
mm
–
100
–
K/W
Supply current
Reverse current
Output saturation
voltage
Output rise time
Chopper frequency
Switching frequency
Delay time
3)
Count Signal Delay
Output jitter 4)
tPON
Distance of hall plates dHALL
Thermal resistance 7) RthJA
see:
Figure 3
VS ≥ 2.7 V
PG-TSOP6-6-5
1) over operating range, unless otherwise specified. Typical values correspond to VS = 12 V and TA = 25°C
2) To operate the sensor at the max. switching frequency, the magnetic signal amplitude must be 1.4 times
higher than for static fields. This is due to the -3 dB corner frequency of the low pass filter in the signal path.
3) Systematic delay between magnetic threshold reached and output switching
4) Jitter is the unpredictable deviation of the output switching delay
5) BREP is equivalent to the noise constant
6) Time from applying VS ≥ 2.7 V to the sensor until the output state is valid
7) Thermal resistance from junction to ambient
Data Sheet
11
Rev. 1.01, 2019-10-25
TLE4966K
Electrical and Magnetic Parameters
Calculation of the ambient temperature (PG-TSOP6-6-5 example)
e.g. for VS = 12.0 V, IStyp = 5.5 mA, VQSATtyp = 0.3 V and 2 x IQ = 10 mA :
Power Dissipation: PDIS = 72.0 mW.
In TA = Tj – (RthJA × PDIS) = 175°C – (100 K / W × 0.072 W)
Resulting max. ambient temperature: TA = 167.8°C
Table 6
Magnetic Characteristics 1).
Parameter
Symbol
Tj [°C]
min.
typ.
max.
Operate point
BOP
-40
25
150
5.2
5.0
4.7
7.7
7.5
7.1
10.3
10.0
9.5
mT
Release point
BRP
-40
25
150
-10.3
-10.0
-9.5
-7.7
-7.5
-7.1
-5.2
-5.0
-4.7
mT
Hysteresis
BHYS
-40
25
150
–
10.0
–
–
15.0
–
–
20.0
–
mT
Magnetic
matching
BMATCH
-40
25
150
–
-2.0
–
–
0
–
–
2.0
–
mT
Valid for
BOP1 - BOP2
and
BRP1 - BRP2
Magnetic offset
BOFF
-40
25
150
–
-2.0
–
–
0
–
–
2.0
–
mT
(BOP + BRP)/2
–
–
-350
–
ppm/°C
Temperature
TC
compensation of
magnetic
thresholds
Limit Values
Unit
Conditions
1) over operating range, unless otherwise specified. Typical values correspond to VS = 12 V
Note: Typical characteristics specify mean values expected over the production spread.
Field Direction Definition
Positive magnetic fields related with south pole of magnet to the branded side of
package.
Data Sheet
12
Rev. 1.01, 2019-10-25
TLE4966K
Timing Diagrams for the Speed and Direction Outputs
6
Timing Diagrams for the Speed and Direction
Outputs
Applied Magnetic Field
BOP
BRP
td
td
tf
VQ
tr
90%
10%
Figure 3
Timing Definition of the Speed Signal
tdc
tdc
Speed
Direction
t
Change of Direction
Figure 4
Data Sheet
Timing Definition of the Direction Signal
13
Rev. 1.01, 2019-10-25
TLE4966K
Timing Diagrams for the Speed and Direction Outputs
N
S
S
N
N
S
Rotation
Direction
S
N
N
Branded Side of
IC
S
N
S
TLE4966
Figure 5
Definition of the Direction Signal
Rotation Direction
State of Direction Output VQ1
Left to right
Low
Right to left
High
Data Sheet
14
Rev. 1.01, 2019-10-25
TLE4966K
Package Information
Package Information
7.1
Package Marking
s 66
Figure 6
7.2
ym
7
Year(y ) =0...9
Month( m ) =1...9,
o - October
n - November
d - December
Marking PG-TSOP6-6-5
Distance between Chip and Package Surface
d
Branded Side
0.56 ± 0.1 mm
Figure 7
Data Sheet
Distance Chip to Upper Side of IC
15
Rev. 1.01, 2019-10-25
TLE4966K
Package Information
Package Outlines
2.9±0.2
(2.25)
B
1.1 MAX.
(0.35)
4
1
2
3
+0.2
acc. to DIN 6784
0.35+0.1
-0.05
0.15+0.1
-0.06
0.2M B 6x
0.95
1.6±0.1
5
10˚ MAX.
6
2.6 MAX.
0.1 MAX.
10˚ MAX.
7.3
A
0.2M A
1.9
GPX09300
Figure 8
PG-TSOP6-6-5 (Plastic Thin Small Outline Package)
PCB Footprint for PG-TSOP6-6-5
2.9
1.9
The following picture shows a recommendation for the PCB layout.
0.5
0.95
Remark: Wave soldering possible dep.
on customers process conditions
HLG09283
Figure 9
Footprint PG-TSOP6-6-5
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
16
Dimensions in mm
Rev. 1.01, 2019-10-25
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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