TLE6368-G2
Multi-Voltage Processor Power Supply
Data Sheet
Rev. 2.32, Oct. 2010
Automotive Power
Multi-Voltage Processor Power Supply
1
Overview
1.1
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TLE6368-G2
Features
High efficiency regulator system
Wide input voltage range from 5.5V to 60V
Stand-by mode with low current consumption
Suitable for standard 12V/24V and 42V PowerNets
Step down converter as pre-regulator:
5.5V / 1.5A
Step down slope control for lowest EME
Switching loss min2010-10imization
Three high current linear post-regulators with
selectable output voltages:
5V / 800mA
3.3V or 2.6V / 500mA
3.3V or 2.6V / 350mA
Six independent voltage trackers (followers):
5V / 17mA each
Stand-by regulator with 1mA current capability
Three independent undervoltage detection circuits
(e.g. reset, early warning) for each linear post-regulator
Power on reset functionality
Tracker control and diagnosis by SPI
All outputs protected against short-circuit
Power PG-DSO-36-26 package
Green (RoHS compliant) version of TLE6368-G2
AEC qualified
PG-DSO-36-26
Type
Package
TLE6368-G2 / SONIC
PG-DSO-36-26 (RoHS compliant)
SMD = Surface Mounted Device
Data Sheet
2
Rev. 2.32, 2010-10-19
TLE6368-G2
1.2
Short functional description
The TLE6368-G2 is a multi voltage power supply system especially designed for
automotive applications using a standard 12V / 24V battery as well as the new 42V
powernet. The device is intended to supply 32 bit micro-controller systems which require
different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external
sensors are also provided.
The TLE6368-G2 cascades a Buck converter block with a linear regulator and tracker
block on a single chip to achieve lowest power dissipation thus being able to power the
application even at very high ambient temperatures.
The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum
current capability of 1.5A.
Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V,
or 2.6V of output voltages depending on the configuration of the device with current
capabilities of 800mA, 500mA and 350mA.
In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their
outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to
drive a current of 17mA each. The trackers can be turned on and off individually by a 16
bit serial peripheral interface (SPI). Through this interface also the status information of
each tracker (i.e. short circuit) can be read out.
To monitor the output voltage levels of each of the linear regulators three independent
undervoltage detection circuits are available which can be used to implement the reset
or an early warning function. The supervision of the µC can be managed by the SPItriggered window watchdog.
For energy saving reasons while the motor is turned off, the TLE6368-G2 offers a standby mode, where the quiescent current does not exceed 30µA. In this stand-by mode just
the stand-by regulator remains active.
The TLE6368-G2 is based on Infineon Power technology SPT ™ which allows bipolar,
CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry.
Data Sheet
3
Rev. 2.32, 2010-10-19
TLE6368-G2
1.3
Pin configuration
PG-DSO-36-
GND
1
36
GND
C LK
2
35
SLEW
CS
3
34
W AKE
DI
4
33
BOOST
DO
5
32
IN
ERR
6
31
SW
Q_STB
7
30
IN
Q _T1
8
29
SW
Q _T2
9
28
B o o tstra p
Q _T3
10
27
Q _LD O 1
Q _T4
11
26
F B /L _ IN
Q _T5
12
25
F B /L _ IN
Q _T6
13
24
Q _LD O 2
Q _LDO 3
14
23
SEL
R3
15
22
CCP
R2
16
21
C+
R1
17
20
C-
GND
18
19
GND
TLE 6368
Figure 1 Pin Configuration (Top View),
bottom heat slug and GND corner pins are connected
Data Sheet
4
Rev. 2.32, 2010-10-19
TLE6368-G2
1.4
Pin definitions and functions
Pin No.
Symbol
Function
1,18,19,
36
GND
Ground; to reduce thermal resistance place cooling areas on
PCB close to these pins. The GND pins are connected internally
to the heat slug at the bottom.
2
CLK
SPI Interface Clock input; clocks the shift register; CLK has an
internal active pull down and requires CMOS logic level inputs;
see also chapter SPI
3
CS
SPI Interface chip select input; CS is an active low input; serial
communication is enabled by pulling the CS terminal low; CS
input should only be switched when CLK is low; CS has an
internal active pull up and requires CMOS logic level inputs; see
also chapter SPI.
4
DI
SPI Interface Data input; receives serial data from the control
device; serial data transmitted to DI is a 16 bit control word with
the Least Significant Bit (LSB) being transferred first; the input
has an active pull down and requires CMOS logic level inputs; DI
will accept data on the falling edge of CLK-signal; see also
chapter SPI
5
DO
SPI Interface Data output; this tristate output transfers
diagnosis data to the controlling device; the output will remain 3stated unless the device is selected by a low on Chip-Select CS;
see also the chapter SPI
6
ERR
Error output; push-pull output. Monitors failures in parallel to the
SPI diagnosis word, reset via SPI. ERR is an active low, latched
output.
7
Q_STB
Standby Regulator Output; the output is active even when the
buck regulator and all other circuitry is in off mode
8
Q_T1
Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
9
Q_T2
Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
10
Q_T3
Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
1.4
Pin definitions and functions (cont’d)
Pin No.
Symbol
Function
11
Q_T4
Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
12
Q_T5
Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
13
Q_T6
Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
14
Q_LDO3
Voltage Regulator Output 3; 3.3V or 2.6V output; output
voltage is selected by pin SEL (see also 2.2.2); For stability a
ceramic capacitor of 470nF to GND is sufficient.
15
R3
Reset output 3, undervoltage detection for output Q_LDO3;
open drain output; an external pull-up resistor of 10kΩ is
required
16
R2
Reset output 2, undervoltage detection for output Q_LDO2;
open drain output; an external pull-up resistor of 10kΩ is
required
17
R1
Reset output 1, undervoltage detection for output Q_LDO1 and
watchdog failure reset; open drain output; an external pull-up
resistor of 10kΩ is required
20
C-
Charge pump capacitor connection; Add the fly-capacitor of
100nF between C+ and C-
21
C+
Charge pump capacitor connection; Add the fly-capacitor of
100nF between C+ and C-
22
CCP
Charge Pump Storage Capacitor Output; Add the storage
capacitor of 220nF between pin CCP and GND.
23
SEL
Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3
(see also 2.2.2)
24
Q_LDO2
Voltage Regulator Output 2; 3.3V or 2.6V output; output
voltage is selected by pin SEL (see also 2.2.2); For stability a
ceramic capacitor of 470nF to GND is sufficient.
25, 26
FB/L_IN
Feedback and Linear Regulator Input; input connection for
the Buck converter output
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
1.4
Pin definitions and functions (cont’d)
Pin No.
Symbol
Function
27
Q_LDO1
Voltage Regulator Output 1; 5V output; acts as the reference
for the voltage trackers.The SPI and window watchdog logic is
supplied from this voltage. For stability a ceramic capacitor of
470nF to GND is sufficient.
28
Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW
and pin Bootstrap, the capacitance value should be 2% of the
Buck converter output capacitance
29, 31
SW
Switch Output; connect both pins externally through short lines
directly to the cathode of the catch diode and the Buck circuit
inductance.
30, 32
IN
Supply Voltage Input; connect both pins externally through
short lines to the input filter/the input capacitors.
33
BOOST
Boost Input; for switching loss minimization connect a diode
(cathode directly to boost pin) in series with a 100nF ceramic
capacitor to the IN pin and from the anode of the diode to the
buck converter output a 22Ω resistor. Recommended for 42V
applications. In 12/24V applications connect boost directly to IN.
34
WAKE
Wake Up Input; a positive voltage applied to this pin turns on
the device
35
SLEW
Slew control Input; a resistor to GND defines the current slope
in the buck switch for reduced EME
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
1.5
Basic block diagram
TLE 6368
Q_STB
Standby
Regulator
Boost
SW
2*
IN
2*
BUCK
REGULATOR
Slew
Bootstrap
Driver
OSZ
ErrorAmplifier
PWM
Internal
Reference
feedback
FB/L_IN
2*
C+
Charge
Pump
CCP
Protection
Wake
C-
Power
Down
Logic
SEL
R1
R2
Reset
Logic
R3
ref
Window
Watchdog
ref
CLK
ref
CS
ref
SPI
16 bit
DI
ref
DO
ref
ERR
Linear
Reg. 1
Q_LDO1
Linear
Reg. 2
Q_LDO2
Linear
Reg. 3
Q_LDO3
Tracker
5V
Q_T1
Tracker
5V
Q_T2
Tracker
5V
Q_T3
Tracker
5V
Q_T4
Tracker
5V
Q_T5
Tracker
5V
Q_T6
µ-controller /
memory
supply
Sensor
supplies
(off board
supplies)
GND
4*
Figure 2 Block Diagram
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
2
Detailed circuit description
In the following major buck regulator blocks, the linear voltage regulators and trackers,
the undervoltage reset function, the watchdog and the SPI are described in more detail.
For applications information e.g. choice of external components, please refer to section
5.
2.1
Buck Regulator
The diagram below shows the internal implemented circuit of the Buck converter, i. e. the
internal DMOS devices, the regulation loop and the other major blocks.
IN
5V
Int. voltage
regulator
Int. charge
pump
14V
150µA
to
current sense
amplifier
8 to 10V
FB/L_IN
C+
CCP
Gate driver
Main switch ON/OFF
Main
DMOS
IN
undervoltage
lockout
CSW
BOOTSTRAP
Slope switch
charge signal
switching frequency 330kHz
Divider
BOOST
Slope
DMOS
Oscillator
1.4MHz
Slope switch
discharge signal
Slope
compensation
Gate off signal
from overtemp or
sleep command
Lowpass
Voltage
feedback
amplifier
Current
comparator
Vref=6V
SW
Trigger for
gate on
PWM logic
Slope logic
Zero cross
detection
Trigger for
gate off
Lowpass
from
current sensing
Current
sense
amplifier
Delay unit
+
Slope
control
SLEW
external components
pins
Figure 3 Detailed Buck regulator diagram
The 1.5A Buck regulator consists of two internal DMOS power stages including a current
mode regulation scheme to avoid external compensation components plus additional
blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
the gate driver supply is managed by the combination of internal charge pump, external
charge pump and bootstrap capacitor.
2.1.1
Current mode control scheme
The regulation loop is located at the left lower corner in the schematic, there you find the
voltage feedback amplifier which gives the actual information of the actual output voltage
level and the current sense amplifier for the load current information to form finally the
regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the
slope compensation block is necessary.
The control signal formed out of those three blocks is finally the input of the PWM
regulator for the DMOS gate turn off command, which means this signal determines the
duty cycle. The gate turn on signal is set by the oscillator periodically every 3µs which
leads to a Buck converter switching frequency around 330kHz.
With decreasing input voltage the device changes to the so called pulse skipping mode
which means basically that some of the oscillator gate turn off signals are ignored. When
the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and
its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin
the device is turned off.During normal switching operation the gate driver is supplied by
the bootstrap capacitor.
2.1.2
Start-up procedure
To guarantee a device startup even under full load condition at the linear regulator
outputs a special start up procedure is implemented. At first the bootstrap capacitor is
charged by the internal charge pump. Afterwards the output capacitor is charged where
the driver supply in that case is maintained only by the bootstrap capacitor. Once the
output capacitor of the buck converter is charged the external charge pump is activated
being able to supply the linear regulators and finally the linear regulators are released to
supply the loads.
2.1.3
Reduction of electromagnetic emission
In figure 3 it is recognized that two internal DMOS switches are used, a main switch and
an auxiliary switch. The second implemented switch is used to adjust the current slope
of the switching current. The slope adjustment is done by a controlled charge and
discharge of the gate of this DMOS. By choosing the external resistor on the SLEW pin
appropriate the current transition time can be adjusted between 20ns and 100ns.
2.1.4
Reducing the switching losses
The second purpose of the slope DMOS is to minimise the switching losses. Once being
in freewheeling mode of the buck regulator the output voltage level is sufficient to force
the load current to flow, the input voltage level is not needed in the first moment. By a
feedback network consisting of a resistor and a diode to the boost pin (connection see
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
section 5) the output voltage level is present at the drain of the switch. As soon as the
voltage at the SW pin passes zero volts the handover to the main switch occurs and the
traditional switching behaviour of the Buck switch can be observed.
2.2
Linear Voltage Regulators
The Linear regulators offer, depending on the version, voltage rails of 5V, 3.3V and 2.6V
which can be determined by a hardware connection (see table at 2.2.2) for proper power
up procedure. Being supplied by the output of the Buck pre-regulator the power loss
within the three linear regulators is minimized.
All voltage regulators are short circuit protected which means that each regulator
provides a maximum current according to its current limit when shorted. Together with
the external charge pump the NPN pass elements of the regulators allow low dropout
voltage operation. By using this structure the linear regulators work stable even with a
minimum of 470nF ceramic capacitors at their output.
Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable output
voltage of 3.3V or 2.6V and Q_LDO3 is also programmable to 3.3V or 2.6V (see section
2.2.2). All three regulators are on all the time, if one regulator is not needed a base load
resistor in parallel to the output capacitance for controlled power down is recommended.
2.2.1
Startup Sequence Linear Regulators
When acting as a 32 bit µC supply the so-called power sequencing (the dependency of
the different voltage rails to each other) is important. Within the TLE6368-G2, the
following Startup-Sequence is defined (see also figure 4):
VQ_LDO2 ≤ VQ_LDO1; VQ_LDO3 ≤ VQ_LDO1
with VQ_LDO1=5V, VQ_LDO2 = 2.6V or 3.3V and VQ_LDO3 = 2.6V or 3.3V
The power sequencing refers to the regulator itself, externally voltages applied at
Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower
than those outputs.
That means for the power down sequencing if different output capacitors and different
loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and
Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this
behaviour three Schottky diodes have to be connected between the three outputs of the
linear regulators in that way that the cathodes of the diodes are always connected to the
higher nominal rail.
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
Power Sequencing
VFB/L_IN
VLDO_EN
t
VQ_LDO1
5V
VRth5
3.3V
2.6V
t
VQ_LDO2 (2.6V Mode)
0.7V
2.6V
VRth2.6
5V LDO
5V LDO
0.7V
t
VQ_LDO3 (3.3V Mode)
5V LDO
3.3V
VRth3.3
5V LDO
+/- 50mV
+/- 50mV
t
Figure 4 Power-up and -down sequencing of the regulators
2.2.2
Q_LDO2 and Q_LDO3 output voltage selection*
To determine the output voltage levels of the three linear regulators, the selection pin
(SEL, pin 23) has to be connected according to the matrix given in the table below.
Definition of Output voltage Q_LDO2 and Q_LDO3
Select Pin SEL connected to Q_LDO2 output voltage
Q_LDO3 output voltage
GND
3.3 V
3.3 V
Q_LDO1
2.6 V
2.6 V
Q_LDO2
2.6 V
3.3 V
* for different output voltages please refer to the multi voltage supply TLE6361
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
2.3
Voltage Trackers
For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output
current capability each are available. The output voltages match Q_LDO1 within
+5 / -15mV. They can be individually turned on and off by the appropriate SPI command
word sent by the microcontroller. A ceramic capacitor with the value of 1µF at the output
of each tracker is sufficient for stable operation without oscillation.
The tracker outputs can be connected in parallel to obtain a higher output current
capability, no matter if only two or up to all six trackers are tied together. For uniformly
distributed current density in each tracker internal balance resistors at each output are
foreseen internally. By connecting two sets of three trackers in parallel two sensors with
more than 50mA each can be supplied, all six in parallel give more than 100mA.
The tracker outputs can withstand short circuits to GND or battery in a range from -4 to
+40V. A short circuit to GND is detected and indicated individually for each tracker in the
SPI status word. Also an open load condition might be recognized and indicated as a
failure condition in the SPI status word. A minimum load current of 2mA is required to
avoid open load failure indication. In case of connecting several trackers to a common
branch balancing currents can prevent proper operation of the failure indication.
2.4
Standby Regulator
The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output
current which is on all the time. It is intended to supply the microcontroller in stop mode
and requires then only a minimum of quiescent current ( 1/48 of the actual OW/CW time between a “Watchdog disable”
and ’Watchdog enable’ SPI-command should be maintained. This allows the internal
Watchdog counters to be resetted. Thus after the enable command the Watchdog will
start properly with a full CW of the adjusted length.
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
P e rfe c t trig g e rin g a fte r P o w e r o n R e s e t
V Q _LD O 1
V R th 1
1V
t
tR ES
R1
t
tC W
W a tc h d o g
w in d o w
CW
tSR
OW
CW
OW
CW
CW
OW
t
CS
1)
2)
2)
2)
t
ERR
t
In c o rre c t trig g e rin g
W a tc h d o g
w in d o w
CW
OW
3)
4)
t
CS
w ith W D trig = 1
1)
2)
3)
4)
t
W a tc h d o g e n a b le c o m m a n d w ith n o trig g e r: D 0 D 9 D 1 4 D 1 5 = 0 1 0 0
W a tc h d o g trig g e r: D 1 5 = 1
P re trig g e r
M is s in g trig g e r
Legend:
O W = O p e n w in d o w
C W = C lo s e d w in d o w
Figure 7 Window watchdog timing
Figure 7 gives some timing information about the window watchdog. Looking at the
upper signals the perfect triggering of the watchdog is shown. When the 5V linear
regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect
on the reset line and/or error pin is observed. With the missing watchdog trigger signal
the error signal turns low immediately where the reset is asserted after another delay of
half the closed window time.
Also shown in the figure are two typical failure modes, one pretrigger and one missing
signal. In both cases the error signal will go low immediately the failure is detected with
the reset following after the half closed window time.
2.10
Overtemperature Protection
At a chip temperature of more than 150° an error and temperature flag is set and can be
read through the SPI. The device is switched off if the device reaches the
overtemperature threshold of 170°C. The overtemperature shutdown has a hysteresis to
avoid thermal pumping.
2.11
Power Down Mode
The TLE6368-G2 is started by a static high signal at the wake input or a high pulse with
a minimum of 50µs duration at the Wake input (pin 34). Voltages in the range between
the turn on and turn off thresholds for a few 100µs must be avoided!
By SPI command (“Sleep”-bit, D8, equals zero) all voltage regulators including the
switching regulator except the standby regulator can be turned off completely only if the
wake input is low. In the case the Wake input is permanently connected to battery the
device cannot be turned off by SPI command, it will always turn on again.
For stable “on” operation of the device the “Sleep”-bit, D8 has to be set to high at each
SPI cycle!
When powering the device again after power down the status of the SPI controlled
devices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Did
the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section)
is set otherwise the last SPI command defines the status.
2.12
Serial Peripheral Interface
A standard 16 bit SPI is available for control and diagnostics. It is capable to operate in
a daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI
interface.
The 16-bit control word (write bit assignment, see Figure 8) is read in via the data input
DI, synchronous to the clock input CLK supplied by the µC beginning with the LSB D0.
The diagnosis word appears in the same way synchronously at the data output DO (read
bit assignment, see figure 9), so with the first bit shifted on the DI line the first bit appears
on the DO line.
The transmission cycle begins when the TLE6368-G2 is selected by the “not chip select”
input CS (H to L). After the CS input returns from L to H, the word that has been read in
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
at the DI line becomes the new control word. The DO output switches to tristate status at
this point, thereby releasing the DO bus circuit for other uses. For details of the SPI
timing please refer to Figures 10 to 13.
The SPI will be reset to default values given in the following table “write bit meaning” if
the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).
The register content of the SPI - including watchdog timings and reset delay timings - is
maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not
decrease below 3.3V).
For details please refer to Application Note TLE6368 SPI.
2.12.1
Write mode
The following tables show the bit assignment to the different control functions, how to
change settings with the right bit combination and also the default status at power up.
2.12.2
Write mode bit assignment
BIT
Name
Default
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D 15
WD_
OFF1
NOT
assigned
T1control
T2control
T6control
T4control
T5control
T6control
sleep
WD_
OFF2
reset 1
reset 2
WD1
WD2
WD_
OFF3
WD_
TRIG
1
X
1
1
1
1
1
1
1
0
1
1
0
0
1
0
Figure 8 Write Bit assignment
Write Bit meaning
Function
Bit
Combination
Default
Not assigned
D1
X
X
Tracker 1 to 6 - control:
turn on/off the individual trackers
D2
D3
D4
D5
D6
D7
0: OFF
1: ON
1
Power down:
send device to sleep
D8
0: SLEEP
1: NORMAL
1
Data Sheet
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Rev. 2.32, 2010-10-19
TLE6368-G2
Write Bit meaning
Function
Bit
Combination
Default
Reset timing:
Reset delay time tRES valid at warm start
D10D11
00: 64ms
10: 32ms
01: 16ms
11: 8ms
11
Window watchdog timing:
Open window time tOW and
closed window time tCW valid at warm start
D12D13
00: 128ms
10: 64ms
01: 32ms
11: 16ms
00
Window watchdog function:
Enable /disable window watchdog
D0D9D14
010: ON
1xx: OFF
x0x: OFF
xx1: OFF
101
Window watchdog trigger:
Enable / disable window watchdog trigger
D15
0: not triggered 0
1: triggered
2.12.3 Read mode
Below the status information word and the bit assignments for diagnosis are shown.
2.12.3.1 Read mode bit assignment
BIT
Name
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
ERROR
temp_
warn
T1status
T2status
T3status
T4status
T5status
T6status
RAM
Good 1
RAM
Good 2
0
0
1
1
1
1
1
1
0
0
Default
D10
D11
D12
D13
WD
R-Error1 R-Error2 R-Error3
Window
0
0
0
0
D14
D 15
WD
Error
DC/DC
status
0
1
Figure 9 Read Bit assignment
Read Bit meaning
Function
Type
Bit
Combination
D0
0: normal operation 0
1: fail function
Not latched D1
0: normal operation 0
1: prewarning
Error indication, explanation Latched
see below this table
Overtemperature warning
Data Sheet
19
Default
Rev. 2.32, 2010-10-19
TLE6368-G2
Read Bit meaning
Function
Status of Tracker Output
Q_T[1:6],only if output is
ON
Type
Bit
Not latched D2
D3
D4
D5
D6
D7
Combination
Default
1
1: settled output
voltage
0:Tracker turned
off or shorted
output. Also open
load may possibly
be indicated as 0.1)
Indication of cold start/warm Latched
start, Q_LDO1
D8
0: cold start
1: warm start
0
Indication of cold start/warm Latched
start, Q_LDO2
D9
0: cold start
1: warm start
0
0
Indication for open or
closed window
Not latched D10
0: open window
1: closed window
Reset condition at output
Q_LDO1
Not latched D11
0: normal operation 0
1: Reset R1
Reset condition at output
Q_LDO2
Not latched D12
0: normal operation 0
1: Reset R2
Reset condition at output
Q_LDO3
Not latched D13
0: normal operation 0
1: Reset R3
Watchdog Error
Latched
DC/DC converter status
Not latched D15
1)
D14
0: normal operation
1: WD error
0: off
1: on
0
1
Min. load current to avoid ’0’ signal caused by open load is 2mA.
Error bit D0:
The error output ERR is low and the error bit indicates fail function if the temperature
prewarning or the watchdog error is active, further if one RAM good indicates a cold start
or if a voltage tracker does not settle within 1ms when it is turned on.
Data Sheet
20
Rev. 2.32, 2010-10-19
TLE6368-G2
2.12.4 SPI Timings
CS High to Low & rising edge of CLK: DO is enabled.
Status information is transferred to Output Shift Register
CS
CS Low to High: Data from Register
are transferred to e.g. Trackers
CLK
0
1
2
3
13
14
15
Data In (N)
DI
D0
D1
D2
D13 D14 D15
D3
time
0
1
Data In (N+1)
D0
+
D1
+
DI: Data will be accepted on the falling edge of CLK-Signal
Data Out (N-1)
DO
D0
D1
D2
D3
D13 D14 D15
Data Out (N)
D1
D0
DO: State will change on the rising edge of CLK-Signal
e.g.
Trackercontrol
Setting (N)
Setting (N-1)
e.g.
Trackerstatus
Status (N)
Status (N-1)
Figure 10 SPI Data Transfer Timing
Data Sheet
21
Rev. 2.32, 2010-10-19
TLE6368-G2
Figure 11 SPI-Input Timing
WU,1
WI,1 QV
94B/'2
&/.
94B/'2
WU'2
'2
ORZWRKLJK
W9$'2
WI'2
'2
KLJKWRORZ
Figure 12 DO Valid Data Delay Time and Valid Time
Data Sheet
22
Rev. 2.32, 2010-10-19
TLE6368-G2
tfIN
trIN
