TLE72742DATMA1

TLE7274-2 5-V Low Dropout Voltage Regulator TLE7274-2E TLE7274-2D TLE7274-2G Data Sheet Rev. 1.01, 2011-11-30 Automotive Power 5-V Low Dropout Voltage Regulator 1 TLE7274-2 Overview Features • • • • • • • • • Ultra Low Current Consumption 20 μA Output Voltage 5 V ±2% Output Current up to 300 mA Very Low Dropout Voltage Output Current Limitation Overtemperature Shutdown Wide Temperature Range From -40 °C up to 150 °C Green Product (RoHS compliant) AEC Qualified PG-SSOP-14 Exposed Pad Description The TLE7274-2 is a monolithic integrated low dropout voltage regulator for load currents up to 300 mA. An input voltage up to 42 V is regulated to VQ,nom = 5.0 V with a precision of ±2%. The sophisticated design allows to achieve stable operation even with ceramic output capacitors down to 470 nF. The device is designed for the harsh environment of automotive applications. Therefore it is protected against overload, short circuit and overtemperature conditions by the implemented output current limitation and the overtemperature shutdown circuit. The TLE7274-2 can be also used in all other applications requiring a stabilized 5 V voltage. PG-TO252-3 Due to its ultra low quiescent current of typically 20 µA the TLE7274-2 is dedicated for use in applications permanently connected to VBAT. An integrated output sink current circuitry keeps the voltage at the Output pin Q below 5.5 V even in case of occuring reverse currents. Thus connected devices are protected from overvoltage damage. For applications requiring extremely low noise levels the Infineon voltage regulator family TLE 42XX and TLE 44XX is more suited than the TLE7274-2. A mVrange output noise on the TLE7274-2 caused by the charge pump operation is unavoidable due to the ultra low quiescent current concept. PG-TO263-3 Type Package Marking TLE7274-2E PG-SSOP-14 Exposed Pad 7274-2E TLE7274-2D PG-TO252-3 7274-2D TLE7274-2G PG-TO263-3 7274-2G Data Sheet 2 Rev. 1.01, 2011-11-30 TLE7274-2 Block Diagram 2 Block Diagram TLE7274- 2 I Q Overtemperature Shutdown Bandgap Reference 1 Charge Pump GND Figure 1 Data Sheet A E B 03613.V S D Block Diagram 3 Rev. 1.01, 2011-11-30 TLE7274-2 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-SSOP-14 Exposed Pad n.c. n.c. 1 14 2 13 n.c. I n.c. 3 12 n.c. GND 4 11 n.c. n.c. 5 10 n.c. n.c. 6 9 Q n.c. 7 8 n.c. TLE7274-2_PINCONFIG_SSOP14.SVG Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions PG-SSOP-14 Exposed Pad Pin No. Symbol Function 1,2,3,5,6,7 n.c. non connected can be open or connected to GND 4 GND Ground 8,10,11,12,14 n.c. non connected can be open or connected to GND 9 Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 6 13 I Input block to ground directly at the IC with a ceramic capacitor Pad – Exposed Pad connect to GND and heatsink area Data Sheet 4 Rev. 1.01, 2011-11-30 TLE7274-2 Pin Configuration 3.3 Pin Assignment PG-TO252-3, PG-TO263-3 GND GND GND Ι GND Q AEP02512 I Q PG- TO263 -3-2 .vsd Figure 3 Pin Configuration (top view) 3.4 Pin Definitions and Functions PG-TO252-3, PG-TO263-3 Pin No. Symbol Function 1 I Input block to ground directly at the IC with a ceramic capacitor 2 GND Ground internally connected to heat slug 3 Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 6 Heat Slug – Heat Slug internally connected to GND; connect to GND and heatsink area Data Sheet 5 Rev. 1.01, 2011-11-30 TLE7274-2 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings1) Tj = -40 °C to 150 °C; all voltages with respect to ground, (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Max. Unit Test Condition Input I Voltage VI -0.3 45 V – 4.1.2 Voltage -0.3 6 V – 4.1.3 Voltage VQ VQ -0.3 6.2 V t < 10 s2) Tj Tstg -40 150 °C – -50 150 °C – Voltage - 3 kV – Voltage - 1.5 kV – 4.1.1 Output Q Temperature 4.1.4 Junction temperature 4.1.5 Storage temperature ESD Susceptibility 4.1.6 4.1.7 1) 2) 3) 4) Human Body Model (HBM)3) Charged Device Model (CDM) 4) not subject to production test, specified by design exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114 ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Pos. Functional Range Parameter 4.2.1 Input voltage 4.2.2 4.2.3 Output Capacitor’s Requirements 4.2.4 Junction temperature Symbol VI CQ ESR(CQ) Tj Limit Values Unit Remarks Min. Max. 5.5 42 V – 470 – nF 1) – 10 Ω 2) -40 150 °C – 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. Data Sheet 6 Rev. 1.01, 2011-11-30 TLE7274-2 General Product Characteristics 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions TLE7274-2E (PG-SSOP-14 Exposed Pad) 4.3.1 Junction to Case1) RthJC – 14 – K/W measured to exposed pad 4.3.2 Junction to Ambient1) – 47 – K/W 2) – 141 – K/W footprint only3) 4.3.4 RthJA RthJA RthJA – 66 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 56 – K/W 600 mm² heatsink area3) – 6 – K/W measured to tab – 32 – K/W 2) – 115 – K/W footprint only3) 4.3.4 RthJC RthJA RthJA RthJA – 62 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 47 – K/W 600 mm² heatsink area3) 4.3.3 TLE7274-2D (PG-TO252-3) 4.3.1 Junction to Case1) 4.3.2 Junction to Ambient1) 4.3.3 TLE7274-2G (PG-TO263-3) 4.3.1 Junction to Case1) RthJC – 6 – K/W measured to exposed pad 4.3.2 Junction to Ambient1) – 27 – K/W 2) – 75 – K/W footprint only3) 4.3.4 RthJA RthJA RthJA – 47 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 38 – K/W 600 mm² heatsink area3) 4.3.3 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 7 Rev. 1.01, 2011-11-30 TLE7274-2 Electrical Characteristics 5 Electrical Characteristics 5.1 Electrical Characteristics Voltage Regulator Electrical Characteristics VI =13.5 V; Tj = -40 °C to 150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Measuring Condition Output Q 5.1.1 Output Voltage VQ 4.9 5.0 5.1 V 0.1 mA < IQ