TLE75004-EPD
SPIDER+ 12V
SPI Driver for Enhanced Relay Control
1
Package
PG-TSDSO-14
Marking
TLE75004
Overview
Applications
•
Low-side switches for 12 V in automotive or industrial applications such
as lighting, heating, motor driving, energy and power distribution
•
Especially designed for driving relays, LEDs and motors.
VBA TT
CVDD
VDD
VDD
GPO
RIN
GPO
RIN
GPO
RIDLE
ROUT1
IN0_LH
IN1_LH
CVS
ZOUT2
RVDD
ZOUT3
VDD
VS
IN0
IN1
RLH
OUT0_LS
IDLE
OUT1_LS
LIMPHOME
ZVS
OUT2_LS
GPO
RCSN
CSN
GPO
RSCLK
SCLK
GPO
RSI
SI
GPI
RSO
SO
COUT
COUT
COUT
GND
COUT
GND
OUT3_LS
Application_4LS.emf
Figure 1
Datasheet
TLE75004-EPD Application Diagram
www.infineon.com
1
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Overview
Basic Features
•
16-bit serial peripheral interface for control and diagnosis
•
Daisy Chain capability SPI also compatible with 8-bit SPI devices
•
2 CMOS compatible parallel input pins with Input Mapping functionality
•
Cranking capability down to VS = 3.0 V (supports LV124)
•
Digital supply voltage range compatible with 3.3 V and 5 V microcontrollers
•
Very low quiescent current (with usage of IDLE pin)
•
Limp Home mode (with usage of IDLE and IN pins)
•
Green Product (RoHS compliant)
•
AEC Qualified
Protection Features
•
Reverse battery protection on VS without external components
•
Short circuit to ground and battery protection
•
Stable behavior at under voltage conditions (“Lower Supply Voltage Range for Extended Operation”)
•
Over Current latch OFF
•
Thermal shutdown latch OFF
•
Overvoltage protection
•
Loss of ground protection
•
Loss of battery protection
•
Electrostatic discharge (ESD) protection
Diagnostic Features
•
Latched diagnostic information via SPI register
•
Over Load detection at ON state
•
Open Load detection at OFF state using Output Status Monitor function
•
Output Status Monitor
•
Input Status Monitor
Application Specific Features
•
Fail-safe activation via Input pins in Limp-Home Mode
•
SPI with Daisy Chain capability
•
Safe operation at low battery voltage (cranking)
Description
The TLE75004-EPD is a four channel low-side power switch in PG-TSDSO-14 package providing embedded
protective functions. It is specially designed to control relays and LEDs in automotive and industrial
applications.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the loads as well as of the device. For
direct control and PWM there are two input pins available connected to two outputs by default. Additional or
different outputs can be controlled by the same input pins (programmable via SPI).
Datasheet
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Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Overview
Table 1
Product Summary
Parameter
Symbol
Values
Analog supply voltage
VS
3.0 V … 28 V
Digital supply voltage
VDD
3.0 V … 5.5 V
Minimum overvoltage protection
VS(AZ)
42 V (see Chapter 8.5 for details)
Maximum on-state resistance at TJ = 150 °C
RDS(ON)
2.2 Ω
Nominal load current (TA = 85 °C, all channels)
IL(NOM)
470 mA
Maximum Energy dissipation - repetitive
EAR
10 mJ @ IL(EAR) = 220 mA
Minimum Drain to Source clamping voltage
VDS(CL)
42 V
Maximum overload switch OFF threshold
IL(OVL0)
2.3 A
Maximum total quiescent current at TJ ≤ 85 °C
ISLEEP
5 µA
Maximum SPI clock frequency
fSCLK
5 MHz
Detailed Description
The TLE75004-EPD is a four channel low-side switch providing embedded protective functions. The output
stages incorporate four low-side switches (typical RDS(ON) at TJ = 25°C is 1 Ω).
The 16-bit serial peripheral interface (SPI) is utilized to control and diagnose the device and the loads. The SPI
interface provides daisy chain capability in order to assemble multiple devices (also devices with 8 bit SPI) in
one SPI chain by using the same number of microcontroller pins.
This device is designed for low supply voltage operation, therefore being able to keep its state at low battery
voltage (VS ≥ 3.0 V). The SPI functionality, including the possibility to program the device, is available only
when the digital power supply is present (see Chapter 6 for more details).
The TLE75004-EPD is equipped with two input pins that are connected to two outputs, making them
controllable even when the digital supply voltage is not available. With the Input Mapping functionality it is
possible to connect the input pins to different outputs, or assign more outputs to the same input pin. In this
case more channels can be controlled with one signal applied to one input pin.
In Limp Home mode (Fail-Safe mode) the input pins are directly routed to channels 2 and 3. When IDLE pin is
“low”, it is possible to activate the two channels using the input pins independently from the presence of the
digital supply voltage.
The device provides diagnosis of the load via Open Load at OFF state (with DIAG_OSM.OUTn bits) and short
circuit detection. For Open Load at OFF state detection, a internal current source IOL can be activated via SPI.
Each output stage is protected against short circuit. In case of Overload, the affected channel switches OFF
when the Overload Detection Current IL(OVLn) is reached and can be reactivated via SPI. In Limp Home mode
operation, the channels connected to an input pin set to “high” restart automatically after Output Restart time
tRETRY(LH) is elapsed. Temperature sensors are available for each channel to protect the device against Over
Temperature.
The power transistors are built by N-channel power MOSFET . The inputs are ground referenced TTL
compatible. The device is monolithically integrated in Smart Power Technology.
Datasheet
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Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Block Diagram and Terms
2
Block Diagram and Terms
2.1
Block Diagram
VS
VDD
power supply
IDLE
Power mode
control
IN0
Limp Home
IN1
input register
CSN
SCLK
SI
SO
control,
diagnostic
and
protective
functions
temperature
sensor
Over Load
detection
SPI
Output Status
Monitor
diagnosis
register
low-side
gate control
OUT3_LS
OUT2_LS
OUT1_LS
OUT0_LS
GND
BlockDiagram _4LS.emf
Figure 2
Datasheet
Block Diagram of TLE75004-EPD
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TLE75004-EPD
SPIDER+ 12V
Block Diagram and Terms
2.2
Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
VS
IVS
VS
IVD D
VDD
VDD
IL_D0
IIDLE
OUT0_LS
IDLE
VIDLE
VDS0
IIN 0
IN0
VIN 0
IL_D1
IIN 1
OUT1_LS
VDS1
IN1
VIN 1
ICSN
IL_D2
CSN
VCSN
OUT2_LS
ISCLK
VSCLK
VSI
VSO
VDS2
SCLK
ISI
IL_D3
SI
OUT3_LS
ISO
SO
VDS3
GND
IGND
Terms_4LS.emf
Figure 3
Voltage and Current definition
In all tables of electrical characteristics the channel related symbols without channel numbers are valid for
each channel separately (e.g. VDS specification is valid for VDS0 ... VDS3).
Furthermore, parameters relative to output current can be indicated without specifying whether the current
is going into the Drain pin or going out of the Source pin, unless otherwise specified. For instance, nominal
output current can be indicated in the following ways: IL(NOM) IL_LS(NOM) IL_D(NOM)
All SPI registers bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.RST) with the exception of the
bits in the Diagnosis frames which are marked only with PARAMETER (e.g. UVRVS).
Datasheet
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Rev. 1.10
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TLE75004-EPD
SPIDER+ 12V
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
CSN
SCLK
SI
SO
GND
OUT0_LS
OUT2_LS
1
2
3
4
5
6
7
15
SUB
exposed pad (bottom)
(top view)
14
13
12
11
10
9
8
VDD
IN0
IN1
IDLE
VS
OUT1_LS
OUT3_LS
PinOut_4LS.emf
Figure 4
Datasheet
Pin Configuration TLE75004-EPD in PG-TSDSO-14
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TLE75004-EPD
SPIDER+ 12V
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
I/O
Function
Power Supply Pins
10
VS
–
Analog supply VS
Positive supply voltage for power switches gate control (incl.
protections)
14
VDD
–
Digital supply VDD
Supply voltage for SPI with support function to VS
5
GND
–
Ground
Ground connection
1
CSN
I
Chip Select
“low” active, integrated pull-up to VDD
2
SCLK
I
Serial Clock
“high” active, integrated pull-down to ground
3
SI
I
Serial Input
“high” active, integrated pull-down to ground
4
SO
O
Serial Output
“Z” (tri-state) when CSN is “high”
SPI Pins
Input and Stand-by Pins
11
IDLE
I
Idle mode
power mode control, “high” active, integrated pull-down to ground
13
IN0
I
Input pin 0
connected to channel 2 by default and in Limp Home mode, “high”
active, integrated pull-down to ground
12
IN1
I
Input pin 1
connected to channel 3 by default and Limp Home mode, “high”
active, integrated pull-down to ground
Power Ouput Pins
6
OUT0_LS
O
Drain of low-side power transistor (channel 0)
7
OUT2_LS
O
Drain of low-side power transistor (channel 2)
8
OUT3_LS
O
Drain of low-side power transistor (channel 3)
9
OUT1_LS
O
Drain of low-side power transistor (channel 1)
GND
–
Exposed pad
It is recommended to connect it to PCB ground for cooling and EMC not usable as electrical GND pin. Electrical ground must be provided
by pin 5.
Cooling Tab
15
Datasheet
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Rev. 1.10
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TLE75004-EPD
SPIDER+ 12V
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings 1)
TJ = -40 °C to +150 °C
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or
Test Condition
Number
Supply Voltages
Analog Supply voltage
VS
-0.3
–
28
V
–
P_4.1.1
Digital Supply voltage
VDD
-0.3
–
5.5
V
–
P_4.1.2
Supply voltage for load dump
protection
VS(LD)
–
–
42
V
2)
P_4.1.3
Supply voltage for short circuit VS(SC)
protection (single pulse)
0
–
28
V
–
P_4.1.4
Reverse polarity voltage
-VS(REV)
–
–
16
V
3)
P_4.1.5
Current through VS pin
IVS
-10
–
10
mA
t ≤ 2 min
P_4.1.7
Current through VDD pin
IVDD
-50
–
10
mA
t ≤ 2 min
P_4.1.8
Load current
|IL|
–
–
IL(OVL0)
A
single channel
P_4.1.9
Voltage at power transistor
VDS
-0.3
–
42
V
–
P_4.1.10
Maximum energy dissipation
single pulse
EAS
–
–
50
mJ
4)
P_4.1.13
Maximum energy dissipation
single pulse
EAS
–
Maximum energy dissipation
repetitive pulses - IL(EAR)
EAR
–
Voltage at IDLE pin
VIDLE
-0.3
5.5
V
–
P_4.1.23
Current through IDLE pin
IIDLE
-0.75
0.75
mA
–
P_4.1.25
TJ(0) = 25 °C
t ≤ 2 min
See Chapter 11 for
general setup.
RL = 70 Ω on all
channels
Power Stages
TJ(0) = 25 °C
IL(0) = 2*IL(EAR)
–
25
mJ
4)
P_4.1.14
TJ(0) = 150 °C
IL(0) = 400 mA
–
10
mJ
4)
P_4.1.16
TJ(0) = 85 °C
IL(0) = IL(EAR)
2*106 cycles
IDLE pin
Datasheet
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Rev. 1.10
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TLE75004-EPD
SPIDER+ 12V
General Product Characteristics
Table 2
Absolute Maximum Ratings (cont’d)1)
TJ = -40 °C to +150 °C
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Min.
Unit
Note or
Test Condition
Number
Typ. Max.
IIDLE
-10.0
2.0
mA
t ≤ 2 min.
P_4.1.26
Voltage at input pins
VIN
-0.3
5.5
V
–
P_4.1.28
Current through input pins
IIN
-0.75
0.75
mA
–
P_4.1.30
Current through input pins
IIN
-10.0
2.0
mA
t ≤ 2 min.
P_4.1.31
VCSN
-0.3
5.5
V
–
P_4.1.33
Current through chip select pin ICSN
-0.75
0.75
mA
–
P_4.1.34
Current through chip select pin ICSN
-10.0
2.0
mA
t ≤ 2 min.
P_4.1.35
Voltage at serial clock pin
-0.3
5.5
V
Current through serial clock pin ISCLK
-0.75
0.75
mA
–
P_4.1.38
Current through serial clock pin ISCLK
-10.0
2.0
mA
t ≤ 2 min.
P_4.1.39
Voltage at serial input pin
-0.3
5.5
V
Current through serial input pin ISI
-0.75
0.75
mA
–
P_4.1.42
Current through serial input pin ISI
-10.0
2.0
mA
t ≤ 2 min.
P_4.1.43
Voltage at serial output pin SO
VSO
-0.3
VDD+0.3 V
P_4.1.58
Current through serial output
pin SO
ISO
-0.75
0.75
mA
P_4.1.45
Current through serial output
pin SO
ISO
-2.0
10.0
mA
t ≤ 2 min.
P_4.1.46
Junction Temperature
TJ
-40
–
150
°C
–
P_4.1.48
Storage Temperature
Tstg
-55
–
150
°C
–
P_4.1.49
ESD Susceptibility HBM
OUT pins vs. VS or GND
VESD
-4
–
4
kV
5)
P_4.1.50
ESD Susceptibility HBM
other pins
VESD
-2
ESD Susceptibility CDM
Pin 1, 7, 8, 14 (corner pins)
VESD
-750
ESD Susceptibility CDM
VESD
-500
Current through IDLE pin
Input Pins
SPI Pins
Voltage at chip select pin
VSCLK
VSI
P_4.1.37
P_4.1.41
Temperatures
ESD Susceptibility
HBM
–
2
kV
5)
P_4.1.51
HBM
–
750
V
6)
P_4.1.53
CDM
–
500
V
6)
P_4.1.54
CDM
1) Not subject to production test, specified by design.
2) For a duration of ton = 400 ms; ton/toff = 10%; limited to 100 pulses
3) Device is mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; the Product
(Chip+Package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Datasheet
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TLE75004-EPD
SPIDER+ 12V
General Product Characteristics
4) Pulse shape represents inductive switch off: IL(t) = IL(0) x (1 - t / tpulse); 0 < t < tpulse
5) ESD susceptibility, Human Body Model “HBM” according to AEC Q100-002
6) ESD susceptibility, Charged Device Mode “CDM” according to AECQ100-011 Rev D
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Table 3
Functional range
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
7
–
18
V
–
P_4.2.1
Upper Supply Voltage Range VS(EXT,UP)
for Extended Operation
18
–
28
V
Parameter
deviation possible
P_4.2.2
Lower Supply Voltage Range VS(EXT,LOW)
for Extended Operation
3
–
7
V
Parameter
deviation possible
P_4.2.3
Junction Temperature
TJ
-40
–
150
°C
–
P_4.2.4
Logic supply voltage
VDD
3
–
5.5
V
–
P_4.2.5
Supply Voltage Range for
Normal Operation
Note:
Datasheet
VS(NOR)
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
table.
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TLE75004-EPD
SPIDER+ 12V
General Product Characteristics
4.3
Thermal Resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 4
Thermal Resistance
Parameter
Symbol
Values
Min.
Typ.
Max.
Junction to Soldering Point RthJSP
–
5
7
Junction to Ambient
–
RthJA
Unit
Note or
Test Condition
Number
K/W
1)
P_4.3.2
measured to
exposed pad (pin 15)
40
–
K/W
2)
P_4.3.6
1) not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product
(Chip+Package) was simulated on a 76.2 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.1
PCB set up
70µm
1.5mm
35µm
0.3mm
Figure 5
Datasheet
Zth_PCB_2s2p.emf
2s2p PCB Cross Section
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TLE75004-EPD
SPIDER+ 12V
General Product Characteristics
Figure 6
PC Board for Thermal Simulation with 600 mm2 Cooling Area
Figure 7
PC Board for Thermal Simulation with 2s2p Cooling Area
Datasheet
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TLE75004-EPD
SPIDER+ 12V
General Product Characteristics
4.3.2
Thermal Impedance
4 Channels Low-side
100
ZthJA (K/W)
Tambient = 105°C
10
1
2s2p
1s0p - 600 mm²
1s0p - 300 mm²
1s0p - footprint
0.1
0.0001
Figure 8
0.001
0.01
0.1
Time (s)
1
10
100
1000
Typical Thermal Impedance. PCB setup according Chapter 4.3.1
4 Channels Low-side
140
1s0p - Tambient = 105°C
130
120
110
RthJA (K/W)
100
90
80
70
60
50
40
0
100
200
300
400
500
600
Area (mm²)
Figure 9
Datasheet
Typical Thermal Resistance. PCB setup 1s0p
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TLE75004-EPD
SPIDER+ 12V
Control Pins
5
Control Pins
The device has three pins (IN0, IN1 and IDLE) to control directly the device without using SPI.
5.1
Input pins
TLE75004-EPD has two input pins available. Each input pin is connected by default to one channel (IN0 to
channel 2, IN1 to channel 3). Input Mapping Registers MAPIN0 and MAPIN1 can be programmed to connect
additional or different channels to each input pin, as shown in Figure 10. The signals driving the channels are
an OR combination between OUT register status, IN0 and IN1 (according to Input Mapping registers status).
IN1
Limp Home mode
(default )
IIN1
MAPIN1
&
4
4
IN0
Limp Home mode
(default )
IIN0
OR
MAPIN0
&
4
4
Channel 3
Channel 2
Channel 1
Channel 0
4
OR
OUT
4
4
InputMapping_4ch.emf
Figure 10
Input Mapping
The logic level of the input pins can be monitored via the Input Status Monitor Register (INST). The Input
Status Monitor is operative also when TLE75004-EPD is in Limp Home mode. If one of the Input pins is set to
“high” and the IDLE pin is set to “low”, the device switches into Limp Home mode and activates the channel
mapped by default to the input pins. See Chapter 6.1.5 for further details.
5.2
IDLE pin
The IDLE pin is used to bring the device into Sleep mode operation when is set to “low” and all input pins are
set to “low”.When IDLE pin is set to “low” while one of the input pins is set to “high” the device enters Limp
Home mode.
To ensure a proper mode transition, IDLE pin must be set for at least tIDLE2SLEEP (P_6.3.54, transition from “high”
to “low”) or tSLEEP2IDLE (P_6.3.53, transition from “low” to “high”).
Setting the IDLE pin to “low” has the following consequences:
•
All registers in the SPI are reset to default values
•
VDD and VS Undervoltage detection circuits are disabled to decrease current consumption (if both inputs
are set to “low”)
Datasheet
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TLE75004-EPD
SPIDER+ 12V
Control Pins
•
No SPI communication is allowed (SO pin remains in high impedance state also when CSN pin is set to
“low”) if both input pins are set to “low”
Datasheet
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TLE75004-EPD
SPIDER+ 12V
Control Pins
5.3
Electrical Characteristics Control Pins
Table 5
Electrical Characteristics: Control Pins
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
Test Condition
Number
Max.
IDLE pin
L-input level
VIDLE(L)
0
0.8
V
–
P_5.3.1
H-input level
VIDLE(H)
2.0
5.5
V
–
P_5.3.2
L-input current
IIDLE(L)
5
12
20
μA
VIDLE = 0.8 V
P_5.3.3
H-input current
IIDLE(H)
14
28
45
μA
VIDLE = 2.0 V
P_5.3.4
L-input level
VIN(L)
0
0.8
V
–
P_5.3.5
H-input level
VIN(H)
2.0
5.5
V
–
P_5.3.6
L-input current
IIN(L)
5
12
20
μA
VIN = 0.8 V
P_5.3.7
H-input current
IIN(H)
14
28
45
μA
VIN = 2.0 V
P_5.3.8
Input Pins
Datasheet
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TLE75004-EPD
SPIDER+ 12V
Power Supply
6
Power Supply
The TLE75004-EPD is supplied by two supply voltages:
•
VS (analog supply voltage used also for the logic)
•
VDD (digital supply voltage)
The VS supply line is connected to a battery feed and used, in combination with VDD supply, for the driving
circuitry of the power stages. In situations where VS voltage drops below VDD voltage (for instance during
cranking events down to 3.0 V), an increased current consumption may be observed at VDD pin.
VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the
associated function in case the measured voltage is below the undervoltage threshold. More in detail:
•
An undervoltage on both VS and VDD supply voltages prevents the activation of the power stages and any
SPI communication (the SPI registers are reset)
•
An undervoltage on VDD supply prevents any SPI communication. SPI read/write registers are reset to
default values.
•
An undervoltage on VS supply forces the TLE75004-EPD to drain all needed current for the low-side
switches and for the logic from VDD supply.
Figure 11 shows a basic concept drawing of the interaction between supply pins VS and VDD, the output stage
drivers and SO supply line.
VS
LS
IVS
VREG
VDD
GD
UVR
VDD
IVDD
GND
UVR
VS
SO
SPI
SupplyConcept_xLS.emf
Figure 11
TLE75004-EPD Internal Power Supply concept
When 3.0 V ≤ VS ≤ VDD - VSDIFF TLE75004-EPD operates in “Cranking Operative Range” (COR). In this condition the
current consumption from VDD pin increases while it decreases from VS pin where the total current
consumption remains within the specified limits. Figure 12 shows the voltage levels at VS pin where the
device goes in and out of COR. During the transition to and from COR operative region, IVS and IVDD change
between values defined for normal operation and for COR operation. The sum of both current remains within
limits specified in “Overall current consumption” section (see Table 8).
Datasheet
17
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Power Supply
VS
VDD + V SDIFF
VDD
V DD - V SDIFF
3.0 V
t
COR
(no)
yes
(no)
t
IVS
Supply transition
Supply transition
IVDD
t
SupplyConcept_COR.emf
Figure 12
“Cranking Operative Range”
Furthermore, when VS(UV) ≤ VS ≤ VS(OP) it may be not possible to switch ON a channel that was previously OFF.
All channels that are already ON keep their state unless they are switched OFF via SPI or via INn pins. An
overview of channel behavior according to different VS and VDD supply voltages is shown in Table 6 (the table
is valid after a successful power-up, see Chapter 6.1.1 for more details).
Datasheet
18
Rev. 1.10
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TLE75004-EPD
SPIDER+ 12V
Power Supply
Table 6
Device capability as function of VS and VDD
VS ≤ 3.0 V
3.0 V = VS(UV),max
(P_6.3.1)
3.0 V < VS ≤ VS(OP)
(VS(OP) = P_6.3.2)
VS > VS(OP)
VDD ≤ VDD(UV)
(VDD(UV) = P_6.3.25)
VDD = VDD(LOP)
(VDD(LOP) = P_6.3.24)
VDD > VDD(LOP)
channels cannot be
controlled
channels can be switched channels can be switched
ON and OFF (SPI control)
ON and OFF (SPI control)
(RDS(ON) deviations possible) (RDS(ON) deviations possible)
SPI registers reset
SPI registers available
SPI registers available
SPI communication not
available (fSCLK = 0 MHz)
SPI communication
possible (fSCLK = 1 MHz)
(P_10.4.34)
SPI communication
possible (fSCLK = 5 MHz)
(P_10.4.22)
Limp Home mode not
available
Limp Home mode available Limp Home mode available
(RDS(ON) deviations possible) (RDS(ON) deviations possible)
channels cannot be
controlled by SPI
channels can be switched channels can be switched
ON and OFF (SPI control)1) ON and OFF (SPI control)1)
(RDS(ON) deviations possible) (RDS(ON) deviations possible)
SPI registers reset
SPI registers available
SPI registers available
SPI communication not
available (fSCLK = 0 MHz)
SPI communication
possible (fSCLK = 1 MHz)
(P_10.4.34)
SPI communication
possible (fSCLK = 5 MHz)
(P_10.4.22)
Limp Home mode
available1) (RDS(ON)
deviations possible)
Limp Home mode
available1) (RDS(ON)
deviations possible)
Limp Home mode available
(RDS(ON) deviations possible)
channels cannot be
controlled by SPI
channels can be switched
ON and OFF
(small RDS(ON) dev. possible
when VS = VS(EXT,LOW))
channels can be switched
ON and OFF
(small RDS(ON) dev. possible
when VS = VS(EXT,LOW))
SPI registers reset
SPI registers available
SPI registers available
SPI communication not
available (fSCLK = 0 MHz)
SPI communication
possible (fSCLK = 5 MHz)
(P_10.4.22)
SPI communication
possible (fSCLK = 5 MHz)
(P_10.4.22)
Limp Home mode available Limp Home mode available Limp Home mode available
(RDS(ON) dev. possible when (RDS(ON) dev. possible when (RDS(ON) dev. possible when
VS = VS(EXT,LOW))
VS = VS(EXT,LOW))
VS = VS(EXT,LOW))
1) undervoltage condition on VS must be considered - see Chapter 6.2.1 for more details
Datasheet
19
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TLE75004-EPD
SPIDER+ 12V
Power Supply
6.1
Operation Modes
TLE75004-EPD has the following operation modes:
•
Sleep mode
•
Idle mode
•
Active mode
•
Limp Home mode
The transition between operation modes is determined according to following levels and states:
•
logic level at IDLE pin
•
logic level at INn pins
•
OUT.OUTn bits state
•
HWCR.ACT bit state
The state diagram including the possible transitions is shown in Figure 13. The behaviour of TLE75004-EPD as
well as some parameters may change in dependence from the operation mode of the device. Furthermore,
due to the undervoltage detection circuitry which monitors VS and VDD supply voltages, some changes within
the same operation mode can be seen accordingly.
The operation mode of the TLE75004-EPD can be observed by:
•
status of output channels
•
status of SPI registers
•
current consumption at VDD pin (IVDD)
•
current consumption at VS pin (IVS)
The default operation mode to switch ON the loads is Active mode. If the device is not in Active mode and a
request to switch ON one or more outputs comes (via SPI or via Input pins), it will switch into Active or Limp
Home mode, according to IDLE pin status. Due to the time needed for such transitions, output turn-on time
tON will be extended due to the mode transition latency.
init
IDLE = „high“
INn = „low“
Sleep
INn = „high“
& IDLE = „low“
IDLE = „low“
Idle
INn = „low“
& VDD < VDD(UV)
IDLE = „low“
& INn = „low“
HWCR.ACT = 0
& OUT.OUTn = 0
& INn = „low“
Limp Home
IDLE = „high“
Active
IDLE = „low“
& INn = „high“
HWCR.ACT = 1
or OUT.OUTn = 1
or INn = „high“
Figure 13
Datasheet
OpModes.emf
Operation Mode state diagram
20
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SPIDER+ 12V
Power Supply
Table 7 shows the correlation between device operation modes, VS and VDD supply voltages, and state of the
most important functions (channels operativity, SPI communication and SPI registers).
Table 7
Device function in relation to operation modes, VS and VDD voltages
Operation
Mode
Function
Undervoltage
Undervoltage
1)
condition on VS
condition on VS
VDD ≤ VDD(UV)
VDD > VDD(UV)
VS not in
undervoltage
VDD ≤ VDD(UV)
VS not in
undervoltage
VDD >VDD(UV)
Sleep
Channels
not available
not available
not available
not available
SPI comm.
not available
not available
not available
not available
SPI registers
reset
reset
reset
reset
Channels
not available
not available
not available
not available
SPI comm.
not available
✓
not available
✓
SPI registers
reset
✓
reset
✓
Channels
not available
✓
✓ (IN pins only)
✓
SPI comm.
not available
✓
not available
✓
SPI registers
reset
✓
reset
✓
not available
✓ (IN pins only)
✓ (IN pins only)
✓ (IN pins only)
not available
✓ (read-only)
not available
✓ (read-only)
reset
✓ (read-only)2)
Idle
Active
Limp Home Channels
SPI comm.
SPI registers
reset
✓ (read-only)
2)
1) see Chapter 6.2.1 for more details
2) see Chapter 6.1.5 for a detailed overview
6.1.1
Power-up
The Power-up condition is satisfied when one of the supply voltages (VS or VDD) is applied to the device and the
INn or IDLE pins are set to “high”. If VS is above the threshold VS(OP) or if VDD is above the threshold VDD(LOP) the
internal power-on signal is set.
6.1.2
Sleep mode
When TLE75004-EPD is in Sleep mode, all outputs are OFF and the SPI registers are reset, independently from
the supply voltages. The current consumption is minimum. See parameters IVDD(SLEEP) and IVS(SLEEP), or
parameter ISLEEP for the whole device.
6.1.3
Idle mode
In Idle mode, the current consumption of the device can reach the limits given by parameters IVDD(IDLE) and
IVS(IDLE), or by parameter IIDLE for the whole device. The internal voltage regulator is working. Diagnosis
functions are not available. The output channels are switched OFF, independently from the supply voltages.
When VDD is available, the SPI registers are working and SPI communication is possible. In Idle mode the ERRn
bits are not cleared for functional safety reasons.
Datasheet
21
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TLE75004-EPD
SPIDER+ 12V
Power Supply
6.1.4
Active mode
Active mode is the normal operation mode of TLE75004-EPD when no Limp Home condition is set and it is
necessary to drive some or all loads. Voltage levels of VDD and VS influence the behavior as described at the
beginning of Chapter 6. Device current consumption is specified with IVDD(ACTIVE) and IVS(ACTIVE) (IACTIVE for the
whole device). The device enters Active mode when IDLE pin is set to “high” and one of the input pins is set to
“high” or one OUT.OUTn bit is set to “1”. If HWCR.ACT is set to “0”, the device returns to Idle mode as soon as
all inputs pins are set to “low” and OUT.OUTn bits are set to “0”. If HWCR.ACT is set to “1”, the device remains
in Active mode independently of the status of input pins and OUT.OUTn bits. An undervoltage condition on
VDD supply brings the device into Idle mode, if all input pins are set to “low”. Even if the registers MAPIN0 and
MAPIN1 are both set to “00H” but one of the input pins INn is set to “high”, the device goes into Active mode.
6.1.5
Limp Home mode
TLE75004-EPD enters Limp Home mode when IDLE pin is “low” and one of the input pins is set to “high”,
switching ON the channel connected to it. SPI communication is possible but only in read-only mode (SPI
registers can be read but cannot be written). More in detail:
•
UVRVS and LOPVDD are set to “1”
•
MODE bits are set to “01B” (Limp Home mode)
•
TER bit is set to “1” on the first SPI command after entering Limp Home mode. Afterwards it works
normally
•
OLOFF bits is set to “0”
•
ERRn bits work normally
•
DIAG_OSM.OUTn bits can be read and work normally
•
All other registers are set to their default value and cannot be programmed as long as the device is in Limp
Home mode
See Table 6 for a detailed overview of supply voltage conditions required to switch ON channels 2 and 3 during
Limp Home. All other channels are OFF.
A transmission of SPI commands during transition from Active to Limp Home mode or Limp Home to Active
mode may result in undefined SPI responses.
6.1.6
Definition of Power Supply modes transition times
The channel turn-ON time is as defined by parameter tON when TLE75004-EPD is in Active mode or in Limp
Home mode. In all other cases, it is necessary to add the transition time required to reach one of the two
aforementioned Power Supply modes (as shown in Figure 14).
Datasheet
22
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TLE75004-EPD
SPIDER+ 12V
Power Supply
init
tSLEEP2IDLE
tLH2SLEEP
Sleep
tIDLE2SLEEP
tACTIVE2SLEEP
Idle
tSLEEP2LH
Channel ON
tON
Limp Home
tON
tACTIVE2IDLE
tLH2ACTIVE
Active
tIDLE2ACTIVE
tACTIVE2LH
OpModesTimings.emf
Figure 14
Transition Time diagram
6.2
Reset condition
One of the following 3 conditions resets the SPI registers to the default value:
•
VDD is not present or below the undervoltage threshold VDD(UV)
•
IDLE pin is set to “low”
•
a reset command (HWCR.RST set to “1”) is executed
– ERRn bits are not cleared by a reset command (for functional safety)
– UVRVS and LOPVDD bits are cleared by a reset command
In particular, all channels are switched OFF (if there are no input pin set to “high”) and the Input Mapping
configuration is reset.
6.2.1
Undervoltage on VS
Between VS(UV) and VS(OP) the undervoltage mechanism is triggered. If the device is operative and the supply
voltage drops below the undervoltage threshold VS(UV), the logic set the bit UVRVS to “1”. As soon as the supply
voltage VS is above the minimum voltage operative threshold VS(OP), the bit UVRVS is set to “0” after the first
Standard Diagnosis readout. Undervoltage condition on VS influences the status of the channels, as described
in Table 6. Figure 15 sketches the undervoltage behavior.
Datasheet
23
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TLE75004-EPD
SPIDER+ 12V
Power Supply
VS
VS(OP)
VS(UV)
VS(HYS)
t
UVRVS
1
0
1
t
Supply_UVRVS_LS.emf
Figure 15
VS Undervoltage Behavior
6.2.2
Low Operating Power on VDD
When VDD supply voltage is in the range indicated by VDD(LOP), the bit LOPVDD is set to “1”. As soon as VDD >
VDD(LOP) the bit LOPVDD is set to “0” after the first Standard Diagnosis readout.
If VDD supply voltage is not present, a voltage applied to pins CSN or SO can supply the internal logic (not
recommended in normal operation due to internal design limitations).
Datasheet
24
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TLE75004-EPD
SPIDER+ 12V
Power Supply
6.3
Electrical Characteristics Power Supply
Table 8
Electrical Characteristics Power Supply
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
Analog supply undervoltage VS(UV)
shutdown
1.5
–
3.0
V
OUTn = ON
from VDS ≤ 1 V
to UVRVS = 1B
RL = 50 Ω
P_6.3.1
Analog supply minimum
operative voltage
VS(OP)
–
–
4.0
V
OUT.OUTn = 1B
from UVRVS = 1B
to VDS ≤ 1 V
RL = 50 Ω
P_6.3.2
Undervoltage shutdown
hysteresis
VS(HYS)
–
1
–
V
1)
P_6.3.3
Analog supply current
IVS(SLEEP)
consumption in Sleep mode
with loads
–
0.1
3
µA
1)
P_6.3.4
Analog supply current
IVS(SLEEP)
consumption in Sleep mode
with loads
–
Analog supply current
IVS(SLEEP)
consumption in Sleep mode
with loads
–
0.1
20
µA
VIDLE floating
VINn floating
VCSN = VDD
TJ = 150 °C
Analog supply current
consumption in Idle mode
with loads
–
–
2.2
mA
IDLE = “high”
P_6.3.6
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS pin
Datasheet
IVS(IDLE)
VIDLE floating
VINn floating
VCSN = VDD
TJ ≤ 85 °C
0.1
–
µA
1)
P_6.3.63
VIDLE floating
VINn floating
VCSN = VDD
TJ ≤ 85 °C
VS = 13.5 V
25
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TLE75004-EPD
SPIDER+ 12V
Power Supply
Table 8
Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
–
–
0.3
mA
P_6.3.7
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS ≤ VDD - 1 V
Analog supply current
IVS(ACTIVE)
consumption in Active mode
with loads - channels OFF
–
–
3.2
mA
IDLE = “high”
P_6.3.11
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
IVS(ACTIVE)
Analog supply current
consumption in Active mode
with loads - channels OFF
(COR)
–
0.1
0.3
mA
P_6.3.12
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS ≤ VDD - 1 V
Analog supply current
IVS(ACTIVE)
consumption in Active mode
with loads - channels ON
–
–
3.2
mA
IDLE = “high”
P_6.3.19
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
DIAG_IOL.OUTn =
0B
VCSN = VDD
Analog supply current
consumption in Idle mode
with loads (COR)
Datasheet
IVS(IDLE)
26
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SPIDER+ 12V
Power Supply
Table 8
Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Analog supply current
IVS(ACTIVE)
consumption in Active mode
with loads - channels ON
(COR)
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
–
0.1
0.3
mA
P_6.3.20
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS ≤ VDD - 1 V
VDD pin
Logic Supply Operating
voltage
VDD(OP)
3.0
–
5.5
V
fSCLK = 5 MHz
P_6.3.23
Logic Supply Lower
Operating Voltage
VDD(LOP)
3.0
–
4.5
V
–
P_6.3.24
Undervoltage shutdown
VDD(UV)
1
–
3.0
V
VSI = 0 V
VSCLK = 0 V
VCSN = 0 V
SO from “low” to
high impedance
P_6.3.25
Logic supply current in
Sleep mode
IVDD(SLEEP)
–
0.1
2.5
µA
1)
P_6.3.26
Logic supply current in
Sleep mode
IVDD(SLEEP)
–
–
10
µA
VIDLE floating
VINn floating
VCSN = VDD
TJ = 150 °C
P_6.3.27
Logic supply current in Idle
mode
IVDD(IDLE)
–
–
0.3
mA
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
VCSN = VDD
P_6.3.28
Logic supply current in Idle
mode (COR)
IVDD(IDLE)
–
–
2.2
mA
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
VCSN = VDD
VS ≤ VDD - 1 V
P_6.3.29
Datasheet
VIDLE floating
VINn floating
VCSN = VDD
TJ ≤ 85 °C
27
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SPIDER+ 12V
Power Supply
Table 8
Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
Logic supply current in
IVDD(ACTIVE)
Active mode - channels OFF
–
–
0.3
mA
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
VCSN = VDD
P_6.3.30
Logic supply current in
IVDD(ACTIVE)
Active mode - channels OFF
(COR)
–
–
3.2
mA
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
VCSN = VDD
VS ≤ VDD - 1 V
P_6.3.34
Logic supply current in
Active mode - channels ON
IVDD(ACTIVE)
–
–
0.3
mA
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1
VCSN = VDD
P_6.3.35
Logic supply current in
Active mode - channels ON
(COR)
IVDD(ACTIVE)
–
–
3.2
mA
IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
VCSN = VDD
VS = VDD - 1 V
P_6.3.38
Overall current
ISLEEP
consumption in Sleep mode
IVS(SLEEP) + IVDD(SLEEP)
–
–
5
µA
1)
P_6.3.40
Overall current
ISLEEP
consumption in Sleep mode
IVS(SLEEP) + IVDD(SLEEP)
–
Overall current consumption
Datasheet
VIDLE floating
VINn floating
VCSN = VDD
TJ ≤ 85 °C
–
5
µA
1)
P_6.3.64
VIDLE floating
VINn floating
VCSN = VDD
TJ ≤ 85 °C
VS = 13.5 V
28
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SPIDER+ 12V
Power Supply
Table 8
Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
P_6.3.41
Min.
Typ.
Max.
–
–
30
µA
VIDLE floating
VINn floating
VCSN = VDD
TJ = 150 °C
–
–
2.5
mA
IDLE = “high”
P_6.3.42
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
Overall current
IACTIVE
consumption in Active mode
- channels OFF
IVS(ACTIVE) + IVDD(ACTIVE)
–
–
3.5
mA
IDLE = “high”
P_6.3.46
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
Overall current
IACTIVE
consumption in Active mode
- channels ON
IVS(ACTIVE) + IVDD(ACTIVE)
–
–
3.5
mA
IDLE = “high”
P_6.3.51
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
DIAG_IOL.OUTn =
0B
VCSN = VDD
Voltage difference between VSDIFF
VS and VDD supply lines
–
200
–
mV
1)
P_6.3.52
–
200
400
µs
1)
P_6.3.53
ISLEEP
Overall current
consumption in Sleep mode
IVS(SLEEP) + IVDD(SLEEP)
Overall current
consumption in Idle mode
IVS(IDLE) + IVDD(IDLE)
IIDLE
Timings
Sleep to Idle delay
Datasheet
tSLEEP2IDLE
from IDLE pin to
TER + INST
register = 8680H
(see
Chapter 10.6.1 for
details)
29
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SPIDER+ 12V
Power Supply
Table 8
Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Idle to Sleep delay
Idle to Active delay
Active to Idle delay
Sleep to Limp Home delay
Limp Home to Sleep delay
Limp Home to Active delay
Datasheet
Symbol
Values
Min.
Typ.
Max.
tIDLE2SLEEP
–
100
200
tIDLE2ACTIVE
–
tACTIVE2IDLE
–
tSLEEP2LH
–
tLH2SLEEP
–
tLH2ACTIVE
–
Unit
Note or
Test Condition
Number
µs
1)
P_6.3.54
from IDLE pin to
Standard
Diagnosis = 0000H
(see Chapter 10.5
for details)
external pull-down
SO to GND
required
100
200
µs
1)
P_6.3.55
from INn or CSN
pins to MODE = 10B
100
200
µs
1)
P_6.3.56
from INn or CSN
pins to MODE = 11B
300
+tON
600
+tON
µs
200
+tOFF
400
+tOFF
µs
50
100
µs
1)
P_6.3.57
from INn pins
to VDS = 10% VS
1)
P_6.3.58
from INn pins to
Standard
Diagnosis = 0000H
(see
Chapter 10.6.1 for
details). External
pull-down SO to
GND required
1)
P_6.3.59
from IDLE pin to
MODE = 10B
30
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SPIDER+ 12V
Power Supply
Table 8
Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 3 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Active to Limp Home delay
Active to Sleep delay
Symbol
tACTIVE2LH
Values
Min.
Typ.
Max.
–
50
100
tACTIVE2SLEEP –
Unit
Note or
Test Condition
Number
µs
1)
P_6.3.60
from IDLE pin to
TER + INST
register = 8683H
(IN0 = IN1 = “high”)
or 8682H(IN1 =
“high”, IN0 =
“low”) or 8681H
(IN1 = “low”, IN0 =
“high”) (see
Chapter 10.5 for
details)
50
100
µs
1)
P_6.3.61
from IDLE pin to
Standard
Diagnosis = 0000H
(see
Chapter 10.6.1 for
details). External
pull-down SO to
GND required.
1) Not subject to production test - specified by design
Datasheet
31
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Power Stages
7
Power Stages
The TLE75004-EPD is an four channels low-side relay switch. The power stages are built by N-channel lateral
power MOSFET transistors.
7.1
Output ON-state resistance
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ.
7.1.1
Switching Resistive Loads
When switching resistive loads the following switching times and slew rates can be considered.
INn /
OUT.OUTn
t ON
V DS
t OFF
t DELAY (ON)
t
t DELAY (OFF)
90% of V S
70% of V S
70%
dV /
dtOFF
dV /
dtON
30%
30% of V S
10% of V S
t
SwitchON .emf
Figure 16
Switching a Resistive Load
7.1.2
Inductive Output Clamp
When switching off inductive loads, the voltage across the power switch rises to VDS(CL) potential, because the
inductance intends to continue driving the current. The voltage clamping is necessary to prevent device
destruction.
Figure 17 shows a concept drawing of the implementation. Nevertheless, the maximum allowed load
inductance is limited. The clamping structure protects the device in all operative modes (Sleep, Idle, Active,
Limp Home).
Datasheet
32
Rev. 1.10
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TLE75004-EPD
SPIDER+ 12V
Power Stages
VS
Low -side
Channel
IL
OUT
I L_D
L,
RL
V DS
V DS(CL)
GND
PowerStage_LS.emf
Figure 17
Output Clamp concept
7.1.3
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE75004-EPD. Equation (7.1)
shows how to calculate the energy for low-side switches:
RL ⋅ IL
V S – V DS ( CL )
L
E = V DS ( CL ) ⋅ --------------------------------- ⋅ ln æ 1 – ---------------------------------ö + I L ⋅ -----è
RL
V S – V DS ( CL )ø
RL
(7.1)
The maximum energy, which is converted into heat, is limited by the thermal design of the component. The
EAR value provided in Table 2 assumes that all channels can dissipate the same energy when the inductances
connected to the outputs are demagnetized at the same time.
7.2
Switching Channels in parallel
In case of appearance of a short circuit with channels in parallel, it may happen that the two channels switch
OFF asynchronously, therefore bringing an additional thermal stress to the channel that switches OFF last. In
order to avoid this condition, it is possible to parametrize in the SPI registers the parallel operation of two
neighbour channels (bits HWCR.PAR). When operating in this mode, the fastest channel to react to an Over
Load or Over Temperature condition will deactivate also the other. The inductive energy that two channels
can handle once set in parallel is lower than twice the single channel energy (see P_7.6.11). It is possible to
synchronize the following couples of channels:
•
channel 0 and channel 2 → HWCR.PAR (0) set to “1”
•
channel 1 and channel 3 → HWCR.PAR (1) set to “1”
The synchronization bits influence only how the channels react to Over Load or Over Temperature conditions.
Synchronized channels have to be switched ON and OFF individually by the micro-controller.
Datasheet
33
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Power Stages
7.3
Electrical Characteristics Power Stages
Table 9
Electrical Characteristics: Power Stage
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Ω
1)
P_7.6.1
Min.
Typ.
Max.
RDS(ON)
–
1.0
–
On-State Resistance
RDS(ON)
–
1.8
2.2
Ω
TJ = 150 °C
P_7.6.2
IL = IL(EAR) = 220 mA
Nominal load current
(all channels active)
IL(NOM)
–
470
5002)3)
mA
1)
Nominal load current
(all channels active)
IL(NOM)
–
Load current for maximum
energy dissipation repetitive
(all channels active)
IL(EAR)
–
Output Characteristics
On-State Resistance
TJ = 25 °C
P_7.6.6
TA = 85 °C
TJ ≤ 150 °C
370
5002)3)
mA
1)
P_7.6.7
TA = 105 °C
TJ ≤ 150 °C
220
–
mA
1)
P_7.6.8
TA = 85 °C
TJ ≤ 150 °C
15
mJ
P_7.6.11
–
Power stage voltage drop at VDS(OP)
low battery
–
–
1
V
RL = 50 Ω supplied P_7.6.12
by VS = 4 V
VS = VS(OP),max or
VDD = 4.5 V, VS pin
open
refer to Figure 17
Drain to Source Output
clamping voltage
VDS(CL)
42
46
55
V
IL = 20 mA
P_7.6.16
Output leakage current
(each channel)
TJ ≤ 85 °C
IL(OFF)
–
0.01
0.5
µA
1)
P_7.6.19
Datasheet
–
1)
EAR
Maximum energy
dissipation repetitive pulses
- 2*IL(EAR)
(two channels in parallel)
TJ(0) = 85 °C
IL(0) = 2*IL(EAR)
2*106 cycles
HWCR.PAR = “1”
for affected
channels
VIN = 0 V or floating
VDS = 28 V
OUT.OUTn = 0
TJ ≤ 85 °C
34
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SPIDER+ 12V
Power Stages
Table 9
Electrical Characteristics: Power Stage (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Output leakage current
(each channel)
TJ = 150 °C
(Low-Side channels)
Symbol
IL(OFF)
Values
Min.
Typ.
Max.
–
0.1
5
Unit
Note or
Test Condition
Number
µA
1)
P_7.6.20
VIN = 0 V or floating
VDS = 28 V
OUT.OUTn = 0
TJ = 150 °C
Timings
Turn-ON delay
tDELAY(ON)
(from INn pin or bit to VOUT =
90% VS)
1
4
8
µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.21
tDELAY(OFF)
Turn-OFF delay
(from INn pin or bit to VOUT =
10% VS)
1
6
12
µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.22
tON
Turn-ON time
(from INn pin or bit to VOUT =
10% VS)
6
15
35
µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.23
tOFF
Turn-OFF time
(from INn pin or bit to VOUT =
90% VS)
6
15
35
µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.24
Turn-ON/OFF matching
tON - tOFF
-10
0
10
µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.25
Turn-ON slew rate
VDS = 70% to 30% VS
dV/dtON
0.7
1.3
1.9
V/µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.26
Turn-OFF slew rate
VDS = 30% to 70% VS
-dV/dtOFF
0.7
1.3
1.9
V/µs
RL = 50 Ω
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.27
–
5
10
µs
1)
P_7.6.45
Internal reference frequency tSYNC
synchronization time
1) Not subject to production test - specified by design
2) If one channel has IL(NOM),max applied, the remaining channels must be underloaded accordingly so that TJ < 150°C
3) IL(NOM),max can reach IL(OVL1),min
Datasheet
35
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Protection Functions
8
Protection Functions
8.1
Over Load Protection
The TLE75004-EPD is protected in case of over load or short circuit of the load. There are two over load current
thresholds (see Figure 18):
•
IL(OVL0) between channel switch ON and tOVLIN
•
IL(OVL1) after tOVLIN
Every time the channel is switched OFF for a time longer than 2 * tSYNC the over load current threshold is set
back to IL(OVL0).
INn
OUT.OUTn
t
IL(OVL0)
IL(OVL)
IL(OVL 1)
t
tOVLIN
OverLoadStep.emf
Figure 18
Over Load current thresholds
In case the load current is higher than IL(OVL0) or IL(OVL1), after time tOFF(OVL) the over loaded channel is switched
OFF and the according diagnosis bit ERRn is set. The channel can be switched ON after clearing the protection
latch by setting the corresponding HWCR_OCL.OUTn bit to “1”. This bit is set back to “0” internally after delatching the channel. Please refer to Figure 19 for details.
INn
OUT.OUTn
t
ILn
IL(OVLn)
tOFF(OVL)
t
ERRn
0
1
0
t
SPI command to set
HWCR_OCL.OUTn = 1b
HWCR_OCL.OUTn
t
0
1
0
t
OverLoad.emf
Figure 19
Latch OFF at Over Load
8.2
Over Temperature Protection
A temperature sensor is integrated for each channel, causing an overheated channel to switch OFF to prevent
destruction. The according diagnosis bit ERRn is set (combined with Over Load protection). The channel can
Datasheet
36
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Protection Functions
be switched ON after clearing the protection latch by setting the corresponding HWCR_OCL.OUTn bit to “1”.
This bit is set back to “0” internally after de-latching the channel.
8.3
Over Temperature and Over Load Protection in Limp Home mode
When TLE75004-EPD is in Limp Home mode, channels 2 and 3 can be switched ON using the input pins. In case
of Over Load, Short Circuit or Over Temperature the channels switch OFF. If the input pins remain “high”, the
channels restart with the following timings:
•
10 ms (first 8 retries)
•
20 ms (following 8 retries)
•
40 ms (following 8 retries)
•
80 ms (as long as the input pin remains “high” and the error is still present)
If at any time the input pin is set to “low” for longer than 2*tSYNC, the restart timer is reset. At the next channel
activation while in Limp Home mode the timer starts from 10 ms again. See Figure 20 for details. Over Load
current thresholds behave as described in Chapter 8.1.
IN0
IN1
IL2
IL3
0
1
8
1
8
1
0
8
t RETRY0(LH)
tRETRY 1(LH)
t RETRY2(LH)
tRETRY 3(LH)
10 ms
20 ms
40 ms
80 ms
1
tRETRY 0(LH)
t
t
10 ms
LHrestart.emf
Figure 20
Restart timer in Limp Home mode
8.4
Reverse Polarity Protection
In Reverse Polarity (also known as Reverse Battery) condition, power dissipation is caused by the intrinsic
body diode of each DMOS channel. Each ESD diode of the logic and supply pins contributes to total power
dissipation. The reverse current through the channels has to be limited by the connected loads. The current
through digital power supply VDD and input pins has to be limited as well (please refer to the Absolute
Maximum Ratings listed on Chapter 4.1).
Note:
No protection mechanism like temperature protection or current limitation is active during reverse
polarity.
8.5
Over Voltage Protection
In the case of supply voltages between VS(SC) and VS(LD) the output transistors are still operational and follow
the input pins or the OUT register.
In addition to the output clamp for inductive loads as described in Chapter 7.1.2, there is a clamp mechanism
available for over voltage protection for the logic and all channels, monitoring the voltage between VS and
GND pins (VS(AZ)).
Datasheet
37
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Protection Functions
8.6
Electrical Characteristics Protection
Table 10
Electrical Characteristics Protection
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
Over Load detection current IL(OVL0)
1.3
1.7
2.3
A
TJ = -40 °C
P_8.8.19
Over Load detection current IL(OVL0)
1.25
1.55
2.3
A
1)
P_8.8.20
Over Load detection current IL(OVL0)
1
1.45
2
A
TJ = 150 °C
P_8.8.21
Over Load detection current IL(OVL1)
0.7
0.95
1.3
A
P_8.8.22
Over Load detection current IL(OVL1)
0.65
0.85
1.3
A
TJ = -40 °C
1)
Over Load detection current IL(OVL1)
0.5
0.8
1.25
A
Over Load threshold switch tOVLIN
delay time
110
170
260
µs
Over Load shut-down delay tOFF(OVL)
time
4
7
11
µs
Over Load
TJ = 25 °C
P_8.8.23
TJ = 25 °C
TJ = 150 °C
1)
1)
P_8.8.24
P_8.8.5
P_8.8.26
Over Temperature and Over Voltage
Thermal shut-down
temperature
TJ(SC)
150
1751)
2201)
°C
Over voltage protection
VS(AZ)
42
50
60
V
IVS = 10 mA
Sleep mode
P_8.8.8
Drain Source diode during
reverse polarity
VDS(REV)
–
800
–
mV
1)
P_8.8.9
Drain Source diode during
reverse polarity
VDS(REV)
–
650
–
mV
IL = -10 mA
TJ = 150 °C
Sleep mode
P_8.8.10
Restart time in Limp Home
mode
tRETRY0(LH)
7
10
13
ms
1)
P_8.8.13
Restart time in Limp Home
mode
tRETRY1(LH)
14
20
26
ms
1)
P_8.8.14
Restart time in Limp Home
mode
tRETRY2(LH)
28
40
52
ms
1)
P_8.8.15
Restart time in Limp Home
mode
tRETRY3(LH)
56
80
104
ms
1)
P_8.8.16
P_8.8.7
Reverse Polarity
IL = -10 mA
TJ = 25 °C
Sleep mode
Timings
1) Not subject to production test - specified by design
Datasheet
38
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Diagnosis
9
Diagnosis
The SPI of TLE75004-EPD provides diagnosis information about the device and the load status. Each channel
diagnosis information is independent from other channels. An error condition on one channel has no
influence on the diagnostic of other channels in the device (unless configured to work in parallel, see
Chapter 7.2 for more details).
9.1
Over Load and Over Temperature
When either an Over Load or an Over Temperature occurs on one channel, the diagnosis bit ERRn is set
accordingly. As described in Chapter 8.1 and Chapter 8.2, the channel latches OFF and must be reactivated
setting corresponding HWCR_OCL.OUTn bit to “1”.
9.2
Output Status Monitor
The device compares each channel VDS with VDS(OL) and sets the corresponding DIAG_OSM.OUTn bits
accordingly. The bits are updated every time DIAG_OSM register is read.
•
VDS < VDS(OL) → DIAG_OSM.OUTn = “1”
A diagnosis current IOL in parallel to the power switch can be enabled by programming the DIAG_IOL.OUTn
bit, which can be used for Open Load at OFF detection. Each channel has its dedicated diagnosis current
source. If the diagnosis current IOL is enabled or if the channel changes state (ON → OFF or OFF → ON) it is
necessary to wait a time tOSM for a reliable diagnosis. Enabling IOL current sources increases the current
consumption of the device. Even if an Open Load is detected, the channel is not latched OFF.
See Figure 21 for a timing overview (the values of DIAG_IOL.OUTn refer to a channel in normal operation
properly connected to the load).
INn
OUT.OUTn
t
Output voltage
comparator
0
x
1
x
tON + tOSM
0
t
tOFF + tOSM
SPI readout of
DIAG_OSM.OUTn
t
DIAG_OSM.OUTn
x
1
x
0
0
t
OutStatMon_timings.emf
Figure 21
Output Status Monitor timing
Output Status Monitor diagnostic is available when VS = VS(NOR) and VDD ≥ VDD(UV).
Due to the fact that Output Status Monitor checks the voltage level at the outputs in real time, for Open Load
in OFF diagnostic it is necessary to synchronize the reading of DIAG_OSM register with the OFF state of the
channels.
Datasheet
39
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Diagnosis
Figure 22 shows how Output Status Monitor is implemented at concept level.
VS
Low-side
Channel
VDS < V DS(OL) à DIAG_OSM.OUTn = „1"
IOL
ROL
OUT
DIAG_OSM.OUTn
VDS
IOL
V DS(OL)
GND
OutStatMon_LS.emf
Figure 22
Output Status Monitor - concept
In Standard Diagnosis the bit OLOFF represents the OR combination of all DIAG_OSM.OUTn bits for all
channels in OFF state which have the corresponding current source IOL activated.
Datasheet
40
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Diagnosis
9.3
Electrical Characteristics Diagnosis
Table 11
Electrical Characteristics Diagnosis
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
1)
P_9.5.1
Output Status Monitor
Output Status Monitor
comparator settling time
tOSM
–
–
20
µs
Output Status Monitor
threshold voltage
VDS(OL)
3
3.3
3.6
V
Output diagnosis current
IOL
70
85
100
µA
VDS = 3.3 V
P_9.5.5
Open Load equivalent
resistance
ROL
30
–
300
kΩ
1)
P_9.5.6
P_9.5.2
1) Not subject to production test - specified by design
Datasheet
41
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
10
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:
SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of
CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted
out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo
8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.
Otherwise a TER bit is asserted. In this way the interface provides daisy chain capability with 16 bit as well as
with 8 bit SPI devices.
SO
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SI
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
LSB
CSN
SCLK
time
SPI _16bit.emf
Figure 23
Serial Peripheral Interface
10.1
SPI Signal Description
CSN - Chip Select
The system microcontroller selects the TLE75004-EPD by means of the CSN pin. Whenever the pin is in “low”
state, data transfer can take place. When CSN is in "high" state, any signals at the SCLK and SI pins are ignored
and SO is forced into a high impedance state.
CSN “high” to “low” Transition
•
The requested information is transferred into the shift register.
•
SO changes from high impedance state to "high" or “low” state depending on the logic OR combination
between the transmission error flag (TER) and the signal level at pin SI. This allows to detect a faulty
transmission even in daisy chain configuration.
•
If the device is in Sleep mode, SO pin remains in high impedance state and no SPI transmission occurs.
TER
SI
OR
1
SO
0
SI
SO
SPI
S
CSN
SCLK
S
SPI _TER.emf
Figure 24
Datasheet
Combinatorial Logic for TER bit
42
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2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
CSN “low” to "high" Transition
•
Command decoding is only done, when after the falling edge of CSN exactly a multiple (1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
•
Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the
falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the
serial clock. It is essential that the SCLK pin is in “low” state whenever chip select CSN makes any transition,
otherwise the command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling
edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to
Chapter 10.5 for further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN
pin goes to “low” state. New data appears at the SO pin following the rising edge of SCLK.
Please refer to Chapter 10.5 for further information.
10.2
Daisy Chain Capability
The SPI of TLE75004-EPD provides daisy chain capability. In this configuration several devices are activated by
the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 25), in order to build a chain. The end of the chain is connected to the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
Figure 25
SO
SPI
SI
SO
SPI
SCLK
SI
device 3
CSN
SCLK
MI
MCSN
MCLK
SO
SPI
CSN
SI
CSN
MO
device 2
SCLK
device 1
SPI_DaisyChain_1.emf
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK.
The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is finished.
Datasheet
43
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
In single chip configuration, the CSN line must turn “high” to make the device acknowledge the transferred
data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using
three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on
how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn “high” (see
Figure 26).
MI
SO device 3
SO device 2
SO device 1
MO
SI device 3
SI device 2
SI device 1
MCSN
MCLK
SPI_DaisyChain_2.emf
Figure 26
Data Transfer in Daisy Chain Configuration
10.3
Timing Diagrams
t CSN(lead)
t CSN(lag)
tCSN(td)
tSCLK(P )
CSN
tSCLK (H)
V CSN(H)
V CSN(L)
tSCLK (L)
V SCLK(H)
V SCLK(L)
SCLK
tSI (s u)
t SI (h)
V SI (H)
V SI (L)
SI
t SO(en)
tSO(v )
tSO (dis )
V SO(H)
V SO(L)
SO
SPI _Timings.emf
Figure 27
Datasheet
Timing Diagram SPI Access
44
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
10.4
Electrical Characteristics
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Table 12
Electrical Characteristics Serial Peripheral Interface (SPI)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
Input Characteristics (CSN, SCLK, SI) - “low” level of pin
CSN
VCSN(L)
0
–
0.8
V
–
P_10.4.1
SCLK
VSCLK(L)
0
–
0.8
V
–
P_10.4.2
SI
VSI(L)
0
–
0.8
V
–
P_10.4.3
Input Characteristics (CSN, SCLK, SI) - “high” level of pin
CSN
VCSN(H)
2
–
VDD
V
–
P_10.4.4
SCLK
VSCLK(H)
2
–
VDD
V
–
P_10.4.5
SI
VSI(H)
2
–
VDD
V
–
P_10.4.6
L-input pull-up current at CSN pin -ICSN(L)
30
60
90
μA
VDD = 5 V
VCSN = 0.8 V
P_10.4.7
H-input pull-up current at CSN pin -ICSN(H)
20
40
65
μA
VDD = 5 V
VCSN = 2 V
P_10.4.8
Input Pull-Up Current at Pin CSN
L-Input Pull-Down Current at Pin
SCLK
ISCLK(L)
5
12
20
μA
VSCLK = 0.8 V
P_10.4.9
SI
ISI(L)
5
12
20
μA
VSI = 0.8 V
P_10.4.10
SCLK
ISCLK(H)
14
28
45
μA
VSCLK = 2 V
P_10.4.11
SI
ISI(H)
14
28
45
μA
VSI = 2 V
P_10.4.12
L level output voltage
VSO(L)
0
–
0.4
V
ISO = -1.5 mA
P_10.4.13
H level output voltage
VSO(H)
VDD - 0.4 –
VDD
V
ISO = 1.5 mA
P_10.4.14
Output tristate leakage current
ISO(OFF)
-1
–
1
μA
VCSN =VDD
VSO = 0 V
P_10.4.15
Output tristate leakage current
ISO(OFF)
-1
–
1
μA
VCSN =VDD
VSO = VDD
P_10.4.16
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead)
200
–
–
ns
1)
P_10.4.17
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag)
200
H-Input Pull-Down Current at Pin
Output Characteristics (SO)
Timings
Datasheet
VDD = 4.5 V or VS
>7V
–
–
ns
1)
P_10.4.18
VDD = 4.5 V or VS
>7V
45
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
Table 12
Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)
Parameter
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
Transfer delay time (rising CSN to tCSN(td)
falling CSN)
250
–
–
ns
Output enable time (falling CSN to tSO(en)
SO valid)
–
Output disable time (rising CSN to tSO(dis)
SO tristate)
–
Serial clock frequency
fSCLK
–
tSCLK(P)
200
tSCLK(H)
75
tSCLK(L)
75
Serial clock period
Serial clock “high” time
Serial clock “low” time
Symbol
Values
–
200
ns
1)
P_10.4.20
VDD = 4.5 V or VS
>7V
CL = 20 pF at SO
pin
–
200
ns
1)
P_10.4.21
VDD = 4.5 V or VS
>7V
CL = 20 pF at SO
pin
–
5
MHz
1)
P_10.4.22
VDD = 4.5 V or VS
>7V
–
–
ns
1)
P_10.4.23
VDD = 4.5 V or VS
>7V
–
–
ns
1)
P_10.4.24
VDD = 4.5 V or VS
>7V
–
–
ns
1)
P_10.4.25
VDD = 4.5 V or VS
>7V
20
Data hold time (falling SCLK to SI) tSI(h)
20
Output data valid time with
capacitive load
tSO(v)
–
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead)
1
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag)
1
Datasheet
P_10.4.19
VDD = 4.5 V or VS
>7V
Data setup time (required time SI tSI(su)
to falling SCLK)
Transfer delay time (rising CSN to tCSN(td)
falling CSN)
1)
–
–
ns
1)
P_10.4.26
VDD = 4.5 V or VS
>7V
–
–
ns
1)
P_10.4.27
VDD = 4.5 V or VS
>7V
–
100
ns
1)
P_10.4.28
VDD = 4.5 V or VS
>7V
CL = 20 pF at SO
pin
–
–
μs
1)
P_10.4.29
VDD = VS = 3.0 V
–
–
μs
1)
P_10.4.30
VDD = VS = 3.0 V
1.25
–
–
μs
1)
P_10.4.31
VDD = VS = 3.0 V
46
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
Table 12
Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)
Parameter
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
Output enable time (falling CSN to tSO(en)
SO valid)
–
–
1
μs
Output disable time (rising CSN to tSO(dis)
SO tristate)
–
Serial clock frequency
fSCLK
–
tSCLK(P)
1
tSCLK(H)
375
tSCLK(L)
375
Serial clock period
Serial clock “high” time
Serial clock “low” time
Symbol
Values
P_10.4.32
VDD = VS = 3.0 V
CL = 20 pF at SO
pin
–
1
μs
1)
P_10.4.33
VDD = VS = 3.0 V
CL = 20 pF at SO
pin
–
1
MHz
1)
P_10.4.34
VDD = VS = 3.0 V
–
–
μs
1)
P_10.4.35
VDD = VS = 3.0 V
–
–
ns
1)
P_10.4.36
VDD = VS = 3.0 V
–
–
ns
1)
P_10.4.37
VDD = VS = 3.0 V
Data setup time (required time SI tSI(su)
to falling SCLK)
100
Data hold time (falling SCLK to SI) tSI(h)
100
Output data valid time with
capacitive load
–
tSO(v)
1)
–
–
ns
1)
P_10.4.38
VDD = VS = 3.0 V
–
–
ns
1)
P_10.4.39
VDD = VS = 3.0 V
–
500
ns
1)
P_10.4.40
VDD = VS = 3.0 V
CL = 20 pF at SO
pin
1) Not subject to production test, specified by design
Datasheet
47
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
10.5
SPI Protocol
The relationship between SI and SO content during SPI communication is shown in Figure 28. SI line
represents the frame sent from the µC and SO line is the answer provided by TLE75004-EPD.
SI
frame A
frame B
frame C
SO
(previous
response )
response to
frame A
response to
frame B
SPI_SI2SO.emf
Figure 28
Relationship between SI and SO during SPI communication
The SPI protocol provides the answer to a command frame only with the next transmission triggered by the
µC. Although the biggest majority of commands and frames implemented in TLE75004-EPD can be decoded
without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous
transmission to decode TLE75004-EPD response frame completely.
More in detail, the sequence of commands to “read” and “write” the content of a register looks as follows:
SI
write register A
read register A
(new command )
SO
(previous
response )
Standard
diagnostic
register A
content
SPI_RWseq.emf
Figure 29
Register content sent back to µC
There are 3 special situations where the frame sent back to the µC is not related directly to the previous
received frame:
•
in case an error in transmission happened during the previous frame (for instance, the clock pulses were
not multiple of 8 with a minimum of 16 bits), shown in Figure 30
•
when TLE75004-EPD logic supply comes out of Power-On reset condition or after a Software Reset, as
shown in Figure 31
•
in case of command syntax errors
– “write” command starting with “11” instead of “10”
– “read” command starting with “00” instead of “01”
– “read” or “write” commands on registers which are “reserved” or “not used”
Datasheet
48
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
SI
frame A
(error in transmission )
SO
(previous response )
(new command)
Standard diagnostic + TER
SPI_SO_TER.emf
Figure 30
TLE75004-EPD response after a error in transmission
VDD ≥ VDD(PO)
SI
SO
frame A
frame B
frame C
INST register + TER
(8680h)
(SO = „Z“)
response to frame B
SPI _SO_POR.emf
Figure 31
TLE75004-EPD response after coming out of Power-On reset at VDD
SI
frame A
(syntax or addressing error )
(new command)
SO
(previous response )
Standard diagnostic
SPI_SO_SyntaxError.emf
Figure 32
TLE75004-EPD response after a command syntax error
A summary of all possible SPI commands is presented in Table 13, including the answer that TLE75004-EPD
sends back at the next transmission.
Datasheet
49
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
Table 13
SPI Command summary1)
Requested Operation
Frame sent to SPIDER+ (SI pin)
Frame received from SPIDER+ (SO
pin) with the next command
Read Standard Diagnosis
0xxxxxxxxxxxxx01B
(“xxxxxxxxxxxxB” = don´t care)
0dddddddddddddddB
(Standard Diagnosis)
Write 8 bit register
0dddddddddddddddB
10aaaabbccccccccB
where:
(Standard Diagnosis)
“aaaaB” = register address ADDR0
“bbB” = register address ADDR1
“ccccccccB” = new register content
Read 8 bit registers
01aaaabbxxxxxx10B
where:
“aaaaB” = register address ADDR0
“bbB” = register address ADDR1
“xxxxxxB” = don´t care
10aaaabbccccccccB
where:
“aaaaB” = register address ADDR0
“bbB” = register address ADDR1
“ccccccccB” = register content
1) “a” = address bits for ADDR0 field, “b” = address bit for ADDR1 field, “c” = register content, “d” = diagnostic bit
Datasheet
50
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
10.6
SPI Registers Overview
10.6.1
Standard Diagnosis
Table 14
Standard Diagnosis
15
0
14
13
12
UVR LOP MODE
VS
VDD
11
10
TER 0
9
8
OL
OFF
7
6
0
0
5
0
4
0
3
2
1
0
ERR
Default
7800H
Field
Bits
Type
Description
UVRVS
14
r
VS Undervoltage Monitor
0B No undervoltage condition on VS detected (see Chapter 6.2.1
for more details)
1B (default) There was at least one VS Undervoltage condition
since last Standard Diagnosis readout
LOPVDD
13
r
VDD Lower Operating Range Monitor
0B VDD is above VDD(LOP)
1B (default) There was at least one “VDD = VDD(LOP)” condition since
last Standard Diagnosis readout
MODE
12:11
r
Operative Mode Monitor
00B (reserved)
01B Limp Home Mode
10B Active Mode
11B (default) Idle Mode
TER
10
r
Transmission Error
0B Previous transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1B (default) Previous transmission failed
The first frame after a reset is TER set to “high” and the INST
register. The second frame is the Standard Diagnosis with TER set to
“low” (if there was no fail in the previous transmission).
OLOFF
8
r
Open Load in OFF Diagnosis
0B (default) All channels in OFF state (which have
DIAG_IOL.OUTn bit set to “1”) have VDS > VDS(OL)
1B At least one channel in OFF state (with DIAG_IOL.OUTn bit set
to “1”) has VDS < VDS(OL)
Channels in ON state are not considered
ERRn
n:0
r
Over Load / Over Temperature Diagnosis of channel n
0B (default) No failure detected
1B Over Temperature or Over Load
bits 7:4 - reserved (default: 0B)
n = 3 to 0
Datasheet
51
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
10.6.2
Register structure
The register banks the digital part have following structure:
Table 15
15
14
Register structure - all registers
13
12
11
10
9
r = 0 r = 1 ADDR0
w=1 w=0
8
ADDR1
7
6
5
4
3
DATA
2
1
0
Default
XXXXH
Table 16 summarizes the available registers with their addresing space and size
Table 16
Register addressing space
Register name ADDR0 ADDR1 Size Type
OUT
0000B
00B
n
r/w
Power output control register
bits OUT.OUTn
0B (default) Output is OFF
1B Output is ON
bits 7:4 - reserved (read default: 0B, write ignored)
0001B
00B
n
r/w
Input Mapping (Input Pin 0)
bits MAPIN0.OUTn
0B (default) The output is not connected to the input
pin
1B The output is connected to the input pin
Note: Channel 2 has the corresponding bit set to “1” by
default
bits 7:4 - reserved (read default: 0B, write ignored)
0001B
01B
n
r/w
Input Mapping (Input Pin 1)
bits MAPIN1.OUTn
0B (default) The output is not connected to the input
pin
1B The output is connected to the input pin
Note: Channel 3 has the corresponding bit set to “1” by
default
bits 7:4 - reserved (read default: 0B, write ignored)
0001B
10B
8
r
Input Status Monitor
bit TER
0B Previous transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1B (default) Previous transmission failed
bits INST.RES (6:2) - reserved
bits INST.INn (1:0)
0B (default) The input pin is set to “low”
1B The input pin is set to “high”
First register transmitted after a reset of the logic
n = 3 to 0
MAPIN0
n = 3 to 0
MAPIN1
n = 3 to 0
INST
Datasheet
Purpose
52
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
Table 16
Register addressing space (cont’d)
Register name ADDR0 ADDR1 Size Type
DIAG_IOL
0010B
00B
n
r/w
Open Load diagnostic current control
bits DIAG_IOL.OUTn
0B (default) Diagnosis current not enabled
1B Diagnosis current enabled
bits 7:4 - reserved (read default: 0B, write ignored)
0010B
01B
n
r
Output Status Monitor
bits DIAG_OSM.OUTn
0B (default) VDS > VDS(OL)
1B VDS < VDS(OL)
bits 7:4 - reserved (default: 0B)
0011B
00B
8
r/w
Hardware Configuration Register
bit HWCR.ACT (7) (Active Mode)
0B (default) Normal operation or device leaves Active
Mode
1B Device enters Active Mode
(see Chapter 6.1 for a description of the possible
operative mode transitions)
bit HWCR.RST (6) (Reset)
0B (default) Normal operation
1B Execute Reset command (self clearing)
bits HWCR.PAR (1:0) (channels operating in parallel)
0B (default) Normal operation
1B two neighbour channels have Over Load and Over
Temperature synchronized (see Chapter 7.2 for
more details)
n = 3 to 0
DIAG_OSM
n = 3 to 0
HWCR
Purpose
bits 5:2 - reserved (read default: 0B, write ignored)
HWCR_OCL
01B
0011B
n
w
Output Clear Latch
bits HWCR_OCL.OUTn
0B (default) Normal operation
1B Clear the error latch for the selected output
bits 7:4 - reserved (default: 0B, write ignored)
n = 3 to 0
10.6.3
Register summary
All registers with addresses not mentioned in Table 17 have to be considered as “reserved”. “Read”
operations performed on those registers return the Standard Diagnosis. The column “Default” indicates the
content of the register (8 bits) after a reset.
Table 17
15
14
Addressable registers
13-10
9
8
7
6
5
4
3
2
1
0
Default
r = 0 r = 1 0000
w=1 w=0
00
(reserved)
OUT.OUTn
00H
r = 0 r = 1 0001
w=1 w=0
00
(reserved)
MAPIN0.OUTn
04H
Datasheet
53
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Serial Peripheral Interface (SPI)
Table 17
15
14
Addressable registers
13-10
9
8
7
6
5
4
3
2
1
0
r = 0 r = 1 0001
w=1 w=0
01
(reserved)
0
0001
10
TER
r = 0 r = 1 0010
w=1 w=0
00
(reserved)
DIAG_IOL.OUTn
00H
0
0010
01
(reserved)
DIAG_OSM.OUTn
00H
r = 0 r = 1 0011
w=1 w=0
00
HWC HWC (reserved)
R.ACT R.RST
r = 0 r = 1 0011
w=1 w=0
01
(reserved)
1
1
10.6.4
MAPIN1.OUTn
Default
(reserved)
08H
INST.INn
HWCR.PAR
HWCR_OCL.OUTn
00H
00H
00H
SPI command quick list
A summary of the most used SPI commands (read and write operations on all registers) is shown in Table 18
Table 18
SPI command quick list
Register
“read” command”
“write” command
content written
OUT
4002H
80XXH
XXH = xxxxxxxxB
MAPIN0
4402H
84XXH
XXH = xxxxxxxxB
MAPIN1
4502H
85XXH
XXH = xxxxxxxxB
INST
4602H
n.a. (read-only)
–
DIAG_IOL
4802H
88XXH
XXH = xxxxxxxxB
DIAG_OSM
4902H
n.a. (read-only)
–
HWCR
4C02H
8CXXH
XXH = xxxxxxxxB
HWCR_OCL
4D02H
8DXXH
XXH = xxxxxxxxB
Datasheet
54
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Application Information
11
Application Information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBA TT
CVDD
VDD
VDD
GPO
RIN
GPO
RIN
GPO
RIDLE
ROUT1
IN0_LH
IN1_LH
CVS
ZOUT2
RVDD
ZOUT3
VDD
VS
IN0
IN1
RLH
OUT0_LS
IDLE
OUT1_LS
LIMPHOME
ZVS
OUT2_LS
GPO
RCSN
CSN
GPO
RSCLK
SCLK
GPO
RSI
SI
GPI
RSO
SO
COUT
COUT
COUT
GND
COUT
GND
OUT3_LS
Application_4LS.emf
Figure 33
TLE75004-EPD Application Diagram
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.
Table 19
Suggested Component values
Reference
Value
Purpose
RIN
4.7 kΩ
Protection of the micro-controller during Over Voltage and Reverse Polarity
Guarantee TLE75004-EPD channels OFF during Loss of Ground
RIDLE
4.7 kΩ
Protection of the micro-controller during Over Voltage and Reverse Polarity
Guarantee TLE75004-EPD channels OFF during Loss of Ground
RCSN
500 Ω
Protection of the micro-controller during Over Voltage and Reverse Polarity
RSCLK
500 Ω
Protection of the micro-controller during Over Voltage and Reverse Polarity
RSI
500 Ω
Protection of the micro-controller during Over Voltage and Reverse Polarity
RSO
500 Ω
Protection of the micro-controller during Over Voltage and Reverse Polarity
RVDD
100 Ω
Logic supply voltage spikes filtering
Datasheet
55
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Application Information
Table 19
Suggested Component values (cont’d)
Reference
Value
Purpose
CVDD
100 nF
Logic supply voltage spikes filtering
CVS
68 nF
Analog supply voltage spikes filtering
ZVS
P6SMB30
Protection of device during Over Voltage. Zener diode
COUT
10 nF
Protection of TLE75004-EPD against ESD and BCI
11.1
Further Application Information
•
Please contact us for information regarding the Pin FMEA
•
For further information you may contact http://www.infineon.com/
Datasheet
56
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Package Outlines
H
8° M
.06
0.2 +0
0.00
6 x 0.65 = 3.9
1.15 MAX.
Package Outlines
0.05±0.05
STANDOFF
0.95±0.05
12
AX
0.65
C
0.08 14x
SEATING COPLANARITY
PLANE
0.25±0.05
0.2
4.9±0.1
A
2)
1
7
0.2 C 14x
4±0.1
0.1 H A-B 2x
0.1 H B 2x
8
14
0.15
A-B C
0.15
D
INDEX
MARKING
B
1
7
2.65±0.1
1)
3.9±0.1
8
6±0.2
A-B C 14x
1)
14
0.67±0.25
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.15 MAX. PER SIDE
2) 2) DOES NOT INCLUDE DAMBAR PROTRUSION OF 0.13 MAX.
Figure 34
PG-TSDSO-14 Package drawing
PG-TSDSO-14: Boardpads & Apertures
0.45
0.65
0.45
2.65
5.7
5.7
2.65
1.31
1.31
0.65
1.075
1.85
4
copper
Figure 35
Datasheet
solder mask
stencil apertures
TLE75004-EPD Package pads and stencil
57
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Datasheet
58
Dimensions in mm
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Revision History
13
Revision History
Page or Item
Changes since previous revision
Rev. 1.10, 2020-09-02
All
Package name updated
Table 2
Updated ESD susceptibility footnotes for HBM and CDM
Updated backcover
Rev.1.00, 2017-11-23
All
Datasheet released
TLE75004-EPD
Datasheet
59
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.2
4.3
4.3.1
4.3.2
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
5.1
5.2
5.3
Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IDLE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical Characteristics Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.2.1
6.2.2
6.3
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Definition of Power Supply modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low Operating Power on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Inductive Output Clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum Load Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Switching Channels in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
8.1
8.2
8.3
8.4
8.5
8.6
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Over Temperature and Over Load Protection in Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9
9.1
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Over Load and Over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Datasheet
60
Rev. 1.10
2020-09-02
TLE75004-EPD
SPIDER+ 12V
9.2
9.3
Output Status Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
10.1
10.2
10.3
10.4
10.5
10.6
10.6.1
10.6.2
10.6.3
10.6.4
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11
11.1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Datasheet
61
Rev. 1.10
2020-09-02
Please read the Important Notice and Warnings at the end of this document
Trademarks of Infineon Technologies AG
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2020-09-02
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
Email: erratum@infineon.com
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
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In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
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For further information on technology, delivery terms
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WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
