TLE8080EM
Engine Management IC for Small Engines
1
Overview
Features
•
Supply 5 V (+/-2%), 250 mA
•
K-line transceiver (ISO 9141)
•
Serial Peripheral Interface (SPI)
•
4 low side driver for inductive loads with overtemperature and
overcurrent protection and open load/short to GND in off diagnosis:
– 2 low side switches with maximum operation of 2.6 A
– 2 low side switches with maximum operation of 350 mA
•
1 low side driver for resistive loads with maximum operation current
of 3 A including overtemperature and overcurrent protection
•
Configurable variable reluctance sensor interface
•
Reset output and 5 V undervoltage detection
•
Watchdog
•
Green Product (RoHS compliant)
•
AEC Qualified
Description
The TLE8080EM is an engine management IC based on Infineon Smart Power Technology (SPT). It is protected
by embedded protection functions and integrates a power supply, K-line, SPI, variable reluctance sensor
interface and power stages to drive different loads in an engine management system. It provides a compact
and cost optimized solution for engine management systems. It is very suitable for one cylinder motorcycle
engine management systems.
TLE8080-2EM and TLE8080-3EM
TLE8080-2EM differs from the main version in parameters “V5DD reset threshold for TLE8080-2EM and
TLE8080-3EM” and “Power on reset delay time for TLE8080-2EM” in Chapter 5.4.
TLE8080-3EM differs from the main version in parameter “V5DD reset threshold for TLE8080-2EM and
TLE8080-3EM” in Chapter 5.4.
Type
Package
Marking
TLE8080EM
PG-SSOP24
TLE8080EM
TLE8080-2EM
PG-SSOP24
TLE8080-2EM
TLE8080-3EM
PG-SSOP24
TLE8080-3EM
Data Sheet
www.infineon.com
1
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Table of contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
3.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
5.1
5.2
5.3
5.4
5 V supply, reset and supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 V supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power on reset and reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Watchdog operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics 5 V supply, reset and supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
6.1
6.2
Power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Low side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical characteristics low side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
7.1
Variable reluctance sensor ( VRS ) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical characteristics VR sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
8.1
8.2
8.2.1
8.2.2
8.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set and reset of diagnosis register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9.1
9.2
K-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
K-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical characteristics K-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
2
23
23
23
25
28
31
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Block diagram
2
Block diagram
VS
5V Voltage
Supply
V5DD
Undervoltage
Detection
WD_DIS
CSN; SI;
SO; SCLK
4
SPI
Watchdog
Reset
NRO
LS Driver
OUT5
inductive loads
350 mA
LS Driver
OUT4
inductive loads
350mA
LS Driver
IN3
OUT3
inductive loads
2.6A
LS Driver
resistive loads
3A
OUT2
LS Driver
IN1
VR_IN1; VR_IN2
2
2
VR_OUT
VR Sensor
KIO
K-Line
AGND
PGND
RX; TX
OUT1
inductive loads
2.6A
Figure 1
Data Sheet
Block diagram
3
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Pin configuration
3
Pin configuration
3.1
Pin assignment
KIO
1
2
24
23
TX
VS
OUT5
3
22
AGND
OUT4
4
21
OUT3
5
20
V5DD
NRO
PGND
OUT2
6
7
19
18
OUT1
8
17
IN1
CSN
PGND
25
PGND
RX
IN3
9
16
SCLK
VR_IN1
10
SI
VR_IN2
WD_DIS
11
15
14
12
13
SO
VR_OUT
Pg-ssop-24 .vsd
Figure 2
3.2
Pin configuration
Pin definitions and functions
Pin
Symbol
Function
1
KIO
K-Line Bus Connection
2
VS
Battery Voltage: Block to AGND directly at the IC with min. 100nF ceramic capacitor
3
OUT5
Output Channel 5
4
OUT4
Output Channel 4
5
OUT3
Output Channel 3
6
PGND
Power Ground: internally connected to pin 9, connect externally to pin 9
7
OUT2
Output Channel 2
8
OUT1
Output Channel 1
9
PGND
Power Ground: internally connected to pin 6, connect externally to pin 6
10
VR_IN1
VR Sensor Interface Input 1
11
VR_IN2
VR Sensor Interface Input 2
12
WD_DIS
Watchdog Disable: high active; internal pull down
13
VR_OUT
VR Sensor Output
14
SO
SPI Slave Output: high impedance
15
SI
SPI Slave Input: internal pull down
16
SCLK
SPI Clock Input: internal pull down
17
CSN
SPI Chip Select Input: low active; internal pull up
18
IN1
Control Input Channel 1: internal pull down
Data Sheet
4
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Pin configuration
Pin
Symbol
Function
19
IN3
Control Input Channel 3: internal pull down
20
NRO
Reset Output: low active, open drain
21
V5DD
5V Supply Output: connected to external blocking capacitor
22
AGND
Analog Ground: connected to system logic ground
23
RX
K-Line Receive Output: logic output of data received from the K-Line bus KIO
24
TX
K-Line Transmit Input: logic level input for data to be transmitted on the K-Line bus KIO;
internal pull up
25
Exposed
Pad
Substrate Connection: must be connected to PGND externally on PCB
Data Sheet
5
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
General product characteristics
4
Table 1
General product characteristics
Absolute maximum ratings 1)
Tj = -40°C to +150°C: All voltages with respect to ground unless otherwise specified. Positive current flowing
into pin (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Voltages
Supply voltage VS
VVS
-0.3
–
40
V
–
P_4.1.1
Supply voltage V5DD
VV5DD
-0.3
–
5.5
V
–
P_4.1.2
Input voltage on pins IN1, IN3, Vx
SCLK, SI, WD_DIS
-0.3
–
5.5
V
–
P_4.1.3 a
Input voltage on pins CSN, TX Vx
-0.3
–
V5DD V
+0.3 V
–
P_4.1.3 b
Input voltage VR_IN1, VR_IN2 VVR_IN1/2
-0.3
–
5.5
V
see also 4.2.1 and
4.2.2
P_4.1.4
DC voltage on pins OUT1-5
Vx
-0.3
–
30
V
respect to PGND
all channels are
switched off
P_4.1.5
DC voltage on pins VR_OUT,
SO, RX, NRO
Vx
-0.3
–
5.5
V
Ix < 1 mA
P_4.1.6
DC voltage AGND to PGND
Vx
-0.3
–
0.3
V
DC voltage on pin KIO
VKIO
-1
–
35
V
respect to PGND
KIO is switched off
P_4.1.8
Input current between VR_IN1 IVR_IN1,VR_IN2 -–
and VR_IN2
–
50
mA
–
P_4.2.1
-–
–
10
mA
–
P_4.2.2
P_4.1.7
Currents
Input current VR_IN1, VR_IN2 IVR_IN1/2,GND
to GND
Temperatures
Junction temperature
Tj
-40
–
150
o
C
–
P_4.3.1
Storage temperature
Tstg
-55
–
150
o
C
–
P_4.3.2
-2
–
2
kV
ESD susceptibility
ESD resistivity all Pins to GND VESD
ESD resistivity all Pins to GND VESD
-500
ESD resistivity Pin 1, 12, 13, 24 VESD1,19,20,36 -750
(corner pins) to GND
–
500
–
750
V
V
HBM 2)
P_4.4.1
CDM
3)
P_4.4.2
CDM
3)
P_4.4.3
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to EIA/JESD 22-A114B.
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1.
Data Sheet
6
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
General product characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Table 2
Functional range
Parameter
Symbol
Supply voltage
Junction Ttemperature
Note:
Table 3
VS
Tj
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
6
–
40
V
–
P_4.5.1
150
o
–
P_4.5.2
-40
–
C
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Thermal resistance
Parameter
Junction to case
Junction to ambient
Symbol
RthJC
RthJA
Values
Min.
Typ.
Max.
–
7
–
–
29
–
Unit
NoteorTest Condition Number
K/W
1)
P_4.6.1
K/W
1) 2)
P_4.6.2
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Data Sheet
7
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
5 V supply, reset and supervision
5
5 V supply, reset and supervision
5.1
5 V supply
The TLE8080EM integrates a voltage regulator for load currents up to 250 mA. The input voltage at VS is
regulated to 5 V on V5DD with a precision of ±2%. The design allows to achieve stable operation even with
ceramic output capacitors down to 470 nF. It is protected against overload, short circuit, and over
temperature conditions. For low drop operation, a charge pump is implemented.
VS
Vref
I VS
+
-
V5DD
IV5DD
e.g. µC
Figure 3
5.2
5 V supply
Power on reset and reset output
The reset output NRO is an open drain output. When the level of VV5DD reaches the reset threshold (VRT)
(increasing voltage VV5DD) the signal at NRO remains low for the power-up reset delay time (tRD). The reset
function and timing is illustrated in Figure 4. The reset reaction time (tRR ) avoids wrong triggering caused by
short “glitches” on the V5DD-line. In case of V5DD power down (decreasing voltage; VV5DD < VRT for t < tRR ) a logic
low signal is generated at the pin NRO to reset an external micro controller. The level of the reset threshold for
increasing VV5DD is for the hysteresis (VRH) higher than the level for decreasing VV5DD.
With an active reset all power stages and the K-Line output are disabled and SPI commands are ignored.
Data Sheet
8
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
5 V supply, reset and supervision
Vs
t
VV5DD
<
tRR
VRT
V NRO
tRR
t RD
t RD
tRR
t
VNRO_H
V NRO_L
t
Figure 4
5.3
Reset Timing Diagram
Watchdog operation
The TLE8080EM integrates a watchdog function which monitors the correct SPI communication with the
micro controller. A watchdog disable pin ( WD_DIS ) with an internal pull down current source is implemented.
With a high level the watchdog function is disabled.
For enabled watchdog function after power-up reset delay time ( tRD ), valid SPI communication from the micro
controller must occur within the watchdog period ( tWP ) specified in the electrical characteristics. A restart of
the watchdog period is done with a low to high transition of the CSN pin of a valid transmission of a 16 bit
message.
A reset is generated (NRO goes LOW) for the time ( tWR ) if there is no restart during the watchdog period as
shown in Figure 5.
Status after watchdog overflow:
•
all outputs are switched off
•
SPI registers are not influenced
•
Watchdog Time Out bit in SPI status register is set
•
first answer to SPI communication is the content of the status register
Switching of Outputs and reset of Watchdog Time Out Bit after watchdog overflow:
•
Outputs 1 and 3 will be switched on with an positive edge at IN1 respectively IN3
•
Outputs 2, 4 and 5 will be switched on with a write command to CMD register
•
the watchdog time out bit will be reset with the rising edge of CSN of the first read command of the status
register
Data Sheet
9
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
5 V supply, reset and supervision
Vs
t
V5DD
VRT
t
VNRO
tWR
t RD
Normal operation
trr
t
Watchdog
Period
t
restart
tWP
CSN
t
SI
16 Bits
16 Bits
16 Bits
Data Sheet
t
No correct SPI
communication
within the
Watchdog Period
causing reset
1. correct SPI
communication
Figure 5
e.g. 4 Bits
Watchdog timing diagram
10
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
5 V supply, reset and supervision
5.4
Table 4
Electrical characteristics 5 V supply, reset and supervision
Electrical characteristics: 5 V supply, reset and supervision
VS = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
5 V supply
Output voltage
VV5DD
4.9
5
5.1
V
0 mA < IV5DD <
250 mA,
6 V < VS < 40 V
P_5.1.1
Output current limitation
IV5DD
250
–
650
mA
VV5DD = 0 V
P_5.1.2
Load regulation
ΔVV5DD, Lo
–
–
20
mV
1 mA < IV5DD <
250 mA
P_5.1.3
Line regulation
ΔVV5DD, Li
–
–
10
mV
IV5DD = 1 mA,
6 V < VS < 40 V
P_5.1.4
Power supply rejection
PSRR
–
60
–
dB
f = 100 Hz,
VS, ripple = 0.5
Vpp 1)
P_5.1.5
Output capacitor
CV5DD
470
–
–
nF
1)
P_5.1.6
P_5.1.7
Output capacitor ESR
ESR(CV5DD)
–
–
10
Ω
1)
Current consumption
IVS
–
5.5
8
mA
IV5DD= 0 mA, all P_5.1.8
channels and KLine off
Low drop resistance
RDSon,V5
–
–
1.2
Ω
VS ≥ 4.8 V
I ≤ 250 mA
P_5.1.11
TOT
150
–
200
°C
1)
P_5.2.1
°C
1)
P_5.2.2
Over temperature protection
Over temperature threshold
Over temperature hysteresis
Data Sheet
TOT,Hys
–
20
11
–
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
5 V supply, reset and supervision
Table 4
Electrical characteristics: 5 V supply, reset and supervision (cont’d)
VS = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
Under voltage detection
V5DD reset threshold for
TLE8080EM
VRT
4.00
4.25
4.50
V
VV5DD
decreasing,
only at version
TLE8080EM
P_5.3.1
Reset hysteresis
VRH
10
–
150
mV
V5DD reset threshold for
VRT
TLE8080-2EM and TLE8080-3EM
3.4
3.65
3.9
V
P_5.3.3
VV5DD
decreasing,
only at versions
TLE8080-2EM
and TLE80803EM
P_5.3.2
Power on reset
Power on reset delay time for
TLE8080EM and TLE8080-3EM
tRD
10
15
20
ms
only at versions P_5.4.1
TLE8080EM and
TLE8080-3EM
Power on reset delay time for
TLE8080-2EM
tRD
30
40
50
ms
only at version
TLE8080-2EM
Reset reaction time
tRR
10
15
20
µs
VNRO,L
–
–
1.1
V
Watchdog period
tWP
50
60
70
ms
P_5.6.1
Watchdog reset time
tWR
120
240
360
µs
P_5.6.2
Low level input voltage
VWD_DIS,L
–
–
1
V
P_5.7.1
High level input voltage
VWD_DIS,H
2
–
–
V
P_5.7.2
Pull down current
IWD_DIS,pd
20
50
100
µA
at VIN = 5 V
P_5.7.3
Pull down current
IWD_DIS,pd
2.4
–
–
µA
at VIN = 0.6 V
P_5.7.4
Hysteresis
VWD_DIS,Hys
30
250
mV
P_5.4.2
P_5.4.3
Reset output NRO
Low level output voltage
INRO = 1 mA
P_5.5.1
Watchdog
Input characteristics WD_DIS
P_5.7.5
1) Not subject to production test, specified by design.
Data Sheet
12
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
6
Power stages
6.1
Low side switches
The power stages are built by N-channel power MOSFET transistors. The channels are universal multi channel
switches, but are mostly suitable to be used in engine management systems. Within an engine management
system, the best fit of the channels to the typical loads is:
•
Channel 1 and 3 for injector valves or similar sized solenoids with a maximum operation current
requirement of 2.6 A.
•
Channel 2 for malfunction indication lamps or other resistive loads with a maximum current requirement
of 3 A.
•
Channel 4 and 5 for relays or other inductive loads with a maximum current requirement of 350 mA.
The channels are switched off while reset is active (pin NRO is low). After an power on reset the channels will
be switched on with a positive edge at IN1 respectively IN3 or with a switch on command over SPI.
V bat
V bat
ID
OUT
V
L,
RL
OUT
V DS
R
V DS
DScl
GND
GND
Channel 1, 3, 4, 5
Figure 6
ID
Channel2
Low side switches
In Table 5 the control concept, typical loads, the implemented protection and monitor functions are
illustrated.
Table 5
Overview diagnosis function
Channel Control
Recommended Over Temperature
Load
Over Current
Open Load/
Short to GND
1
Pin IN1
Injector valve
x
Latch 1)
x
2
SPI CMD register bit 0 MIL (max. 3W)
x
repetitive
switching;
off time toc,off 1)
–
3
Pin IN3
x
Latch 1)
x
1)
x
x
Valve
4
SPI CMD register bit 1 Relay
one temperature sensor Latch
for channel 4 and
channel 5
5
SPI CMD register bit 2 Relay
one temperature sensor Latch 1)
for channel 4 and
channel 5
1) Reset behavior of the diagnosis bits see Chapter 8.2.
Data Sheet
13
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
In overcurrent condition the affected channel will be switched off. There are two different implementations
for switching on again after an over current event.
For channels 1, 3, 4 and 5 the switch off state is latched. The input pins IN1, IN3 must be set to low to reset the
latch before the channel can be switched on again.
For channels 4 and 5 the over current status is reset with a write command to the CMD register after a
Diagnosis Read Command has been sent. The switching state is according to the status of bit 1 and 2.
Channel 2 will be switched off and after toc_off = 5 ms typically the channel will be switched on again
automatically. The result is repetitive switching with a fixed off time of toc,off. The overcurrent status of channel
2 is internally latched. For releasing the over current diagnosis bit after over current condition, channel 2 must
stay switched on for at least toc,St.
The bits 0 to 4 in the Stat register reflect the actual switching status of the channels. For detailed description
see Chapter 8.2.2.
All the channels are protected from over temperature. In an overtemperature situation the affected channel
will be switched off. The channel will restart operation if the junction temperature decreases by thermal
shutdown hysteresis TOT,Hys. Channels 4 and 5 are using a common temperature sensor. Therefore, the two
channels are switched together during over temperature.
For channels 1, 3, 4 and 5 an open load/short to GND in off detection with a pull down current source (active
in off) and a comparator is implemented. In case of switch off and the output voltage is below the open load
detection threshold (Voutx < Vol,th), the open load in off timer is started. After the open load in off delay time tol,d
, the open load is detected (timing see Figure 9 and Figure 10).
The diagnosis status of the channels is monitored in the SPI Diagnosis Register DIAG (see Chapter 8.2).
Data Sheet
14
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
6.2
Electrical characteristics low side switches
Table 6
Electrical characteristics: power stage
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Number
Test Condition
Output channel 1 and 3
On resistance
ROUTx_on
–
0.6
0.7
Ω
IOUTx_nom = 1.3 A, P_6.1.1
Tj = 150°C
Output clamping voltage
VOUTx_cl
30
35
40
V
IOUTx = 0.02 A
Over-current switch off threshold
IOUTx_oc
2.6
–
5
A
P_6.1.3
Over-current switch off filter time
toc,f
0.5
–
3
µs
P_6.1.4
Over temperature switch off
TOT
150
–
200
°C
P_6.1.5
Over temperature yysteresis
TOT,Hys
–
20
–
°C
P_6.1.6
Open load in off detection threshold
Vol,th
2
2.8
3.2
V
P_6.1.7
Open load in off pull down diagnosis
current
Iol
50
100
150
µA
Open load in off diagnosis delay
time
tol,d
100
–
200
µs
Turn on delay time
td,ON
–
0.25
1
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.1.10
Turn off delay time
td,OFF
–
0.9
1.5
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.1.11
Turn on time
ts,ON
–
0.6
1.2
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.1.12
Turn off time
ts,OFF
–
0.6
1.2
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.1.13
Output leakage current in off mode
IOUTx_off
–
–
3
µA
VOUTx = 13.5 V,
Tj = 150°C2)
P_6.1.14
On resistance
ROUTx_on
–
1.1
1.2
Ω
IOUTx_nom = 0.3 A, P_6.2.1
Tj = 150°C
Over-current switch off threshold
IOUTx_oc
3
–
6.5
A
P_6.2.2
Over-current switch off filter time
toc,f
0.5
–
3
µs
P_6.2.3
Over-current switch off time
toc,off
3
–
8
ms
P_6.2.4
Over-current status time
toc,St
1
–
12
ms
P_6.2.5
Over temperature switch off
TOT
150
–
200
°C
P_6.2.6
VOUTx = 13.5 V
P_6.1.2
P_6.1.8
P_6.1.9
Output channel 2
Data Sheet
15
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
Table 6
Electrical characteristics: power stage (cont’d)
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note or
Number
Test Condition
Over temperature hysteresis
TOT,Hys
–
20
–
°C
P_6.2.7
Turn on delay time
td,ON
–
0.6
1.2
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.2.8
Turn off delay time
td,OFF
–
0.7
1.5
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.2.9
Turn on time
ts,ON
–
0.4
1
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.2.10
Turn off time
ts,OFF
–
0.4
1
µs
VOUTx = 13.5 V,
IOUTx = 1.3 A,
resistive load 1)
P_6.2.11
Output leakage current in off mode
IOUTx_off
–
–
3
µA
VOUTx = 13.5 V,
Tj = 150°C
P_6.2.12
On resistance
ROUTx_on
–
3.3
3.6
Ω
IOUTx_nom = 0.3 A, P_6.3.1
Tj = 150°C
Output clamping voltage
VOUTx_cl
30
35
40
V
IOUTx = 0.02 A
Over-current switch off threshold
IOUTx_oc
350
–
600
mA
P_6.3.3
Over-current switch off filter time
toc,f
0.8
–
2.4
µs
P_6.3.4
Over temperature switch off
TOT
150
–
200
°C
P_6.3.5
Over temperature hysteresis
TOT,Hys
–
20
–
°C
P_6.3.6
Open load in off detection threshold
Vol,th
2
2.8
3.2
V
P_6.3.7
Open load in off pull down diagnosis
current
Iol
50
100
150
µA
Open load in off diagnosis delay time tol,d
100
–
200
µs
Turn on delay time
td,ON
–
0.5
1.2
µs
VOUTx = 13.5 V,
IOUTx = 0.3 A,
resistive load1)
P_6.3.10
Turn off delay time
td,OFF
–
0.7
1.5
µs
VOUTx = 13.5 V,
IOUTx = 0.3 A,
resistive load1)
P_6.3.11
Turn on time
ts,ON
–
0.1
0.8
µs
VOUTx = 13.5 V
IOUTx = 0.3 A,
resistive load1)
P_6.3.12
Turn off time
ts,OFF
–
0.1
0.8
µs
VOUTx = 13.5 V,
IOUTx = 0.3 A,
resistive load 1)
P_6.3.13
Output channel 4 and 5
Data Sheet
16
VOUTx = 13.5 V
P_6.3.2
P_6.3.8
P_6.3.9
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
Table 6
Electrical characteristics: power stage (cont’d)
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Unit
Note or
Number
Test Condition
VOUTx = 13.5 V,
Tj = 150°C 2)
Min.
Typ.
Max.
IOUTx_off
–
–
2
µA
Low level input voltage
VIN,L
–
–
1
V
P_6.4.1
High level input voltage
VIN,H
2
–
–
V
P_6.4.2
Input voltage hysteresis
VIN,Hys
50
110
250
mV
P_6.4.3
Pull down current
IIN,PD
20
50
100
µA
VIN = 5 V
P_6.4.4
Pull down current
IIN,PD
2.4
–
–
µA
VIN = 0.6 V
P_6.4.5
Output leakage current in off mode
P_6.3.14
Input characteristic IN1 and IN3
1) Definition of timing see Figure 7 or Figure 8.
2) In OFF mode open load diagnosis pull down current active.
VINx
VOUTx
t
V BATT
80%
20%
t
td, ON
Figure 7
Data Sheet
t s, ON
td,OFF
t s, OFF
Timing low side switches channel 1 and 3
17
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
VCSN
t
VOUTx
V BATT
80%
20%
t
td, ON
Figure 8
t s, ON
td,OFF
t s, OFF
Timing low side switches channel 2, 4 and 5
VINx
t
VOUTx
VBATT
open
open
Vol.th
t ol.d
tol.d
t
CHx_OL
t
Figure 9
Data Sheet
Timing open load/short to GND in off detection channel 1 and 3
18
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Power stages
VCSN
t
VOUTx
VBATT
open
open
Vol.th
t ol.d
tol.d
t
CHx_OL
t
Figure 10
Data Sheet
Timing open load/short to GND in off detection channel 2, 4 and 5
19
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Variable reluctance sensor ( VRS ) interface
7
Variable reluctance sensor ( VRS ) interface
The variable reluctance (VR) sensor interface converts an output signal of a VR sensor into a logic level signal
suited for µC 5 V input ports. The voltage difference between the two input pins, VR_IN1 and VR_IN2, which
are connected to the two output pins of the VR sensor, is detected and the output pin VR_OUT is switched
depending on the sign of the voltage difference (see Figure 12 ). The amplitude of the VR sensor signal is
limited by an internal clamping circuit to avoid damage of the device due to over voltage caused by the VR
sensor signal.
VR_IN1
Select Load
Clamp
&
Load
2,5V
Buffer
Detection
VR_OUT
VR_IN2
Select Threshold
Figure 11
Data Sheet
VR sensor interface block diagram
20
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Variable reluctance sensor ( VRS ) interface
7.1
Table 7
Electrical characteristics VR sensor interface
Electrical Characteristics: VR Sensor Interface
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note or Test Condition Number
Input characteristics:
Positive VR sensor interface
detection threshold
VVR,th_pos
-30
0
30
mV
Negative VR sensor interface
detection threshold
VVR,th_neg
-80
-50
-20
mV
CMD Register:
VR_T[1:0] = “00”
Reset State
P_7.1.2
Negative VR sensor interface
detection threshold
-130
-100
-70
mV
CMD Register:
VR_T[1:0] = “01”
P_7.1.3
Negative VR sensor interface
detection threshold
-550
-500
-450
mV
CMD Register:
VR_T[1:0] = “10”
P_7.1.4
Negative VR sensor interface
detection threshold
-1.1
-1
-0.9
V
CMD Register:
VR_T[1:0] = “11”
P_7.1.5
30
75
120
kΩ
Tj = 25°C,
CMD Register:
VR_L[1:0] = “00”
Reset State
P_7.1.6
90
kΩ
Tj = -40°C,
CMD Register:
VR_L[1:0] = “00”
Reset State
60
kΩ
Tj = 150°C,
CMD Register:
VR_L[1:0] = “00”
Reset State
VR sensor interface load
selection
RVR,Load
P_7.1.1
VR sensor interface load
selection
3
4.5
8
kΩ
CMD Register:
VR_L[1:0] = “01”
P_7.1.7
VR sensor interface load
selection
1.5
2.2
3.3
kΩ
CMD Register:
VR_L[1:0] = “10”
P_7.1.8
VR sensor interface load
selection
0.7
1.2
1.9
kΩ
CMD Register:
VR_L[1:0] = “11”
P_7.1.9
VR sensor interface input
clamping current
IVR,clamp
–
–
±50
mA
VR sensor interface input
clamping voltage
VVR,clamp
±2.5
±3
±3.5
V
Data Sheet
21
P_7.1.10
IVR,clamp = ±50 mA
P_7.1.11
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Variable reluctance sensor ( VRS ) interface
Table 7
Electrical Characteristics: VR Sensor Interface (cont’d)
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit
Note or Test Condition Number
Min.
Typ.
Max.
–
0.3
V
IVR_OUT = 100 µA
P_7.2.1
IVR_OUT = -100 µA
P_7.2.2
Output characteristics:
Low level output voltage
VVR_OUT,L
–
High level output voltage
VVR_OUT,H
V5DD –
-0.3
–
V
Delay time input to VR_OUT
falling edge
tdr
1
1.5
2.5
µs
P_7.3.1
Delay time input to VR_OUT
rising edge
tdf
1
1.5
2.5
µs
P_7.3.2
Transfer characteristics:
VVR_IN1 – VR_IN2
V V RT h_pos =0V
VVR_OUT
V V RT h_neg
t dr
t
tdf
50%
t
Figure 12
Data Sheet
Timing characteristics of the VR sensor interface
22
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
8
Serial peripheral interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a 16 bit full duplex synchronous serial slave interface, which uses four lines: SI, SO, SCLK and CSN.
8.1
SPI signal description
CSN - chip select:
The system micro controller selects the IC by means of the CSN pin. Whenever the pin is in low state, data
transfer can take place. As long as CSN is in high state, all signals at the SCLK and SI pins are ignored and SO
is forced to high impedance.
CSN - High to Low Transition:
SO changes from high impedance to high or low state depending on the Status Flag (see Chapter 8.2).
CSN - Low to High Transition:
End of transmission, the validation check of the communication is done (number of bits and valid command)
and valid commands are executed.
SCLK - serial clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the
falling edge of SCLK while the serial output (SO) shifts information out on the rising edge of the serial clock. It
is essential that the SCLK pin is in low state whenever chip select CSN makes any transition.
SI - serial input:
Serial input data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read on the
falling edge of SCLK. Please refer to Section 8.2 for further information.
SO - serial output:
Data is shifted out serially at this pin, the MSB first. SO is in high impedance until the CSN pin goes to low. The
output level before the first rising edge of SCLK depends on the status flag. New data will appear at the SO pin
following the rising edge of SCLK. Please refer to Section 8.2 for further information.
8.2
SPI protocol
The principle of the SPI communication is shown in Figure 13. The message from the micro controller must
be sent MSB first. The data from the SO pin is sent MSB first. The TLE8080EM samples data from the SI pin on
the falling edge of SCLK and shifts data out of the SO pin on the rising edge of SCLK. Each access must be
terminated by a rising edge of CSN.
All SPI messages must be exactly 16-bits long, otherwise the SPI message is discarded.
There is a one message delay in the response to each message (i.e. the response for message N will be returned
during message N+1).
The SPI protocol of the TLE8080EM provides three registers. The control register, the diagnosis, and the status
register. The control register contains the set up bits for the VR sensor interface and the control bits of
channels 2, 4 and 5. The diagnosis register contains the diagnosis bits of the five low side switches. The status
register contains the status bits of the five low side switches, the watchdog status bit, and the watchdog time
out bit. After power-on reset, all register bits are set to reset state (see Chapter 8.2.1).
Data Sheet
23
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
There are four ways of valid access:
•
Write access to the command register: the answer is 1 for the R/W bit, 00 for the address and the content
of the register
•
Read access to the command register: the answer is 0 for the R/W bit, 00 for the address and the content of
the register
•
Read access to the diagnosis register: the answer is 0 for the R/W bit, 01 for the address and the content of
the register
•
Read access to the status register: the answer is 0 for the R/W bit, 10 for the address and the content of the
register
Any other access is recognized as an invalid message.
Status flag Indication: after the falling edge of CSN and before the first rising edge of SCLK, the level of the SO
indicates the status of the diagnosis register:
•
SO = “0”: no error condition detected; all diagnosis register bits are “0”
•
SO = “1”: one or more error conditions are detected; one or more diagnosis register bits are “1”
With this feature during every SPI communication a check of the diagnosis status can be done without
additional read access of the diagnosis register.
CSN
SCLK
SI
SO
time
clock
1
don’t care
Status
Flag
*
Figure 13
)
Bit 15
MSB
don’t care
tristate
*
)
Bit 15
MSB
clock
2
clock
3
Bit 14
Bit 14
clock
15
Bit 13
Bit 13
clock
16
don’t care
Bit 1
Bit 0
LSB
Bit 1
Bit 0
LSB
time
don’t care
time
tristate
time
active clock edge for reading data at SI
SPI Pprotocol
SPI answers:
•
during power on reset: SPI commands are ignored, SO is always low
•
after power on reset: the content of the command register is transmitted with the next SPI transmission
•
during watchdog reset: SPI commands are ignored, SO has the value of the status flag
•
after watchdog overflow: the content of the status register is transmitted with the first SPI transmission
after the low to high transition of NRO
Data Sheet
24
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
•
after a read or write command: the content of the selected register is transmitted with the next SPI
transmission
•
after an invalid communication: the content of the diagnosis register is transmitted with the next SPI
transmission
8.2.1
SPI register
Overview
15
14
13
R/W
AD1
AD0
12
11
10
9
8
7
6
5
4
3
2
Field
Bits
Type
Description
AD1:AD0
[14:13]
w
Address Bits:
00B Control Register
01B Diagnosis Register
10B Status Register
R/W
15
w
Read - Write Bit:
0B Read Access
1B Write Access
CMD Register
Command Register (Identifier x00x xxxx xxxx xxxxB)
15
14
R/W
AD1
13
12
11
10
9
8
rw
rw
0
Reset Value: 0H
7
6
5
4
AD0 VR_T1 VR_T0 VR_L1 VR_L0
rw
1
3
2
1
0
CTR5 CTR4 CTR2
rw
rw
rw
rw
Field
Bits
Type
Description
CTR2
0
rw
Control Bit Channel 2:
0B Channel 2 is switched off (Reset
State)
1B Channel 2 is switched on
CTR4
1
rw
Control Bit Channel 4:
0B Channel 4 is switched off (Reset
State)
1B Channel 4 is switched on
CTR5
2
rw
Control Bit Channel 5:
0B Channel 5 is switched off (Reset
State)
1B Channel 5 is switched on
Data Sheet
25
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
Field
Bits
Type
Description
VR_L1: VR_L0
[10:9]
rw
Load Register of VR Interface:
( c.f. VR sensor interface load
selection )
00B RLoad = 75kΩ (Reset State)
01B RLoad = 4.5kΩ
10B RLoad = 2.2kΩ
11B RLoad = 1.2kΩ
VR_T1: VR_T0
[12:11]
rw
Threshold Register of VR Interface:
00B -50mV (Reset State)
01B -100mV
10B -500mV
11B -1V
Diag Register
Diagnosis Register (Identifier x01x xxxx xxxx xxxxB)
15
14
13
R/W
AD1
AD0
12
11
10
9
8
Reset Value: 0H
7
6
5
4
3
2
1
CH45_ CH5_ CH5_ CH4_ CH4_ CH3_ CH3_ CH3_ CH2_ CH2_ CH1_ CH1_ CH1_
OT
OC
OL
OC
OL
OT
OC
OL
OT
OC
OT
OC
OL
r
r
r
r
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
CH1_OL
0
r
Open Load Diagnosis Bit of Channel 1:
0B no open load in off detected (Reset State)
1B open load in off detected
CH1_OC
1
r
Over Current Diagnosis Bit of Channel 1:
0B no over current detected (Reset State)
1B over current detected
CH1_OT
2
r
Over Temperature Diagnosis Bit of Channel 1:
0B no over temperature detected (Reset State)
1B over temperature detected
CH2_OC
3
r
Over Current Diagnosis Bit of Channel 2:
0B no over current detected (Reset State)
1B over current detected
CH2_OT
4
r
Over Temperature Diagnosis Bit of Channel 2:
0B no over temperature detected (Reset State)
1B over temperature detected
CH3_OL
5
r
Open Load Diagnosis Bit of Channel 3:
0B no open load in off detected (Reset State)
1B open load in off detected
CH3_OC
6
r
Over Current Diagnosis Bit of Channel 3:
0B no over current detected (Reset State)
1B over current detected
Data Sheet
0
26
r
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
Field
Bits
Type
Description
CH3_OT
7
r
Over Temperature Diagnosis Bit of Channel 3:
0B no over temperature detected (Reset State)
1B over temperature detected
CH4_OL
8
r
Open Load Diagnosis Bit of Channel 4:
0B no open load in off detected (Reset State)
1B open load in off detected
CH4_OC
9
r
Over Current Diagnosis Bit of Channel 4:
0B no over current detected (Reset State)
1B over current detected
CH5_OL
10
r
Open Load Diagnosis Bit of Channel 5:
0B no open load in off detected (Reset State)
1B open load in off detected
CH5_OC
11
r
Over Current Diagnosis Bit of Channel 5:
0B no over current detected (Reset State)
1B over current detected
CH45_OT
12
r
Over Temperature Diagnosis Bit of Channel 4 and 5:
0B no over temperature detected (Reset State)
1B over temperature detected
Stat Register
Status Register (Identifier x10x xxxx xxxx xxxxB)
15
14
13
R/W
AD1
AD0
12
11
10
9
Reset Value: 0H
8
7
WD_DI WD_T
S
O
r
r
6
5
4
3
2
1
0
ST5
ST4
ST3
ST2
ST1
r
r
r
r
r
Field
Bits
Type
Description
ST1
0
r
Status Bit Channel 1:
0B Channel 1 is switched off (Reset State)
1B Channel 1 is switched on
ST2
1
r
Status Bit Channel 2:
0B Channel 2 is switched off (Reset State)
1B Channel 2 is switched on
ST3
2
r
Status Bit Channel 3:
0B Channel 3 is switched off (Reset State)
1B Channel 3 is switched on
ST4
3
r
Status Bit Channel 4:
0B Channel 4 is switched off (Reset State)
1B Channel 4 is switched on
ST5
4
r
Status Bit Channel 5:
0B Channel 5 is switched off (Reset State)
1B Channel 5 is switched on
Data Sheet
27
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
Field
Bits
Type
Description
WD_TO
11
r
Watchdog Time Out Bit:
0B no watchdog time out
1B watchdog time out occurred
WD_DIS
12
r
Watchdog Status Bit:
0B Watchdog enabled (VWD_DIS = 0V)
1B Watchdog disabled (VWD_DIS = 5V)
8.2.2
Set and reset of diagnosis register bits
Set of the over current diagnosis bits of channels 1, 3, 4 and 5:
The over current diagnosis bits of channels 1, 3, 4 and 5 are set asynchronously of the internal clock with the
output signal of the detection circuit (details see Chapter 6.1).
Reset of the over current diagnosis bits of channels 1 and 3:
•
Diagnosis register was read out:
– input pin INx remains high: no reset of the over current diagnosis bit, the channel remains switched off
– input pin INx transition from high to low: the over current diagnosis bit is reset, the channel could be
switched on again
•
Diagnosis register was not read out
–
channel remains switched off and no reset of the over current diagnosis bit is done
– input pin INx is low: with the next read access of the diagnosis register the diagnosis bits are reset
Reset of the over current diagnosis bits of channels 4 and 5:
•
Diagnosis register was not read out
–
•
channel remains switched off and no reset of the over current diagnosis bit is done
Diagnosis register was read out:
– SPI command register write command is not sent: no reset of the over current diagnosis bit, the
channel remains switched off
– SPI command register write command is sent: the over current diagnosis bit is reset, the channel will
be switched according the status of the control bit
Set and Reset of the over current diagnosis bit of channel 2:
The over current diagnosis register bit for channel 2 is set asynchronously of the internal clock with the output
signal of the detection circuit. With this signal the output is switched off and the counter for the off time toc,off
of the repetitive switching cycle starts. After toc,off the channel will be switched on again. With an remaining
over current condition the channel will be switched on repetitively. This internal overcurrent status of the
channel is latched internally. The internal over current status is reset in two situations.
•
over current condition exists no longer: the internal over current status is reset after the time toc,St
•
over current condition remains and the channel is switched off: the internal over current status is reset
after the time toc,off
The reset of the over current diagnosis register bit for channel 2 is related to the internal over current status.
In Figure 14 and Figure 15 the behavior of the diagnosis with temporary and permanent over current
condition is drawn.
Data Sheet
28
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
Over Current
No Over Current
Cont Reg.
Bit 1
toc,f
t oc,f
t oc,f
IOUT2
ID,oc
t oc,off
Internal Over
Current Status
t oc,off
toc,St
Diag Reg.
Bit 3
SPI Diag Reg.
Read Out
Figure 14
SPI Diag Reg.
Read Out
SPI Diag Reg.
Read Out
Behavior of diagnosis with temporary over current condition at channel 2
Permanent Over Current
Cont Reg.
Bit 1
toc,f
t oc,f
t oc,f
IOUT2
ID,oc
Internal Over
Current Status
t oc,off
t oc,off
toc,off
Diag Reg.
Bit 3
SPI Diag SPI Diag
Reg.
Reg.
Read Out Read Out
Figure 15
Data Sheet
SPI Diag Reg.
Read Out
Behavior if diagnosis with permanent over current condition at channel 2
29
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
Reset of the over temperature diagnosis bits:
The over temperature diagnosis bits will be reset with read access of the diagnosis register if no over
temperature condition is detected.
Reset of the open load in off diagnosis bits:
The open load in off diagnosis bits will be reset with read access of the diagnosis register if no open load
condition is detected.
Data Sheet
30
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
8.3
Electrical characteristics SPI
Table 8
Electrical characteristics: SPI
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Unit
Note or Test Condition
Number
Min. Typ. Max.
Input characteristics (CSN, SCLK, SI):
Low level input voltage
Vx,L
–
–
1
V
P_8.1.1
High level input voltage
Vx,H
2
–
–
V
P_8.1.2
Hysteresis
Vx,Hys
50
250
mV
Pull up current CSN
Ix,pu
-25
-50
-100 µA
at VIN = 0 V
P_8.1.3
Pull up current CSN
Ix.pu
-25
–
–
µA
at VIN = VV5DD - 0.6 V
P_8.1.4
Pull down current SCLK, SI
Ix,pu
20
50
100
µA
at VIN = VV5DD
P_8.1.5
Pull down current SCLK, SI
Ix.pu
2.4
–
–
µA
at VIN = 0.6 V
P_8.1.6
Low level output voltage
VSo,L
–
–
0.4
V
Ix = 100 µA
P_8.2.1
High level output voltage
VSO,H
V5DD –
-0.4
–
V
Ix = -100 µA
P_8.2.2
-3
–
3
µA
0 V < VSO < 5 V
P_8.2.3
Output characteristics (SO):
Output high impedance leakage ISO,TRI
current
Timings:
Lead time
t1
210
–
–
ns
CSN falling to SCLK rising
P_8.3.1
Lag time
t2
75
–
–
ns
SCLK falling to CSN rising
P_8.3.2
CSN high time
t3
550
–
–
ns
CSN rising to CSN falling
P_8.3.3
Period of SCLK
t4
200
–
–
ns
P_8.3.4
SCLK to CSN set up time
t5
10
–
–
ns
SCLK falling to CSN falling P_8.3.5
SCLK low time
t7
60
–
–
ns
P_8.3.6
CSN to SCLK hold time
t8
15
–
–
ns
CSN rising to SCLK rising
P_8.3.7
SI set up time
t9
30
–
–
ns
SI set up time to SCLK
falling
P_8.3.8
SI hold up time
t10
30
–
–
ns
SI holdup time after SCLK P_8.3.9
falling
SO enable time
t11
–
–
165
ns
CSN falling to SO active
P_8.3.10
SO valid time
t12
–
–
120
ns
SO data valid after SCLK
rising
P_8.3.11
SO disable time
t13
–
–
165
ns
SO high impedance after
CSN rising
P_8.3.12
16
–
16
pulses
Number of clock pulses while
CSN = low
Data Sheet
31
P_8.3.13
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Serial peripheral interface (SPI)
Table 8
Electrical characteristics: SPI (cont’d)
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground. Positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Unit
Note or Test Condition
Number
Min. Typ. Max.
SO rise time
tSO_rise
–
–
75
ns
20% to 80%,
Cload=1.6 pF
P_8.3.14
SO fall time
tSO_fall
–
–
75
ns
80% to 20%
Cload=1.6 pF
P_8.3.15
t1
t2
t3
CSN
time
t4
t5
SCLK
t6
clock
1
don’t care
t9
SI
t7
clock
2
Bit 15
MSB
don’t care
Figure 16
Data Sheet
tristate
clock
3
clock
15
clock
16
don’t care
Bit 14
Bit 13
Bit 1
Bit 0
LSB
t12
Status
Flag
time
t10
t11
SO
t8
Bit 15
MSB
don’t care
time
t13
Bit 14
Bit 13
Bit 1
Bit 0
LSB
tristate
time
SPI timing diagram
32
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
K-line
9
K-line
9.1
K-line
The K-line module is a serial link bus interface device designed to provide bi-directional half-duplex
communication interfacing. It is designed to interface vehicles via the special ISO K-line and meets the ISO
standard 9141. The device’s K-line bus driver’s output is protected against bus shorts.
VS
RX
KIO
V5DD
TX
Driver &
Protection
Figure 17
Data Sheet
K-line block diagram
33
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
K-line
9.2
Table 9
Electrical characteristics K-line
Electrical characteristics: K-line
VS = 13.5 V, Tj = -40°C to +150°C: All voltages with respect to ground.
Positive current flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
Output RX
Low level output voltage
VRX,L
–
–
0.4
V
IRX = 100 µA
P_9.1.1
High level output voltage
VRX,H
V5DD0.4
–
–
V
IRX = -100 µA
P_9.1.2
Low level input voltage
VTX,L
–
–
1
V
P_9.2.1
High level input voltage
VTX,H
3.2
–
–
V
P_9.2.2
Hysteresis
VTX,Hys
280
500
700
mV
P_9.2.3
Pull up current
IPU_L
-70
-100
-150
µA
at VTX = 0 V
P_9.2.4
Pull up current
IPU_L
-30
–
–
µA
at VTX = VV5DD 0.6 V
P_9.2.5
TX = low,
RKIO= 480 Ω
P_9.3.1
Input TX
K-Line bus driver input/output KIO
Low level output voltage
VKIO,O,L
–
–
1.4
V
Current limitation
IKIO(lim)
40
–
140
mA
P_9.3.2
Low level input voltage
VKIO,I,L
–
–
0.4*VS
V
P_9.3.3
High level input voltage
VKIO,I,H
0.6*VS
–
–
V
P_9.3.4
Hysteresis
VKIO,I,Hys
0.02 *VS –
0.175
*VS
V
P_9.3.5
Pull down current
IKIO,pd
5
10
15
µA
P_9.3.6
fKIO,rec
–
–
500
kHz
fKIO,tran
–
–
100
kHz
tdrR
0.05
–
0.5
µs
CRX,load = 1.6 pF
P_9.4.3
tdfR
0.05
–
0.5
µs
CRX,load = 1.6 pF
P_9.4.4
Delay time TX -> KIO rising edge1)2) tdrT
0.05
–
0.5
µs
CKIO,load = 1.6 pF P_9.4.5
0.05
–
0.5
µs
CKIO,load = 1.6 pF P_9.4.6
Transfer characteristics
CRX = 25 pF; RKIO = 540 Ω; CKIO ≤ 1.3 nF
Receive frequency
Transmit frequency
1)
Delay time KIO -> RX rising edge
1)
Delay time KIO -> RX falling edge
1)
Delay time TX -> KIO falling edge
tdfT
CKIO = 0 pF
P_9.4.1
P_9.4.2
1) For definition see Figure 18.
2) Not subject of production test, behavior defined by external devices.
Data Sheet
34
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
K-line
VTxD
VV5DD
0.5*VV5DD
t
Vbus
tdfT
t drT
VS
0.7*VS
0.3*VS
t
VRxD
t drR
tdfR
VV5DD
0.5*VV5DD
t
Figure 18
Data Sheet
K-line transfer characteristics
35
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Package outlines
2)
0.2
M
0.1 C D
0.08 C
Seating Plane
C A-B D 24x
6 ±0.2
0.2
M
D
12
B
8.65 ±0.1
Index Marking
1
12
24
13
2.65 ±0.25
Bottom View
13
1
0.64 ±0.25
D
A
24
3.9 ±0.11)
8˚ MAX.
2x
0.19 +0.06
0.35 x 45˚
1.7 MAX.
C
0.65
0.25 ±0.05
Stand Off
(1.47)
Package outlines
0.1+0
-0.1
10
6.4 ±0.25
0.1 C A-B 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 19
PG-SSOP24
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products, and to be compliant
with government regulations, the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
36
Dimensions in mm
Rev. 1.3
2021-01-15
TLE8080EM
Engine Management IC for Small Engines
Revision history
11
Revision history
Revision
Date
Changes
1.0
2012-09-12
Data Sheet.
1.1
2012-12-19
Parameter “Reset reaction time” on Page 12 increased.
1.2
2016-10-26
Added variant TLE8080-3EM.
Parameter ”Low Drop Voltage” on Page 11 is spilt in P_5.1.10a and P.5.1.10b.
Removed “50%” indicator for VCSN signals in Figure 7, Figure 8, Figure 9 and
Figure 10.
Removed pin “KIO” from P_4.1.5 in Table 1 as covered by P_4.1.8.
Added “after a Diagnosis Read has been performed” to description of channel
4 and 5 over current status reset behavior.
Editorial changes.
1.3
2021-01-15
Parameter updates and improvements:
P_4.1.8: Maximum rating of KIO - minimum value reduced.
P_4.5.1: VS functional range increased.
P_5.1.1: VDD functional range condition increased.
P:_5.1.3: Load regulation improved
P:_5.1.4: Line regulation voltage range condition increased.
P_5.1.11: Re-defintion of low drop operation, P_5.1.9, P_5.1.10a and P_5.1.10b
removed, low drop resistance value added.
Editorial changes.
Data Sheet
37
Rev. 1.3
2021-01-15
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2021-01-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
Email: erratum@infineon.com
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