TLE82453SAAUMA1

TLE82453SA 3 Channel High-Side and Low-Side Linear Solenoid Driver IC TLE82453SA Data Sheet Rev 1.0, 2013-03-21 Automotive Power TLE82453SA Table of Contents Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 4.1 4.2 4.3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 5.1 5.2 Input / Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Characteristics I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Supply (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Supplies (LSUP2, LSUP1, LSUP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Supplies (VDDA and VDDAREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Supply (VDDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Supply (VIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 16 16 16 16 16 17 17 17 18 20 7 7.1 7.2 7.3 7.4 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 22 22 23 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Average current setpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dither waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Frequency Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autozero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 25 26 26 27 28 28 28 29 9 9.1 9.2 9.3 9.4 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 31 Data Sheet - 2 Rev 1.0, 2013-03-21 TLE82453SA 9.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Diagnosis Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAULTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAULT mask bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load / Switch Bypass Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Out of Range Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulator Error Fault (REx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 34 34 35 39 40 40 41 11 11.1 11.2 11.3 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 43 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICVID REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIAGNOSIS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK-DIVIDER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CALIBRATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SETPOINT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DITHER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTEGRATOR LIMIT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM PERIOD REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTEGRATOR THRESHOLD &OPEN ON REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTOZERO REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEEDBACK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 45 45 46 47 48 49 51 52 53 54 55 56 13 13.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Data Sheet - 3 Rev 1.0, 2013-03-21 3 Channel High-Side and Low-Side Linear Solenoid Driver IC Dragon IC 1 TLE82453SA Overview Features • • • • • • • • • • • • • • • Three independent low side / high side configurable channels Integrated half-bridge power stages RON(max) = 250 m@ Tj = 150 °C Integrated sense resistor with internal TCR compensation Load current measurement range = 0 mA to 1500 mA (typical) Current setpoint resolution = 0.73 mA Current control accuracy – +/- 5mA for load currents less than 500 mA PG-DSO-36 – +/- 1% for load currents greater than 500 mA Excellent immunity to large load supply voltage changes Integrated dither generator with programmable amplitude & frequency SPI interface for output control, diagnosis, and configuration Independent thermal shutdown for each channel Open load, switch bypass, and overcurrent protection and diagnosis for each channel Programmable slew rate control for reduced EMI Green Product (RoHS compliant) AEC Qualified Description The TLE 82453 is a flexible, monolithic solenoid driver IC designed for the control of linear solenoids in automatic transmission, electronic stability control, and active suspension applications. The three channels can be used as either lowside or highside drivers in any combination. The device includes the drive transistor, recirculation transistor, and current sensing resistor; minimizing the number of required external components. This device is capable of regulating the average current flow in a load up to 1500 mA, depending on the dither settings and the load characteristics, with 0.73 mA resolution. A triangular dither waveform generator, when enabled, superimposes a triangular waveform with programmable amplitude and frequency on the programmed current setpoint. A 32 bit SPI interface is used to control the three channels and to monitor the status of the diagnostic functions. An active low reset input, RESN, is used to disable all of the channels and reset the internal registers to the default values. An active high enable pin, EN, is used to enable or disable the operation of the output channels. When the EN pin is low, the channels are disabled, and the SPI interface is fully functional. A fault output pin is provided to generate a signal that can be used as an external interrupt to the microcontroller whenever a fault is detected. Type Package Marking TLE82453SA PG-DSO-36 TLE82453SA Data Sheet - 4 Rev 1.0, 2013-03-21 TLE82453SA Block Diagram CPOUT CPC2H CPC2L CPC1H CPC1L Block Diagram VBAT 2 VDDA GNDA VDDAREF GNDAREF VDDD power supply & under voltage detection charge pump LSUP 0 GNDD LSUP 1 LSUP 2 load current limitation EN RESN gate control FAULTN load current sense HSLS0 HSLS1 HSLS2 logic temperature sensor control logic TM TMO 1 diagnostics load current limitation TMO 2 CLK watchdog LOAD0 LOAD1 LOAD2 gate control VIO channel 2 channel 1 channel 0 CSN SCK SPI SO GNDP2 GNDP1 GNDP0 SI Block_Diagram.vsd Figure 1 Data Sheet - Block Diagram 5 Rev 1.0, 2013-03-21 TLE82453SA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GNDP0 LOAD0 LSUP0 HSLS0 GNDP1 LOAD1 LSUP1 HSLS1 GNDP2 LOAD2 LSUP2 HSLS2 VBAT CPC1H CPC1L CPC2H CPC2L CPOUT 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VIO SO SI SCK CSN CLK TMO2 VDDD GNDD VDDA GNDA GNDAREF VDDAREF TMO1 FAULTN RESN EN TM Pinout.vsd Figure 2 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 GNDP0 Ground; Ground connection for channel 0 power stage. Chip damaged if connection lost 2 LOAD0 Output Connect a ceramic capacitor VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV VDDA X < VDDx_UV X > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV VDDAREF X X < VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV RESN X X X LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH CLK X X X X TCLK > TCLK_MSS TCLK > TCLK_MSS TCLK < TCLK_MSS TCLK < TCLK_MSS TCLK < TCLK_MSS TCLK < TCLK_MSS TCLK < TCLK_MSS TCLK < TCLK_MSS VIO X X X X > 3.0V > 3.0V 0V > 3.0V > 3.0V > 3.0V > 3.0V > 3.0V WDEN X X X X LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH EN X X X X X X HIGH LOW HIGH HIGH HIGH HIGH VCPOUT VBAT X X X X X X > CPUV X < CPUV > CPUV > CPUV > CPUV VBAT X X X X X X < VBATOV X X > VBATOV < VBATOV < VBATOV VLSUPX X X X X X X > VLSUPUV X X X < VLSUPUV > VLSUPUV Sleep Mode YES YES YES NO NO NO NO NO NO NO NO NO Watchdog Fault NO NO NO NO NO YES NO NO NO NO NO NO Channel Operational NO NO NO NO NO NO YES NO NO NO NO YES SPI Functional NO NO NO NO YES NO INPUT – YES Response is ICVID Response is 0000 H YES YES YES Diagnostics Functional NO NO NO NO NO NO FAULTN LOW LOW LOW LOW LOW LOW RST bit HIGH (2) HIGH (2) HIGH (2) HIGH (2) HIGH (3) HIGH (3) Figure 3 1. 2. 3. 4. HIGH (Channel X only) YES YES YES NO Load faults are detected YES YES YES YES Undefined LOW (1) LOW LOW LOW (4) HIGH unchanged unchanged unchanged unchanged unchanged unchanged Power Supply Mode Diagram The FAULTN pin is LOW if the FME fault mask bit is set to 1 The RST bit in the DIAGNOSIS register will be set after the device exits the reset state A missing CLK signal will result in a reset only if the CLK Watchdog has been enabled. The FAULTN pin is LOW if the FMx fault mask bit is set to 1 5.11 Initialization The following figure illustrates the initialization sequence for the device after power-up. Data Sheet - 15 Rev 1.0, 2013-03-21 TLE82453SA Power Supply Apply +5V to each VDDx pin and the VIO pin FAULTN Pin = LOW Transition the RESN pin from LOW to HIGH and Apply the clock signal to the CLK pin FAULTN Pin = LOW TPOR max = 2.1 ms Wait for the POR timer to elapse FAULTN Pin = LOW Write to the CLK -DIVIDER register via the SPI interface . Enable the watchdog and set the system clock divider. FAULTN Pin = HIGH TWU max = 15 ms Wait for TWU wake up timer to elapse FAULTN Pin = HIGH Device is ready to operate Figure 4 Data Sheet - Initialization Sequence 16 Rev 1.0, 2013-03-21 TLE82453SA Power Supply 5.12 Electrical Characteristics Table 4 Electrical Characteristics: Power Supply VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, CPC1 and CP2 = 27nF CPCOUT = 220nF, all voltages with respect to ground (GNDD), positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number all channels active P_6.12.1 Max. VBAT Current Consumption normal mode IVBAT – 10 mA VBAT Current Consumption sleep mode IVBAT_SLP – 8  P_6.12.2 IVDDD VDDA Current Consumption IVDDA VDDAREF Current IVDDAREF – 20 mA P_6.12.3 – 13 mA P_6.12.4 – 4 mA P_6.12.5 – 1 mA CSN=VIO=5.25V P_6.12.6 Undervoltage reset (internally VDDA_UV generated) - VDDA 3.8 4.3 V VDDA decreasing P_6.12.7 Undervoltage reset (internally VDDAREF_UV generated) - VDDAREF 3.8 4.3 V VDDAREF decreasing P_6.12.8 Undervoltage reset (internally VDDD_UV generated) - VDDD 3.8 4.3 V VDDD decreasing P_6.12.9 VDDD Current Consumption Consumption VIO Current Consumption Undervoltage hysteresis IVIO VUV_HYS LSUP undervoltage threshold VLSUP_UV 150 4.5 mV P_6.12.10 5.5 V P_6.12.11 P_6.12.12 Missing CLK clock detection time TCLK_MSS 10 s Power On Reset time TPOR 2.1 ms Logic circuits are functional after POR timer Power-on wake up time TWU 15 ms Timer starts when P_6.12.14 all supplies are above the UV thresholds and RESN pin is high FCLK = 8 MHz. Output stages functional after TWU VBAT +13 1) V P_6.12.13 Charge Pump Charge pump voltage VCP_OUT Charge pump clock frequency FCP Charge pump warning threshold voltage VCPOUT_W Data Sheet - VBAT+8 65 VBAT+7 KHz VBAT+ 8.5 17 V P_6.12.15 FSYS = 6 MHz 2) P_6.12.16 P_6.12.17 Rev 1.0, 2013-03-21 TLE82453SA Power Supply Table 4 Electrical Characteristics: Power Supply VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, CPC1 and CP2 = 27nF CPCOUT = 220nF, all voltages with respect to ground (GNDD), positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Charge pump undervoltage threshold voltage VCPOUT_UV Charge pump overvoltage clamp VCPOUT_OV Typ. VBAT +4.5 Unit Max. VBAT +5.5 48.5 Note / Test Condition Number V P_6.12.18 V P_6.12.19 1) Will not exceed VCPOUT_OV 2) Parameter not subject to production test, specified by design Attention: Voltage Ratings for Charge Pump caps: CPC1/CPC2: Vmin=VBATmax + 10V, CCPOUT: Vmin=VBATmax + 16V Data Sheet - 18 Rev 1.0, 2013-03-21 TLE82453SA Input / Output 6 Input / Output 6.1 I/O Description The CLK pin must be connected to a precise clock signal. This clock is used by the internal analog to digital converters and by the internal logic. A small internal pull down current will keep the voltage on this pin near ground when the pin is open. The device includes a programmable divider to generate the internal system clock from the CLK pin signal. This divider ratio is programmed in the CLK-DIVIDER register by the SPI interface. The output stages cannot be enabled until this field has been written. An internal watchdog circuit will hold the device in an internal reset state if the delay between rising edges on the CLK pin is greater than the threshold time, TCLK_MSS. The watchdog is initially disabled when the device exits the reset state. The watchdog is enabled by setting the WDEN bit in the CLK-DIVIDER register. Until the watchdog is enabled, the output stages are disabled. Once the watchdog function is enabled, a missing CLK signal will set the Watchdog Status Bit in the IC VERSION register, set the FAULTN pin to a logic low state, disable the output stages, and cause the device to enter an internal reset state. In this mode of operation, the SPI response from the device will always be the response to a IC VERSION register read command. To exit this mode of operation, the device must be reset externally by the RESN pin. The EN pin is used to enable / disable the output stages. If the EN pin is low, all of the channels are disabled and (when the fault mask bit FME = 1) the FAULTN pin is pulled low. The SPI interface remains functional, however. When the EN pin is low, the EN bits in the SET-POINT registers are cleared. The EN pin can be connected to a general purpose output pin of the microcontroller or to an output of a safing circuit. The RESN pin is the reset input for the device. If the RESN pin is low, the device is held in an internal reset state, the FAULTN pin is held low, and the SPI interface is disabled. An internal pull down current source will hold the RESN pin low in case the pin is open. The FAULTN pin is an open drain output. This pin is pulled low when a fault is detected by the diagnosis circuit or when the device is in an internal reset state. An external resistor should be connected between this pin and the VIO supply. The SI, SO, CSN, and SCLK pins comprise the SPI interface. See Sections 11 and 12 for details. Data Sheet - 19 Rev 1.0, 2013-03-21 TLE82453SA Input / Output CLK FCLK FSYS First Clock Divider Divider = 2, 4, 6, or 8 (default = 8) Second Clock Divider FDITH Divider = (M+1)*2N 6 MHz (max) ADC Figure 5 Data Sheet - Logic Circuits Dither Circuit Block Clock Divider 20 Rev 1.0, 2013-03-21 TLE82453SA Input / Output 6.2 Electrical Characteristics I/O Table 5 Electrical Characteristics: VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, all voltages with respect to ground (GNDD), positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number V VIN increasing VIN decreasing P_5.2.1 Max. Control Inputs EN, RESN, CSN, SI, SCK, CLK Input threshold - low Input threshold - high Input hysteresis Pull up current - CSN Pull down current - EN, SI, SCK, CLK, RESN VIN_L VIN_H VIN_HYS IPU IPD 0.8 VSO_L VSO_H 2.0 50 V P_5.2.2 mV P_5.2.3 -50 -10 A P_5.2.4 10 50 A P_5.2.5 0 0.5 V ISO = 0.5mA VIO 0.5 VIO V ISO = -0.5mA, P_5.2.7 3.0V < VIO < 5.5V ISO_OFF -10 10 A VCSN=VIO P_5.2.8 VFLT_L 0 0.4 V IFLT = 2mA P_5.2.9 Output SO Output low-level voltage Output high-level voltage Output tri-state leakage current P_5.2.6 Output FAULTN Output low-level voltage Data Sheet - 21 Rev 1.0, 2013-03-21 TLE82453SA Power Stages 7 Power Stages 7.1 Overview There are three output channels implemented in this device. The output power stages of each channel consists of a half bridge made up of two n-channel DMOS transistors and a current sensing resistor. An internal charge pump generates the voltage required to switch the n-channel DMOS high-side switches. The switches are protected from external failures by built in over current and over temperature detection circuits. CPOUT CPC2H CPC2L CPC1L VBAT CPC1H The half bridge arrangement allows the use of active freewheeling, which reduces the power dissipation of the device. The arrangement also allows each channel to be individually programmed for lowside or highside drive. The output current slew rate of the power stages can be programmed to one of three values by programming the CONFIGURATION register by SPI. Charge Pump LSUPx VIO CSB SCK control logic LOADx SO +5V SI PGNDx Power Stage.vsd Figure 6 Power Stages 7.2 Channel Disabled When the channel is disabled, both transistors of the half bridge are turned off. The output stage is in a high output impedance state in this condition. 7.3 Channel Enabled When a channel is configured for lowside operation, the lowside DMOS switch is the “drive” switch and the highside DMOS switch is the “recirculation” switch. Likewise, when a channel is configured for highside operation, the highside DMOS switch is the “drive” switch and the lowside switch is the “recirculation” switch. In normal operation, the “drive” switch is turned on and off with the duty cycle needed to regulate the solenoid current at the target value. During the time that the “drive” switch is turned off, the device is in active freewheeling mode. The “recirculation” switch is turned on in this mode to reduce the voltage drop across the device during recirculation. Data Sheet - 22 Rev 1.0, 2013-03-21 TLE82453SA Power Stages The transistors are controlled in a way that prevents shoot through current during switching, that is the control logic prevents the simultaneous activation of both the “drive” switch and the “recirculation” switch. 7.4 Configuration of Channels The pins HSLS0, HSLS1, and HSLS2 are used to configure each channel for highside or lowside operation. The pin must be connected to ground for highside operation and to VBAT or + 5V for lowside operation. The configuration of each channel can be verified by reading the CONFIGURATION register via SPI. Data Sheet - 23 Rev 1.0, 2013-03-21 TLE82453SA Power Stages 7.5 Electrical Characteristics Power Stages Table 6 Electrical Characteristics: Power Stages VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, all voltages with respect to ground (GNDD), positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition 150 A set-point = 0mA P_7.6.1 8V < VLSUP < VBAT + 0.3V Max. Number LSUPx leakage current ILSUP_LKG LSUPx leakage current in sleep mode ILSUP_LG_SLP – 50 A Sleep mode All VDDx=0V P_7.6.2 On-State Resistance - high side FET RDS(ON)_HS – 250 mΩ Tj = 150°C; ILOAD = -1.6A P_7.6.3 On-State Resistance - low side FET RDS(ON)_LS – 250 mΩ Tj = 150°C; ILOAD P_7.6.4 OUTx leakage current ILOAD_LKG -150 150 A set-point = 0mA P_7.6.5 8V < VLSUP < VBAT + 0.3V; 0V < VLOAD < VLSUP 80 – = 1.6A Load_LKG sleep mode A P_7.6.6 1) -80 Current rise and fall times SR0 TR0, TF0, 1 s ILOAD = 1.4A; 8V < P_7.6.7 VLSUP < VBAT + 0.3V; 20% to 80% ILSUP & IGNDP Current rise and fall times SR1 TR1, TF1 0.51) s ILOAD = 1.4A; 8V < P_7.6.8 VLSUP < VBAT + 0.3V; 20% to 80% ILSUP & IGNDP Current rise and fall times  TR2, TF2 21) s ILOAD = 1.4A; 8V < P_7.6.9 VLSUP < VBAT + 0.3V; 20% to 80% ILSUP & IGNDP Voltage slew rate SR0 5 V/s P_7.6.10 Voltage slew rate SR1 10 V/s P_7.6.11 Voltage slew rate SR2 2.5 V/s P_7.6.12 mΩ P_7.6.13 Current Sense Resistor Sense resistor resistance RSENSE 250 380 1) Not subject to production test, specified by design Data Sheet - 24 Rev 1.0, 2013-03-21 TLE82453SA Current Control 8 Current Control 8.1 Overview The device has independent controller blocks for each channel. Each control loop consists of the average current setpoint input, the dither generator, the load current feedback path, the controller block, and the output stage. LSUPx Amp LOADx setpoint + + + SPI Controller steps step size Dither GNDPx Current Control.vsd Figure 7 Controller Block Diagram 8.2 Average current setpoint The average current setpoint value is determined by the contents of the SETPOINT register. The relationship between the value of the setpoint register and the average load current is shown in Figure 8.The accuracy band of the current regulation is also shown in Figure 8. The accuracy is specified over the normal operating range of the device (including the full normal operating junction temperature range). An automatic auto-zero feature is included in the device. The auto-zero feature will automatically measure the offset of the current measurement circuits of each channel after power-up. When a channel is programmed to regulate current, the offset is compensated by an automatic modification of the setpoint. The content of the SPI accessed average current setpoint register is not influenced by the autozero circuit. Data Sheet - 25 Rev 1.0, 2013-03-21 TLE82453SA Current Control 1500 +/- 1.5% 1000 500 +/- 7.5 mA ILOAD_AVG (mA) Setpoint (decimal) 1365 683 2047 Current control transfer function.vsd Figure 8 Output current transfer function and accuracy 8.3 Dither waveform A triangular dither waveform can be added to the average current setpoint in order to reduce the hysteresis of the driven solenoid valve. The dither waveform is shown in Figure 9. The frequency of the dither waveform is set by programming the STEPS field in the DITHER register. The value of the STEPS field determines the number of dither steps in one quarter of the dither waveform. The time duration of each step is set by programming the N and M fields in the CLOCK-DIVIDER register. The amplitude of the signal is determined by the contents of the STEPS field and the contents of the STEP SIZE field of the DITHER register (see Figure 9). The application software must take care that the product of the steps and stepsize does not exceed 0x03FF hex. When dither is disabled or a new value is entered, the current dither period will be completed. Entering 0 steps causes the loss of dither. entering new values will not result in a correct waveform until dither is disabled and re-enabled. See Application note for details. Data Sheet - 26 Rev 1.0, 2013-03-21 TLE82453SA Current Control Dither Period steps = 3 Dither Amplitude step size SYNC occurs Switching Cycle period Load Current without SYNC Setpoint + Dither shape without SYNC Load Current with SYNC Setpoint + Dither shape with SYNC SYNC = 0 : Dither period is independent of switching cycle period SYNC = 1 : Start of dither period is delayed until start of next switching cycle period Current Control dither.vsd Figure 9 Dither Waveform The dither waveform can be synchronized to the PWM frequency by setting the SYNC bit in the DITHER register. When the SYNC bit is set to 0, the triangular dither waveform is free-running and is asynchronous to the PWM frequency. When the SYNC bit is set to 1, a new dither period will not start until the start of the next PWM cycle. The start of a PWM cycle period is defined to be when the output stage turns on. The start of a dither period is defined to be when the dither increases one step above zero on this rising slope of the waveform. Data Sheet - 27 Rev 1.0, 2013-03-21 TLE82453SA Current Control 8.4 Sense Resistor The current sense resistor is integrated into the device. The initial error and the temperature drift of this resistor are measured and trimmed during the device manufacturing process.The internal protection circuits are built in a way, that repeated shorts to VBAT/GND will not destroy the internal shunt. 8.5 Current Controller The current controller regulates the load current by alternatively turning on the drive switch and the recirculation switch. The on time of the drive switch is determined by the integrated PWM period controller. The off time of the transistor is determined by the average current controller. When the average load current over the current PWM period is equal to the setpoint during freewheeling, the drive transistor is turned on again and the next PWM cycle is started. Output Stage State “on time” “off time” Load Current I setpoint Error Integrator threshold Current control waveform.vsd Figure 10 Controller waveforms The controller includes an integrator which integrates the difference between the average load current and the setpoint over the time duration of the PWM cycle. At the start of a PWM cycle, the driving FET is turned on and the recirculation FET is turned off. In this phase of operation, the load current will increase. When the value of the error integrator exceeds the integrator threshold, the driving FET is turned off and the recirculation FET is turned on. The load current will decrease in this phase of operation. The integrator threshold is adjusted automatically by the internal PWM period controller until the desired PWM period is reached. When the error integrator decreases to 0, the recirculation FET is turned off and the driving FET is turned on to start the next PWM cycle. The integrator can be automatically limited by the device after a change in setpoint by setting the Auto-Limit bit in the SETPOINT register. The device will limit the integrator output to a small value (+/- 20d) during the setpoint change and then automatically revert back to the normal integrator limit values after the setpoint change has been achieved when this bit is set. A “Regulator Error” fault bit in the DIAGNOSIS register is set when the programmed setpoint current is not reached after 8 PWM cycles after the SETPOINT register is written. Data Sheet - 28 Rev 1.0, 2013-03-21 TLE82453SA Current Control 8.6 PWM Frequency Controller The integrated PWM Frequency controller regulates the PWM Frequency using an “Integral” control loop with a programmable gain, KI. This control loop monitors the actual PWM period and compares it to the PWM period setting in the PWM Period Register. The error in the PWM period is multiplied by the gain KI and then integrated at each PWM cycle. The output of the controller adjusts the “on time” of the PWM signal until the actual PWM period matches the programmed PWM period. KI gains of 1, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 can be selected in the PWM Period Register. The KI value of 1, KI_index =0, has the fastest response time, the KI value of 1/64, KI_index=6, has the slowest response time, but with less overshoot and less ringing. KI_index = 6 is the recommended setting for initial evaluation. 8.7 Autozero Each channel has an autozero function which measures and compensates for the offset of analog current measurement circuits. The autozero function is automatically initiated during power up after the first write to the CLK-DIVIDER register. The function can also be initiated by the user by setting the AZ start bit in the AUTOZERO SPI message. The EN bit in the SETPOINT register must be set to “0” to initiate the auto-zero function. This AZ START bit is automatically cleared by the device when the autozero sequence is complete. The measured offset of current measurement circuits can be read by the micro controller via the SPI message AUTOZERO. 8.8 Measurement Functions The SPI register FEEDBACK can be read to access the value of the load current measured by the device and the value of the output PWM period. The CFB bit in the DITHER register selects between two measurement types. When CFB=0, the average current and the switching period are measured over each switching cycle. When CFB=1, the maximum current and minimum currents are measured over a dither cycle. Also the number of switching cycles occurring in the last dither cycle is measured. When the CFB bit = 0 and the device is not in calibration mode, the FEEDBACK register contains a 12 bit Current Feedback field. The content of this field represents the integration of the load current measured by the analog current measurement circuit blocks over the most recent switching period. The average load current can be calculated according to the equation I_load_avg = 0.75 * Current Measurement_Feedback / (Period Measurement Feedback). When the CFB bit = 0 and the device is not in calibration mode, the actual output frequency of each channel can be determined by reading the 12 bit Period Feedback field in the FEEDBACK register. This field contains the number of system clocks (Fsys) counted during the most recently completed PWM period divided by 16, this is the same resolution as the PWM set register. When the CFB bit = 1 and the device is not in calibration mode, the FEEDBACK register contains two 8 bit Current Feedback (CFB) fields. The contents of these fields represent the minimum and maximum load current measured by the analog current measurement circuit blocks over the most recent dither cycle when dither is enabled. Otherwise, these fields contain the minimum and maximum load current values since the last read of the FEEDBACK register. I min and I max = 3 * readout / 256. When the CFB bit = 1 and the device is not in calibration mode, the FEEDBACK register contains an 8 bit field which contains the number of full switching cycles in the last dither cycle. This information can be used by the microcontroller to calculate the average switching cycle period over a dither period. If dither is disabled, the contents of this register is 0. The contents of the feedback registers are 0 when the respective channel is not operating. The number of PWM cycles per dither cycle value is 0 if dither is disabled. 8.9 Calibration Mode In case the accuracy of the current regulation must be improved by module calibration, the TLE 82453 device includes a calibration mode of operation. In order to enter calibration mode, the CM bit in the CALIBRATION Data Sheet - 29 Rev 1.0, 2013-03-21 TLE82453SA Current Control register must be set by writing a 1 to this bit location. Calibration mode will not be entered unless the setpoint for all three channels is zero and the EN enable bit (in the SETPOINT register) is set to “1”. If one or more of the channels is not off and a “1” is written to the CM bit, the write command is ignored and the CM bit will remain at 0. In the Calibration Mode of operation, the individual transistors of the output stages can be controlled by writing to the CALx bits in the CALIBRATION register. The resulting output current will be measured by the device and can be monitored by reading the FEEDBACK register. When the device is in calibration mode, the FEEDBACK register contains a 16 bit field which represents the average load current measured during the calibration. Ical = 1.5 * readout / 65536. The Current Feedback Register is not valid if the PWM period is set to 0x00 in the PWM Register. Current limitation is not active during calibration mode. Exceeding 1.5 amps may damage the the device. Data Sheet - 30 Rev 1.0, 2013-03-21 TLE82453SA Current Control 8.10 Electrical Characteristics Table 7 Electrical Characteristics: Current Control VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number 15001) mA target P_8.10.1 – mA P_8.10.2 Max. Average Current Regulation 0 Output current accuracy IMEAS ISPRES ISPACCL1 -5 5 mA 0A < ILOAD < 0.5A P_8.10.3 -40C < Tj < 125C Output current accuracy ISPACCH1 -1 1 % 0.5A< ILOAD 0ma SI DIAGNOSIS DIAG- DIAGNOSIS NOSIS DIAG- DIAGNOSIS NOSIS OTx = 0 OTx=1 OTx=1 OTx=1 OTx=0 SO FAULTN (FMx = 1) Figure 12 Data Sheet - Over Temperature Timing Diagram (High-Side Configuration) 33 Rev 1.0, 2013-03-21 TLE82453SA Protection Functions JUNCTION TEMP Tj > OTSD Tj < OTSD Tj < OTSD I LOADx VLOADx OTx CSN DIAGNOSIS DIAG- DIAGNOSIS NOSIS DIAG- DIAGNOSIS NOSIS I > 0ma SI DIAGNOSIS DIAG- DIAGNOSIS NOSIS DIAG- DIAGNOSIS NOSIS OTx = 0 OTx=1 OTx=1 OTx=1 OTx=0 SO FAULTN (FMx = 1) Figure 13 Over Temperature Timing Diagram (Low-Side Configuration) 9.4 Over Voltage Shutdown This feature is implemented to protect the internal power transistors from damage due to overvoltage on the VBAT pin. If the voltage on the VBAT pin exceeds the VBAT overvoltage threshold an overvoltage fault bit will be set in the diagnostic register. This fault bit will be latched until the diagnostic register is read by SPI and the overvoltage condition no longer exists. All channels are disabled while the overvoltage condition exists and the setpoints of all channels are cleared to 0 mA. The charge pump output voltage is clamped to approximately 50V. The charge pump undervoltage fault (CPUV) may be set before the VBAT over voltage fault bit is set depending on the rise time of the VBAT voltage. Data Sheet - 34 Rev 1.0, 2013-03-21 TLE82453SA Protection Functions 9.5 Electrical Characteristics Table 8 Electrical Characteristics: Protection Functions VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number note: operates over range VLSUP_UV < VLSUP < VBAT+0.3V, VDDx_UV 0ma I > 0ma DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OVCx=0 OVCx=1 OVCx=0 OVCx=1 OVCx=0 FAULTN (FMx = 1) Figure 17 Data Sheet - Over-Current Fault in High-Side Configuration 38 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions Load State NORMAL LOAD NORMAL LOAD SHORT TO BATTERY ILOADx TOC TOC VLOADx OVCx CSN DIAGNOSIS DIAGNOSIS DIAGNOSIS I > 0ma I > 0ma DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS OVCx =0 OVCx =1 OVCx =0 OVCx =1 OVCx =0 SO FAULTN (FMx = 1) Figure 18 Over-Current Fault in Low-Side Configuration 10.5 Open Load / Switch Bypass Fault An open load fault and a switch bypass fault can be detected when the setpoint of the faulted channel is equal to 0 mA (channel off) and when the setpoint is greater than 0 mA (channel operating). The switch bypass fault is a short to battery fault when the channel is configured as a high-side driver and a short to ground when the channel is configured as a low-side driver. The device detects an open load or switch bypass fault in the operating condition by monitoring the load current. If the load current is below the OLSB threshold current for a time greater than the OLSB delay time (on state), then the OLSBx fault bit is set and the channel is turned off. The OLSBx fault bit is latched when the fault occurs, and it is cleared when the DIAGNOSIS register is read and the fault is no longer present. The channel may be turned on again writing the desired setpoint to the setpoint register after the diagnosis register has been read. The type of fault needs to be verified using the OLoff test discribed in Application note. Data Sheet - 39 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions Load State NORMAL LOAD OPEN LOAD or SWITCH BYPASS NORMAL LOAD ILOADx VLOADx Tolsb_on OLSBx CSN DIAGNOSIS DIAG- DIAGNOSIS NOSIS Set-point >0 SI DIAGNOSIS DIAGNOSIS OLOFFx =0 OLOFFx =1 SO FAULTN (FMx = 1) Figure 19 OLSB Fault - On State Timing Diagram (High-Side Configuration) Load State NORMAL LOAD OPEN LOAD or SWITCH BYPASS NORMAL LOAD ILOADx VLOADx Tolsb_on OLSBx CSN DIAGNOSIS DIAG- DIAGNOSIS NOSIS Set-point >0 SI DIAGNOSIS DIAGNOSIS OLSBx =0 OLSBx =1 SO FAULTN (FMx = 1) Figure 20 OLSB Fault - On State Timing Diagram (Low-Side Configuration) The device detects an open load / switch bypass fault when the channel is turned off by applying a weak current source to the LOADx pin and comparing the LOADx pin voltage to VLSUPx/2. A pull up current source or a pull down current sink can be activated by setting the IDIAGx Select field of the CONFIGURATION register. The programmed current source is automatically enabled when the setpoint is set to 0 and the EN bit in the setpoint register is set to 1. It is disabled when the setpoint is set to a value greater than 0 or the EN bit is set to 0. A simplified block diagram of the OLOFF detection circuit when the channel is disabled is shown in Figure 21. The OL-OFF fault bit is not latched in this case. The fault bit will be cleared when the fault is no longer present. When the channel is disabled and an OL-OFF fault is detected, it is possible to discriminate between an open load fault and a switch bypass fault by changing the IDIAG current source. For a high-side configured channel, the pull Data Sheet - 40 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions up current source must be initially enabled in order to detect the OL-OFF fault. Once this fault is detected, the pull up current source current can be disabled and the pull down current can be enabled by SPI in order to determine if the fault is an open load or a short to battery. LSUP0 VL0 IDI AG_P U IDIAG LOGIC + OLOFFx filter LOAD 0 IDI AG_P D - C ESD GNDP0 V LS UP x 2 Figure 21 OLSB Fault - Off State Block Diagram Load State NORMAL LOAD OPEN LOAD NORMAL LOAD Pull up diagnostic current is active VLOADx OL-OFFx CSN DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OLOFFx =0 OLOFFx OLOFFx =1 =1 OLOFFx OLOFFx =0 =0 FAULTN (FMx=1) Figure 22 Data Sheet - Open Load Fault - Off State Timing Diagram (High-Side Configuration) 41 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions Load State NORMAL LOAD OPEN LOAD NORMAL LOAD Pull down diagnostic current is active VLOADx OL-OFFx CSN DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OLOFFx =0 OLOFF OLOFFx =0 x=0 OLOFFx OLOFFx =1 =1 FAULTN (FMx=1) Figure 23 Open Load Fault - Off State Timing Diagram (Low-Side Configuration) Load State NORMAL LOAD SHORT TO BATTERY NORMAL LOAD Pull up diagnostic current is active VLOADx OL-OFFx CSN DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS OLOFFx =0 OLOFFx =1 OLOFFx =1 OLOFFx =0 DIAGNOSIS SO OLOFFx =0 FAULTN (FMx=1) Figure 24 Data Sheet - Switch Bypass Fault - Off State Timing Diagram (High-Side Configuration) 42 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions Load State NORMAL LOAD SHORT TO GROUND NORMAL LOAD Pull down diagnostic current is active VLOADx OL-OFFx CSN DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OLOFFx =0 OLOFFx OLOFFx =0 =0 OLOFFx OLOFFx =1 =1 FAULTN (FMx=1) Figure 25 Switch Bypass Fault - Off State Timing Diagram (Low-Side Configuration) OLSB OFF Current PULL UP CURRENT ACTIVE PULL DOWN CURRENT ACTIVE VLOADx OL-OFFx CSN DIAGNOSIS Diag current = pull down DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OLOFFx OLOFFx =0 =0 OLOFFx =1 FAULTN (FMx=1) Figure 26 Data Sheet - Open Load Fault - Off State Discrimination Timing Diagram (High-Side Configuration) 43 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions OLSB OFF Current PULL DOWN CURRENT ACTIVE PULL UP CURRENT ACTIVE VLOADx OL-OFFx CSN DIAGNOSIS Diag current = pull up DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OLOFFx OLOFFx =0 =0 OLOFFx =1 FAULTN (FMx=1) Figure 27 Open Load Fault - Off State Discrimination Timing Diagram (Low-Side Configuration) OLSB OFF Current PULL UP CURRENT ACTIVE PULL DOWN CURRENT ACTIVE VLOADx OL-OFFx CSN DIAGNOSIS Diag current = pull down DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OLOFFx OLOFFx =1 =1 OLOFFx =1 FAULTN (FMx=1) Figure 28 Data Sheet - Switch Bypass Fault - Off State Discrimination Timing Diagram (High-Side Configuration) 44 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions OLSB OFF Current PULL DOWN CURRENT ACTIVE PULL UP CURRENT ACTIVE VLOADx OL-OFFx CSN Diag current = pull up DIAGNOSIS DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS OLOFFx =1 OLOFFx =1 DIAGNOSIS SO OLOFFx =1 FAULTN (FMx=1) Figure 29 Switch Bypass Fault - Off State Discrimination Timing Diagram (Low-Side Configuration) 10.6 Supply Out of Range Fault The LSUPx pins, the CPOUT pin, and the VBAT pin are connected to internal monitor circuits which disable the output channels if the pin voltage is out of range. The VBAT pin is connected to an over-voltage detection circuit block. The CPOUT and LSUPx pins are connected to undervoltage detection circuits. When the voltage on these pins exceeds the shutdown threshold, a fault bit is set and the channel is disabled. The fault bits are latched until the DIAGNOSIS register is read and the voltage is in the correct range. When a CPUV fault occurs, all channels are turned off and the setpoints are cleared. The channels can be reactivated when the CPUV fault is not present by reading the DIAGNOSIS register and setting the setpoint. Data Sheet - 45 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions VBAT < OVSD THRESHOLD AND CPOUT – VBAT > UV THRESHOLD VBAT > OVSD THRESHOLD AND CPOUT – VBAT < UV THRESHOLD CPOUT – VBAT > UV THRESHOLD AND LSUPx > UV THRESHOLD VBAT < OVSD THRESHOLD OR OR AND LSUPx < UV THRESHOLD LSUPx > UV THRESHOLD I LOADx VLOADx OVB, CPUV, LSUPUVx CSN DIAGNOSIS Set-point DIAG>0 NOSIS DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS DIAGNOSIS SO OVB = 0 CPUV = 0 LSUPUVx=0 OVB = 1 CPUV = 1 LSUPUVx=1 OVB = 1 OVB = 0 CPUV = 1 CPUV = 0 LSUPUVx=1 LSUPUVx=0 FAULT (FMx=1 LSUPUVx) Figure 30 Supply Out of Range Fault in High-Side Configuration VBAT < OVSD THRESHOLD VBAT < OVSD THRESHOLD VBAT > OVSD THRESHOLD OR AND AND CPOUT – VBAT < UV THRESHOLD OR CPOUT – VBAT > UV THRESHOLD AND LSUPx > UV THRESHOLD LSUPx < UV THRESHOLD LSUPx > UV THRESHOLD AND CPOUT – VBAT > UV THRESHOLD I LOADx VLOADx OVB, CPUV, LSUPUVx CSN DIAGNOSIS Set-point DIAGNOSIS >0 DIAGNOSIS DIAGNOSIS SI DIAGNOSIS DIAGNOSIS DIAGNOSIS OVB = 0 CPUV = 0 LSUPUVx=0 OVB = 1 CPUV = 1 LSUPUVx=1 DIAGNOSIS SO OVB = 1 OVB = 0 CPUV = 1 CPUV = 0 LSUPUVx=1 LSUPUVx=0 FAULT (FMx=1 LSUPUVx) Figure 31 Data Sheet - Supply Out of Range Fault in Low-Side Configuration 46 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions 10.7 CRC Fault The device contains EEPROM cells for storing calibration data. These cells are accessed during start up and periodically during operation of the device. A Cyclical Redundancy Checking (CRC) feature is included to detect errors in the reading of the EEPROM. If an error is detected, the CRC error bit will be set in the DIAGNOSIS register. All channels will remain operational, but the accuracy of the current control may be degraded. The CRC fault bit is cleared upon reading the Diagnosis Register. 10.8 Regulator Error Fault (REx) The DIAGNOSIS register includes a regulator error bit for each channel. This bit is set when the controller is not able to regulate the load current to the setpoint value. The RE bit is set when the integrator output exceeds the lower or upper integrator limits. When Autolimit is active (during a setpoint change), the RE bit is set if the integrator output exceeds the upper or lower limit for more than 8 PWM cycles. The REx fault bits are cleared upon reading the Diagnosis Register. During a REx error the output will not shut off. The output goes into a 100% duty cycle until the load and voltage conditions allow pwm to resume. During a REx the current feedback values will not be correct until normal pwm conditions return. Data Sheet - 47 Rev 1.0, 2013-03-21 TLE82453SA Diagnosis Functions 10.9 Electrical Characteristics Table 9 Electrical Characteristics: Diagnosis VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Shorted load resistance threshold RSL_ON 0.5 Open load - switch bypass threshold current range (on state) IOLSB_ON 0 Open load - switch bypass delay time (on state) TOLSB ON Off-State pull up current IDIAG_UP -600 Off-State pull down current IDIAG_DN VLOAD_DIAG Off-state LOADx threshold voltage Typ. Unit Note / Test Condition Number Ω 1) P_10.9.1 mA Configurable P_10.9.2 Max. 375 8192 cycles Fsys cycles P_10.9.3 -100 A VLOAD < VLSUP 4V P_10.9.4 100 600 A VLOAD > 4V P_10.9.5 0.42* VLSUP 0.58* V VLSUP independent of VBAT voltage P_10.9.6 1) Not subject to production test, specified by design. Data Sheet - 48 Rev 1.0, 2013-03-21 TLE82453SA Serial Peripheral Interface (SPI) 11 Serial Peripheral Interface (SPI) 11.1 Description of Interface The diagnosis and control communication interface is based on the standard serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface which uses four signal lines: SO, SI, SCK, and CSN. Data is transferred by the lines SI and SO at the data rate given by SCK. The falling edge of CSN indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCK and shifted out on line SO at the rising edge of SCK. Each access must be terminated by a rising edge of CSN. A counter ensures that data is taken only when 32 bits have been transferred. If in one transfer cycle the number of bits transferred is not 32, the data frame is ignored SO MSB 30 29 28 27 26 8 7 6 5 4 3 2 1 LSB SI MSB 30 29 28 27 26 8 7 6 5 4 3 2 1 LSB CSN SCLK time Figure 32 SPI Interface Signal Overview 11.2 Timing Diagrams tCSN(lead) tCSN(lag) tCSN(td) tSCLK(P) CS VIH VIL tSCLK(H) tSCLK(L) VIH SCLK VIL tSI(su) tSI(h) VIH SI VIL tSO(en) tSO(v) tSO(dis) VIH VIL SO Figure 33 Data Sheet - SPI Signal Timing Diagram - Thresholds = 20% / 80% 49 Rev 1.0, 2013-03-21 TLE82453SA Serial Peripheral Interface (SPI) 11.3 Electrical Characteristics SPI Interface Table 10 Electrical Characteristics: SPI VBAT = 8 V to 17 V, VDDx = 4.75 V to 5.25 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number MHz 1) 2) P_11.3.1 ns 1) P_11.3.2 ns 1) P_11.3.3 250 ns 1) P_11.3.4 250 ns 1) P_11.3.5 Min. fSCLK Serial clock high time tSCLKH Serial clock low time tSCLKL Enable lead time (falling CSN tCSN_LEAD Serial clock frequency Typ. 0 Max. 8 50 50 to rising SCLK) Enable lag time (falling SCLK tCSN_LAG to rising CSN) Transfer delay time (rising CSN to falling CSN) tCSN_TD 5 cycles Fsys cycles 1) Data setup time (required time SI to falling SCLK) tSI_SU 20 ns 1) P_11.3.7 20 ns 1) P_11.3.8 Data hold time (required time tSI_H falling SCLK to SI) P_11.3.6 Output enable time (falling CSN to SO valid) tSO_EN 200 ns CL = 200 pF 1) P_11.3.9 Output disable time (rising CSN to SO tri-state) tSO_DIS 200 ns CL = 200 pF 1) P_11.3.10 Output data valid time with capacitive load tSO_V 100 ns CL = 200 pF 1) P_11.3.11 SO rise time tSO_R tSO_F CIN 50 ns CL = 200 pF 1) P_11.3.12 50 ns CL = 200 pF 1) P_11.3.13 20 pF 1) P_11.3.14 CSO_HIZ 25 pF Tri-state 1) P_11.3.15 SO fall time Input pin capacitance: CSN, SCLK, SI SO pin capacitance 1) Not subject to production test, specified by design 2) Maximum SPI clock frequency in the application may be less depending on the load at the SO pin and the microcontroller SPI peripheral timing requirements Data Sheet - 50 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12 SPI Registers 12.1 Description of Protocol For each command received at the SI pin of the SPI interface, a serial data stream is returned at the same time on the SO pin. The content of the SO data frame is dependent on the command which was received on the SI pin during the previous frame. A READ command (R/W = 0) returns the contents of the addressed register one SPI frame later. The data bits in the READ command are ignored. A WRITE command (R/W = 1) will write the databits in the SPI word to the addressed register. The actual contents of that register will be returned to the SPI master (microcontroller) during the next SPI frame. The response is not an echo of the data received from the SI pin, it is the actual contents of the register addressed in the previous SPI frame. CSN SI R Message #1 W Message #2 R Message #3 SO Response #1 Figure 34 Response #2 SPI Protocol Each SPI message for the TLE82453 has a length of 32 bit. The message from the microcontroller must be sent MSB first. The data from the SO pin is sent MSB first. The response to an invalid SPI message is the IC Version and Manufacturer ID register (ICVID). The SO data in the frame immediately following a reset condition is the IC Version and Manufacturer ID (ICVID) register. Data Sheet - 51 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.2 ICVID REGISTER ICVID IC Version and Manufacturer ID Reset Value: 00C1 xx00H 31 30 29 28 27 26 25 24 R/W 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 2 1 0 Manufacturer ID 7 Version 6 5 4 3 not used WDS Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Read (cannot write to this register) When reading this register, the R/W bit is 0 Manuf ID 23:16 r IC Manufacturer ID 1100 0001 = Infineon Version 15:8 r IC Version B13 step = 00000100 WDS 1 r CLK Watchdog Status 0 = CLK signal OK or watchdog disabled (Reset value) 1 = Watchdog timeout fault (cleared only by reset) Data Sheet - 52 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.3 CONFIGURATION REGISTER CONFIG Configuration Register Reset Value: 0100 000xH 31 30 29 28 27 26 25 24 R/W 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 IDIAG IDIAG IDIAG 2 1 0 SR2 SR1 23 22 21 20 19 18 17 16 not used 7 SR0 6 5 4 3 2 1 0 FME FM2 FM1 FM0 HL2 HL1 HL0 Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write When reading this register, the R/W bit is 0 IDIAG0-2 15:13 rw Set Off State Diagnostic current 0 = High-Side current source is active (Reset value) 1 = Low-Side current source is active SR0-2 12:7 rw Set slew rate setting of channel 00 = Set the channel slew rate to SR0 (Reset value) 01 = Set the channel slew rate to SR1  10 = Set the channel slew rate to SR2 11 = Ignored (previous setting is used) FME 6 rw Set Fault Mask for EN pin 0 = EN pin state does not influence the FAULTN pin (Reset value) 1 = FAULTN pin is driven low if the EN pin is low. FM0-2 5:3 rw Set Fault Mask for channel 0 = Channel faults do not influence the FAULTN pin (Reset value) 1 = FAULTN pin is driven low when a fault is detected on the channel HL0-2 2:0 r HSLS2, HSLS1, and HSLS0 pin status (Reset value = state of HSLS pins) 0 = Highside configuration 1 = Lowside configuration Data Sheet - 53 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.4 DIAGNOSIS REGISTER DIAG Diagnosis Register Reset Value: 02x0 0000H 31 30 29 28 27 26 25 24 23 22 R/W 0 0 0 0 0 1 0 CRC RST 15 14 13 12 11 10 9 8 7 6 RE0 UV2 UV1 UV0 OT2 OT1 OT0 21 20 CPUV CPW 5 4 19 18 17 16 OVB not used RE2 RE1 3 2 1 0 OL OL OL OLSB OLSB OLSB OVC2 OVC1 OVC0 OFF2 OFF1 OFF0 2 1 0 Field Bits Type Description CRC 23 r EEPROM CRC fault bit 0 = no fault detected (Reset value) 1 = fault detected RST 22 r Reset bit 0 = no reset detected 1 = reset detected (cleared after register is read) CPUV 21 r Charge Pump undervoltage shutdown 0 = no fault detected (Reset value) 1 = fault detected CPUV may be set after power up CPW 20 r Charge Pump undervoltage warning 0 = no fault detected (Reset value) 1 = fault detected CPW may be set after power up OVB 19 r Overvoltage on VBAT pin 0 = no fault detected (Reset value) 1 = fault detected RE0-2 17:15 r Regulator Error 0 = no fault detected (Reset value) 1 = fault detected REx bit is set if the commanded current is not reached after 8 PWM periods UV0-2 12:14 r Undervoltage on Load Supply pin 0 = no fault detected (Reset value) 1 = fault detected OT0-2 11:9 r Over Temperature fault bits 0 = no fault detected (Reset value) 1 = fault detected OL OFF0-2 8:6 r Open Load Fault when channel is off 0 = no fault detected (Reset value) 1 = fault detected Data Sheet - 54 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers Field Bits Type Description OLSB0-2 5:3 r Open Load / Switch-Bypass fault bit 0 = no fault detected (Reset value) 1 = fault detected OVC0-2 2:0 r Overcurrent fault bit 0 = no fault detected (Reset value) 1 = fault detected 12.5 CLK-DIVIDER REGISTER CLK-DVD Clock Divider Register Reset Value: 0300 0000H 31 30 29 28 27 26 25 24 R/W 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 not used WDEN 23 22 21 20 19 18 17 16 2 1 0 not used 7 M 6 5 4 3 N Fsys div Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write When reading the register, the R/W bit is 0 WDEN 12 rw Enable CLK pin watchdog 0 = Disable Watchdog (Reset value) 1 = Enable Watchdog The output stages are disabled until the WDEN bit is set. To operate the device without the watchdog function, the WDEN bit must be set to 1 and then cleared to 0. M 11:6 rw Set mantissa of pre-divider (Reset value = 32 decimal) Fdither = Fsys / ((M+1) * 2^N) N 5:2 rw Set exponent of pre-divider (Reset value = 6) Fdither = Fsys / ((M+1) * 2^N) Fsys div 1:0 rw Set FCLK / FSYS divider 00 - divide by 8 (Reset value) 01 - divide by 6 10 - divide by 4 11 - divide by 2 Note: Autozero should be initiated after changing the divider, first write to this register after powerup automatically starts the autozero process Note: Following a reset or power up event, the outputs are disabled until this register has been written to. Data Sheet - 55 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.6 CALIBRATION REGISTER CAL Calibration Register Reset Value: 0500 0000H 31 30 29 28 27 26 25 24 23 R/W 0 0 0 0 1 0 1 CM 15 14 13 12 11 10 9 8 7 not used 22 21 20 19 18 17 16 2 1 0 not used 6 5 4 CAL2 3 CAL1 Field Bits Type Description R/W 31 w Read / Write bit 0 = Read 1 = Write When this register is read, the R/W bit is 0 CM 23 rw Enable Calibration Mode 0 = Disable Calibration Mode (Reset value) 1 = Enable Calibration Mode CAL2 5:4 rw Set LOAD2 output stage state in calibration mode 00 = HS and LS FETs off (Reset value) 01 = HS FET off, LS FET on 10 = HS FET on, LS FET off 11 = HS and LS FETs off CAL1 3:2 rw Set LOAD1 output stage state in calibration mode 00 = HS and LS FETs off (Reset value) 01 = HS FET off, LS FET on 10 = HS FET on, LS FET off 11 = HS and LS FETs off CAL0 1:0 rw Set LOAD0 output stage state in calibration mode 00 = HS and LS FETs off (Reset value) 01 = HS FET off, LS FET on 10 = HS FET on, LS FET off 11 = HS and LS FETs off Data Sheet - 56 CAL0 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.7 SETPOINT REGISTER SETPOINT Setpoint register Reset Value: 1000 0000H 31 30 29 28 27 26 R/W 0 0 1 0 not used 15 14 13 12 11 10 25 24 23 22 Channel # EN AL 7 6 9 8 not used 21 20 19 18 17 16 1 0 not used 5 4 3 2 Setpoint Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write When reading this register, the R/W bit is 0 Channel 25:24 rw Select Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 EN 23 rw Enable channel 1 = enable the addressed channel 0 = disable the addressed channel Auto Limit 22 rw Enable integrator autolimit for the addressed channel 1 = enable autolimit (Reset value) limit=20d and -20d 0 = disable autolimit Setpoint 10:0 rw Set average current setpoint of addressed channel (Reset value=0) lsb = 0.73 mA Data Sheet - 57 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.8 DITHER REGISTER DITHER Dither Register Reset Value: 1800 0000H 31 30 29 28 27 26 R/W 0 0 1 1 not used 15 14 13 12 11 10 Number of dither steps 25 24 23 22 21 Channel # EN SYNC CFB MODE 7 6 5 9 8 not used 20 19 18 17 16 1 0 not used 4 3 2 Dither step size Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write When reading this register, the R/W bit is 0 Channel 25:24 rw Select Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 EN 23 rw Enable dither for the addressed channel 1 = enable dither 0 = disable dither (reset value) SYNC 22 rw Enable Synchronization of Dither to PWM frequency 1 = enable synchronization - start of dither synched to start of PWM cycle 0 = disable synchronization - free running dither (Reset value) CFB MODE 21 rw Select Mode for Current Feedback 1 = Min / Max / PWM periods per dither period 0 = Average current and switching period Steps 15:10 rw Set the dither steps of the addressed channel (Reset value = 0) number of steps in a quarter dither cycle. Step duration = 1/Fdith Step Size 5:0 rw Set the dither stepsize of addressed channel (Reset value = 0) lsb = 0.73 mA. Note: the product of the Steps and Step Size values must not exceed 1023, otherwise the dither waveform will be incorrect. Data Sheet - 58 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.9 INTEGRATOR LIMIT REGISTER INT LIMIT Integrator Register Reset Value: 20BF FFFFH 31 30 29 28 27 26 R/W 0 1 0 0 not used 15 14 13 12 11 10 25 24 23 Channel # 9 22 21 20 not used 8 7 High Limit (cont) 6 19 18 16 1 0 High Limit 5 4 3 2 Low Limit Field Bits Type Description R/W 1 rw Read / Write bit 0 = Read 1 = Write When reading this register, the R/W bit is 0 Channel 25:24 rw Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 High Limit 21:11 rw Set high limit of integrator (Reset value = 07FFH) effective value is 32 * High Limit value Low Limit 10:0 rw Set low limit of integrator (Reset value= 07FFH) effective value is -32 * Low Limit value Data Sheet - 17 59 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.10 PWM PERIOD REGISTER PWM PERIOD PWM period register Reset Value: 2800 0000H 31 30 29 28 27 26 R/W 0 1 0 1 not used 15 14 13 12 11 10 25 24 23 not used Channel # 9 22 8 20 19 KI_index 7 not used 21 6 5 18 17 16 not used 4 3 2 1 0 PWM Period Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write Channel 25:24 rw Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 KI_index 22:20 rw Set the KI gain for the PWM period controller KI = 2^-KI_index. Maximum value = 6. Writing 7 to this field will result in KI_index=6 KI_index reset value = 010B KI reset value = 1/4 rw Set the PWM period lsb = 16 / FSYS PWM Period 11:0 Data Sheet - 60 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.11 INTEGRATOR THRESHOLD &OPEN ON REGISTER INT HYST Integrator hysteresis register Reset Value: 3000 0000H 31 30 29 28 27 26 R/W 0 1 1 0 not used 15 14 13 12 11 10 25 24 23 Channel # 9 22 21 20 not used 8 7 Integrator Threshold (cont) 6 19 18 17 16 Integrator Threshold 5 4 3 2 1 0 Open Load on Limit Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write Channel 25:24 rw Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 Integrator Threshold 21:6 r Integrator Threshold - Read Only threshold at which the output stage is turned off. Controlled by PWM period controller. Reset value = 0 Open Load on Limit 5:0 rw Set the open load while on current threshold lsb = 5.9 mA Reset value = 0 Must be written with a non=zero value to enable open load while on fault detection Data Sheet - 61 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.12 AUTOZERO REGISTER AUTOZERO Autozero Register Reset Value: 3800 0000H 31 30 29 28 27 26 R/W 0 1 1 1 not used 15 14 13 12 11 10 25 24 23 21 20 19 18 17 16 6 5 4 3 2 1 0 AZ Start Channel # 9 22 8 7 not used AZ Value Field Bits Type Description R/W 31 rw Read / Write bit 0 = Read 1 = Write Channel 25:24 rw Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 AZ Start 23 rw Initiate Auto Zero 1 = start autozero sequence 0 = no effect (Reset value) The EN bit in the SETPOINT register must be set to 0 in order to perform the autozero function. AZ Value 12:0 r Read the offset of addressed channel (Reset value = 0) After the autozero sequence is completed, the AZ Value field will contain the measured offset. Data Sheet - 62 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers 12.13 FEEDBACK REGISTER FEEDBACK Feedback Register 31 30 29 Reset Value: 4000 0000H 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 CAL MODE - Current Feedback R/W 1 0 0 0 not used Channel # CFB=0 - Current Feedback CFB=1 - Max Current 15 14 13 12 11 10 9 8 7 6 5 CAL MODE - Current Feedback (cont) 4 3 2 not used CFB=0 Current FB (cont) CFB=0 Period Feedback CFB=1 - MIN Current CFB = 1 - # switching periods in dither cycle Field Bits Type Description R/W 31 r Read / Write bit 0 = Read 1 = Write Channel 25:24 r Channel Number 00 = LOAD0 01 = LOAD1 10 = LOAD2 CAL MODE Current FB 23:8 r CAL Mode =1 Current Feedback 1 lsb = 0.023 mA Ical = 1.5 * readout / 65536 Current FB 23:12 r CAL Mode =0 & CFB Mode=0 Current Feedback Average Load Current = 0.75* Current FB / Period FB Average current measured over the last switching cycle Field value = 0 if channel is not operating Period FB 11:0 r CAL Mode =0 & CFB Mode=0 Switching Period Feedback 1 lsb = 16 / FSYS Period of last switching cycle Field value = 0 if channel is not operating MAX Current 23:16 r CAL Mode =0 & CFB Mode=1 MAX Current Feedback 1 lsb = 11.7 mA I max = 3 * readout / 256 Maximum current measured over last dither cycle (dither enabled) Maximum current measured since last read of this register (dither off) Field value = 0 if channel is not operating Data Sheet - 63 Rev 1.0, 2013-03-21 TLE82453SA SPI Registers Field Bits MIN Current 15:8 Switching cycles per dither cycle Data Sheet - 7:0 Type Description r CAL Mode =0 & CFB Mode=1 MIN Current Feedback 1 lsb = 11.7 mA I min = 3 * readout / 256 Minimum current measured over last dither cycle (dither enabled) Minimum current measured since last read of this register (dither off) Field value = 0 if channel is not operating r CAL Mode =0 & CFB Mode=1 Switching cycles per dither cycle 1 lsb = 1 switching cycle Field value = 0 if channel is not operating or dither is disabled 64 Rev 1.0, 2013-03-21 TLE82453SA Application Information 13 Application Information This is the description how the IC is used in its environment… Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VBAT HSD e.g. ~100uF BTS5246 2L 100 nF LSUP0 L SUP 1 L SUP 2 CPC2H 27nF CPC2L 5V Power Supply CPC1H CPC1L 27nF CPOUT 220 nF VBAT charge pump 100nF VDDA 100nF GNDA VDDD 100nF GNDD supply VDDAREF 100nF GNDAREF VCC 10K LOAD 0 LOAD1 RESN RESN GPIO EN GPIO FAULTN LOAD 2 CLK CLKOUT HSLS0 5V HSLS1 control HSLS2 µC e.g. TC1766 TM TMO1 4.7nF to 10nF TM02 VIO CSB SPI SPI SO SI GNDP0 GNDP1 GNDP2 VSS SCK Application Circuit LS.vsd Figure 35 Application Diagram - Low-Side Configuration Figure 36 - Low-Side Configuration Figure 37 - Low-Side Configuration Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Data Sheet - 65 Rev 1.0, 2013-03-21 TLE82453SA Application Information VBAT HSD e.g. ~100uF BTS5246 2L 100nF LSUP0 L SUP 1 L SUP 2 CPC2H CPC2L 5V Power Supply 27nF CPC1H CPC1L 27nF 100 nF CPOUT 220 nF VBAT charge pump 100nF VDDA 100nF GNDA VDDD 100nF GNDD supply VDDAREF 100nF GNDAREF VCC RESN 10K LOAD 0 GPIO EN GPIO FAULTN CLKOUT LOAD1 RESN LOAD 2 CLK HSLS0 HSLS1 control HSLS2 µC e.g. TC1766 TM TMO1 4.7nF to 10nF TM02 VIO CSB SPI SPI SO SI GNDP0 GNDP1 GNDP2 VSS SCK Application Circuit HS.vsd Figure 38 Application Diagram - High side configuration Note: This is a very simplified example of an application circuit. The function must be verified in the real application. 13.1 • • Further Application Information Please contact us for information regarding the pin FMEA For further information you may contact http://www.infineon.com/ Data Sheet - 66 Rev 1.0, 2013-03-21 TLE82453SA Package Outlines 14 Package Outlines Figure 39 PG-DSO-36 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet - 67 Dimensions in mm Rev 1.0, 2013-03-21 Edition 2013-03-21 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE82453SA Revision History 15 Revision History Revision Date Changes 0.7 2011-06-07 Section 12.3 Removed the OCDT bit from the configuration register Section 12.10 Added the PWM register to the SPI Register description Section 12.7 Removed the on-time filed from the setpoint register Section 12.7 Moved the AL bit from the Integrator Limit register to the Setpoint register Section 12.11 Removed Integrator Hysteresis field from Integrator hysteresis register and added the integrator threshold field Section 12.12 Changed location of the AZ start bit and expanded the AZ value field to 13 bits Section 5.1 Corrected Figure 3 Section 12.11 Added comment in Integrator Threshold & Open On register than the open on threshold must be written with a non zero value to enable the open on feature Section 6.11 changed maximum limit of Vddx undervoltage from 4.2 to 4.3V Section 9.5 changed maximum overvoltage VBAT limit from 45V to 44V Section 6.11 Added Charge pump overvoltage clamp parameter Section 9.4: added comment that CPUV may be set before VBAT OV during a VBAT transient depending on the rise time. Section 6.11 Changed charge pump warning threshold maximum limit to 8.5V Section 12.12 Changed auto-limit values from 20 to 40 Section 6.11, changed wake up time from 10ms to 15 ms Section 4.2 Revised maximum PWM frequency from 10 KHz to 4 KHz Section 8.9 Added PWM period range and resolution parameters Section 8.5 Revised controller description 0.8 July 22, 2011 Section 1 Features: updated accuracy overview Section 1 Description: added comment to maximum average current value Section 4, Table 1: added footnote to output current rating Section 4.2 Table 2: revised maximum supply voltage Section 4.2 Table 2: added CLK pin frequency parameter Section 4.2 Table 2: added minimum load pin frequency of 100 Hz Section 6.3: added note about connection of LSUP pins for unused channels Section 6.10 Figure 4: revised table Section 8.2: deleted comment that a single temperature module calibration is needed to meet the accuracy specifications Section 8.3: added comment to end of paragraph Section 8.5: corrected autolimit values and number of PWM cycles which trigger a Regulator Error Section 8.7: corrected formulas Section 8.8: Added calibration mode formula Section 8.9 updated PWM period range, dither amplitude range, and dither period range Data Sheet - 69 Rev 1.0, 2013-03-21 TLE82453SA Revision History Revision Date Changes Section 9, corrected FAULTN signal of Figure 11 Section 9.5 Table 8, updated over current detection filter time Section 10.8. Added description of the RE fault bit Section 12.2. Corrected the IC Version # Section 12.4. Corrected number of PWM cycles to set RE bit Section 12.7. Corrected autolimit values Section 12.8. Added note about maximum value of the product of the number of steps and the step size Section 12.9. Added notes on effective values of integrator limits Section 12.10. Updated the formula and reset value of the KI parameter Section 12.13. Corrected current feedback formulas and lsb weighting 0.9 July 27, 2012 Section 5.1. Removed comment that the state of the EN pin can be monitored by reading the Diagnosis register Section 5.1. Added comment that the EN bits in the SetPoint register are cleared when the EN pin is low Section 5.2. Removed maximum value for Vin_l and minimum value for Vin-high Section 5.2 Added hysteresis parameter Section 5.2. Adjusted limits of Output tri-state leakage current Section 6.7. Changed the name of the reset timer to Tpor Section 6.10. Corrected footnotes to the Power Supply Modes table Section 6.11. Added section regarding initialization Section 7.5. Added LSUP current in sleep mode parameter Section 8.8 Added comment that the enter calibration mode, setpoint must be set to 0 and the EN bit (in the setpoint register) must be set to 1. And added comment that the Current Mode Feedback register contents are only valid if the PWM period is > 0 Section 8.9. Removed long term drift parameter Section 9.5. Changed minimum limit of the over current detection filter time from 30 to 20 Fsys cycles Section 10.7. Added comment that the CRC bit is cleared after reading the diagnosis register Section 10.8. Added comment that the RE bits are cleared after reading the diagnosis register Section 10.9. Changed the name of the open load - switch bypass delay time (on state) parameter. Section 10.9. Updated the limits of the Off-state pull up and pull down currents Section 10.9. Updated the off-state LOADx threshold voltage Section 11.2. Added comment that the SPI parameters are using 20%/80% thresholds. Section 12.10. reduced field width of the KI parameter from 4 bits to 3 bits Section 13. Added comments to the application circuits that the output capacitors should be 4.7nF to 10nF. 1.0 Data Sheet - March 6 2013 Section 3.2 Added chip damaged if connection lost Pins 1,5,9,25,26,28 and tab 70 Rev 1.0, 2013-03-21 TLE82453SA Revision History Revision Date Changes Section 4.1.2 Vlsup 45V max added. Section 4.1.2 Added Vlsup must not exceed Vbat +0.3V Section 5.1 RESN resistor changed to current source Section 6.12.1 IVbat changed from 20ma to 10ma. Section 6.11.2 IVbat_slp changed from 10ua to 8ua Section 6.11.3 IVddd changed from 50ma to 20ma Section 6.11.4 IVdda changed from 5ma to 4ma Section 6.11.7-9 150mv hysteresis note added. Section 6.11 charge pump capacitor values added. Section 7.4.1 Ilsup_lkg 200us changed to 150ua Section 7.4.2 Ilsup_lkgslp 50ua max added. Section 7.4.5 Iload_lkg 200ua reduced to 150ua. Section 7.4.51 ILOAD_lkg sleep mode added -80ua and +80ua. Section 7.4.9 Sense resistor max380mohm added. Section 8.2 Auto zero changed from during to after power up. Section 8.3 Additional dither operation detials added. Section 8.4 Additional sense resistor protection details added. Section 8.5 Additional current controller details added. Section 8.9 Calibration mode current limit added. Section 8.9.4,8.9.6 changed from1.2A to 1.5A Section 9.5.1 6A max added. Section 10.4 OVC confirmation test added, OVC detection range added. Section 10.5 OLSB confirmation test added. Section 12.2 B12&B13 versions added. Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of Data Sheet - 71 Rev 1.0, 2013-03-21 TLE82453SA Revision History MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Data Sheet - 72 Rev 1.0, 2013-03-21