Data Sheet, Rev. 1.0, April 2010
TLE84106EL
Hex-Half-Bridge Driver IC
Automotive Power
TLE84106EL
Hex Half Bridge IC
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.2
4.3
4.4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.4.1
5.2.4.2
5.2.5
5.3
5.4
5.4.1
5.4.2
5.4.3
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit of Output to Supply or Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross-Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
15
15
16
16
16
17
18
18
18
19
6
6.1
6.2
6.3
6.3.1
6.3.2
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control - Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis - Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
23
24
24
25
7
7.1
7.2
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
2
Rev. 1.0, 2010-04-27
Hex-Half-Bridge Driver IC
1
TLE84106EL
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
6 Half Bridge Power Outputs
3.3V / 5V compatible inputs with hysteresis
Independently Diagnosable Outputs
16-bit Standard SPI interface with daisy chain capability for control and
diagnosis
Open load diagnostics in ON-state for all outputs
All outputs with overload and short circuit protection and diagnosis
Overtemperature prewarning and protection
Over- and Undervoltage lockout
Cross-current protection
Thermally enhanced exposed pad package
Green Product (RoHS compliant)
AEC Qualified
PG-SSOP-24-4
Description
The TLE84106EL is a protected Hex-Half-Bridge-Driver designed especially for automotive motion control applications
such as Heating, Ventilation and Air Conditioning (HVAC) flap DC motor control. It is part of the MonolythIC family in
Infineon’s Smart Power Technology SPT® which combines bipolar and CMOS control circuitry with DMOS power
devices.
The 6 half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation modes
forward (cw), reverse (ccw), brake and high impedance are controlled from a 16-bit SPI interface. The diagnosis features
such as short circuit, open load, power supply failure and overtemperature in combination with its low quiescent current
makes this device attractive for automotive applications. The extremely small fine pitch exposed pad PG-SSOP-24-4
package in a SO -14 body provides good thermal performance and reduces PCB-board space and costs.
Table 1
Product Summary
Operating Voltage
VS
7 ... 18 V
Logic Supply Voltage
VDD
3.0 ... 5.5 V
Maximum Supply Voltage for Load Dump
Protection
VS(LD)
40 V
Minimum Overcurrent Threshold
ISD1-6_MOTOR
0.8 A
Maximum On-State Path Resistance at Tj = 150°C RDSON(total)_HSx+LSy
2+2Ω
Typical Quiescent Current at Tj = 85°C
IS (off))
1 µA
Maximum SPI Access Frequency
fSCLK
5 MHz
Type
Package
Marking
TLE84106EL
PG-SSOP-24-4
TLE84106EL
Data Sheet
3
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Diagram
2
Block Diagram
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Figure 1
Data Sheet
Block Diagram
4
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Diagram
96
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Figure 2
Data Sheet
Terms
5
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
GND
OUT 1
OUT 5
NC
SDI
VDD
SDO
INH
NC
OUT 6
OUT 4
GND
Figure 3
Data Sheet
1
2
3
4
5
Exposed
6
Die
7
Pad
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
OUT 2
NC
VS2
SCLK
CSN
TEST
TEST
VS1
NC
OUT 3
GND
Pin Configuration
6
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
GND
Ground
2
OUT 1
Power Half-Bridge 1
3
OUT 5
Power Half-Bridge 5
4
NC
Not Connected. This pin can either be left open or connected to ground.
5
SDI
Serial-Data-Input
6
VDD
Logic Supply Voltage
7
SDO
Serial-Data-Output
8
INH
Inhibit input with internal pull-down; Place device in standby mode by pulling the INH
line LOW
9
NC
Not Connected. This pin can either be left open or connected to ground.
10
OUT 6
Power Half-Bridge 6
11
OUT 4
Power Half-Bridge 4
12
GND
Ground
13
GND
Ground
14
OUT 3
Power Half-Bridge 3
15
NC
Not Connected. This pin can either be left open or connected to ground.
16
VS1
Power Supply Voltage for Group 1 supplying current to OUT 3, OUT 4 and OUT 6.
17
TEST
Test input with internal pull down. Used for production test only. This pin should be left
open or connected to ground on board.
18
TEST
Test input with internal pull down. Used for production test only. This pin should be left
open or connected to ground on board.
19
CSN
Chip-Select-Not-Input
20
SCLK
Serial Clock Input
21
VS2
Power Supply Voltage for Group 2 supplying current to OUT 1, OUT 2 and OUT 5.
22
NC
Not Connected. This pin can either be left open or connected to ground.
23
OUT 2
Power Half-Bridge 2
24
GND
Ground
EDP
-
Exposed Die Pad; For cooling purposes only; Do not use as electrical ground.1)
1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The exposed
die pad is not connected to any active part of the IC. When connecting onto PCB, it can either be left floating or connected
to GND for the best EMC and thermal performance.
Note: All GND pins must be externally connected together to a common GND potential. All VS pins must be
externally connected together to a common Vs potential. See Figure 17 for more Application Information.
Data Sheet
7
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
VS = VS1 = VS2
0 V < VS < 40 V
0 V < VS < 40 V
0 V < VDD < 5.5V
0 V < VS < 40 V
0 V < VDD < 5.5V
Min.
Max.
-0.3
40
V
Voltages
4.1.1
Supply voltage
4.1.2
Logic supply voltage
VS
VDD
-0.3
5.5
V
4.1.3
Logic input voltages
(SDI, SCLK, CSN; INH)
VSDI, VSCLK, -0.3
VCSN, VINH
5.5
V
4.1.4
Logic output voltage
(SDO)
VSDO
-0.3
5.5
V
Currents
4.1.5
Continuous Supply Current for VS1 IS1
0
1.80
A
–
4.1.6
Continuous Supply Current for VS2 IS2
0
1.80
A
–
-40
150
°C
–
-50
150
°C
–
Temperatures
4.1.7
Junction temperature
4.1.8
Storage temperature
Tj
Tstg
ESD Susceptibility
4.1.9
ESD capability of OUTx and VS pin VESD
-4
4
kV
2)
4.1.10
ESD capability of other pins
VESD
-2
2
kV
2)
1) Not subject to production test, specified by design.
2) Human Body Model according to ANSI EOS\ESD S5.1 standard (eqv. to MIL STD 883D and JEDEC JESD22-A114)
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
8
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4.2
Pos.
Functional Range
Parameter
Symbol
VS(nor)
4.2.1
Supply voltage range for
normal operation
4.2.2
Extended Supply Voltage Range VS(ext)
for Operation
4.2.3
Supply Voltage Slew Rate
|dVS /dt|
Limit Values
Unit
Conditions
Min.
Max.
7
18
V
–
VUV OFF
VOV OFF
V
Limit Values
Deviations Possible;
After VS rising above
–
10
V/µs
VUV ON
VS increasing and
decreasing 1)
4.2.4
Logic supply voltage range for
normal operation
VDD
4.2.5
Logic input voltages
(DI, CLK, CSN; INH)
4.2.6
Junction temperature
3.0
5.5
V
–
VDI, VCLK, -0.3
VCSN, VINH
5.5
V
–
Tj
150
°C
–
-40
1) Not subject to production test, specified by design.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
9
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4.3
Pos.
Thermal Resistance
Parameter
Symbol
Limit Values
Min.
Unit
Conditions
Typ.
Max.
RthjC_cold
–
RthjC_hot
–
RthjA_cold_min –
4
–
K/W
1)
5
–
K/W
1)
124
–
K/W
1) 2)
103
–
K/W
1) 2)
4.3.1
Junction to Case, Ta = -40°C
4.3.2
Junction to Case, Ta = 85°C
4.3.3
Junction to Ambient, Ta = -40°C
(1s0p, minimal footprint)
4.3.4
Junction to Ambient, Ta = 85°C
(1s0p, minimal footprint)
RthjA_hot_min
4.3.5
Junction to Ambient, Ta = -40°C
(1s0p, 300mm2 Cu)
RthjA_cold_300 –
75
–
K/W
1) 3)
4.3.6
Junction to Ambient, Ta = 85°C
(1s0p, 300mm2 Cu)
RthjA_hot_300
–
60
–
K/W
1) 3)
4.3.7
Junction to Ambient, Ta = -40°C
(1s0p, 600mm2 Cu)
RthjA_cold_600 –
67
–
K/W
1) 4)
4.3.8
Junction to Ambient, Ta = 85°C
(1s0p, 600mm2 Cu)
RthjA_hot_600
–
54
–
K/W
1) 4)
4.3.9
Junction to Ambient, Ta = -40°C
(2s2p)
RthjA_cold_2s2p –
38
–
K/W
1) 5)
4.3.10
Junction to Ambient, Ta = 85°C
(2s2p)
RthjA_hot_2s2p –
31
–
K/W
1) 5)
–
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 35 µm thickness.
Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating a total of
1.08W (0.18W each).
3) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional cooling of 300 mm2 copper area and 35
µm thickness. Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating
a total of 1.08W (0.18W each).
4) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional cooling of 600 mm2 copper area and 35
µm thickness. Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating
a total of 1.08W (0.18W each).
5) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (4 x 35µm Cu). Ta = -40°C,
Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating a total of 1.08W (0.18W
each).
Data Sheet
10
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4.4
Electrical Characteristics
Electrical Characteristics
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
VS = 13.5 V;
VDD= 0 V
Tj = 85°C
Tj = 85°C
Tj = 85°C
Current Consumption, INH = GND
4.4.1
Supply Quiescent current
ISQ
–
1
2.5
µA
4.4.2
Logic supply quiescent current
IDD_Q
–
0.5
1
µA
4.4.3
Total quiescent current
ISQ + IDD_Q
–
2
4
µA
Current Consumption, INH = HIGH
4.4.4
Supply current
IS
–
4.5
10
mA
Power drivers and
power stages are off
4.4.5
Logic supply current
–
1.5
3
mA
SPI not active
4.4.6
Logic supply current
IDD
IDD_RUN
–
5
–
mA
VDD = 3.0V;
SPI 5MHz
4.4.7
Total supply current
IS + IDD_RUN –
9.5
–
mA
–
VUV ON
VUV OFF
VUV HY
VOV OFF
VOV ON
VOV HY
VDD POR
VDD POffR
–
–
5.2
V
4
–
5.0
V
–
0.25
–
V
21
–
25
V
20
–
24
V
–
1
–
V
2.60
2.80
3.00
V
2.50
2.70
2.90
V
VS increasing
VS decreasing
VUV ON - VUV OFF
VS increasing;
VS decreasing;
VOV OFF - VOV ON;
VDD increasing
VDD decreasing
RDSON(1-6)
–
0.8
–
Ω
–
1.4
2
Ω
Over- and Undervoltage Lockout
4.4.8
UV Switch ON voltage
4.4.9
UV Switch OFF voltage
4.4.10
UV ON/OFF hysteresis
4.4.11
OV Switch OFF voltage
4.4.12
OV Switch ON voltage
4.4.13
OV ON/OFF hysteresis
4.4.14
VDD Power-On-Reset
4.4.15
VDD Power-Off-Reset
Static Drain-source ON-Resistance
4.4.16
High- and Low-side switch
IOUT (1-6)= ±0.5 A;
Tj = 25 °C
IOUT (1-6)= ±0.5 A;
Tj = 150 °C
Output Protection and Diagnosis
High-Side Switches
4.4.17
HS Overcurrent Shutdown
Threshold
ISD_HS
-1.6
-1.15
-0.8
A
HS Switch;
VS=13.5V; See
Figure 7
4.4.18
HS Short Circuit Current Limit
-2.0
-1.5
-1.0
A
1)
4.4.19
HS_Shutdown Delay Time
ISC_HS
tdSD
10
25
50
µs
HS Switch;
VS=13.5V; See
Figure 7
Data Sheet
11
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
Electrical Characteristics (cont’d)
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
Low-Side Switches
4.4.20
LS Overcurrent Shutdown
Threshold
ISD_LS
0.8
1.15
1.6
A
LS Switch;
VS=13.5V; See
Figure 7
4.4.21
LS Short Circuit Current Limit
1.0
1.5
2.0
A
1)
4.4.22
LS_Shutdown Delay Time
ISC_LS
tdSD
10
25
50
µs
LS Switch;
VS=13.5V; See
Figure 7
4.4.23
Open Load Detection Current
IOLD
tdOLD
3
8
15
mA
LS Switch;
200
350
600
µs
VS=13.5V; See
tdONH
tdOFFH
tdONL
tdOFFL
tDHL
tDLH
tONH
tOFFH
tOFFL
tONL
–
7.5
12
µs
VS=13.5V, resistive
–
3
6
µs
–
6.5
12
µs
–
2
5
µs
Load = 100Ω, See
Figure 9 and
Figure 10
1.5
–
–
µs
2.5
–
–
µs
–
4
–
µs
–
2
–
µs
–
1
–
µs
–
1
–
µs
VINHH
VINHL
VINHHY
RPD_INH
70
–
–
% VDD –
–
–
30
% VDD –
50
200
500
mV
–
–
120
–
kΩ
–
–
–
100
µs
1)
100
–
–
µs
1)
70
–
–
% VDD –
–
–
30
% VDD –
50
200
500
mV
–
–
140
–
kΩ
–
–
120
–
kΩ
–
4.4.24
Open Load Delay Time
Figure 8
Output Switching Times
4.4.25
High-Side ON delay-time
4.4.26
High-Side OFF delay-time
4.4.27
Low-Side ON delay-time
4.4.28
Low-Side OFF delay-time
4.4.29
Dead Time H to L
4.4.30
Dead Time L to H
4.4.31
High-Side RiseTime
4.4.32
High-Side Fall Time
4.4.33
Low-Side RiseTime
4.4.34
Low-Side Fall Time
Input Interface, Logic Inputs INH
4.4.35
High-input voltage
4.4.36
Low-input voltage
4.4.37
Hysteresis of input voltage
4.4.38 Pull down resistor
SPI INTERFACE
Delay Time from Sleep mode to first Data in
4.4.39
4.4.40
tset
Time between two consecutive SRR tSRR
Setup time
commands
Input Interface, Logic Inputs SDI, SCLK, CSN
4.4.41
4.4.42
4.4.43
4.4.44
4.4.45
VIH
Low-input voltage
VIL
Hysteresis of input voltage
VIHY
Pull up resistor at pin CSN
RPU_CSN
Pull down resistor at pin SDI, SCLK RPD_SDI,
RPD_SCLK
High-input voltage
Data Sheet
12
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
Electrical Characteristics (cont’d)
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
4.4.46
Parameter
Input capacitance at pin CSN, SDI
or SCLK
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
CI
–
10
15
pF
0V < VDD < 5.25V 1)
VSDOH
VDD -
VDD -
–
V
ISDOH = -1 mA
1.0
0.7
–
0.2
0.4
V
-10
–
10
µA
ISDOL = 1.6 mA
VCSN = VDD
0V < VSDO < VDD
fCLK
tpCLK
–
–
5
MHz
1)
500
200
–
–
–
–
ns
ns
VDD = 5.25V
VDD = 3.0V 1)
tSCLKH
tSCLKL
tlag
tSDI_setup
tSDI_hold
tlead
tCSNH
trIN
85
–
–
ns
1)
85
–
–
ns
1)
85
–
–
ns
1)
50
–
–
ns
1)
50
–
–
ns
1)
100
–
–
ns
1)
500
–
–
ns
1) 2)
–
–
50
ns
1)
tfIN
–
–
50
ns
1)
–
10
25
ns
Cload = 40pF 1)
–
10
25
ns
Cload = 40pF 1)
–
20
50
ns
VSDO < 0.2VDD
VSDO > 0.7VDD
Input Interface, Logic Outputs SDO
4.4.47
High-output voltage
4.4.48
Low-output voltage
4.4.49
Tri-state Leakage Current
VSDOL
ISDOLK
Data Input Timing. See Figure 12 and Figure 15
4.4.50
SCLK Frequency
4.4.51
SCLK Period
4.4.52
SCLK High Time
4.4.53
SCLK Low Time
4.4.54
SCLK Setup Time
4.4.55
SDI Setup Time
4.4.56
SDI Hold Time
4.4.57
CSN Setup Time
4.4.58
CSN High Time
4.4.59
Input Signal Rise Time at pin SDI,
SCLK, CSN
4.4.60
Input Signal Fall Time at pin SDI,
SCLK, CSN
Data Output Timing. See Figure 14 and Figure 15
4.4.61
SDO Rise Time
4.4.62
SDO Fall Time
4.4.63
SDO Valid Time
trSDO
tfSDO
tVASDO
Cload = 40pF 1)
4.4.64
SDO Enable Time after CSN falling tENSDO
edge
–
–
50
ns
Low Impedance 1)
4.4.65
SDO Disable Time after CSN rising tDISSDO
edge
–
–
50
ns
High Impedance 1)
4.4.66
Duty cycle of incoming clock at
SCLK
40
–
60
%
1)
Data Sheet
dutySCLK
13
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
Electrical Characteristics (cont’d)
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
See Figure 6 1)
Thermal Prewarning & Shutdown
4.4.67
Thermal warning junction
temperature
TjW_enter
120
140
170
°C
4.4.68
Thermal warning junction
temperature - switch off
TjW_exit
90
–
140
°C
4.4.69
Temperature warning hysteresis
∆TjW
–
30
–
K
4.4.70
Thermal shutdown junction
temperature
TjSD
150
175
200
°C
4.4.71
Thermal switch-on junction
temperature
TjSO
130
–
180
°C
4.4.72
Temperature shutdown hysteresis
∆TjSD
–
20
–
K
4.4.73
Ratio of SD to W temperature
TjSD / TjW
1.05
1.20
–
–
1) Not subject to production test, specified by design
2) CSN High Time : This is the minimum time the user must wait between SPI commands
Data Sheet
14
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5
Block Description
5.1
General
5.2
Power Supply
5.2.1
General
The TLE84106EL has two power supply inputs: The half bridge outputs are connected to VS supply, which is
connected to the 12V automotive supply rail. The internal logic part is supplied by a separate voltage VDD = 5 V.
VS and VDD supplies are separated so that information stored in the logic block remains intact in the event of
voltage drop outs or disturbances on VS. The system can therefore continue to operate once VS has recovered,
without having to resend commands to the device.
A rising edge on VDD triggers an internal Power-On Reset (POR) to initialize the IC at power-on. All data stored
internally is deleted, and the outputs are switched to high-impedance status (tristate). A 10µF electrolytic and
100nF ceramic capacitor are recommended to be placed as close as possible to the VS supply pin of the device
for improved EMC performance in the high and low frequency band.
5.2.2
Sleep Mode
The TLE84106EL enters low power mode (or sleep mode) by setting the INH input to low. The INH input has an
internal pull-down resistor. In sleep-mode, all output transistors are turned off and the SPI register banks are reset.
5.2.3
Reverse Polarity Protection
The TLE84106EL requires an external reverse polarity protection. During reverse polarity, the freewheeling diodes
across the half bridge output will begin to conduct, causing an undesired current flow (IRB) from ground potential
to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection diode is
recommended (see Figure 4).
D
*1'
96
E
'53
&6
+6[
&6
'=6
+6[
287[
287[
/6[
/6[
7/([(/
7/([(/
,5%
96
Figure 4
Reverse Polarity Protection
5.2.4
Power Supply Monitoring
*1'
The power supply rails VS and VDD are monitored for over- and undervoltage. See Figure 5.
Data Sheet
15
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5.2.4.1
VS Undervoltage
If the supply voltage VS drops below the switch off voltage VUVOFF, all output transistors are switched off but logic
information remains intact and uncorrupted. The “undervoltage” (Power Supply Fail, PSF) error bit is flagged and
can be read out via SPI. Once VS rises again and reaches the threshold switch on voltage VUVON, the power stages
are restarted and the PSF error bit is reset.
5.2.4.2
VS Overvoltage
If the supply voltage VS rises above the switch off voltage VOVOFF, all output transistors are switched off and the
“overvoltage” (PSF) error bit is set. The error is not latched, i.e. if VS falls again and reaches the switch on voltage
VOVON, the power stages are restarted and the Error Flags are reset.
VS
VOVOFF
VOVH Y
VOVON
VU VH Y
VU VON
VU VOFF
t
VOU Tx
ON
t
High Z
PSF error bit
Under -voltage output &
error flag behaviour
Over-voltage output &
error flag behaviour
High
Low
t
Figure 5
Output behavior during Over- and Undervoltage VS condition
5.2.5
Reset Behavior
The following reset triggers have been implemented in the TLE84106EL:-
VDD Undervoltage Reset:
The SPI Interface shall not function if VDD is below the undervoltage threshold, VDD POffR. The digital Block will be
initialized. The output stages are switched off to High-Z. The undervoltage reset and SRR is released once VDD
voltage levels are above the undervoltage threshold, VDD POR.
Reset on INH pin:
If the INH pin level is low, the device shall enter reset and the current consumption is reduced to ISQ + IDD_Q.
Data Sheet
16
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5.3
Temperature Monitoring
Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the
measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach the
warning temperature, the temperature warning bit, TW is set to HIGH. This bit is not latched (i.e. if the temperature
falls below the warning threshold (with hysteresis), the TW bit is reset to LOW again).
If one or more temperature sensors reach the shut-down temperature threshold, all outputs are shut down and
latched (i.e. the output stages remain off until an SRR command is sent or a power-on reset is performed). See
Figure 6.
Tj
TjSD
∆ΤS D
Tj SO
TjW_ent er
∆ΤJW
TjW _exit
t
V OUTx
Output is switched off if
TjSD is reached and can
only be reset via SRR
ON
High Z
no error
t
TW error bit
High
Error flag is reset
automatically
Low
t
no error
Figure 6
Data Sheet
Overtemperature Behavior
17
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5.4
Protection and Diagnosis
This device features embedded protective functions which are designed to prevent IC destruction under fault
conditions described in the following sections. Fault conditions are treated as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
5.4.1
Short Circuit of Output to Supply or Ground
The high-side switches are protected against short to ground where as the low-side switches are protected against
short to supply.
If a switch is turned on and the current rises above the overcurrent shutdown threshold, ISD for longer than the
shutdown delay time tdSD, the output transistor is turned off and the corresponding diagnosis bit, OC, is set. During
this delay time, the current is limited to ISC as shown in Figure 7. The output stage remains off and the error bit
remains set until a status register reset is sent to the SPI or a power-on reset is performed.
..
,+6B/6
9V
,6&
VKRUWWR6XSSO\
,6'
287[
WG6'
VKRUWWR*1'
W
6KRUWFRQGLWLRQRQ+LJK±RU/RZ6LGH6ZLWFK
Figure 7
High-Side and Low-Side Switch - Short Circuit and Overcurrent Protection
5.4.2
Open Load
Open-load detection in ON-state is implemented in the Low-Side switches of the bridge outputs: If the current
through the low side transistor is lower than the reference current IOLD in ON-state for longer than the open-load
detection delay time tdOLD, the corresponding open-load, OL diagnosis bit is set. The output transistor, however,
remains ON. The open load error bit is latched and can be reset by the SPI status register reset or by a power-on
reset.
As an example, if a motor is connected between outputs OUT 1 and OUT 2 with a broken wire as shown in
Figure 8, the resulting diagnostic information is shown in Table 2.
Open Load Detection Shutdown (OL SD EN) Bit via the Control Register can be activated or deactivated as
required. If the OL SD EN bit is set and an open load on the Low-Side Switch is detected, the respective output is
disabled. The error remains latched and output is off until an SRR or power on reset is performed. This has the
added advantage of independently diagnosing and isolating error flags to the corresponding failed output.
Data Sheet
18
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
OUT 1
Open
Load
M
OUT 2
Figure 8
Open Load Example
Table 2
Open Load Diagnosis Example
Control
LS1
ON
HS1
ON
LS2
ON
HS2
ON
Diagnostic Information
Motor Rotation
Motor
Connected
Motor
Open Load Detection
Disconnected (OPLD) Error Flag
LS1
OpL
LS1
OpL
LS2
OpL
LS2
OpL
0
0
0
0
motor off
0
0
0
0
de-activated
1
0
0
1
clock-wise
0
0
1
0
activated
0
1
1
0
counter clock-wise 0
0
0
1
activated
0
1
0
1
brake high
0
0
0
0
de-activated
1
0
1
0
brake low
1
1
1
1
activated
5.4.3
Cross-Current
In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously “ON”
to avoid cross currents. This is realized by integrating delays in the driver stage of the power outputs, intended to
create a dead-time between switching off one Power Transistor and switching on of the other Power Transistor of
the same half-bridge. To ensure that there is no overlap of the switching slopes that would lead to a cross current,
the dead-times, tDHL and tDLH are specified.
In the event a cross-current has occurred, the device shall turn off both switches and the Overcurrent bit is set
High.
Data Sheet
19
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
&61
21!2))
287[
+LJK6LGHRII
GHOD\WLPH
W2))+
WG2))+
2))
W'+/
2))
2))!21
/RZ6LGHRQ
GHOD\WLPH
W21/
287[
WG21/
Figure 9
Timing Bridge Outputs High to Low
&61
W2))/
287[
2))
/RZ6LGHRII
GHOD\WLPH
WG2))/
21!2))
W'/+
W21+
2))!21
287[
+LJK6LGHRQ
GHOD\WLPH
WG21+
2))
Figure 10
Data Sheet
Timing Bridge Outputs Low to High
20
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6
SPI
6.1
General
The SPI is used for bidirectional communication with a control unit. The TLE84106EL acts as SPI-slave and the
control unit acts as SPI-master. The 16-bit control word is read via the SDI serial data input. The status word
appears synchronously at the SDO serial data output. The communication is synchronized by the serial clock input
SCLK.
Standard data transfer timing is shown in Figure 11. The clock polarity is data valid on falling edge. SCLK must
be low during CSN transition. The transfer is MSB first.
The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L). Then the
data is clocked through the shift register. The transmission ends when the CSN input changes from L to H and the
word which has been read into the shift register becomes the control word. The SDO output switches then to
tristate status, thereby releasing the SDO bus circuit for other uses. The SPI allows to parallel multiple SPI devices
by using multiple CSN lines. The SPI can also be used with other SPI-devices in a daisy-chain configuration.
The control word transmitted from the master to the TLE84106EL is executed at the end of the SPI transmission
( CSN L -> H ) and remains valid until a different control word is transmitted or a power on reset occurs. At the
beginning of the SPI transmission ( CSN H -> L ), the diagnostic data currently valid are latched into the SPI and
transferred to the master.
Data integrity is maintained by polling multiples of 8 data bits to ensure that a valid command has been received.
&61+LJKWR/RZ ULVLQJHGJHRI
6&/. 6'2LVHQDEOHG6WDWXV
LQIRUPDWLRQLVWUDQVIHUHGWR
2XWSXW6KLIW5HJLVWHU
&61/RZWR+LJK 'DWDIURP
6KLIW5HJLVWHULVWUDQVIHUHGWR
2XWSXW'ULYHU/RJLF
&61
6&/.
WLPH
FXUUHQWGDWD
06%
6',
/6%
QHZGDWD
6', 'DWDZLOOEHDFFHSWHGRQWKHIDOOLQJHGJHRI&/.6LJQDO
SUHYLRXVVWDWXV
6'2
FXUUHQWVWDWXV
6'2 6WDWHZLOOFKDQJHRQWKHULVLQJHGJHRI&/.6LJQDO
Figure 11
Data Sheet
SPI Data Transfer Protocol
21
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
W&61+
&61
WOHDG
WODJ
6&/.
WODJ
Figure 12
W6&/.+
WOHDG
W6&/./
SPI SCLK and CSN
tSET
INH
SDI
Figure 13
INH and SDI
W(16'2
W',66'2
&61
6'2
Figure 14
Data Sheet
SPI SDO and CSN
22
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6',
W6',BVHWXS
W6',BKROG
6&/.
W9$6'2
6'2
Figure 15
SPI SDI, SDO and SCLK
6.2
Status Register Reset
The SPI is using a standard shift-register concept with daisy-chain capability. Any data transmitted to the SPI will
be available to the internal logic part at the end of the SPI transmission (CSN L -> H). To read a specific register,
the address of the register is sent by the master to the SPI in a first SPI frame. The data that corresponds to this
address is transmitted by the SDO during the following (second) SPI frame to the master. The default address for
Status Register transmission after Power-ON Reset is 0.
The Status-Register-Reset command-bit is executed after the next SPI transmission. The two bits, Address
Register and SRR act as command to read and reset (or not reset) the addressed Status-Register. The request
and response behaviour of the SPI is further illustrated in Figure 16 below.
CSN
SCLK
SDI
SRR 1
Request 1
SRR 2
Request 2
SRR 3
Request 3
SDO
Response 0
Figure 16
Data Sheet
Response 1
Response 2
Status Register Reset
23
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6.3
SPI Bit Definitions
6.3.1
Control - Word
Control Register Overview
15
14
SRR
0
Bit
13
12
OL_SD ACT_
_EN
HB6
11
10
9
8
7
ACT_
HB5
ACT_
HB4
ACT_
HB3
ACT_
HB2
6
5
4
3
2
1
ACT_ CONF_ CONF_ CONF_ CONF_ CONF_ CONF_
HB1
HB6
HB5
HB4
HB3
HB2
HB1
0
0
Control Register Control Register - DESCRIPTION
- LOCATE
Diagnosis Control
15
SRR
Status Register Reset (SRR).
(ALL CHANNELS) If set to high, the errors bits of the coresponding status register are reset on the
rising edge of CSN if sent to the uC. Low indicates no reset.
14
0
13
OL SD EN
Open Load Detection Shutdown Enable (OL SD EN) allows the affected output
(ALL CHANNELS) stage to be switched off if a true open load or underload condition has been
detected. This feature can be activated or deactivated by bit 13.
Set to 0 to select HB 1 to 6
Activate Half-Bridge X
12
ACT_HB 6
H => Half Bridge 6 is active
L => Half Bridge 6 is in Hi-Z
11
ACT_HB 5
H => Half Bridge 5 is active
L => Half Bridge 5 is in Hi-Z
10
ACT_HB 4
H => Half Bridge 4 is active
L => Half Bridge 4 is in Hi-Z
9
ACT_HB 3
H => Half Bridge 3 is active
L => Half Bridge 3 is in Hi-Z
8
ACT_HB 2
H => Half Bridge 2 is active
L => Half Bridge 2 is in Hi-Z
7
ACT_HB 1
H => Half Bridge 1 is active
L => Half Bridge 1 is in Hi-Z
Configure Half-Bridge X
6
CONF_HB 6
H => HSD6 = ON & LSD6 = OFF
L => HSD6 = OFF & LSD6 = ON
5
CONF_HB 5
H => HSD5 = ON & LSD5 = OFF
L => HSD5 = OFF & LSD5 = ON
4
CONF_HB 4
H => HSD4 = ON & LSD4 = OFF
L => HSD4 = OFF & LSD4 =ON
3
CONF_HB 3
H => HSD3 = ON & LSD3 = OFF
L => HSD3 = OFF & LSD3 = ON
2
CONF_HB 2
H => HSD2 = ON & LSD2 = OFF
L => HSD2 = OFF & LSD2 = ON
1
CONF_HB 1
H => HSD1 = ON & LSD1 = OFF
L => HSD1 = OFF & LSD1 = ON
0
Least Significant Bit (LSB) is set to Low
0
Data Sheet
24
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6.3.2
Diagnosis - Word
Diagnosis Register Overview
15
14
13
OC
PSF
OL
Table 4
Bit
12
11
10
9
8
7
6
5
4
3
2
1
SACT_ SACT_ SACT_ SACT_ SACT_ SACT_ SCONF SCONF SCONF SCONF SCONF SCONF
HB6
HB5
HB4
HB3
HB2
HB1
_HB6 _HB5 _HB4 _HB3 _HB2 _HB1
0
TW
Output (Status) Data Register
Status Register Status Register - DESCRIPTION
- LOCATE
15
OC
(ALL
CHANNELS)
Overcurrent Error is set if any one of the Half-Bridges has an overload, short circuit
or cross current; The error is latched and the corresponding output is switched off;
Bit 15 error can only be reset via SRR or power-on reset.
14
PSF
(ALL
CHANNELS)
Power Supply Failure;
Bit 14 is set if VS has an overvoltage or undervoltage condition; All outputs are switched
OFF. Bit 14 is automatically reset if VS returns to its normal operating range.
13
OL
(ALL
CHANNELS)
Open Load Error is set if any one of the Half-Bridges has a true open load or
underload error condition; The error is latched. The corresponding output is
switched off if Bit 13, OL SD EN of the Control Register is activated or high. Bit 13
error can only be reset via SRR or power-on reset.
Activated Driver Status of Half-Bridge X
12
SACT_HB 6
H => Half Bridge 6 is active
L => Half Bridge 6 is in Hi-Z
11
SACT_HB 5
H => Half Bridge 5 is active
L => Half Bridge 5 is in Hi-Z
10
SACT_HB 4
H => Half Bridge 4 is active
L => Half Bridge 4 is in Hi-Z
9
SACT_HB 3
H => Half Bridge 3 is active
L => Half Bridge 3 is in Hi-Z
8
SACT_HB 2
H => Half Bridge 2 is active
L => Half Bridge 2 is in Hi-Z
7
SACT_HB 1
H => Half Bridge 1 is active
L => Half Bridge 1 is in Hi-Z
Configured Driver Status of Half-Bridge X
6
SCONF_HB 6
H => HSD6 = ON & LSD6 = OFF
L => HSD6 = OFF & LSD6 = ON
5
SCONF_HB 5
H => HSD5 = ON & LSD5 = OFF
L => HSD5 = OFF & LSD5 = ON
4
SCONF_HB 4
H => HSD4 = ON & LSD4 = OFF
L => HSD4 = OFF & LSD4 = ON
3
SCONF_HB 3
H => HSD3 = ON & LSD3 = OFF
L => HSD3 = OFF & LSD3 = ON
2
SCONF_HB 2
H => HSD2 = ON & LSD2 = OFF
L => HSD2 = OFF & LSD2 = ON
1
SCONF_HB 1
H => HSD1 = ON & LSD1 = OFF
L => HSD1 = OFF & LSD1 = ON
TW
Thermal Warning Bit; Global Error Flag;
This bit is treated as an early warning and will be set to High if the junction
temperature reaches TJW. The output remains on until one or more sensors
reaches TSD causing all outputs to be switched off simultaneously.
Bit 0 is automatically reset if the junction temperature cools down to TJSO
0
Note: Status HBx represents status of Half-Bridge Driver and NOT status of Control Register.
Note: The PSF and TW bits in the first Diagnosis word will reflect the current clock cycle status, all other remaining
bits are 0.
Data Sheet
25
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Application Information
7
Application Information
Note: The following simplified application examples are given as a hint for the implementation of the device only
and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the
device. The function of the described circuits must be verified in the real application.
Application Diagram
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Application Example for DC-motor Loads
st
Figure 17
di
For optimum EMC performance, a ferrite is recommended to be placed in series and as close as possible to the
Vdd line of the TLE841xy device. This is shown in the above application diagram example. The ferrite should have
an impedance of 1000ohm at an effective frequency of 100MHz frequency. A recommended ferrite is the
MMZ1608 type series available in a geometry size of 0603 with a DC resistance of 0.6ohm and allowable DC
current of 190mA.
Data Sheet
26
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Application Information
7.2
Thermal application information
Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each).
Ta = 85°C, Ch 1 to Ch 6 are dissipating a total of 1.08W (0.18W each).
ly
Zth-ja Curves for TLE 84106EL (6 channels on)
120
90
75
ti
60
ng
-40°C; 1s0p + 600 mm²
-40°C; 1s0p + 300 mm²
-40°C; 1s0p +footprint
-40°C; 2s2p
+85°C; 1s0p + 600 mm²
+85°C; 1s0p + 300 mm²
+85°C; 1s0p + footprint
+85°C; 2s2p
105
Zth-ja [K/W]
on
135
ke
45
30
0,0001
0,001
0,01
0,1
1
10
m
0
0,00001
ar
15
Pulse [sec]
1000
10000
ZthJA Curve for different PCB setups
by
Figure 18
100
on
Zth-jc C urves for TLE 84106E L (6 channels on)
ti
5
bu
2
Ta = + 85°C
di
1
0
0,00001
Ta = -40°C
ri
3
st
Zth-jc [K/W]
4
0,0001
0,001
0,01
0,1
1
10
100
1000
Pulse [se c]
Figure 19
Data Sheet
ZthJC Curve
27
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
ke
ti
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on
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Application Information
Board Setup
m
Figure 20
2s2p / 1s0p + foot print
ar
1s0p + 600mm² cooling
area
di
st
ri
bu
ti
on
by
Board Setup based on JESD 51-3, -7 FR4 PCB with 35µm Cu.
Data Sheet
28
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Package Outlines
2)
0.2
M
0.1 C D
3.9 ±0.11)
0.08 C
Seating Plane
C A-B D 24x
0.64 ±0.25
0.2
M
D
24
13
12
B
8.65 ±0.1
Index Marking
1
12
24
13
2.65 ±0.25
Bottom View
A
1
6 ±0.2
D
8˚ MAX.
2x
0.19 +0.06
0.35 x 45˚
1.7 MAX.
C
0.65
0.25 ±0.05
Stand Off
(1.47)
Package Outlines
0.1+0
-0.1
8
6.4 ±0.25
0.1 C A-B 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 21
PG-SSOP-24-4 (Plastic/Plastic Green - Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
29
Dimensions in mm
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Revision History
9
Revision History
0.30.40.3
TLE84106EL
Revision History: Rev. 1.0, 2010-04-27
Version
Subjects (major changes since last revision)
1.0
Final Data Sheet Release
Data Sheet
30
Rev. 1.0, 2010-04-27
Edition 2010-04-27
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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