TLE8888-1QK
Engine Machi ne System IC
1
Overview
Quality Requirement Category: Automotive
Features
•
Voltage pre-regulator
•
Integrated 5 V regulator
•
2 integrated 5 V trackers
•
Standby regulator
•
Separate internal supply
•
Voltage monitoring
•
High speed CAN interface with wake-up by bus
•
LIN interface with high speed mode for K-Line operation
•
Variable reluctance sensor interface
•
Microsecond Channel interface (MSC) with low voltage differential signal (LVDS) inputs pads for low EME
•
SPI and direct control inputs for high flexibility
•
Main relay driver
•
Ignition Key detection with key off delay output
•
Wake-up input
•
Engine off timer
•
4 low-side power stages especially to drive injectors (Ron = 550 mΩ) with enable input
•
3 low-side power stages (Ron = 350 mΩ)
•
6 push pull stages for driving on-board MOSFET with drain feedback
•
7 low-side power stages especially to drive relays (Ron = 1.5 Ω), one with delayed switch off functionality
•
4 half bridge stages for high flexibility, one with delayed switch off functionality
•
4 push pull stages for driving on- and off- board IGBT with back supply suppression and high voltage
capability
•
Open-load, short-to-GND and short-to-BAT diagnostic
•
Overtemperature and short-to-BAT protection
•
Monitoring watchdog module
•
AEC Qualified
Data Sheet
www.infineon.com
1
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Overview
Description
The TLE8888-1QK is a U-Chip suitable for automotive engine management systems. It contains the basic
functionality to supply the microcontroller and the ECU, establish the communication on- and off- board and
drive EMS typical actuators. Furthermore it controls the main relay driver.
Type
Package
Marking
TLE8888-1QK
LQFP-100
TLE8888-1QK
TLE8888QK
LQFP-100
TLE8888QK
TLE8888-2QK
LQFP-100
TLE8888-2QK
Device Variants TLE8888QK and TLE8888-2QK
The device variants TLE8888QK and TLE8888-2QK differ from the main version TLE8888-1QK in the watchdog
functionality.
The TLE8888QK has a fixed set of parameter for the watchdog (see datasheet addendum “TLE8888QK Addendum”).
For the TLE8888-2QK the watchdog function is disabled (see datasheet addendum “TLE8888-2QK Addendum”).
Only the main version TLE8888-1QK is described in this datasheet.
For order conditions please contact the nearest Infineon Technologies office.
Abbreviations
Symbol
Explanation
MSC
Microsecond channel
SPI
Serial peripheral interface
LVDS
Low voltage differential signal
EME
Electromagnetic emission
EMI
Electromagnetic interference
LIN
Local interconnect network
HS CAN
High speed controller area network
Data Sheet
2
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
5.1
5.2
5.3
Operation Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset and Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Operation Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
21
29
6
6.1
6.2
6.2.1
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Monitoring Watchdog Module (Signature Watchdog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Question and Response Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total Error Counter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Reset Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secure Shut Off Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation State Definition and Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronisation of Window Watchdog Sequence and Heartbeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Monitoring Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
33
35
37
38
39
39
39
40
42
44
7
7.1
7.2
7.3
7.4
7.5
Wake-Up Detection and Main Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up Detection by Pin KEY and Key Off Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up Detection by Pin WK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Engine Off Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Key Detection, Wake-up Detection and Main Relay Driver . . . . . . . . . . . .
45
46
47
50
51
55
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 V Main Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sensor Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IO Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
58
59
59
59
59
59
59
60
9
9.1
9.2
9.3
9.4
9.5
9.6
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stages Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stages Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function “Delayed Switch Off” for OUT17 and OUT21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Direct Drive Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Side Switches OUT1 to OUT7 and OUT14 to OUT20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
65
66
67
67
70
71
Data Sheet
3
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
9.6.1
9.6.2
9.6.3
9.7
9.7.1
9.7.2
9.7.3
9.8
9.8.1
9.8.2
9.9
9.10
9.10.1
9.10.2
9.11
Protection of OUT1 to OUT7 and OUT14 to OUT20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis of OUT1 to OUT7 and OUT14 to OUT20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Low-Side Switches OUT1 to OUT7 and OUT14 to OUT20 . . . . . . . . .
Half Bridges OUT21 to OUT24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection of Half Bridges OUT21 to OUT24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis of Half Bridges OUT21 to OUT24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Half Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Push Pull Stages OUT8 to OUT13 and DFB8 to DFB13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection of OUT8 to OUT13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis of OUT8 to OUT13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Push Pull Stages OUT8 to OUT13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Push Pull Stages IGN1 to IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection of IGN1 to IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis of IGN1 to IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Push Pull Stages IGN1 to IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
71
72
76
78
78
81
84
84
84
85
86
86
87
88
10
10.1
10.2
10.3
10.4
VR and Hall Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis for VR Sensor Signal Detection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics VR Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
90
92
92
97
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
Local Interconnect Network (LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Failure Modes in LIN/K-Line Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Performance in Non Operation Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Loss of Supply Voltage and GND Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Bus Wiring Short to Battery or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TX Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Electrical Characteristics LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.3.1
12.3.2
12.4
High Speed Controller Area Network (CAN) Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Bus Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
105
105
106
106
106
106
108
108
108
109
13
13.1
13.1.1
13.1.2
13.1.3
13.2
Microsecond Channel MSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Downstream Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Downstream Supervisory Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
112
114
115
115
117
Data Sheet
4
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
13.3
13.4
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
Register and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
128
130
144
155
162
192
15
15.1
15.2
15.3
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Frame Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
197
197
199
200
16
16.1
EMC Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
ISO Pulse Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
17
17.1
17.2
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Supply Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
VR Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
18
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Data Sheet
5
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Block Diagram
Key and WK
Detection
Standby Supply
BATPB
Chargepump
BATPA
CP
V5VSTBY
Engine
Off
Timer
BATSTBY
EOTEN
Key Off
Delay
WK
KOFFDO
Block Diagram
KEY
2
Half Bridge
Half Bridge
OUT21
OUT22
OUT23
Main Relay Driver
MR
OUT24
INJEN
Power Stage 2.2A
Power Stage 2.2A
Linear
Pre-regulator
BAT
Voltage Monitoring
OUT2A
OUT2B
OUT3A
OUT3B
Vref
VG
OUT1A
OUT1B
OUT4A
OUT4B
V6V
to internal
supply
Power Stage 4.5A
Linear
Regulator
OUT5A
OUT5B
OUT5C
Vref
Power Stage 4.5A
V5V
Linear
Regulator (Tracker)
Linear
Regulator (Tracker)
OUT6A
OUT6B
OUT6C
OUT7A
OUT7B
OUT7C
Power Stage 0.6A
V5V
Power Stage 0.6A
T5V1
OUT14
OUT15
OUT16
Control Logic
T5V2
OUT17
OUT18
OUT19
VRIN1
OUT20
VRIN2
VR Sensor
Interface
IGNEN
Ignition Driver 20mA
Ignition Driver
VROUT
IGN1
IGN2
LINIO
IGN3
IGN4
LIN Interface
LINTX
LINRX
Push Pull Driver 20mA
Monitoring
Watchdog
DFBx
Diagnosis
V5VCAN
CANWKEN
CANH
CANL
CANTX
Push Pull Driver 20mA
CAN Interface
+
Wake Receiver
DFBx
Diagnosis
DFB9
OUT9
DFB10
OUT10
DFB11
OUT11
DFB12
OUT12
CANRX
MSC/SPI
Interface
Direct Drive
Inputs
DFB8
OUT8
DFB13
OUT13
Exposed pad
internally connected
to PGND pins
Figure 1
Data Sheet
SDO
CSN
FCLN
SIN
FCLP
SIP
IN1
IN12
RST
MON
VDDIO
PGND
PGND
AGND
Exposed
Pad
Block Diagram
6
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Pin Configuration
Pin Configuration
3.1
Pin Assignment
PGND
OUT10
DFB10
OUT9
DFB9
OUT8
DFB8
OUT14
OUT15
OUT4B
OUT4A
OUT3B
OUT3A
OUT2B
OUT2A
OUT1B
OUT1A
OUT16
OUT17
OUT18
MR
BAT
BATSTBY
VRIN1
VRIN2
3
75
76
51
50
100
1
26
25
PGND
KEY
WK
CANL
CANH
V5VCAN
CANTX
CANRX
CANWKEN
V5VSTBY
EOTEN
IN12
IN11
IN10
IN9
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IGNEN
KOFFDO
RST
MON
CSN
SDO
SIP
SIN
FCLP
FCLN
T5V1
T5V2
V5V
V6V
VG
OUT7A
OUT7B
OUT7C
OUT20
OUT19
n.c.
VDDIO
VROUT
LINTX
LINRX
INJEN
PGND
DFB11
OUT11
DFB12
OUT12
DFB13
OUT13
LINIO
OUT5A
OUT5B
OUT5C
OUT24
BATPA
OUT23
OUT22
BATPB
OUT21
OUT6A
OUT6B
OUT6C
CP
IGN1
IGN2
IGN3
IGN4
AGND
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function Function
1
RST
IN/OUT
Reset; Bidirectional pin for reset functions
2
MON
IN/OUT
Monitor; Bidirectional pin for monitoring functions
3
CSN
IN
MSC/SPI slave chip select; Single ended chip select for MSC and SPI
4
SDO
OUT
MSC/SPI serial data output; Output for MSC and SPI
5
SIP
IN
MSC/SPI Data input; positive data input of LVDS in MSC mode or single
ended data input in SPI mode
Data Sheet
7
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Pin Configuration
Pin
Symbol
Function Function
6
SIN
IN
MSC data input or select input; negative data input of LVDS in MSC mode
or select input for SPI mode
7
FCLP
IN
MSC/SPI Clock input; positive clock input of LVDS in MSC mode or single
ended clock input in SPI mode
8
FCLN
IN
Select input or MSC clock input; negative clock input of LVDS in MSC
mode or select input for single ended mode (SPI or MSC)
9
T5V1
OUT
5 V tracker; Supply voltage for off- board sensors
10
T5V2
OUT
5 V tracker; Supply voltage for off- board sensors
11
V5V
OUT
5 V supply; Supply voltage for main functions of the ECU
12
V6V
IN
Source of external pre-regulator
13
VG
OUT
Gate of external pre-regulator
14
OUT7A
OUT
Low-side power stage; Must be connected to OUT7B and OUT7C
without any parasitic
15
OUT7B
OUT
Low-side power stage; Must be connected to OUT7A and OUT7C
without any parasitic
16
OUT7C
OUT
Low-side power stage; Must be connected to OUT7A and OUT7B
without any parasitic
17
OUT20
OUT
Low-side small signal stage;
18
OUT19
OUT
Low-side small signal stage;
19
n.c.
20
VDDIO
Supply
Supply input for logic level inputs and outputs
21
VROUT
OUT
Output of variable reluctance sensor interface; Digital output to
microcontroller
22
LINTX
IN
Transmit digital input for LIN interface;
23
LINRX
OUT
Receive digital output for LIN interface;
24
INJEN
IN
Injector enable input;
25
PGND
GND
Power ground; internally connected to cooling tab
26
KOFFDO
OUT
Key off delay output;
27
IGNEN
IN
Ignition enable input;
28
IN1
IN
Parallel input; Input pin for direct control of power stage OUT1,
29
IN2
IN
Parallel input; Input pin for direct control of power stage OUT2
30
IN3
IN
Parallel input; Input pin for direct control of power stage OUT3
31
IN4
IN
Parallel input; Input pin for direct control of power stage OUT4
32
IN5
IN
Parallel input; Input pin for direct control of push pull state IGN1
33
IN6
IN
Parallel input; Input pin for direct control of push pull state IGN2
34
IN7
IN
Parallel input; Input pin for direct control of push pull state IGN3
35
IN8
IN
Parallel input; Input pin for direct control of push pull state IGN4
36
IN9
IN
Parallel input; Input pin for direct control of power stages, could be
multiplexed to various stages
Data Sheet
leave open or connect to GND
8
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Pin Configuration
Pin
Symbol
Function Function
37
IN10
IN
Parallel input; Input pin for direct control of power stages, could be
multiplexed to various stages
38
IN11
IN
Parallel input; Input pin for direct control of power stages, could be
multiplexed to various stages
39
IN12
IN
Parallel input; Input pin for direct control of power stages, could be
multiplexed to various stages
40
EOTEN
IN
Engine off timer enable input;
41
V5VSTBY
OUT
5 V standby supply; Supply voltage in sleep mode
42
CANWKE
N
IN
Enable input for remote CAN wake-up;
43
CANRX
OUT
Receive digital output for CAN;
44
CANTX
IN
Transmit digital input for CAN;
45
V5VCAN
Supply
5 V supply input for CAN;
46
CANH
IN/OUT
CAN bus high;
47
CANL
IN/OUT
CAN bus low;
48
WK
IN
Wake-up input; Input signal and supply for MR
49
KEY
IN
Key input; Input signal and supply for MR
50
PGND
GND
Power ground; internally connected to cooling tab
51
VRIN2
IN
Differential input of variable reluctance sensor; Analog input from
sensor
52
VRIN1
IN
Differential input of variable reluctance sensor; Analog input from
sensor
53
BATSTBY Supply
54
BAT
Supply
Battery; Supply voltage for main functions of the device.
55
MR
OUT
Low-side power stage for main relay;
56
OUT18
OUT
Low-side power stage;
57
OUT17
OUT
Low-side power stage;
58
OUT16
OUT
Low-side power stage;
59
OUT1A
OUT
Low-side power stage; Must be connected to OUT1B without any
parasitic
60
OUT1B
OUT
Low-side power stage; Must be connected to OUT1A without any
parasitic
61
OUT2A
OUT
Low-side power stage; Must be connected to OUT2B without any
parasitic
62
OUT2B
OUT
Low-side power stage; Must be connected to OUT2A without any
parasitic
63
OUT3A
OUT
Low-side power stage; Must be connected to OUT3B without any
parasitic
64
OUT3B
OUT
Low-side power stage; Must be connected to OUT3A without any
parasitic
Data Sheet
Battery input for standby supply; Battery supply voltage standby supply
regulator
9
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Pin Configuration
Pin
Symbol
Function Function
65
OUT4A
OUT
Low-side power stage; Must be connected to OUT4B without any
parasitic
66
OUT4B
OUT
Low-side power stage; Must be connected to OUT4A without any
parasitic
67
OUT15
OUT
Low-side power stage;
68
OUT14
OUT
Low-side power stage;
69
DFB8
IN
Drain Feedback; Related to OUT8
70
OUT8
OUT
Push pull stage; To control on- board MOSFET
71
DFB9
IN
Drain Feedback; Related to OUT9
72
OUT9
OUT
Push pull stage; To control on- board MOSFET
73
DFB10
IN
Drain Feedback; Related to OUT10
74
OUT10
OUT
Push pull stage; To control on- board MOSFET
75
PGND
GND
Power ground; internally connected to cooling tab
76
DFB11
IN
Drain Feedback; Related to OUT11
77
OUT11
OUT
Push pull stage; To control on- board MOSFET
78
DFB12
IN
Drain Feedback; Related to OUT12
79
OUT12
OUT
Push pull stage; To control on- board MOSFET
80
DFB13
IN
Drain Feedback; Related to OUT13
81
OUT13
OUT
Push pull stage; To control on- board MOSFET
82
LINIO
IN/OUT
BUS for LIN interface;
83
OUT5A
OUT
Low-side power stage; Must be connected to OUT5B and OUT5C
without any parasitic
84
OUT5B
OUT
Low-side power stage; Must be connected to OUT5A and OUT5C
without any parasitic
85
OUT5C
OUT
Low-side power stage; Must be connected to OUT5A and OUT5B
without any parasitic
86
OUT24
OUT
Half bridge stage;
87
BATPA
Supply
Battery; Supply voltage for half bridges and the charge pump; must be
connected to BATPB without any parasitic
88
OUT23
OUT
Half bridge stage;
89
OUT22
OUT
Half bridge stage;
90
BATPB
Supply
Battery; Supply voltage for half bridges and the charge pump; must be
connected to BATPA without any parasitic
91
OUT21
OUT
Half bridge stage;
92
OUT6A
OUT
Low-side power stage; Must be connected to OUT6B and OUT6C
without any parasitic
93
OUT6B
OUT
Low-side power stage; Must be connected to OUT6A and OUT6C
without any parasitic
94
OUT6C
OUT
Low-side power stage; Must be connected to OUT6A and OUT6B
without any parasitic
95
CP
OUT
Charge pump; add external capacitance to stabilise charge pump voltage
Data Sheet
10
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Pin Configuration
Pin
Symbol
Function Function
96
IGN1
OUT
Push pull stage; To control on- or off- board IGBT
97
IGN2
OUT
Push pull stage; To control on- or off- board IGBT
98
IGN3
OUT
Push pull stage; To control on- or off- board IGBT
99
IGN4
OUT
Push pull stage; To control on- or off- board IGBT
100
AGND
GND
Signal ground; internally connected to PGND and cooling tab
Cooling PGND
tab1)
GND
Power ground; internally connected PGND pins
1) Cooling tab is also called exposed pad
Data Sheet
11
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
General Product Characteristics
4
General Product Characteristics
General definition:
VS is the short cut for all battery supplies of the TLE8888-1QK (BAT, BATPA, BATPB, BATSTBY) unless
otherwise specified
GND is the short cut for all grounds of the TLE8888-1QK (AGND, PGND) unless otherwise specified.
Table 1
Absolute Maximum Ratings1)
Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise
specified)
Parameter
Symbol
Values
Min.
Number
Typ. Max.
Unit Note or
Test Condition
Voltages
BATPA, BATPB, OUT8…13,
DFB8…13
VBATPA,MR,
-0.3
VBATPB,MR,
VOUT8…13,MR,
VDFB8…13,MR,
–
40
V
–
P_4.1
CP
VCP,MR
-0.3
–
45
V
-0.3 V < VCP VBATPA < 5 V
P_4.2
OUT1…7, OUT14…20
VOUT1…7,MR, -0.3
VOUT14…20,MR
–
50
V
OUTn is switched off, P_4.3
clamping is allowed
according
Chapter 9.6
V6V
VV6V,MR
-0.3
–
10
V
–
P_4.4
VG
VVG,MR
-0.3
–
12
V
VVG - VV6V < 5 V
P_4.5
-0.3
–
5.5
V
–
P_4.6
V5V, V5VSTBY, VDDIO, V5VCAN VV5V,MR,
VV5STBY,MR,
VVDIO,MR,
VV5VCAN,MR
T5V1, T5V2, IGN1…4
VT5V1,MR,
VT5V2,MR,
VIGN1…4,MR
-1
–
40
V
–
P_4.7
BAT, BATSTBY, KEY, WK, MR
VBAT,MR,
VKEY,MR,
VWK,MR,
VBATSTBY,MR,
VMR,MR,
-16
–
40
V
–
P_4.8
Data Sheet
12
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
General Product Characteristics
Table 1
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise
specified)
Parameter
Symbol
Values
Min.
IN1…12, SIP, SIN, FCLP, FCLN, VIN1…12,MR, -0.3
VFCLP,MR,
CSN, LINTX, CANTX, IGNEN,
VFCLN,MR,
INJEN, CANWKEN, EOTEN
VSIP,MR,
VSIN,MR,
VCSN,MR,
VLINTX,MR,
VCANTX,MR,
VIGNEN,MR,
VINJEN,MR,
VEOTEN,MR,
VCANWKEN,MR
Number
Typ. Max.
Unit Note or
Test Condition
–
5.5
V
–
P_4.9
both conditions
must be observed
P_4.31
P_4.10
VSDO,MR,
VRST,MR,
VVROUT,MR,
VLINRX,MR,
VCANRX,MR
-0.3
–
VDDIO+ V
0.3
-0.3
–
5.5
VMON,MR,
VKOFFDO,MR
-0.3
–
V5V+0.3 V
-0.3
–
5.5
V
both conditions
must be observed
VRIN1
VVRIN1,MR
-0.3
–
40
V
VRIN2 open
P_4.11
VRIN2
VVRIN2_MR
-0.3
–
40
V
VRIN1 open
P_4.12
LINIO, CANH, CANL
VLINIO,MR,
VCANH,MR,
VCANL,MR
-40
–
40
V
–
P_4.13
OUT21…24
VOUT21…24,MR -0.3
–
BATPx+0 V
.3
–
P_4.14
SDO, RST,VROUT, LINRX,
CANRX
MON, KOFFDO
V
Currents
IDFB8…13,MR
-5
–
5
mA
2)
P_4.15
Common Mode Input Current I VRIN,CM,MR
of VRIN1 and VRIN2
-5
–
5
mA
I VRIN,CM,MR = I VRIN1 +
I VRIN22)
P_4.16
Common Mode Input Current I VRIN,CM,MR
of VRIN1 and VRIN2, non
permanent
-15
–
15
mA
P_4.34
I VRIN,CM,MR = I VRIN1 +
I VRIN22), maximum
duty cycle 60% and
maximum on time of
1 ms, 100 h
Differential Current of VRIN1
and VRIN2
ΔI VRIN,MR
-50
–
50
mA
ΔI VRIN,MR = (I VRIN1 I VRIN2)/22)
P_4.17
PGND
IPGND,MR
-25
–
25
A
–
P_4.18
mA
2)
P_4.19
DFB8…13
IGN1…4
IIGN1…4,MR
-50
–
–
Temperatures
Data Sheet
13
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
General Product Characteristics
Table 1
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise
specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note or
Test Condition
Number
Junction Temperature
Tj
-40
–
150
°C
3)
P_4.20
Storage Temperature
Tstg
-55
–
150
°C
–
P_4.21
ESD Susceptibility
VESDHBM
-2
–
2
kV
HBM4)
P_4.22
ESD Susceptibility BAT,
BATPA, BATPB, T5V1, T5V2,
BATSTBY, KEY, WK, MR,
OUT1…7, OUT14…24,
DFB8…13, IGN1…4, CANH,
CANL, LINIO, VRIN1, VRIN2 to
PGND
VESD,HBM
-4
–
4
kV
HBM4)
P_4.23
ESD Susceptibility
VESDCDM
-500
–
500
V
CDM5)
P_4.24
V
5)
P_4.25
ESD Susceptibility
ESD Susceptibility Pin 1, 25,
26, 50, 51, 75, 76, and 100
(corner pins)
1)
2)
3)
4)
5)
VESD1, 25, 26,
-750
–
750
CDM
50, 51, 75, 76, 100
not subject to production test
Current has to be limited when maximum voltages are exceeded
according to qualification
ESD susceptibility, HBM according to EIA/JESD 22-A114F (1.5k Ω, 100 pF)
ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
14
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
General Product Characteristics
Table 2
Functional Range
Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise
specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Supply Voltage - Reduced
Operation
VBAT,ro
4.5
–
6
V
P_4.26
reduced
operation range,
main relay and
delayed off
power stages are
on if enabled,
remaining
functions not
working
Supply Voltage - Low Drop
Range
VBAT,ld
6
–
9
V
P_4.27
low drop
operation range,
supply
regulators
working with
supply out of the
charge pump,
standby supply
regulator out of
operation range
Supply Voltage - Normal
Operation range
VBAT,nop
9
–
28
V
normal
operation
range1)
Supply Voltage Overvoltage Range
VBAT,ov
28
–
40
V
overvoltage,
P_4.29
power stages are
switched off
Supply Voltage transients2)
dVBAT/dt
-1
–
1
V/µs
–
P_4.28
P_4.30
1) overtemperature due to bad RthJA of the ECU or overload can happen
2) not subject to production test, specified by design
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Table 3
Thermal Resistance
Parameter
Junction to Case1)
Junction to Ambient
Symbol
RthJC
RthJA
Values
Unit
Min.
Typ.
Max.
–
2.4
–
–
–
–
Note or
Test Condition
Number
K/W
–
P_4.32
K/W
2)
P_4.33
1) Not subject to production test, specified by design.
2) EIA/JESD 52_2, FR4, 80 × 80 × 1.5 mm; 35 × Cu, 5 × Sn; 300 mm2
Data Sheet
15
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
5
Operation Behavior
The TLE8888-1QK has implemented the whole supply of an ECU. Therefore a complex control logic is
implemented to provide several operation states.
In this chapter
•
the ramp up and down behavior and
•
the status of the TLE8888-1QK during special conditions like 5 V undervoltage
is described. For the description of the monitoring watchdog module see Chapter 6.
In Figure 3 the block diagram with all blocks affecting the status of the device and the ECU are shown.
Following blocks are influenced during the different operation states and reset functions:
•
Serial Interface MSC/SPI: with the serial interface the setup of the device is done
•
Key input detection: start signal from key switch (KL15)
•
Wake-up input detection: additional start signal e.g. from external CAN with wake-up by bus function
•
Engine off timer: wake-up signal in comparator mode
•
Power supply: ECU 5 V supply and 5 V sensor supplies, 5 V standby supply
•
Voltage monitoring: supervision of all supplies (BAT, V5V, T5V1, T5V2)
•
Main relay driver: controls external main relay to switch battery voltage to an ECU supply pin (see also
application setups in Chapter 17)
•
Power stages and half-bridges control block
•
LIN/K-Line: transmission mode depends on operation state of the ECU
•
CAN: transmission mode depends on operation state of the ECU, remote wake-up function
•
Reset outputs MON and RST
•
Monitoring watchdog module: signature watchdog for safety applications
•
Operation Mode Control
The operation mode control block consists of:
•
ramp up and down sequence control logic
•
the reset control logic and
•
status output logic.
Data Sheet
16
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
BAT
T5V2
T5V1
V5V
BATPA
BATPB
BATSTBY
V5VSTBY
Operation Behavior
Battery
Detection
Voltage
Monitoring
Power Supply
CANWKEN
CANWKEN
CANL
CANH
CAN &
remote
wake up
WK
Wake Up Input
Detection
KEY
Key Input
Detection
EOTEN
Main Relay
Driver
Engine Off Timer
MR
Power Stages
&
Half Bridges
OUTx
IGNx
LIN/K-Line
LINIO
Monitoring
Watchdog
MSC/SPI
Input Register
CSN
FCLP
FCLN
SIP
SIN
SDO
Operation Mode
Control
Output Register
MON
RST
Figure 3
Block diagram operation mode control
5.1
Operation States
In Figure 4 the state diagram of the whole ramp up and down sequence is shown. There are seven operation
states:
•
ECU sleep state: KEY and WK input are “low”, no wake-up signals from engine off timer or CAN are active,
main relay is off, the whole ECU inclusive TLE8888-1QK is not supplied, 5 V standby supply is working if pin
BATSTBY is supplied, engine off timer and CAN wake-up circuits are active if enabled and supplied.
Data Sheet
17
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
•
Supply ramp up state: KEY input or wake1) are “high” and the supply of the TLE8888-1QK starts working,
the voltage of V6V, V5V, T5V1 and T5V2 are ramping up but the voltage levels are below the undervoltage
threshold. For wake-up by wake1) the ramp up of the main supply has to be finished before the ramp up
timer overflow. The main relay is switched on depending on the voltage level at the pin BAT (see
Chapter 7.2)
•
Normal operation state: KEY input or wake are “high” and main relay is switched on depending on the
voltage level at the pin BAT or the status of bit MR in the status register OpStat0 (see Chapter 7.2), the
whole ECU is supplied and the status of the different functions and registers is according Table 5 and
Table 6.
•
Afterrun state: KEY is “low” but afterrun enable bit is set and therefore the whole ECU is supplied, the
status of the different functions and registers is according Table 5 and Table 6 and the microcontroller can
execute afterrun routines
•
Afterrun reset state: the reset procedure before direct reentry in normal operation is executed if bit AR =1
in the configuration register OpConfig0
•
General power-down state: the supplies of the ECU (V5V, T5V1, T5V2) are disabled and the power-down
timer is counting, main relay remains in the switching status and the TLE8888-1QK is supplied to ensure
the power-down (V5V drops down to 0 V) of the ECU, V5VSTBY is working if BATSTBY is supplied, all
functions to external are disabled.
•
Wake clear state: this state avoids permanent wake-up in failure cases. The wake clear command is
executed (function according setting bit WKCLR in the command register Cmd0). All wake signals which
are active after the supply ramp up and the general power-down state are reset.
1) description see Figure 4, Chapter 7.2, Chapter 7.4 and Chapter 12.2.4
Data Sheet
18
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
KE
Y=
0
RT & wa
_ O ke
F= =1
1
&
1
KEY=0
Y=
KE
PD
T_
OF
=1
wake clear*
=
KEY
Gerneral
Power Down*
Supply Ramp
Up
0
a ke=
0& w
0&
Y=
KE
SS
&
=0
or
AE
=0
=1
ke
wa
F
_O
D
(P
KE
Y=
0
0
Y=
KE
wa
ke
=0
&
&
1)
F=
=0
AE
O
T_
&
O
PD_OF=1 or SSOT_OF=1
KEY=1 or wake=1
(KEY=1 or wake=1) & V5VUV=0
ECU Sleep
KEY=0 & AE=1
Normal
Operation*
Afterrun*
AR=0 & KEY=1
AR
=1
&
KEY
RT_OF
AE
AR
PDT_OF
PD_OF
POR
SSOT_OF
V5VUV
KE
Y=
1
filtered KEY signal
ramp up timer overflow
afterrun enable bit
afterrun reset configuration bit
power down timer overflow
overflow of minimum one of the three PD counter
internal power on reset
secure shut off timer overflow
under voltage of V5V active
Afterrun
Reset*
wake = WKINT or CANWK or EOTWK
0 … function inactive
1 … function active
wake = 1: one of the signals WKINT, CANWK,
EOTWK is „1"
wake = 0: all signals are „0"
(e.g. V5VUV=1 Æ 5V supply is below undervoltage threshold
V5VUV=0 Æ 5V supply is above undervoltage threshold)
Figure 4
Data Sheet
* POR=1:
active internal power on reset forces transition to
ECU sleep (wake=0 & KEY=0) or supply ramp up
mode (wake=1 or KEY=1) from all states
Operation state diagram
19
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Description of the transitions:
Table 4
Operation State Transitions
Transition
Condition
Description
from all states to ECU
sleep state
internal supply voltage < internal power on reset is active and reset the whole
internal por threshold
digital logic, ECU sleep state is entered due to no wake-up
and KEY = 0 and
signal at KEY or wake
1) 2)
wake =0
from all states to
supply ramp up state
internal supply
voltage < internal por
threshold and KEY = 1
or wake = 12)
ECU sleep state to
supply ramp up state
KEY > VKEY,th or wake = 1 With a “high” voltage at KEY or wake the wake-up of the
TLE8888-1QK starts
Supply ramp up state
to ECU sleep state
KEY < VKEY,th and
wake = 02)
Supply ramp up state
to wake clear state
KEY < VKEY,th and
The KEY signal is low and the wake-up signals are active.
wake = 12) and RT_OF = 1 The ramp up timer has an overflow which indicates a
ramp up problem of the external supply (e.g. short to
GND). To avoid permanent high current consumption the
internal wake signals must be reset to enter the ECU sleep
state.
Supply ramp up state
to normal operation
state
(KEY > VKEY,th or
wake = 1) and
V5V > Vuv,V5V2)
internal power on reset is active and reset the whole
digital logic, supply ramp up state is entered due to a
wake-up signal at KEY or wake
The external supply ramp up is not finished but the wakeup signals are low
normal operation state is entered if the main supply
voltage V5V is above the undervoltage threshold, KEY is
high or one of the wake-up conditions are active
Normal operation state KEY < VKEY,th and AE = 12) KEY is “low” and afterrun function is enabled:
to afterrun state
no changes in the setup of the TLE8888-1QK
Normal operation state AE = 0 and KEY < VKEY,th
to ECU sleep state
and wake = 02)
normal shut off
Normal operation state (PD_OF = 1 or
to general power-down SSOT_OF = 1) and
state
KEY < VKEY,th 2)
KEY is low and
watchdog error shut off with overflow of the power-down
counter or
secure shut off due to expired secure shut off timer
Afterrun state to ECU
sleep state
AE = 0 and KEY < VKEY,th
and wake = 0 2)
normal shut off in afterrun mode with the reset of the
afterrun enable bit AE by the microcontroller
Afterrun state to
general power-down
state
PD_OF = 1
or
SSOT_OF = 1
watchdog error shut off with overflow of the power-down
counter or
secure shut off due to expired secure shut off timer
Afterrun state to
KEY > VKEY,th and AR = 02) reentry of normal operation with KEY on during afterrun
normal operation state
operation, no reset is performed (AR = 0)
Afterrun state to
afterrun reset state
Afterrun reset state to
normal operation state
Data Sheet
KEY > VKEY,th and AR = 12) reentry of normal operation with KEY on during afterrun
operation with reset (AR = 1)
transition to normal operation with the next active
internal clock edge after entry to the afterrun reset state
20
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 4
Operation State Transitions (cont’d)
Transition
Condition
Description
General power-down
state to wake clear
state
PDT_OF = 1
with the power-down timer overflow the reset of the
internal wake signals must be performed
Wake clear state to ECU KEY < VKEY,th
sleep state
after reset of the internal wake signals and KEY is low the
ECU sleep state is entered, no unwanted wake-up due to
a failure condition will occur
Wake clear state to
supply ramp up state
after reset of the internal wake signals and KEY is high
the supply ramp up state is entered, no unwanted wakeup due to a failure condition at the CAN bus and pin WK
will occur
KEY > VKEY,th
1) wake = WKINT or CANWK or EOTWK (see Chapter 7.2, Chapter 7.4 and Chapter 12.2.4)
2) including defined filter times
The two states:
•
normal operation
•
afterrun
are reflected in the bit OM of the status register OpStat0.
The power-down time is defined with the bits PDT of the configuration register OpConfig0.
In Figure 5 a sequence with wake-up by KEY and go to sleep with afterrun mode is shown.
KEY
WK
wake
t
Ramp UP/Down
Statemachine
ECU
Sleep
Supply
Ramp Up
Normal operation
Afterrun
ECU Sleep
V5V
VUVV5V
t
t pu,r
RST
t
AE
t
Figure 5
Ramp up and down sequence diagram with wake-up by KEY and afterrun mode
5.2
Reset and Operation Modes
Data Sheet
21
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
The TLE8888-1QK provides several supervision functions which lead to some dedicated reset states and
special operation modes of the device and the ECU.
There are two bidirectional reset pins MON and RST implemented. For the behavior during reset of the reset
pins MON and RST and the other status of the TLE8888-1QK see Table 5 and Table 6.
Following reset functions and special states are implemented:
•
Internal power on reset: the internal power on reset detection circuit monitors the voltage level of the
internal supply. For an internal supply voltage below the internal power on reset threshold the whole
digital logic of the TLE8888-1QK is reset which results in the ECU sleep state or supply ramp up state
depending on the state of KEY and wake. If the voltage level for operation is high enough the 6 V pre
regulator is working. The 5 V supplies are disabled till the internal supply level is over the power on
threshold level.
•
ECU power on reset: this is the reset at ramp up of the power supplies and the beginning of the operation.
The pins RST and MON are pulled to GND to reset the microcontroller and all devices connected to the
pin MON. The device is reset to the initial reset status. The reset is released with a voltage at pin V5V
higher than the V5V Undervoltage Detection Hysteresis after tpu,r.
•
Reset during undervoltage of the 5 V supply V5V: this reset occurs during undervoltage of the 5 V ECU
supply. The pins RST and MON are pulled to GND to reset the microcontroller and all devices connected
to the pin MON. The delayed switch off function is active regarding the configuration setup. The status of
the main relay is according to the status of the wake-up pins KEY and WK and the voltage level of the
supply pin BAT.
•
State during undervoltage of the 5 V supplies T5V1 and T5V2: with the undervoltage detection of the
tracker supplies diagnosis bits are set but there is no effect to the behavior of the device.
•
Reset during overvoltage of the 5 V supply V5V: with the overvoltage detection of the 5 V ECU supply all
functions of the device which have an effect externally or can lead to overcurrent or overtemperature are
disabled (e.g. power stages, LIN/CAN/MSC/SPI communication). The pins RST and MON are low.
•
State during overvoltage of the 5 V supplies T5V1 and T5V2: with the detection of overvoltage of the tracker
supplies diagnosis bits are set but there is no effect to the behavior of the device.
•
Power stages switch off during overvoltage of the battery supply BAT: For voltages at the supply pin BAT
higher than the overvoltage threshold the power stages are disabled to avoid too high clamping energy
during switch off. Damage of the switches is prevented.
•
Watchdog reset: If the reset counter is incremented and the reset is enabled (bit WDREN = 1) the
microcontroller is reset with a “low” at the pin RST. The power stages are disabled and the LIN/CAN
communication is set to receive only mode.
•
Software reset from microcontroller: with the software reset command (command register CmdSR) the
software reset is activated. The device is reset to the reset status defined in Table 5 and Table 6. The
activation of the software reset triggers an increase of the power-down counter by 1.
•
Reset with an external forced “low” at RST: With a detected “low” at the RST pin the TLE8888-1QK is reset
to the reset status defined in Table 5 and Table 6.
•
Power stages switch off with an external forced “low” at MON: With a detected “low” at the MON pin the
power stages are disabled (O1E to O24E, IGN1E to IGN4E are set to “0”). After MON=0 event the power
stages must be enabled again.
•
State with time out of the MSC communication: With the time out of the MSC communication the power
stages are disabled (O1E to O24E, IGN1E to IGN4E are set to “0”). After the next valid received data frame
the power stages must be enabled again.
•
Afterrun reset: This reset is executed if the bit AR of register OpConfig0 is 1 and the transition from afterrun
state to normal operation is triggered (definition see Table 6).
Data Sheet
22
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 5
Overview Behavior at Reset and Operation Conditions (part 1)
Effect to functions:
Conditions
ECU power on reset
notes
forces state
change
only after transition from timing see
Supply Ramp Up to
Chapter 8.7
Normal Operation state
and Table 7
for tpu,r
timing see
Chapter 8.7
timing see
Chapter 8.7
and Table 7
timing see
Chapter 8.7
timing see
Chapter 8.7
V5VSTBY, V6V
en.
en.
en.
en.
en.
en.
en.
V5V, T5V1, T5V2
dis.
en.
en.
en.
en.
en.
en.
MSC/SPI communication
dis.
dis.
dis.
en.
en.
en.
2)
2)
dis.
2)
en.
en.2)
off/dis./off
no change
off/dis./off
delayed switch en.
off activated
delayed
switch off
activated
en.
dis.
rec. only, after release
setup acc. bits CAN, LIN,
CANWE, LINWE3)
rec. only, after acc. bits CAN,
release setup LIN, CANWE,
acc. bits CAN, LINWE
LIN, CANWE,
LINWE3)
dis., after
release setup
acc. bits CAN,
LIN, CANWE,
LINWE
acc. bits
CAN, LIN,
CANWE,
LINWE
acc. bits CAN,
LIN, CANWE,
LINWE
“low”4)
“low”
“low”
no effect5)
“low”
no effect5)
no effect5)
RST (output function)
“low”4)
“low”
“low”
no effect5)
“low”
no effect5)
no effect5)
Watchdog Sequence,
Heartbeat Timer6)
reset
reset
reset
no effect
reset
no effect
no effect
en.
en.
off/dis./off
off/dis./off
no change
dis.
dis.
LIN/CAN communication
dis.
MON (output function)
Main relay
en.
Low-side switches / Half
bridges / Push Pull Driver
off/dis./off
OUT17 and OUT21 with
delayed switch off function
Data Sheet
en.
2)
Undervoltage Undervoltage Overvoltage
V5V
T5V1, T5V2
V5V1)
Overvoltage Overvoltage
T5V1, T5V2 BAT
Internal power
on reset
23
en.
2)
2)
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 5
Overview Behavior at Reset and Operation Conditions (part 1) (cont’d)
Effect to functions:
Conditions
Internal power
on reset
ECU power on reset
Undervoltage Undervoltage Overvoltage
V5V
T5V1, T5V2
V5V1)
Overvoltage Overvoltage
T5V1, T5V2 BAT
WWD Error Counter, FWD
pass counter, Total error
counter
reset
reset
reset
no effect
reset
no effect
no effect
PD Counter
reset
reset
reset
no effect
reset
no effect
no effect
Reset Counter; SSOT
reset
reset
reset
no effect
reset
no effect
no effect
AR; CANWE; LINWE;
FWDQUEST
reset
reset
reset
no effect
reset
no effect
no effect
AE; WWDConfig0;
WDConfig0; watchdog
diagnosis bits
reset
reset
reset
no effect
reset
no effect
no effect
Logic and MSC/SPI register
bits7)8)
reset
reset
reset,
diagnosis bits no effect
diagnosis bit is are set
set
diagnosis
bits are set
diagnosis bit
is set
EOTWK, CANWK, WKINT
no effect
no effect
reset
no effect
no effect
1)
2)
3)
4)
5)
6)
7)
8)
no effect
no effect
for voltages greater than the maximum ratings of pin V5V behavior is not guaranteed
according the definition in Chapter 7
after release of RST (transition from low to high) there is a time delay of tdel,r before configuration is enabled
active pull down if supply voltage is high enough
pull up of open drain output is active
start of watchdog sequence after release of reset
valid for all register bits which are not described in Table 5 or Table 6
During active delayed switch off mode some register bits related to the power stages are not reset, see Chapter 9.4
Data Sheet
24
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 6
Overview Behavior at Reset and Operation Conditions (part 2)
Effect to functions:
Conditions
Watchdog reset
Safe State
SW reset
MON switch off RST reset
MSC time out
from micro- (input function) (input function)
controller
afterrun reset
no reset
AR=0
reset AR=1
note
status during reset
pulse top,r
V5VSTBY, V6V
en.
en.
en.
en.
en.
en.
en.
en.
V5V, T5V1, T5V2
en.
en.
en.
en.
en.
en.
en.
en.
MSC/SPI
communication
dis.
en.
en.
en.
dis.
en.
en.
dis.
Main relay
en.1)
en.
en.1)
en.1)
en.1)
en.1)
en.1)
en.1)
Low-side switches /
off/dis./off
Half bridges / Push Pull
Driver
off/dis./off
off/dis./off3) off/dis./off
off/dis./off
off/dis./off
no change
off/dis./off
no trigger if
OUT17 and OUT21
with delayed switch off termination of
delayed switch off
function
function
no trigger if dis.3)
termination
of delayed
switch off
function
delayed switch
off activated
delayed switch
off activated
en.
dis.
Data Sheet
status
masked by MON masked by RST status till next
during reset output function output function valid MSC
pulse tint,r
communication
delayed switch
off activated
25
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 6
Overview Behavior at Reset and Operation Conditions (part 2) (cont’d)
Effect to functions:
Conditions
Watchdog reset
Safe State
SW reset
MON switch off RST reset
MSC time out
from micro- (input function) (input function)
controller
afterrun reset
no reset
AR=0
reset AR=1
LIN/CAN
communication
acc. bits CAN, LIN,
CANWE, LINWE
acc. bits
CAN, LIN,
CANWE,
LINWE
acc. bits
CAN, LIN,
CANWE,
LINWE
acc. bits CAN,
LIN, CANWE,
LINWE
rec. only, after
release setup
acc. bits CAN,
LIN, CANWE,
LINWE2)
acc. bits CAN,
LIN, CANWE,
LINWE
acc. bits
CAN, LIN,
CANWE,
LINWE
rec. only,
after
release
setup acc.
bits CAN,
LIN,
CANWE,
LINWE2)
MON
“low”
“low”
“low”3)
forced from
outside
“low”
no effect4)
no effect4)
“low”
RST
“low”
no effect4)
no effect4)
no effect4)
forced from
outside
no effect4)
no effect4)
“low”
Watchdog Sequence,
Heartbeat Timer5)
reset
no effect
reset
no effect
reset
no effect
no effect
reset
WWD Error Counter,
FWD pass counter,
Total error counter
reset
no effect
reset
no effect
reset
no effect
no effect
reset
PD Counter
no effect
no effect
increment
+1
no effect
no effect
no effect
no effect
no effect
Reset Counter; SSOT
no effect
no effect
no effect
no effect
no effect
no effect
no effect6)
no effect6)
AR; CANWE; LINWE;
FWDQUEST
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
Data Sheet
26
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 6
Overview Behavior at Reset and Operation Conditions (part 2) (cont’d)
Effect to functions:
Conditions
Watchdog reset
AE; WWDConfig0;
reset
WDConfig0; watchdog
diagnosis bit
Safe State
SW reset
MON switch off RST reset
MSC time out
from micro- (input function) (input function)
controller
afterrun reset
no reset
AR=0
reset AR=1
no effect
reset
no effect
reset
no effect
no effect
reset
Logic and MSC/SPI
register bits7)8)
no effect
no effect
reset
no effect
reset
diagnosis bit is
set
no effect
reset
EOTWK, CANWK,
WKINT
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
1)
2)
3)
4)
5)
6)
7)
8)
according the definition in Chapter 7
after release of RST (transition from low to high) there is a time delay of tdel,r before configuration is enabled
status for time top,r
pull up of open drain output is active
start of watchdog sequence after release of reset
SSOT reset due to KEY = 1
valid for all register bits which are not described in Table 5 or Table 6
During active delayed switch off mode some register bits related to the power stages are not reset, see Chapter 9.4
Data Sheet
27
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 7
Reset Time Definition
Reset Function
Reset Time at RST Output Related Status Bits in Register
OpStat1
internal power on reset
all registers are reset
ECU power on reset
tpu,r
Undervoltage V5V
tpu,r
V5VUVR
Overvoltage V5V
tpu,r
V5VOVR
Watchdog reset
top,r
WDRES
RST reset forced from outside
forced from outside
RSTR
Software reset from microcontroller
no effect
all registers are reset1)
Afterrun reset
AR=”0”
no effect
AR=”1”
top,r
ARES
1) internal reset with tint,r active
After a reset with pin RST the configuration of the CAN and LIN bus is delayed by the time tdel,r to avoid that
undefined microcontroller pins are affecting the buses. During this delay time the configuration bits can be
changed by a write access to the register.
Data Sheet
28
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
5.3
Electrical Characteristics Operation Behavior
Table 8
Electrical Characteristics: Operation Behavior
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
P_5.3.1
Internal power on reset
threshold
Vpor,int,th
–
–
2.8
V
of internal supply
voltage
Supply voltage range for
internal supply
VBATP,int
4.5
–
–
V
VV6V,int
3.5
–
–
V
P_5.3.2
only valid if the
charge pump has
ramped up before
voltage drop,
both condition
must be fulfilled to
ensure no internal
power on reset
Power-down time 1
tpd,1
–
100
–
ms
–
P_5.3.3
Power-down time 2
tpd,2
–
200
–
ms
–
P_5.3.4
Power-down time 3
tpd,3
–
300
–
ms
–
P_5.3.5
Power-down time 4
tpd,4
–
400
–
ms
–
P_5.3.6
Power-down time accuracy
tpd,a
-10
–
+10
%
–
P_5.3.7
tru
185
–
650
ms
–
P_5.3.8
Input low level
Vil
–
–
0.29*V V
5V
–
P_5.3.10
Input high level
Vih
0.7*V5 –
V
–
V
–
P_5.3.11
Input hysteresis
Vihys
0.1
–
1
V
–
P_5.3.12
Pull up current
Iimax
-100
–
–
µA
Vin = 0 V,
pull up to V5V
P_5.3.13
Input de-glitch time for low
and high level detection
ti,d
0.5
–
3.5
µs
–
P_5.3.14
Output low level operation
Vol
–
–
0.7
V
Iout = 2 mA;
VV5V = 2.5 V
P_5.3.15
Output current capability
Iomax
151)
–
–
mA
VMON = 5 V
P_5.3.16
Vil
–
–
0.29*V V
DDIO
–
P_5.3.17
Power-Down Timer
Ramp Up timer
Ramp up time
MON In- Output
RST In- Output
Input low level
Data Sheet
29
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Operation Behavior
Table 8
Electrical Characteristics: Operation Behavior (cont’d)
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
Test Condition
Number
Max.
Input high level
Vih
0.7*VD –
DIO
–
V
–
P_5.3.18
Input hysteresis
Vihys
0.1
–
1
V
–
P_5.3.19
Pull up current
Iimax
-100
–
–
µA
Vin = 0 V,
pull up to VDDIO
P_5.3.20
Input de-glitch time for low
and high level detection
ti,d
0.5
–
3.5
µs
–
P_5.3.21
Output low level operation
Vol
–
–
0.7
V
Iout = 2 mA;
VV5V = 2.5 V
P_5.3.22
Output current capability
Iomax
151)
–
–
mA
VRST = 5 V
P_5.3.23
Power up reset time
tpu,r
12
16
20
μs
–
P_5.3.24
Operation reset time
top,r
1
2
4
μs
–
P_5.3.25
Internal reset time
tint,r
–
–
1
µs
–
P_5.3.26
Delay time after reset
tdel,r
6
10
14
µs
–
P_5.3.27
Reset Times
1) Application must ensure that current into this pin does not exceed this value.
Data Sheet
30
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
6
Monitoring Watchdog Module (Signature Watchdog)
The watchdog function is intended for a temporal and logical monitoring of the microcontroller’s program
sequence. In Figure 6 the block diagram of the monitoring module is drawn. The module has an interface to
the MSC/SPI block. The monitoring of the microcontroller is done by the separate check of the timing with the
window watchdog and the logical operation check by the functional watchdog. Therefore the microcontroller
must send a window watchdog service command for the window watchdog and four response bytes for the
functional check. The results of the checks affect the corresponding counter (window watchdog error counter
or functional watchdog pass counter). Additionally a total error counter module is implemented which
detects the occurrence of watchdog errors (the timing check or the functional is not passed) and changes the
status of the total error counter accordingly.
For the independent functional watchdog and the total error counter a heartbeat is implemented to define the
increment timing of both functions.
Micro Controller
Interface
Watchdog Heartbeat
Window Watchdog
Service Command
Response
Increment
Pass WWD
fail
Decrement
Fail WWD
Error Check
Statemachine
fail
Increment
Window Watchdog
Statemachine
Question
Functional
Watchdog
Statemachine
Pass FWD
Decrement
Decrement
Window Watchdog
Error Counter
Total Error Counter
OF
OF
Functional
Watchdog Pass
Counter
Increment
OF
Reset/Disable Signal Generation
Window
Watchdog
Power Down
Counter
(Overflow )
Total Error
Power Down
Counter
(Overflow )
RST
Figure 6
Data Sheet
Functional
Watchdog
Power Down
Counter
(Overflow )
Reset Counter
(Overflow)
Power down
&
Restart
MON
Block diagram of the Monitoring Watchdog Function
31
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
The status of the counters (window watchdog error counter, functional watchdog pass counter and total error
counter) and the corresponding overflow signals are inputs to the watchdog reset, power-down counter and
the secure shut off timer. This information is used to affect the operation status of the TLE8888-1QK and the
status of the pins MON and RST.
The software of the microcontroller has to make sure that the program sequence and any safety critical parts
of the microcontroller are self tested by performing related routines according to the received questions.
Table 9
Bit Name
Register
Type
Description
WDRES
OpStat1
status
reset caused by watchdog (general status bit)
RESC
WdStat0
status
reset counter value
SSOTS
WdStat0
status
Secure shut off timer start status
WDHBTPRE
WDHBT0
status
heartbeat timer pre divider value
WDHBT
WDHBT1
status
heartbeat timer value
WDHBTP
WDConfig0
configuration definition of heartbeat period for functional watchdog and
total error counter
CANWE
WDConfig1
configuration CAN operation mode during safe state
LINWE
WDConfig1
configuration LIN operation mode during safe state
WDREN
WDConfig1
configuration watchdog reset enable
FWDQG
WDConfig1
configuration Functional watchdog question generation pattern setup
MSCReadWd0
command
Multi read command for WdStat0, TECStat, FWDStat0,
FWDStat1, WdDiag, WWDStat, WDConfig0 and
WWDConfig0
MSCReadWd1
command
Multi read command for WDHBT0, WDHBT1, WdStat0 and
WdStat1
General
WDHBTS
WDHBTPSyncC command
md
heartbeat period synchronization command
Cmd0
command
watchdog heartbeat timer sample command
Window Watchdog
WWDEC
WWDStat
status
value of error counter for window watchdog
WWDSCR
WdStat0
status
Window watchdog service command received status
WWDPDC
WdStat0
status
power-down counter value of window watchdog
WWDECI
WWDConfig1
configuration definition of the increment value of error counter for window
watchdog
WWDECD
WWDConfig1
configuration definition of the decrement value of error counter for
window watchdog
WWDCWT
WWDConfig0
configuration closed window time
WWDOWT
WWDConfig0
configuration open window time
WWDServiceC
md
command
window watchdog service command
WWDSCE
WdDiag
diagnosis
window watchdog service command too early
WWDTO
WdDiag
diagnosis
window watchdog time out
Data Sheet
32
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
Table 9
(cont’d)
Bit Name
Register
Type
Description
WWDRES
WdDiag
diagnosis
reset caused by window watchdog
Functional Watchdog
FWDQUEST
FWDStat1
status
question definition
FWDRESPC
FWDStat1
status
response counter
FWDPC
FWDStat0
status
pass counter value of functional watchdog
FWDPDC
WdStat1
status
power-down counter value of functional watchdog
FWDPCI
FWDConfig
configuration definition of the increment value of pass counter for
functional watchdog
FWDPCD
FWDConfig
configuration definition of the decrement value of pass counter for
functional watchdog
FWDKQ
WDConfig1
configuration Keep question function set up
FWDRespCmd
command
response write command
FWDRespSync
Cmd
command
response write command with heartbeat synchronization at
received response byte 0
FWDREA
WdDiag
diagnosis
response error of actual question
FWDREL
WdDiag
diagnosis
response error of last answer
FWDRES
WdDiag
diagnosis
reset caused by functional watchdog
Total Error Counter
TEC
TECStat
status
total error counter value
TECPDC
WdStat1
status
power-down counter value of total error counter part
TECI
TECConfig
configuration definition of the increment value of total error counter
TECD
TECConfig
configuration definition of the decrement value of total error counter
TECRES
WdDiag
diagnosis
6.1
reset caused by total error counter
Window Watchdog
For the timing check the microcontroller has to send periodically the window watchdog service command
WWDServiceCmd. The window watchdog is triggered correctly if the command is received inside the open
window of the window watchdog sequence. The check result is used to change the value of the window
watchdog error counter. If the check is passed the counter will be decremented and for errors it will be
incremented. Additionally a write access to configuration register WWDConfig0 causes also an
incrementation of the window watchdog error counter. The incrementation of the window watchdog error
counter (error is occurred) is an input for the total error counter (Chapter 6.3). In Figure 7 the state machine
of the window watchdog is shown.
The values for incrementation or decrementation can be set in the configuration register WWDConfig1. The
window watchdog error counter is a 6 bit counter. The influence of the counter values to the operation
behavior is shown in Table 11 and Table 12.
The window watchdog sequence for the timing check consists of a closed window followed by an open
window (see Figure 8). A watchdog sequence starts with:
•
the release of a reset of the monitoring module (see Table 5 and Table 6 in Chapter 5.2)
•
a window watchdog service command
Data Sheet
33
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
•
a write to the window time configuration register WWDConfig0
•
a timer overflow of the watchdog timer
In Figure 8 the two parts of one watchdog sequence are shown. After the power on reset it is running in an
endless loop with the defined time for the open and closed window. It is only stopped at active reset signals
or outside normal operating conditions Table 5 and Table 6 in Chapter 5.2.
The timing of the window watchdog sequence can be set with a write command to the configuration register
WWDConfig0 or directly with the data bits of the WWDServiceCmd. With a write access to the configuration
register WWDConfig0 the watchdog window sequence is started and the window watchdog error counter is
incremented.
The check is passed if the command is received inside the open window. A command send too early or a
missing command leads to an error. In the diagnosis register WdDiag the bit WWDSCE signalizes a window
watchdog service command received too early and the bit WWDTO signalizes a time out (no window
watchdog service command received before end of open window) of the last sequence. The diagnosis
information is not cleared with the read out.
The bit WWDSCR in the status register WdStat0 signalizes a received window watchdog service command at
the last watchdog sequence. The reset of this bit is done with a readout of the bit or with the window watchdog
time-out.
Reset
Start
watchdog
sequence
Inside open
window
Increment
WWD error
counter
WWD error:
Outside open
window
Decrement
WWD error
counter
WWD error:
Timer expired
OR
Write access to
WWDConfig0
Waiting for
WWD
service
command
WWD
service
command
Timing check
Figure 7
Data Sheet
State Diagram of the Window Watchdog Module
34
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
Correct Timing of WWDService Command
t C1
tO1
t C2
t O2
t C3
CSN
WWD Service
Command
WWD Service
Command
WWD Service
Command
Wrong Timing of WWDService Command
t C1
tO1
tC1
tO1
tC2
tO2
CSN
WWD Service
Command
WWD Service
Command
Time out
Figure 8
Watchdog Sequence Timing
6.2
Functional Watchdog
Too early
For the functional check the microcontroller has to send with the commands FWDRespCmd (functional
watchdog response command) or FWDRespSyncCmd (functional watchdog response and synchronisation
command) the right four response bytes to the actual question defined by the TLE8888-1QK. The response
bytes are checked for correctness.
A pass of the check triggers a decrement of the functional watchdog pass counter. A functional watchdog error
(FWD error) is not affecting the functional watchdog pass counter but it is used for the total error counter as
an input signal (see Chapter 6.3). A FWD error is defined as:
•
received response byte 0 with FWDRespCmd and minimum one of the response bytes are wrong
•
received response byte 0 with FWDRespSyncCmd and minimum one of the response bytes are wrong
•
the watchdog heartbeat timer period synchronisation command WDHBTPSyncCmd is received
In the diagnosis register WdDiag the bit FWDREA signalizes an error of the received response bytes to the
actual question and the bit FWDREL signalizes an error of the response bytes of the last answer. With a read
out the diagnosis bits are not cleared.
To detect that the functional check is missing a heartbeat is implemented. With an heartbeat event the
functional watchdog pass counter is incremented. An heartbeat event occurs:
•
with expiring of the heartbeat period timer or
•
with receiving the watchdog heartbeat period synchronisation command WDHBTPSyncCmd (response
counter is also reset) or
•
with receiving the functional watchdog response and synchronisation command FWDRespSyncCmd if
response byte 0 is received
The heartbeat period can be set by a write access to the configuration register WDConfig0 or by the watchdog
heartbeat period synchronisation command WDHBTPSyncCmd. If the data is 000 0000B the value of the
Data Sheet
35
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
heartbeat period is not changed.
Behavior of the heartbeat period in case of changing the period time:
•
WDHBTPSyncCmd: the response counter and the heartbeat timer are reset and a heartbeat event is
triggered, the new value of the period is executed with next period.
•
write access to the configuration register WDConfig0: the new value of the period is effective after the
write command. If the new value is lower than the actual heartbeat timer value then the heartbeat event
is immediately triggered otherwise the actual period length is immediately changed to the new value.
The functional watchdog pass counter is a six bit counter (see status register FWDStat0). The values for
incrementation or decrementation can be set in the configuration register FWDConfig. The influence of the
counter values to the operation behavior is shown in Table 11 and Table 12.
In Figure 9 the state machine of the functional watchdog is shown. There are two possible principles available
to serve the function watchdog:
•
unsynchronized heartbeat and use of functional watchdog response command FWDRespCmd and write
access to the configuration register WDConfig0 to change the heartbeat period time or
•
heartbeat is started with receiving the functional watchdog response and synchronisation command
FWDRespSyncCmd and use of the watchdog heartbeat period synchronisation command
WDHBTPSyncCmd for changing the heartbeat period
The commands can be used in all possible combinations without restrictions. Using FWDRespCmd has the
advantage that with fast correct responses the decrement of the functional watchdog pass counter can be
speed up.
The bit FWDKQ in the configuration register WDConfig1 is used to enable the keep question function for the
functional watchdog. If the bit is set in case of a passed functional check the next functional check procedure
is done with the same question if minimum one of the bits WWDSCE or WWDTO is set (window watchdog
error).
Data Sheet
36
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Response
check
Waiting for
response 2
FW
FW
Reset
Waiting for
response 3
Response
check
FWD error: WDHBPSynchCmd received
Define start
question
d
m
d
pC
Cm
es
ch
DR R yn d
O
pS ve
FW
es ce i
DR r e
FW
D
R
D
Re O es
pC
s
R
re pS
m
ce y
d
iv n c
ed h C
m
d
Monitoring Watchdog Module (Signature Watchdog)
Increment FWD
pass counter
AND
Restart Heartbeat
Timer
D
WW3.)
No r ror
e
WWD error3.)
Define next
question
FWD pass
1.)
counter change
AND
FWDRespCmd
OR
FWDRespSynchCmd
received
Response
check
FWD error :
Wrong
response 2.)
No WWD
error3.)
error
WWD
3.)
Restart Heartbeat
Timer
Waiting for
response 1
Correct
response
Response
check
FWDRespSynchCmd
received
Decrement
FWD pass
counter
Waiting for
response 0
FWDRespCmd
received
Correct
response
1.)
change value = sum of decrement and increment
value
2.)
wrong response event is also input for the error
check statemachine
3.)
only active if bit FWDKQ=1 , for FWDKQ=0
transition of „No WD error“ is executed
WWD error: minimum one of the bits WWDSCE or
WWDTO in register WDDiag is high;
Response
check
FWD error:
Wrong
response 2.)
Figure 9
Functional Watchdog State diagram
6.2.1
Question and Response Definition
The bits FWDQUEST in the watchdog status register FWDStat1 represent the actual valid question.
The reset value is 0000B and it will be changed regarding the definition of the state machine for the monitoring
module (see Figure 7). The expected response is shown in Table 10. The answer of the microcontroller is done
by a write access to the command registers FWDRespCmd or FWDRespSyncCmd.
The actual value of the bits FWDRESPC in the watchdog status register FWDStat1 defines the interpretation
of the 8 bit content of these commands as RESP3 to RESP0 (definition see FWDRESPC).
Data Sheet
37
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
The definition of the next question is done with a pseudo random algorithm. With the bit FWDQG in the
configuration register WDConfig1 the generation algorithm for the questions is defined. There are two
settings:
•
question pattern length 16: 16 question repeated every 16th watchdog sequence with a minimum
hamming distance of 3
•
question pattern length 256: every 256 question the order of the 16 questions is repeated, minimum
hamming distance is 1
Table 10
Questions and related Response
QUEST[3:0]
RESP3
RESP2
RESP1
RESP0
0
FF
0F
F0
00
1
B0
40
BF
4F
2
E9
19
E6
16
3
A6
56
A9
59
4
75
85
7A
8A
5
3A
CA
35
C5
6
63
93
6C
9C
7
2C
DC
23
D3
8
D2
22
DD
2D
9
9D
6D
92
62
A
C4
34
CB
3B
B
8B
7B
84
74
C
58
A8
57
A7
D
17
E7
18
E8
E
4E
BE
41
B1
F
01
F1
0E
FE
6.3
Total Error Counter Module
The total error module is used to count the errors of the window watchdog and the functional watchdog. In
Figure 10 the error check state machine is shown. If a watchdog error of the functional or the window
watchdog occurs the state machine enters the state “error occurred” and with the next heartbeat event
(definition see Chapter 6.2) the total error counter is incremented.
The counter is also incremented if a functional watchdog error or at the same time a window watchdog error
occurs by using the FWDRespSyncCmd. With the WDHBTPSyncCmd always an increment of the total error
counter is done. A decrement of the total error counter is only possible by using the FWDRespSyncCmd and
no errors are occurred.
The decrement and increment value of the total error counter can be set with the configuration register
TECConfig. The status of the total error counter is available in the status register TECStat.
Data Sheet
38
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
Error Check Statemachine
WWD or
FWD error
Decrement
Total error
counter
Error
occured
Hear
tbe
even at
t
Wait for
error
d l
m na r)
cC tio rro
yn nc e d
pS ( fu WD Cm
es d W nc
n
DR d a or PSy
d
FW ive ile BT
ce f a H
re ck D
e W
ch o r
FW
DR
rec esp
(fu eiv Syn
n
e
pa ction d an cCm
sse al
d d
WW d a che
c
n
De dn k
rro o
r)
Reset
Increment
Total error
counter
Figure 10
State diagram of the Error check State machine for the Total Error Counter Module
6.4
Watchdog Reset Counter
The watchdog reset counter is a three bit counter (bits RESC in WdStat0) and is triggered by an overflow of
one of the three counters of the monitoring functions (see Figure 11). The reset counter can only be
incremented by 1. Each time the watchdog reset counter changes the value a watchdog reset occurs
depending on the status of watchdog reset enable bit WDREN in the configuration register WDConfig1. The
counter stops counting if WDREN = “0” or at full scale. There are no further resets if full scale is reached. The
behavior at the different reset conditions is defined in Chapter 5.2 Table 5 and Table 6.
6.5
Power-Down Counter
There are three power-down counters with three bits implemented. The window watchdog power-down
counter (bits WWDPDC in status register WdStat0) is triggered by an overflow of the window watchdog error
counter, the functional watchdog power-down counter (bits FWDPDC in status register WdStat1) is triggered
by an overflow of the functional watchdog pass counter and the total error power-down counter (bits TECPDC
in status register WdStat1) is triggered by an overflow of the total error counter (see Figure 11).
If a trigger occurs the dedicated power-down counter is incremented by 1. Additionally all three power-down
counters are incremented by 1 if a software reset occurs. The power-down counters are reset if the ready state
is reached (see Table 11 and Table 12).
With an overflow of minimum one of the three power-down counters a power-down of the TLE8888-1QK is
performed if KEY is “low” (see Chapter 5.1). This function can not be disabled. The behavior at the different
reset conditions is defined in Chapter 5.2 Table 5 and Table 6.
6.6
Secure Shut Off Timer
The secure shut off timer (SSOT) is reset with KEY = 1 and the timer starts with an overflow of one of the three
counters of the monitoring functions (see Figure 11) if it is enabled with KEY = 0. If the timer is expired after
the Secure shut off time a power-down of the TLE8888-1QK is performed (see Chapter 5.1).The behavior at
the different reset conditions is defined in Chapter 5.2 Table 5 and Table 6.
Data Sheet
39
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Monitoring Watchdog Module (Signature Watchdog)
6.7
Operation State Definition and Reset Generation
The values of the three counter of the monitoring module are affecting the operation state of the TLE88881QK. There are three states defined:
•
the safe state: this is the reset state. The bits O1E to O24E and IGN1E to IGN4E in the configuration register
OEConfig0 to OEConfig3 are set to “0” to ensure that all actuators are switched off.
•
ready state: the device can be operated without restrictions.
•
watchdog reset: a reset is performed according the definition in Table 5 and Table 6.
The definition of the three states is shown in Table 11. The states are affecting the status of the pins MON and
RST, the power-down counter, the secure shut off timer and the reset counter (definition see Table 12).
Table 11
Definition of Reset, Safe and Ready State
Safe State
WWDEC>32D OR FWDPC >32D OR TEC>32D
Ready State
WWDEC VWK,th1)
WK active
WK inactive
WKINT=1
WKINT=0
VW
&
WK
<
1)
h
K, t
W
1
> V L R=
WK WKC
K , t 1)
h
WK < VWK,th & WKCLR=1
WK
disabled
1)
transition after Wake Up
detection Filter Time
WKINT=0
Figure 20
State Diagram of the Wake State Machine for Internal Wake Signal
At the beginning of the functional diagram of Figure 21 a normal wake-up sequence with a wake signal of the
pin WK is shown. In the second part of the diagram the signal of pin WK stick at high (e.g. short to battery) and
the microcontroller must send a wake clear command (bit WKCLR = 1 in command register Cmd0) for entering
the ECU sleep mode. With a low at pin WK the wake state machine is set to the state “WK inactive” and a wakeup by pin WK is enabled.
Data Sheet
49
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
Wake Up by Signal at Pin WK ; KEY = EOTWK = CANWK = 0; AE=0
WK
t
Status Wake
1)
Statemachine
WK
inactive
WK
active
WK
inactive
WK active
WK disabled
WK
inactive
WK
active
Internal Wake
Up signal
WKINT1)
t
MSC Communication
CSN
ECU
Sleep
ECU
Sleep
ECU Sleep
t
Set
WKCLR=“1“
Set
WKCLR=“1“
1)
Wake Up Detection Filter Time is not
shown in the diagram
Figure 21
Functional Diagram for Internal Wake Signal
Wake Up by Signal at Pin WK ; KEY = EOTWK = CANWK = 0, AE=1
WK
t
WKINT1)
t
wake
1)
Set
WKCLR=“1“
Wake Up detection Filter Time is
not shown in the diagram
Figure 22
Functional Diagram of Detection of Two Internal Wake Signals
7.3
Main Relay Driver
t
The main relay driver is designed to switch on the main relay of engine management applications. It integrates
a reverse protected low-side switch with active clamping freewheeling. The output is protected against
overload with an overtemperature detection and an overcurrent protection circuit. At low battery voltage
(V5V main supply is below undervoltage detection threshold e.g. during cranking) the main relay stays on.
The on resistance is related to the supply voltage at pin BAT and is defined down to 4.5 V.
The main relay is automatically switched on with a wake-up signal according to Table 14. The main relay is
normally switched off automatically according the power-down procedure defined in Chapter 5.
With write access to the command bit MRON of the command register Cmd0 the main relay can be switched
Data Sheet
50
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
additionally by MSC/SPI control according to the status of KEY, WK, EOTWK and CANWK (see Table 15). The
status of the main relay is available in the status register OpStat0 bit MR.
Table 15
Effect of MSC/SPI Write Command Bit MRON
KEY = 0, WK = EOTWK = CANWK = X
MR is switched according to write command
KEY = 1, WK = EOTWK = CANWK = X
MR is always switched on
The main relay driver is protected against overcurrent and overtemperature. In the case of overcurrent and/or
overtemperature the output is switched off and is switched on again after release of the failure condition. This
leads to a repetitive switching. A minimum off time tMR,off is implemented to ensure no destruction due to
repetitive switching.
7.4
Engine Off Timer
The engine off timer is integrated to measure the time in ECU sleep mode. Additionally the comparator mode
is implemented to wake-up the TLE8888-1QK after a defined time. It is internally supplied out of the standby
supply pin V5VSTBY. With the pin EOTEN the function is enabled with a connection to V5VSTBY and
disabled with a connection to AGND. It consists of an oscillator optimized for low current operation, a counter
and a comparator. The counter counts up to 36 hours and if the counter value reaches the comparator
threshold an internal wake-up signal is generated. The activation of the comparator mode is done with a
definition of a comparator threshold greater than 0000H in configuration registers EOTConfig0 and
EOTConfig1. There are two operation modes implemented:
•
Counter Mode: only counter is working, no wake-up with comparator threshold
•
Comparator Mode: counter operation like counter mode, additional wake-up with comparator threshold
In comparator mode the internal EOTWK flag is set if the counter is equal to compare value in the
configuration registers EOTConfig0 and EOTConfig1. The reset of the EOTWK flag is done with the bit WKCLR
in the command register Cmd0 if the counter value is not equal to the compare value.
V5VSTBY
Oscillator
Counter
Comparator
Start
EOTEN
KEY
Figure 23
KEY
Detection
EOTWK
flag
EOTWK
EOTRES
WKCLR
Digital Block
MSC/SPI
Interface
SIN
SDO
Block Diagram Engine Off Timer
The start of the counter can be configured with the bit EOTCONF in the configuration register OpConfig0 to
•
start by KEY signal (reset value) and
•
start by MSC command
Data Sheet
51
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
With the falling edge of the KEY signal or with the execution of the MSC command the counter is reset and
starts counting (see Figure 24). The start command is performed with setting the bit EOTS to “1” in the
command register Cmd0.
The status bit EOTRES (register OpStat1) is implemented to highlight that a standby reset has happened. With
the start of the counter this bit is reset. Therefore the status of this bit must be readout before the start of the
engine off timer.
The 24 bits of the counter are available in the status register EOTStat0, EOTStat1 and EOTStat2. For easier
access to the engine off timer status the multiple read command MSCReadDiag0EOT is implemented.
After wake-up the counter doesn’t stop counting. A readout of the counter value doesn’t stop counting. With
this behavior it is possible to measure the counting time with the microcontroller (see Figure 25).
With a read out of two counter values in a defined time a correction factor can be calculated (difference of
counter values divided by the time between the two read outs). With this measurement of the correction
factor only the variation caused by the temperature of the timer are effective. The absolute variations are
corrected by the correction factor. There are no restrictions for the measurement time but due to the
resolution of the counter a minimum measurement time ∆t of 1 s is recommended.
After power-up of the engine off timer circuit with a supply ramp up at pin V5VSTBY the counter value and
the comparator threshold are reset to the reset value. Additionally the bit EOTRES in the status register
OpStat1 is set to “1”.
Any other resets like ECU power on reset have no impact to the engine off timer counter. The compare
configuration register EOTConfig0 and EOTConfig1 are cleared with an ECU power on reset.
The counter stops counting at full scale. If a standby supply reset occurs the counter stops counting and is
reset to “0”.
WK = EOTWK = CANWK = 0; AE=0
Configuration „Start by Key Signal“
Configuration „Start by Command“
KEY
t
EOT Counter Value
full scale
t
MSC Communication
CSN
ECU Sleep
ECU
Sleep
ECU Sleep
t
readout
counter
value
Figure 24
Data Sheet
set
configuration
„start by
command“
command
start
counter
Function Diagram Engine Off Timer Counter Mode
52
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
WK = EOTWK = CANWK = 0; AE=0
KEY
t
EOT Counter Value
full scale
t
MSC Communication
CSN
ECU
Sleep
t
∆t
readout
counter
value 1
Figure 25
readout
counter
value 2
Correction Factor =
value 2 – value 1
∆t
Function Diagram Engine Off Timer Correction Factor Measurement
In comparator mode there is no difference in the behavior of the counter as described above. Additionally a
comparator threshold different to 0000H for wake-up is defined in the configuration register EOTConfig0 and
EOTConfig1. The comparator mode is enabled with a threshold value different to 0000H. If the counter value
is equal to the comparator threshold the internal wake-up signal EOTWK (status see bit EOTWK in the status
register OpStat0) of the TLE8888-1QK is active (see Figure 26).
With a wake-up clear command (set bit WKCLR to “1” in command register Cmd0) the internal EOTWK signal
is reset.
Table 16
Counter Definition
EOTC[23:0]
000000H
reset value
000001H to FFFFFFH 1/128 s to 131071 s = 36 h + 24 min + 31 s
Table 17
time resolution 1/128 s
Comparator Threshold Definition
EOTTH[15:0]
0000H
reset value
comparator mode disabled
0001H to FFFFH
2 s to 131070 s = 36 h + 24 min + 30 s
comparator mode enabled, time resolution 2 s
Data Sheet
53
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
KEY
t
EOTWK
t
EOT Counter Value
full scale
comparator
threshold
t
ECU
Sleep
MSC Communication
CSN
ECU
Sleep
ECU
Sleep
t
readout
counter
value
Figure 26
Data Sheet
set
WKCLR = “1"
command
start
counter
readout
counter
value
Function Diagram Engine Off Timer Comparator Mode
54
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
7.5
Electrical Characteristics Key Detection, Wake-up Detection and Main Relay
Driver
Table 18
Electrical Characteristics Key Detection
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note or
Test Condition
Number
Key On Detection Threshold
VKEY,th
3.6
–
4.5
V
rising edge
P_7.5.1
Key On Detection Hysteresis
VKEY,h
140
250
400
mV
–
P_7.5.2
1)
Input Current during wake-up
IKEY
–
–
0.55
mA
VKEY = 5 V
P_7.5.3
Input Current after wake-up
IKEY
–
–
0.7
mA
VKEY = VBAT
= 4.5 V
P_7.5.31
Key Detection Filter Time
tKEY,f
7.5
16
24
ms
VKEY = 5 V
P_7.5.4
Key Off Delay Time 1
tKEYoff,d,1
100
–
200
ms
–
P_7.5.5
Key Off Delay Time 2
tKEYoff,d,2
200
–
400
ms
–
P_7.5.6
Key Off Delay Time 3
tKEYoff,d,3
400
–
800
ms
–
P_7.5.7
Key Off Delay Time 4
tKEYoff,d,4
800
–
1600
ms
–
P_7.5.8
Output Current Capability
IKOFFDO
152)
–
–
mA
VKOFFDO = 5 V
P_7.5.9
KOFFDO Output Low Level
VKOFFDO,low
–
–
0.4
V
IKOFFDO < 1 mA
P_7.5.30
Output KOFFDO
1) not subject to production test, specified for design
2) Application must ensure that current into this pin does not exceed this value.
Table 19
Electrical Characteristics Wake-up Detection
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note or
Test Condition
Number
Wake-up Detection Threshold
VWK,th
3.6
–
4.5
V
rising edge
P_7.5.10
Wake-up Detection Hysteresis
VWK,h
140
250
400
mV
–
P_7.5.11
1)
–
–
0.55
mA
VWK = 5 V
Wake-up Detection Filter Time tWK,f
1
2
3.5
ms
VWK = 5 V
P_7.5.13
Battery Detection Threshold
3.5
–
5
V
VWK = 5 V
P_7.5.14
Input Current during Wake-up
IWK
VBat,th
P_7.5.12
1) not subject to production test, specified by design
Data Sheet
55
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
Table 20
Electrical Characteristics Main Relay Driver
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note or
Test Condition
Number
MR Operation Current
IMR
–
–
0.8
A
–
P_7.5.15
MR Overcurrent Limitation
IMR,oc
0.8
–
1.5
A
–
P_7.5.16
MR On Voltage
VMR
–
–
1.35
V
IMR = 0.3 A
P_7.5.17
MR switch off time in failure
case
tMR,off
16
27
–
ms
in case of
overcurrent
and/or overtemperature
P_7.5.32
MR On Voltage at Low Battery
Voltage, low temperature
VMR,l,LT
–
–
1.1
V
IMR = 0.1 A,
VBAT = 4.5 V
(decreasing)
TJ < 25°C
P_7.5.18
MR On Voltage at Low Battery
Voltage, high temperature
VMR,l,HT
–
–
1.05
V
IMR = 0.1 A,
VBAT = 4.5 V
(decreasing)
TJ > 25°C
P_7.5.19
MR Clamping Voltage
VMR,cl
40
–
60
V
IMR = 0.2 A
P_7.5.20
EMR,cl
–
–
6.5
mJ
IMR < 0.3 A,
Tj = 150°C,
40*106 cycles
P_7.5.21
MR leakage current in off mode, IMR.leak,pos
positive voltage
–
–
5
µA
VMR = 13.5 V,
VKEY = 0 V and
VWK = 0 V
P_7.5.22
MR leakage current in off mode, IMR.leak,neg
negative voltage
-100
–
–
µA
VMR = -13.5 V,
VKEY = 0 V and
VWK = 0 V
P_7.5.23
1)
MR Clamping Energy
1) not subject to production test
Table 21
Electrical Characteristics Engine Off Timer
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Min. Typ.
Max.
Unit Note or
Test Condition
-30
–
+30
%
VV5VSTBY = 5 V
P_7.5.24
Oscillator Frequency Variation Δfosc,T
over Temperature
-5
–
+5
%
VV5VSTBY = 5 V,
Tj = -40°C to
85°C, one single
device
P_7.5.25
Counter Resolution
–
1/128
–
s
–
P_7.5.26
Oscillator Accuracy
Data Sheet
Symbol
Δfosc,a
CEOT,r
Values
56
Number
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Wake-Up Detection and Main Relay Driver
Table 21
Electrical Characteristics Engine Off Timer (cont’d)
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Min. Typ.
Max.
Unit Note or
Test Condition
–
–
24
bit
–
–
131071 –
s
–
Additional current
IEOTSUP
consumption at pin BATSTBY
for enabled engine off timer
function
–
–
10
µA
VV5VSTBY = 5 V and P_7.5.28
no wake-up
IEOTSUP,w
Additional current
consumption at pin BATSTBY
for enabled engine off timer
function and wake-up1)
–
–
450
µA
VV5VSTBY = 5 V and P_7.5.29
wake-up
Counter Full Scale
Symbol
CEOT,fs
Values
Number
P_7.5.27
1) not subject to production test, specified by design
Data Sheet
57
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Supply
8
Power Supply
The power supply unit generates the internal supply (including supply for CAN and pre-drivers, voltage
reference and current biasing), the main supply voltage for the ECU (V5V) and sensor supplies for off- board
sensors (T5V1 and T5V2). All supplies start working by the wake-up signal generated by the key and wake-up
detection (see Chapter 7.2 for details).
A linear pre-regulator with an external logic level power MOSFET is implemented to keep the power
dissipation of the TLE8888-1QK low. The precise voltage supplies for the ECU and the sensor supplies are
integrated inclusive the power transistor. All supplies with low drop functionality (main supply V5V, preregulator, sensor supplies T5V1/T5V2) are using an integrated charge pump to provide low drop behavior at
low battery voltages.
BATSTBY
BATPA
CP
BATPB
BAT
Linear Preregulator
V5VSTBY
Standby
Regulator
Chargepump
Half Bridges
Ref
+
VG
V6V
Linear Regulator
Ref
VDDIO
+
-
To Micro
Controller
V5V
Digital
Outputs to
Micro
Controller
Tracker
VV5V
+
-
Key and Wake Up
Detection
T5V1
T5V2
Figure 27
Block diagram of the power supply
8.1
Pre-Regulator
The pre-regulator uses an external logic level power MOSFET and regulates the voltage at pin V6V. The
voltage at the pin is also the input voltage for the main supply of the ECU (V5V), the sensor supplies (T5V1,
T5V2) and the internal supply. The circuit is designed for low drop operation.
It's not allowed to load the external MOSFET with anything else than V6V. The function of the pre-regulator is
guaranteed with the MOSFET IPD30N06S2L-23 of Infineon.
Data Sheet
58
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Supply
8.2
5 V Main Supply
The 5 V main supply is designed to supply the ECU including microcontroller and e.g. other power chips. Out
of V6V a high accurate voltage is provided at the pin V5V. The pin and the circuit is protected against overload
and short circuit. For stabilization and ripple reduction an external buffer capacitor is required. For low drop
operation of the regulator the pins BATPA and BATPB must be supplied.
8.3
Sensor Supply
There are two sensor supplies integrated providing an output voltage based on V5V as reference. Out of V6V
a high accurate voltage is provided at the pins T5V1 and T5V2. The pins and the circuits are protected against
overload, short circuit and reverse supply back to V6V. For stabilization and ripple reduction external buffer
capacitors are required. For low drop operation of the regulator the pins BATPA and BATPB must be
supplied.
8.4
IO Supply
The TLE8888-1QK provides an IO supply pin VDDIO for 3.3 V and 5 V microcontroller interfaces. This pin is
used for the supply of the output driver and defines the output level of all logical interface pins.
8.5
Standby Supply
The TLE8888-1QK integrates a standby supply which is supplied by the pin BATSTBY and provides a 5 V
output supply at pin V5VSTBY. It is not allowed to connect this pin to any other supply.
8.6
Charge Pump
There is a charge pump integrated to supply the half bridges out of BATPA and BATPB. A capacitor has to be
connected on the PCB (between CP and BATPA/BATPB) to buffer the voltage and reduce the ripple. It's not
allowed to apply any external load to the pin CP.
8.7
Voltage Monitoring
The TLE8888-1QK provides voltage monitoring of the main ECU supply V5V, the sensor supplies T5V1 and
T5V2 and the battery voltage. In Chapter 5.2 the effect to the status of theTLE8888-1QK is described. All
detection thresholds are implemented with a hysteresis and a filter time to suppress disturbances.
The status of the over- and undervoltage detection of BAT, T5V1 and T5V2 are available in the diagnosis
resister Diag0 and the bits BATOV, T1UV, T1OV, T2UV and T2OV.
Under- and overvoltage of V5V leads to a reset of the microcontroller (see Table 5 in Chapter 5.2). After
release of the reset the cause of the reset is available in the status register OpStat1 (bits V5VUVR and
V5VOVR).
Data Sheet
59
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Supply
8.8
Electrical Characteristics Power Supply
Table 22
Electrical Characteristics Power Supply
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ Max.
.
IBAT,sum
–
–
50
mA
static, all “off”, no
PWM and MSC/SPI
communication
P_8.8.1
Pre-Driver Output Voltage V6V
VV6V
5.5
6
6.5
V
with respect to
AGND, with
external MOS FET
IPD30N06S2L-23
P_8.8.2
Gate Output Voltage VG
DVVG
4
–
7.5
V
VV6V = 5.5 V;
DVVG = VVG - VV6V
P_8.8.3
Gate Output Voltage VG at low
Supply
DVVG,l
1.7
–
–
V
VBATPx = 4.5 V,
IVG = 1 µA;
DVVG = VVG - VV6V
P_8.8.4
Buffer Capacitor at V6V1)
CV6V
1
20
1000
µF
2) 3)
P_8.8.37
ESRV6V
0.01
2
Ω
for CV6V < 15 µF,
fESR = 10 kHz
P_8.8.38
ESR of Buffer Capacitance at V6V1) ESRV6V
0.5
2
Ω
for 15 µF < CV6V < P_8.8.39
20 µF, fESR = 10 kHz
ESR of Buffer Capacitance at V6V1) ESRV6V
1
2
Ω
for 20 µF < CV6V <
1000 µF,
fESR = 10 kHz
P_8.8.40
Buffer Capacitor at VG1)
–
4.7
15
nF
2)3)
P_8.8.41
–
–
1
Ω
fESR = 10 kHz
P_8.8.42
P_8.8.5
current consumption at pins
BATPA, BATPB, BAT and V6V
Pre-Regulator
1)
ESR of Buffer Capacitance at V6V
CVG
ESR of Buffer Capacitance at VG1) ESRVG
5 V Main Supply V5V
Output Voltage V5V
VV5V
4.9
–
5.1
V
-5 mA < IV5V
< -500 mA, with
respect to AGND
Voltage Drop V6V-V5V at low
Supply
VV5V,d
–
–
0.6
V
IV5V = - 500 mA;
P_8.8.6
VBAT = VBATPx = VKEY
= VV6V = 4.5 V
Voltage Drop V6V-V5V at low
Supply and low temperature
VV5V,d,CT
–
–
0.45
V
Tj = -40°C;
P_8.8.7
IV5V = -500 mA;
VBAT = VBATPx = VKEY
= VV6V = 4.5 V1)
Current Limitation
IV5V,lim
-1200 –
-500
mA
–
Data Sheet
60
P_8.8.8
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Supply
Table 22
Electrical Characteristics Power Supply (cont’d)
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Buffer Capacitor at V5V1)
Values
Min.
Typ Max.
.
CV5V
0.1
10
ESRV5V
Unit Note or
Test Condition
Number
220
µF
2)3)
P_8.8.9
0.01
2
Ω
for CV5V < 10 µF,
fESR = 10 kHz
P_8.8.43
ESR of Buffer Capacitance at V5V1) ESRV5V
0.1
2
Ω
for 10 µF < CV5V < P_8.8.44
47 µF, fESR = 10 kHz
ESR of Buffer Capacitance at V5V1) ESRV5V
0.5
2
Ω
for
P_8.8.45
47 µF < CV5V < 220
µF, fESR = 10 kHz
DVT5Vx = VV5V VT5Vx,
4 V < VV5V < 5.1 V,
VV6V > 5.5 V,
VIGNx ≥ 0 V
1)
ESR of Buffer Capacitance at V5V
Sensor Supplies T5V1 and T5V2
P_8.8.10
Output voltage tracking accuracy
DVT5Vx
-10
–
10
mV
Current Limitation
IT5Vx,lim
-300
–
-100
mA
P_8.8.11
Buffer Capacitor at T5V1 and
T5V21)
CT5Vx
–
–
400
nF
P_8.8.12
IO Supply Voltage Range
VVDDIO
3
–
5.5
V
–
P_8.8.13
Current Consumption at pin
VDDIO
IDDIO
–
–
2
mA
VVDDIO = 5 V,
INx = 0 V,
CSN = LINTX =
CANTX = 5 V, MON
and RST open1)
P_8.8.14
Output Voltage V5VSTBY
VV5VSTBY
4.75
–
5.25
V
-10 µA < IV5VSTBY
< -15 mA
P_8.8.15
Total Standby Current
Consumption at pins BATSTBY,
BAT, V6V and MR
ISTBY
–
–
120
µA
P_8.8.16
ECU sleep mode,
Tj = 25°C,
IV5VSTBY = 0 mA,
VBATSTBY = VBAT =
VMR = 13.5 V,
EOTEN = CANWK
EN = 0 V
Buffer Capacitor at V5VSTBY1)
CV5VSTBY
27
100 270
nF
2)3)
ESR of Buffer Capacitance at
V5VSTBY1)
ESRV5VSTBY 0.01
–
Ω
IO Supply VDDIO
Standby Supply V5VSTBY
1
P_8.8.46
P_8.8.47
Charge Pump
Data Sheet
61
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Supply
Table 22
Electrical Characteristics Power Supply (cont’d)
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ Max.
.
Unit Note or
Test Condition
Number
Charge pump Output Voltage
DVCP
4
5
7
V
DVCP = VCP - VBAT
no external load
currents
P_8.8.17
Charge pump Output Voltage at
low supply
DVCP
3.5
–
–
V
VBAT = 4.5 V after
start up,
DVCP = VCP - VBATPx
P_8.8.18
Buffer Capacitor at CP1)
CCP
–
4.7
–
nF
V5V Undervoltage Detection
Threshold, decreasing
VUV,V5V,dec
4.45
–
4.7
V
VV5V decreasing
P_8.8.20
V5V Undervoltage Detection
Threshold, increasing
VUV,V5V,inc
4.45
–
4.8
V
VV5V increasing
P_8.8.21
V5V Undervoltage Detection
Hysteresis
VHys,UV,V5V
10
50
–
mV
–
P_8.8.22
V5V Undervoltage Filter Time
tf,UV,V5V
5
10
15
µs
–
P_8.8.23
T5V1 and T5V2 Undervoltage
Detection Threshold
VUV,T5Vx,dec
4.45
–
4.7
V
VT5Vx decreasing
P_8.8.24
T5V1 and T5V2 Undervoltage
Detection Threshold
VUV,T5Vx,inc
4.45
–
4.8
V
VT5Vx increasing
P_8.8.25
T5V1 and T5V2 Undervoltage
Detection Hysteresis
VHys,UV,T5Vx
10
50
–
mV
–
P_8.8.26
T5V1 and T5V2 Undervoltage
Filter Time
tf,UV,T5Vx
5
10
15
µs
–
P_8.8.27
V5V Overvoltage Detection
Threshold
VOV,V5V
5.2
–
5.6
V
VV5V increasing
P_8.8.28
V5V Overvoltage Detection
Hysteresis
VHys,OV,V5V
10
–
100
mV
–
P_8.8.29
V5V Overvoltage Filter Time
tf,OV,V5V
5
10
15
µs
–
P_8.8.30
T5V1 and T5V2 Overvoltage
Detection Threshold
VOV,T5Vx
5.2
–
5.6
V
VT5Vx increasing
P_8.8.31
T5V1 and T5V2 Overvoltage
Detection Hysteresis
VHys,OV,T5Vx
10
–
100
mV
–
P_8.8.32
T5V1 and T5V2 Overvoltage Filter tf,OV,T5Vx
Time
5
10
15
µs
–
P_8.8.33
BAT Overvoltage Detection
Threshold
28
–
30.4
V
VBAT increasing
P_8.8.34
P_8.8.19
Voltage Monitoring
Data Sheet
VOV,BAT
62
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Supply
Table 22
Electrical Characteristics Power Supply (cont’d)
VS = 13.5 V, VVSV = 5 V, Tj = -40°C to +150°C, all voltages with respect to GND, positive current flowing into pin,
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ Max.
.
Unit Note or
Test Condition
Number
BAT Overvoltage Detection
Hysteresis
VHys,BAT
50
–
500
mV
–
P_8.8.35
BAT Overvoltage Filter Time
tf,OV,BAT
5
10
15
µs
–
P_8.8.36
1) not subject to production test, specified by design
2) Defined minimum value is needed for regulator stability. Application might need higher value than minimum.
3) additionally in parallel a capacitance up to 0.1*CVxV and low ESR is allowed
Data Sheet
63
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Stages
9
Power Stages
In the TLE8888-1QK there are 14 low-side power stages, 4 half bridges, 4 push-pull outputs for on board and
external ignition driver and 6 push-pull outputs for on board MOSFETs implemented. The 14 low-side power
stages are designed for various inductive and resistive loads, 4 stages to drive especially injectors, 3 with a
higher operating current to drive e.g. O2-heaters and 7 stages to drive relays.
For the injector output stages (OUT1 to OUT4) the common enable input INJEN and for the ignition outputs
the common enable input IGNEN are implemented. The half bridges can be used with high or low-side load,
with active or passive freewheeling or in full bridge configuration.
Power Stage 2.2A
OUT1A OUT1B
INJEN
IN1
IN2
IN3
Protection
Overtemp
Overcurrent
Clamping
IN4
Diagnosis
OUT4A OUT4B
Open Load
Short to GND
Power Stage 4.5A
OUT5A OUT5C
Protection
Overtemp
Overcurrent
Clamping
Diagnosis
Open Load
Short to GND
OUT7A OUT7C
IN9
IN10
IN11
Push Pull Driver 20mA
IN12
DFBx
Diagnosis
DFB8
DFB13
digital block
MSC
OUT8
OUT13
Power Stage 0.6A
OUT14
^^
Protection
Overtemp
Overcurrent
Clamping
Diagnosis
Open Load
Short to GND
OUT20
CP
BATPA
Chargepump
BATPB
Half Bridge 0.6A
Protection
Overtemp
Overcurrent
OUT21
Diagnosis
Open Load
Short to GND
Short to Bat
OUT24
Ignition Driver 20mA
Diagnosis
IN5
IGN1
IN6
IN7
IGN4
IN8
IGNEN
Figure 28
Data Sheet
Block Diagram of the Power stages
64
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Stages
Overview Power Stages
Type
Ron
maximum
operation
current
active clamping
Table 23
Diagnosis in on
Diagnosis in off
OUT1 to OUT4
Low-side
switch
2.2 A
550 mW yes overcurrent (short to
battery)
overtemperature
open load
short to GND
overtemperature
OUT5 to OUT7
Low-side
switch
4.5 A
350 mW yes overcurrent (short to
battery)
overtemperature
open load
short to GND
overtemperature
OUT8 to OUT13
5 V push pull 20/output
20 mA
–
at pin DFBx:
open load
short to GND
no
at pin DFBx:
short to battery
at pin OUTx:
overvoltage
at pin OUTx:
overvoltage
OUT14 to OUT20
Low-side
switch
0.6 A
1.5 W
yes overcurrent (short to
battery)
overtemperature
open load
short to GND
overtemperature
OUT21 to OUT24
Half bridge
0.6 A
2.4 W
no
overcurrent (short to
battery/short to GND)
overtemperature
open load
short to
battery/short to GND
overtemperature
IGN1 to IGN4
5 V push pull 20/output
20 mA
–
no
short to battery
short to GND
open load
short to battery
9.1
Power Stage Control
The output stages will be controlled either by the MSC/SPI data frame or command frame and the control
register Cont0 to Cont3 (see Chapter 14.1.5) or the direct drive inputs IN1 to IN12. The configuration which
control mode is active is done in the configuration register DDConfig0 to DDConfig3 (see Chapter 14.1.4).
A “1” in the control register/data frame bit or a “high” at the direct drive inputs switches on the corresponding
output.
In Table 24 the assignment of the direct drive inputs to the output stages is shown. The set up is valid for MSC
and SPI operation.
The status of the power stages is also affected by the operation state and conditions of the TLE8888-1QK and
is described in Chapter 5. All power stages are switched off if a micro channel time out occurs. Description of
the effect to the control of the power stages see Chapter 13.1.1, Downstream Supervisory Functions.
Data Sheet
65
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Stages
Table 24
Direct Drive Input Assignment to Output Stages
Input
Output
Note
IN1 to IN4
OUT1 to OUT4
configuration for direct drive:
bits O1DD to O4DD of the configuration register DDConfig0
fix assignment of the inputs to the outputs
IN5 to IN8
IGN1 to IGN4
configuration for direct drive:
bits IGN1DD to IGN4DD of the configuration register DDConfig3
fix assignment of the inputs to the outputs
IN9 to IN12
OUT5 to OUT24
configuration for direct drive:
bits O5DD to O24DD of the configuration registers DDConfig0 to
DDConfig2
assignment of input pins:
configuration register InConfig0 to InConfig3
only 4 of this output stages can be switched directly
All direct drive inputs have implemented a pull down current source to define the input voltage.
For a multiple assignment of two direct drive inputs for one output stage (wrong configuration) the output is
switched off independent of the status of the direct drive inputs.
9.2
Power Stages Enable
To enable the power stages a central output enable bit OE is defined. The status of the bit is shown in the
status register OpStat1 and can be set with the command register CmdOE. Additional a dedicated output
enable bit for each output is defined (see register OEConfig0 to OEConfig3) to avoid uncontrolled repetitive
switching in failure case. These enable bits are reset by the protection function of each channel and block
switch on of the channels. The bits could not be set if a protection function is active.
With setting the central enable bit to “1” all dedicated output enable bits are set to “1” (if no protection
function is active) and all channels are enabled and can be controlled according their configuration.
With setting the central enable bit to “0” all dedicated output enable bits are set to “0” and all channels are
disabled.
For the injector channels OUT1 to OUT4 the common enable input INJEN must be set to “high” and for the
ignition outputs IGN1 to IGN4 the common enable input IGNEN must be set to “high” to enable the
channels.
Procedure to switch on after failure condition occurred:
•
Read out of diagnosis bits
•
Second read out to verify that the failure conditions are not remaining
•
Set of the dedicated output enable bit of the affected channel if the diagnosis bit is not active anymore
•
Switch on of the channel
Switch off during battery overvoltage:
To protect the power stages against high energy during freewheeling they are switched off for battery voltages
greater than the “BAT Overvoltage Detection Threshold” (see Table 22 in Chapter 8.8).
Data Sheet
66
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Stages
9.3
Power Stages Configuration
The power stages can be configured according the configuration bits in the configuration registers
OutConfig0 to OutConfig5, BriConfig0, BriConfig1 and IGNConfig. The direct drive input configuration is
described in Table 24.
Table 25
Configuration Overview Power Stages
Configuration
Configuration
Register
OUT1 to OUT4
overcurrent: current limitation or switch off
diagnosis in off: pull down current activated/deactivated
OutConfig0
OUT5 to OUT7
overcurrent: current limitation or switch off
diagnosis in off: pull down current activated/deactivated
OutConfig1
OUT8 to OUT13
at pin DFBx:
diagnosis in off:
pull down current activated/deactivated
diagnosis in on:
short to battery detection thresholds
OutConfig2
and
OutConfig3
bits 0 to 3
OUT14 to OUT20
mode set up: delayed switch off mode for OUT17
overcurrent: current limitation or switch off
diagnosis in off:
pull down current activated/deactivated (OUT14 to OUT17)
pull up and down current activated/deactivated (OUT18 to OUT20)
OutConfig3
bits 4 and 5,
OutConfig4,
OutConfig5
OUT21 to OUT24
mode set up:
active or passive freewheeling
high- or low-side switch mode
half or full bridge mode
delayed switch off mode for OUT21
BriConfig0 and
BriConfig1
IGN1 to IGN4
open load in activation/deactivation
open load current setting
open load detection time
IGNConfig
9.4
Special Function “Delayed Switch Off” for OUT17 and OUT21
A special set up for the control behavior of OUT17 and OUT21 is implemented. With the delayed switch off
functionality the outputs are suited to drive loads (e.g. starter relay) which must be on during very low battery
voltages even if the microcontroller is in reset e.g. due to undervoltage. In this operation conditions all other
power stages are normally switched off.
With the bits O17D in the configuration register OutConfig4 and O21D in the configuration register
BriConfig1 both outputs can be configured to:
•
normal control mode according description in Chapter 9.1
•
delayed switch off mode
For delayed switch off mode OUT17 and OUT21 must be configured as controlled by MSC/SPI (bits
O17DD/O21DD in configuration register DDConfig2 are set to “0”)
Delayed switch off mode for OUT21 is only allowed in high- or low-side switch configuration. Fullbridge
configuration is not allowed.
The delayed switch off mode keeps the two outputs on for the time ton,del after an trigger event. With the
trigger events in normal control mode the outputs are switched off.
Data Sheet
67
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Stages
In delayed switch off mode the delayed switch off timer starts with following trigger events:
The channel must be on before a trigger event, switch on of all channels during the delayed switch off mode
is not possible
•
undervoltage of the main supply V5V is detected
•
or overvoltage of the main supply V5V is detected
•
or the MSC time out occurs
•
or an active signal (“0”) at pin MON
•
or an active signal (“0”) at pin RST
With the bit RDOT in the command register Cmd0 the delayed switch off timer is restarted and the on time is
increased.
The delayed off mode is terminated with following events:
•
overflow of delayed off timer
•
O17/O21 are switched off with command CmdOE, set control register bits O17ON/O21ON or the
configuration register bits O17E/O21E to “0”
•
O17D/O21D are set to “0”
•
Ready State is active and no trigger event is active
The outputs are switched off immediately if an internal power on reset occurs. According to the definition in
Chapter 5.1 if the conditions for a state change to ECU sleep mode are fulfilled the delayed off is terminated
and the transition is executed.
Normally the related register bits of OUT17 and OUT21 are reset during undervoltage of the main supply
V5V or an active signal (“0”) at pin RST (definition see Table 5 and Table 6 in Chapter 5.2). In delayed switch
off configuration following register bits are not reset:
•
OE in status register OpStat1
•
O17E, O21E in configuration register OEConfig2
•
O17D, O17OL, O17OC in configuration register OutConfig4
•
O21F, O21M in configuration register BriConfig0
•
O21D in configuration register BriConfig1
For illustration in Figure 29 and Figure 30 two examples for the delayed switch off mode for are shown.
Data Sheet
68
Rev. 1.2
2017-02-10
TLE8888-1QK
Engine Machine System IC
Power Stages
Start of
delayed off
mode
Watchdog Operation
State
Ready State
Delayed Off Trigger
Status
no trigger event
Delayed Off Timer
reset
O17/O21
„1"
OE17/OE21
„1"
Remaining OEx
Bits
Safe State
e.g. V5VUV=1
no trigger event
Count up
ON
O17D/O21D
Remaining Power
Stages
Delayed off
timer
overflow
OFF
„0"
ON
OFF
„1"
„0"
OE
Figure 29
reset
„1"
Example for Delayed Off Behavior: Overflow of Delayed Off Timer
Start of
delayed off
mode
Watchdog
Error Counter
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