TLE94106ES
Features
•
Six half-bridge power outputs
•
Very low power consumption in sleep mode
•
3.3V / 5V compatible inputs with hysteresis
•
All outputs with overload and short circuit protection
•
Independently diagnosable outputs (overcurrent, open load)
•
Open load diagnostics in ON-state for all high-side and low-side
•
Outputs with selectable open load thresholds (HS1, HS2)
•
16-bit Standard SPI interface with daisy chain and in-frame response capability for control and diagnosis
•
Fast diagnosis with the global error flag
•
PWM capable outputs for frequencies 80Hz, 100Hz and 200Hz with 8-bit duty cycle resolution
•
Overtemperature pre-warning and protection
•
Over- and Undervoltage lockout
•
Cross-current protection
Potential applications
•
HVAC Flap DC motors
•
Monostable and bistable Relays
•
Side mirror x-y adjustment and mirror fold
•
LEDs
Product validation
Qualified for Automotive Applications. Product Validation according to AEC-Q100.
Description
The TLE94106ES is a protected six-fold half-bridge driver designed especially for automotive motion control
applications such as Heating, Ventilation and Air Conditioning (HVAC) flap DC motor control. It is part of a
larger family offering half-bridge drivers from three outputs to twelve outputs with direct interface or SPI
interface.
The half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation
modes forward (cw), reverse (ccw), brake and high impedance are controlled from a 16-bit SPI interface. It
offers diagnosis features such as short circuit, open load, power supply failure and overtemperature
detection. In combination with its low quiescent current, this device is attractive among others for automotive
Datasheet
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1
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2018-01-08
TLE94106ES
applications. The small fine pitch exposed pad package, PG-TSDSO-24, provides good thermal performance
and reduces PCB-board space and costs.
Type
Package
Marking
TLE94106ES
PG-TSDSO-24
TLE94106ES
Table 1
Product Summary
Normal Operating Voltage
VS
5.5 ... 18 V
Extended Operating Voltage
VS(EXT)
18 ... 20 V
Logic Supply Voltage
VDD
3.0 ... 5.5 V
Maximum Supply Voltage for Load Dump
Protection
VS(LD)
40 V
Minimum Overcurrent Threshold
ISD
0.9 A
Maximum On-State Path Resistance at Tj = 150°C RDSON(total)_HSx+LSy
1.8 + 1.8 Ω
Typical Quiescent Current at Tj = 85°C
ISQ
0.1 µA
Maximum SPI Access Frequency
fSCLK
5 MHz
Datasheet
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TLE94106ES
Table of Contents
1
1.1
1.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
2.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
3.4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
5.1
5.2
5.2.1
5.2.2
5.3
5.4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
23
23
24
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.4.1
6.2.4.2
6.2.4.3
6.2.5
Half-Bridge Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half-bridge operation with PWM enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED mode (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection & Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit of Output to Supply or Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross-Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage and undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
26
28
29
31
33
35
36
36
36
36
37
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.4
7.5
7.6
7.6.1
7.7
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI protocol error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI with independent slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status register change during SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
38
39
40
41
43
45
47
50
52
53
62
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7.7.1
Status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8
8.1
8.2
8.3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMC Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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68
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Pin Configuration
1
Pin Configuration
1.1
Pin Assignment
GND
OUT 1
OUT 5
N.C.
SDI
VDD
SDO
EN
N.C.
OUT 6
OUT 4
GND
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
Figure 1
Pin Configuration TLE94106ES
1.2
Pin Definitions and Functions
N.C.
OUT 2
NC
VS2
SCLK
CSN
N.C.
N.C.
VS1
NC
OUT 3
N.C.
Pin
Symbol
Function
1
GND
Ground. All ground pins should be externally connected together.
2
OUT 1
Power half-bridge 1
3
OUT 5
Power half-bridge 5
4
N.C.
Not connected. This pin should either be left open or terminated to ground.
5
SDI
Serial data input with internal pull down
6
VDD
Logic supply voltage
7
SDO
Serial data output
8
EN
Enable with internal pull-down; Places device in standby mode by pulling the EN
line Low
9
N.C.
Not connected. This pin must either be left open or terminated to ground
10
OUT 6
Power half-bridge 6
11
OUT 4
Power half-bridge 4
12
GND
Ground. All ground pins should be externally connected together.
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Pin Configuration
Pin
Symbol
Function
13
N.C.
Not connected. This pin should either be left open or terminated to ground (e.g. for
layout compatibility with TLE94112EL, TLE94110EL or TLE94108EL).
14
OUT 3
Power half-bridge 3
15
N.C.
Not connected. This pin should either be left open or terminated to ground.
16
VS1
Main supply voltage for power half bridges. VS1 should be externally connected to
VS2.
17
N.C.
Not connected. This pin should either be left open or terminated to ground.
18
N.C.
Not connected. This pin should either be left open or terminated to ground.
19
CSN
Chip select Not input with internal pull up
20
SCLK
Serial clock input with internal pull down
21
VS2
Main supply voltage for power half bridges. VS1 should be externally connected to
VS2.
22
N.C.
Not connected. This pin should either be left open or terminated to ground.
23
OUT 2
Power half-bridge 2
24
N.C.
Not connected. This pin should either be left open or terminated to ground (e.g. for
layout compatibility with TLE94112EL, TLE94110EL or TLE94108EL).
EDP
-
Exposed Die Pad; For cooling and EMC purposes only - not usable as electrical
ground. Electrical ground must be provided by pins 1,12.1)
1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The
exposed pad (EP) must be either left open or connected to GND. It is recommended to connect EP to GND for best
EMC and thermal performance.
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Block Diagram
2
Block Diagram
VS1
VDD
Six-Fold Half Bridge Driver
SPI Interface
EN
BIAS
&
MONITOR
UNDERVOLTAGE
&
OVERVOLTAGE
MONITOR
SDI
CHARGE
PUMP
P ower stage
PWM
GENERATOR
short
to
short
short
toto
short
short
open
toto load
battery
short
short
toto
battery
battery
short
detection
battery
batteryto
detection
battery
battery
detection
detection
battery
detection
detection
detection
detection
detection
short to ground
detection
CSN
SCLK
VS2
overtemperature
detection
LOGIC CONTROL & LATCH
SPI INTERFACE
open
open
openload
load
load
detection
open load
detection
detection
open load
detection
detection
current
current
current
open load
current
current
control
current
current
detection
control
control
current
current
control
control
current
control
control
control
control
short
to
control
short
toto
shortto
to battery
short
short
battery
short
short
toto
detection
battery
short
short
toto
battery
battery
detection
short to
battery
battery
detection
battery
battery
detection
detection
battery
detection
detection
detection
detection
overtemperature
detection
SDO
ERROR
DETECTION
Power driver
highhigh
side
-side
high-side
high
-side
high
high
-side
-side
high
-side
driver
driver
driver
driver
driver
driver
driver
high -side
driver
temp
temp
temp
temp
temp
sensor
temp
temp
sensor
sensor
temp
temp
sensor
sensor
sensor
sensor
sensor
sensor
low-side
low-side
low-side
low-side
low-side
low-side
lowside
driver
driver
driver
low-side
driver
driver
driver
driver
driver
low-side
driver
OUT 1
temp
sensor
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
detection
GND
Figure 2
Datasheet
GND
Block Diagram TLE94106ES (SPI Interface)
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TLE94106ES
Block Diagram
2.1
Voltage and current definition
Figure 3 shows terms used in this datasheet, with associated convention for positive values.
VS
IS1
VS1
IDD
ISDO
VDD
I S2
VS2
VDD
SDO
VSDO
ISDI
V SDI
I CSN
VCSN
ISCLK
V SCLK
SDI
SPI INTERFACE
DRIVER
CSN
SCLK
I OUTx
VDS HSx
OUT x
VDSLSx
IEN
EN
V EN
GND GND
IGND
Figure 3
Datasheet
IGND
Voltage and Current Definition
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General Product Characteristics
3
General Product Characteristics
3.1
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings1)Tj = -40°C to +150°C
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or
Test Condition
Number
Voltages
Supply voltage
VS
-0.3
–
40
V
VS = VS1 = VS2
P_4.1.1
Supply Voltage Slew Rate
| dVS/dt |
–
–
10
V/µs
VS increasing and
decreasing 1)
P_4.2.2
Power half-bridge output voltage
VOUT
-0.3
–
40
V
0 V < VOUT < VS
P_4.1.2
Logic supply voltage
VDD
-0.3
–
5.5
V
0 V < VS < 40 V
P_4.1.3
Logic input voltages
(SDI, SCLK, CSN, EN)
VSDI,
VSCLK,
VCSN, VEN
-0.3
–
VDD
V
0 V < VS < 40 V
0 V < VDD < 5.5V
P_4.1.4
Logic output voltage
(SDO)
VSDO
-0.3
–
VDD
V
0 V < VS < 40 V
0 V < VDD < 5.5V
P_4.1.5
Continuous Supply Current for VS1
IS1
0
–
1.5
A
–
P_4.1.6
Continuous Supply Current for VS2
IS2
0
–
1.5
A
–
P_4.1.7
Current per GND pin
IGND
0
–
2.0
A
–
P_4.1.14
Output Currents
IOUT
-2.0
–
2.0
A
–
P_4.1.15
Junction temperature
Tj
-40
–
150
°C
–
P_4.1.8
Storage temperature
Tstg
-50
–
150
°C
–
P_4.1.9
ESD susceptibility OUTn and VSx
pins versus GND. All other pins
grounded.
VESD
-8
–
8
kV
JEDEC HBM1)2)
P_4.1.10
ESD susceptibility all pins
VESD
-2
–
2
kV
JEDEC HBM1)2)
P_4.1.11
ESD susceptibility all pins
VESD
-500
–
500
V
CDM1)3)
P_4.1.12
V
1)3)
P_4.1.13
Currents
Temperatures
ESD Susceptibility
ESD susceptibility corner pins
VESD
-750
–
750
CDM
1) Not subject to production test, specified by design
2) ESD susceptibility, “JEDEC HBM” according to ANSI/ ESDA/ JEDEC JS001 (1.5 kΩ, 100pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
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General Product Characteristics
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
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General Product Characteristics
3.2
Functional Range
Table 3
Functional Range
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or
Test Condition
Number
Supply voltage range for
normal operation
VS(nor)
5.5
–
18
V
–
P_4.2.1
Extended supply voltage range
VS(ext)
18
–
20
V
1)2)
P_4.2.7
Logic supply voltage range for
normal operation
VDD
3.0
–
5.5
V
–
P_4.2.3
Logic input voltages
(SDI, SCLK, CSN, EN)
VSDI,
VSCLK,
VCSN, VEN
-0.3
–
5.5
V
–
P_4.2.4
Junction temperature
Tj
-40
–
150
°C
P_4.2.5
1) Not subject to production test, specified by design.
2) In the extended supply range, the device is still functional. However, deviations of the specified electrical
characteristics are possible.
Note:
Datasheet
Within the normal functional range the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the related electrical
characteristics table.
11
1.0
2018-01-08
TLE94106ES
General Product Characteristics
3.3
Thermal Resistance
Table 4
Thermal Resistance TLE94106ES
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or
Test Condition
Junction to Case, TA = 85°C
RthjC_hot
–
3.0
–
K/W
1)
Junction to ambient, TA = 85°C
(1s0p, minimal footprint)
RthjA_hot_m –
88
–
K/W
1) 2)
50
–
K/W
1) 3)
42
–
K/W
1) 4)
30
–
K/W
1) 5)
Junction to ambient, TA = 85°C
(1s0p, 300mm2 Cu)
Junction to ambient, TA = 85°C
(1s0p, 600mm2 Cu)
Junction to ambient, TA = 85°C
(2s2p)
Number
in
RthjA_hot_30 –
0
RthjA_hot_60 –
0
RthjA_hot_2s –
2p
1) Not subject to production test, specified by design
2) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with minimal footprint copper area and 35µm thickness.
Ta = 85°C, each channel dissipates 0.135W.
3) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 300mm2 copper area and 35µm
thickness. Ta = 85°C, each channel dissipates 0.135W.
4) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 600mm2 copper area and 35µm
thickness. Ta = 85°C, each channel dissipates 0.135W.
5) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 2s2p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with two inner copper layers ( 4 x 35µm Cu). Ta = 85°C,
each channel dissipates 0.135W.
Datasheet
12
1.0
2018-01-08
TLE94106ES
General Product Characteristics
3.4
Electrical Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH,
IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise
specified; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ. Max.
–
0.5
2
µA
-40°C ≤ Tj ≤ 85°C
P_4.4.1
Logic supply quiescent current IDD_Q
–
0.1
1
µA
-40°C ≤ Tj ≤ 85°C
P_4.4.2
Total quiescent current
–
0.6
3
µA
-40°C ≤ Tj ≤ 85°C
P_4.4.3
Current Consumption, EN = GND
Supply Quiescent current
ISQ
ISQ + IDD_Q
Current Consumption, EN=HIGH
Supply current
IS
–
0.5
1
mA
Power drivers and
power stages are
off
P_4.4.4
Supply current
IS_HSON
–
4.5
9
mA
All high-sides ON1)
P_4.4.101
Logic supply current
IDD
–
1.5
3
mA
SPI not active
P_4.4.5
Logic supply current
IDD_RUN
–
5
–
mA
SPI 5MHz 3)
P_4.4.6
3)
P_4.4.7
Total supply current
IS + IDD_RUN
–
5.5
–
mA
SPI 5MHz
Over- and Undervoltage Lockout
Undervoltage Switch ON
voltage threshold
VUV ON
4.25
–
5.25
V
VS increasing
P_4.4.8
Undervoltage Switch OFF
voltage threshold
VUV OFF
4
–
5.0
V
VS decreasing
P_4.4.9
Undervoltage Switch ON/OFF
hysteresis
VUV HY
–
0.25
–
V
VUV ON - VUV OFF 3)
P_4.4.10
Overvoltage Switch OFF voltage VOV OFF
threshold
21
–
25
V
VS increasing
P_4.4.11
Overvoltage Switch ON voltage VOV ON
threshold
20
–
24
V
VS decreasing
P_4.4.12
Overvoltage Switch ON/OFF
hysteresis
VOV HY
–
1
–
V
VOV OFF - VOV ON 3)
P_4.4.13
VDD Power-On-Reset
VDD POR
2.40
2.70
2.90
V
VDD increasing
P_4.4.14
VDD Power-Off-Reset
VDD POffR
2.35
2.65
2.85
V
VDD decreasing
P_4.4.15
VDD Power ON/OFF hysteresis
VDD POR HY
–
0.05
–
V
VDD POR - VDD POffR 3)
P_4.4.98
Static Drain-source ON-Resistance (High-Side or Low-Side)
High-Side or Low-Side RDSON
(all outputs)
RDSON_HB_25C –
850
1200
mΩ
IOUT = ±0.5 A;
Tj = 25 °C
P_4.4.16
High-Side or Low-Side RDSON
(all outputs)
RDSON_HB_150 –
1400 1800
mΩ
IOUT = ±0.5 A;
Tj = 150 °C
P_4.4.17
Datasheet
C
13
1.0
2018-01-08
TLE94106ES
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH,
IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise
specified; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified) (cont’d)
Parameter
Symbol
Values
Min.
High-Side RDSON
(HS1 and HS2 in LED mode)
High-Side RDSON
(HS1 and HS2 in LED mode)
RDSON_HI_HB_ –
Unit
Note or
Test Condition
Number
1300
mΩ
2)
IOUT = ±0.1 A;
Tj = 25 °C
P_4.4.18
1500 2000
mΩ
2)
P_4.4.19
Typ. Max.
950
25C
RDSON_HI_HB_ –
150C
IOUT = ±0.1 A;
Tj = 150 °C
Output Protection and Diagnosis of high-side (HS) channels of half-bridge output
HS Overcurrent Shutdown
Threshold
ISD_HS
-1.4
-1.1
-0.9
A
See Figure 7
P_4.4.89
Difference between shutdown
and limit current
ILIM_HS ISD_HS
-1.2
-0.6
0
A
3)
|ILIM_HS| ≥ |ISD_HS|
See Figure 7
P_4.4.21
Overcurrent Shutdown filter
time
tdSD_HS
15
19
23
µs
3)
P_4.4.22
Open Load Detection Current
IOLD1_HS
-15
-8
-3
mA
-
P_4.4.23
P_4.4.24
P_4.4.25
Open Load Detection filter time tOLD1_HS
2000
3000 4000
µs
3)
Open Load Detection Current
for LED mode
(HS1 & HS2)
IOLD2_HS1,2
-3.2
-2
-0.5
mA
Bit OL_SEL_HS1 =
1, OL_SEL_HS2 = 1
Open Load Detection filter time tOLD2_HS1,2
for LED mode
(HS1 & HS2)
100
200
300
µs
Bit OL_SEL_HS1 = P_4.4.26
1, OL_SEL_HS2 = 1;
3)
Output Protection and Diagnosis of low-side (LS) channels of half-bridge output
LS Overcurrent Shutdown
Threshold
ISD_LS
0.9
1.1
1.4
A
Figure 8
P_4.4.104
Difference between shutdown
and limit current
ILIM_LS ISD_LS
0
0.6
1.2
A
3)
ILIM_LS ≥ ISD_LS
Figure 8
P_4.4.28
Overcurrent Shutdown filter
time
tdSD_LS
15
19
23
µs
3)
P_4.4.29
Open Load Detection Current
IOLD_LS
3
8
15
mA
-
P_4.4.30
P_4.4.31
Open Load Detection filter time tOLD_LS
2000
3000 4000
µs
3)
Outputs OUT(1...n) leakage current
HS leakage current in off state
IQLHn_NOR
-2
-0.5
–
µA
VOUTn = 0V ; EN=High P_4.4.32
HS leakage current in off state
IQLHn_SLE
-2
-0.5
–
µA
VOUTn = 0V; EN=GND P_4.4.33
LS Leakage current in off state
IQLLn_NOR
–
0.5
2
µA
VOUTn = VS ; EN=High P_4.4.34
LS Leakage current in off state
IQLLn_SLE
–
0.5
2
µA
VOUTn = VS ; EN=GND P_4.4.35
0.75
V/µs
Resistive load =
100Ω; VS=13.5V 4)
Output Switching Times. See Figure 9 and Figure 10.
Slew rate of high-side and low- dVOUT/ dt
side outputs
Datasheet
0.1
0.45
14
P_4.4.36
1.0
2018-01-08
TLE94106ES
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH,
IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise
specified; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified) (cont’d)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or
Test Condition
Number
Output delay time high side
driver on
tdONH
5
20
35
µs
Resistive load =
100Ω to GND
P_4.4.37
Output delay time high side
driver off
tdOFFH
15
45
75
µs
Resistive load =
100Ω to GND
P_4.4.38
Output delay time low side
driver on
tdONL
5
20
35
µs
Resistive load =
100Ω to VS
P_4.4.39
Output delay time low side
driver off
tdOFFL
15
45
75
µs
Resistive load =
100Ω to VS
P_4.4.40
Cross current protection time,
high to low
tDHL
100
130
160
µs
Resistive load =
100Ω3)
P_4.4.41
Cross current protection time,
low to high
tDLH
100
130
160
µs
Resistive load =
100Ω3)
P_4.4.42
High-input voltage
VENH
0.7 *
VDD
–
–
V
–
P_4.4.43
Low-input voltage
VENL
–
–
0.3 *
VDD
V
–
P_4.4.44
Hysteresis of input voltage
VENHY
–
500
–
mV
3)
P_4.4.45
Pull down resistor
RPD_EN
20
40
70
kΩ
VEN = 0.2 x VDD
P_4.4.46
fSPI,max
–
–
5.0
MHz
3) 5)
P_4.4.47
µs
3)
P_4.4.48
Input Interface: Logic Input EN
SPI frequency
Maximum SPI frequency
SPI INTERFACE: Delay Time from EN rising edge to first Data in
Setup time
tset
–
–
150
See Figure 14
SPI INTERFACE: Input Interface, Logic Inputs SDI, SCLK, CSN
H-input voltage threshold
VIH
0.7 *
VDD
–
–
V
–
P_4.4.50
L-input voltage threshold
VIL
–
–
0.3 *
VDD
V
–
P_4.4.51
Hysteresis of input voltage
VIHY
–
500
–
mV
3)
P_4.4.52
Pull up resistor at pin CSN
RPU_CSN
30
50
80
kΩ
VCSN = 0.7 x VDD
P_4.4.53
Pull down resistor at pin SDI,
SCLK
RPD_SDI,
RPD_SCLK
20
40
70
kΩ
VSDI, VSCLK = 0.2 x VDD P_4.4.54
Input capacitance at pin CSN,
SDI or SCLK
CI
–
10
15
pF
0V < VDD < 5.25V 3)
P_4.4.55
VDD 0.4
VDD - –
0.2
V
ISDOH = -1.6 mA
P_4.4.56
Input Interface, Logic Output SDO
H-output voltage level
Datasheet
VSDOH
15
1.0
2018-01-08
TLE94106ES
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH,
IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise
specified; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified) (cont’d)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or
Test Condition
Number
L-output voltage level
VSDOL
–
0.2
0.4
V
ISDOL = 1.6 mA
P_4.4.57
Tri-state Leakage Current
ISDOLK
-1
–
1
µA
VCSN = VDD;
0V < VSDO < VDD
P_4.4.58
Tri-state input capacitance
CSDO
–
10
15
pF
3)
P_4.4.59
–
–
ns
3)
P_4.4.60
P_4.4.61
Data Input Timing. See Figure 15 and Figure 17.
SCLK Period
tpCLK
200
SCLK High Time
tSCLKH
0.45 * –
tpCLK
0.55 * ns
tpCLK
3)
SCLK Low Time
tSCLKL
0.45 * –
tpCLK
0.55 * ns
tpCLK
3)
P_4.4.62
SCLK Low before CSN Low
tBEF
125
–
ns
3)
P_4.4.63
P_4.4.64
–
CSN Setup Time
tlead
250
–
–
ns
3)
SCLK Setup Time
tlag
250
–
–
ns
3)
P_4.4.65
ns
3)
P_4.4.66
ns
3)
P_4.4.67
ns
3)
P_4.4.68
P_4.4.69
SCLK Low after CSN High
SDI Setup Time
SDI Hold Time
tBEH
tSDI_setup
tSDI_hold
125
30
30
–
–
–
–
–
–
trIN
–
–
50
ns
3)
Input Signal Fall Time at pin SDI, tfIN
SCLK, CSN
–
–
50
ns
3)
P_4.4.70
Delay time from EN falling edge tDMODE
to standby mode
–
–
8
µs
3)
P_4.4.71
Minimum CSN High Time
5
–
–
µs
3)
P_4.4.72
–
30
80
ns
Cload = 40pF 3)
ns
3)
Input Signal Rise Time at pin
SDI, SCLK, CSN
tCSNH
Data Output Timing. See Figure 15.
SDO Rise Time
SDO Fall Time
trSDO
tfSDO
–
30
80
Cload = 40pF
P_4.4.73
P_4.4.74
3)
P_4.4.75
SDO Enable Time after CSN
falling edge
tENSDO
–
–
75
ns
Low Impedance
SDO Disable Time after CSN
rising edge
tDISSDO
–
–
75
ns
High Impedance 3)
P_4.4.76
Duty cycle of incoming clock at dutySCLK
SCLK
45
–
55
%
3)
P_4.4.77
SDO Valid Time for VDD = 3.3V
–
70
95
ns
VSDO < 0.2 x VDD
VSDO > 0.8 x VDD
Cload = 40pF 3)
P_4.4.78
Datasheet
tVASDO3
16
1.0
2018-01-08
TLE94106ES
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH,
IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise
specified; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified) (cont’d)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ. Max.
tVASDO5
–
50
65
ns
VSDO < 0.2 x VDD
VSDO > 0.8 VDD
Cload = 40pF 3)
P_4.4.79
Thermal warning junction
temperature
TjW
120
140
170
°C
See Figure 113)
P_4.4.80
Thermal shutdown junction
temperature
TjSD
150
175
200
°C
See Figure 113)
P_4.4.81
Thermal comparator hysteresis TjHYS
–
5
–
°C
3)
P_4.4.82
Ratio of SD to W temperature
1.05
1.20
–
–
3)
P_4.4.83
SDO Valid Time for VDD = 5V
Thermal warning & Shutdown
1)
2)
3)
4)
5)
TjSD / TjW
IS_HSON does not include the load current
HS1, respectively HS2, is set to LED mode by setting OL_SEL_HS1 bit to 1, respectively OL_SEL_HS2 bit to 1
Not subject to production test, specified by design
Measured for 20% - 80% of VS.
Not applicable in daisy chain configuration
Datasheet
17
1.0
2018-01-08
TLE94106ES
Characterization results
4
Characterization results
Performed on 7 devices from 2 lots, over operating temperature and nominal/extended supply range.
Typical performance characteristics
Supply quiescent current
Supply current
P_4.4.4
P_4.4.1
300
3.4
2.9
250
2.4
1.9
IS[uA]
ISQ [uA]
200
1.4
150
100
0.9
50
0.4
0
-0.1
-50 -30 -10
VS=5.5V
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
-50 -30 -10
VS=5.5V
VS=21
Logic supply quiescent current
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
VS=21V
Logic supply current
P_4.4.2
P_4.4.5
0.79
0.5
0.4
0.78
IDD[mA]
IDD_Q[uA]
0.3
0.2
0.77
0.76
0.1
0.75
0
-0.1
0.74
-50 -30 -10
VS=5.5V
Datasheet
-50 -30 -10
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
VS=21V
VS=5.5V
18
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
VS=21V
1.0
2018-01-08
TLE94106ES
Characterization results
HS static Drain-source ON-resistance
LS static Drain-source ON-resistance
P_4.4.16 and P_4.4.17
P_4.4.16 and P_4.4.17
1500
1600
1400
1500
1400
1300
1200
RDSON_LS [mΩ]
RDSON_HS [mΩ]
1300
1100
1000
900
1200
1100
1000
900
800
800
700
700
600
600
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=19V
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=21V
HS static drain-source ON-resistance
VS = 13.5V and VDD = 5V
VS=5.5V
VS=18V
VS=19V
VS=21V
LS static drain-source ON-resistance
VS = 13.5V and VDD = 5V
P_4.4.16 and P_4.4.17
P_4.4.16 and P_4.4.17
1500
1600
1400
1500
1400
1300
1300
1200
RDSON_LS [mΩ]
RDSON_HS [mΩ]
VS=13.5V
1100
1000
900
1200
1100
1000
900
800
800
700
700
600
600
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
OUT1
OUT1
Datasheet
OUT2
OUT3
OUT4
OUT5
OUT6
19
OUT2
OUT3
OUT4
OUT5
OUT6
1.0
2018-01-08
TLE94106ES
Characterization results
Slew rate ON of high-side outputs
Slew rate ON of low-side outputs
P_4.4.36
0.6
0.55
0.55
0.5
0.5
dVOUT/ dt [V/us]
dVOUT/ dt [V/us]
P_4.4.36
0.6
0.45
0.4
0.35
0.45
0.4
0.35
0.3
0.3
0.25
0.25
0.2
0.2
-50 -30 -10
VS=5.5V
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
-50 -30 -10
VS=21V
Slew rate OFF of high-side outputs
VS=5.5V
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
VS=21V
Slew rate OFF of low-side outputs
P_4.4.36
P_4.4.36
0.55
0.65
0.6
0.5
0.55
dVOUT/ dt [V/us]
dVOUT/ dt [V/us]
0.45
0.4
0.35
0.5
0.45
0.4
0.35
0.3
0.3
0.25
0.25
0.2
0.2
-50 -30 -10
VS=5.5V
Datasheet
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
-50 -30 -10
VS=21V
VS=5.5V
20
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=13.5V
VS=18V
VS=19V
VS=21V
1.0
2018-01-08
TLE94106ES
Characterization results
HS overcurrent shutdown threshold
LS overcurrent shutdown threshold
P_4.4.104
1200
-1060
1180
-1080
1160
-1100
1140
ISD_LS [mA]
ISD_HS [mA]
P_4.4.89
-1040
-1120
-1140
1120
1100
-1160
1080
-1180
1060
-1200
1040
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=19V
VS=21V
Undervoltage switch ON voltage threshold
VS=5.5V
VS=13.5V
VS=18V
VS=19V
VS=21V
Undervoltage switch OFF voltage threshold
P_4.4.8
P_4.4.9
4.9
4.8
4.75
4.85
VUV_OFF [V]
VUV_ON [V]
4.7
4.8
4.75
4.65
4.6
4.7
4.55
4.65
4.5
-50 -30 -10
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VDD=3V
Datasheet
VDD=5V
-50 -30 -10
VDD=5.5V
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VDD=3V
21
VDD=5V
VDD=5.5V
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TLE94106ES
Characterization results
Overvoltage switch ON voltage threshold
Overvoltage switch OFF voltage threshold
P_4.4.12
P_4.4.11
22.8
23.6
22.7
23.5
22.6
23.4
23.3
22.4
VOV_OFF [V]
VOV_ON [V]
22.5
22.3
22.2
23.2
23.1
23
22.1
22.9
22
22.8
21.9
21.8
22.7
-50 -30 -10
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VDD=3V
VDD=5V
-50 -30 -10
VDD=5.5V
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VDD=3V
VDD=5V
VDD=5.5V
VDD Power-on-reset and VDD Power-off-reset
P_4.4.14 and P_4.4.15
2.72
2.70
VDD threshold [V]
2.68
2.66
2.64
2.62
2.60
2.58
-50 -30 -10
10 30 50 70 90 110 130 150
Junction Temperature [°C]
VDD POR
Datasheet
VDD POffR
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TLE94106ES
General Description
5
General Description
5.1
Power Supply
The TLE94106ES has two power supply inputs, VS and VDD. The half bridge outputs are supplied by VS, which is
connected to the 12V automotive supply rail. VDD is used to supply the I/O buffers and internal voltage
regulator of the device.
VS and VDD supplies are separated so that information stored in the logic block remains intact in the event of
voltage drop outs or disturbances on VS. The system can therefore continue to operate once VS has recovered,
without having to resend commands to the device.
A rising edge on VDD crossing VDD POR triggers an internal Power-On Reset (POR) to initialize the IC at power-on.
All data stored internally is deleted, and the outputs are switched off (high impedance).
An electrolytic and 100nF ceramic capacitors are recommended to be placed as close as possible to the VS
supply pin of the device for improved EMC performance in the high and low frequency band. The electrolytic
capacitor must be dimensioned to prevent the VS voltage from exceeding the absolute maximum rating. In
addition, decoupling capacitors are recommended on the VDD supply pin.
5.2
Operation modes
5.2.1
Normal mode
The TLE94106ES enters normal mode by setting the EN input High. In normal mode, the charge pump is active
and all output transistors can be configured via SPI.
5.2.2
Sleep mode
The TLE94106ES enters sleep mode by setting the EN input Low. The EN input has an internal pull-down
resistor.
In sleep mode, all output transistors are turned off and the SPI register banks are reset. The current
consumption is reduced to ISQ + IDD_Q.
5.3
Reset Behaviour
The following reset triggers have been implemented in the TLE94106ES:
VDD Undervoltage Reset:
The SPI Interface shall not function if VDD is below the undervoltage threshold, VDD POffR. The digital block will
be deactivated, the logic contents cleared and the output stages are switched off . The digital block is
initialized once VDD voltage levels is above the undervoltage threshold, VDD POR. Then the NPOR bit is reset
(NPOR = 0 in SYS_DIAG1 and Global Status Register).
Reset on EN pin:
If the EN pin is pulled Low, the logic content is reset and the device enters sleep mode.
The reset event is reported by the NPOR bit (NPOR = 0) once the TLE94106ES is in normal mode (EN = High; VDD
> VDD POR).
Datasheet
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TLE94106ES
General Description
5.4
Reverse Polarity Protection
The TLE94106ES requires an external reverse polarity protection. During reverse polarity, the free-wheeling
diodes across the half bridge output will begin to conduct, causing an undesired current flow (IRB) from ground
potential to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection
diode is recommended (see Figure 4).
a)
GND
b)
VBAT
D RP
CS2
CS
HSx
HSx
OUTx
OUTx
LSx
LSx
I RB
GND
VBAT
Figure 4
Datasheet
Reverse Polarity Protection
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TLE94106ES
Half-Bridge Outputs
6
Half-Bridge Outputs
6.1
Functional Description
The half-bridge outputs of the TLE94106ES are intended to drive motor loads. These outputs can either be
driven continuously or PWM enabled via SPI.
If the outputs are driven continuously via SPI, for example HS1 and LS2 used to drive a motor, then the
following suggested SPI commands shall be sent:
•
Activate HS1: Bit HB1_HS_EN in HB_ACT_1_CTRL register
•
Activate LS2: Bit HB2_LS_EN in HB_ACT_1_CTRL register
6.1.1
Half-bridge operation with PWM enabled
All half-bridge outputs of the TLE94106ES are capable of PWM operation. They can either be used to drive an
inductive load (e.g. DC brush motor) or optionally a resistive load (e.g. LED). Each half-bridge output has been
allocated a maximum of three PWM channels with individual duty cycle settings with 8-bit resolution. Each
channel is further mapped to a maximum of three PWM frequency options, i.e. 80Hz,100Hz and 200Hz. This
feature enables a highly flexible PWM operation while driving loads with varying control profiles.
PWM frequency and duty cycle can be changed on demand during PWM operation of the desired half-bridge
output. Glitches on the PWM output waveform, which may arise as a result of on-demand changes in PWM
operation, will be prevented by the internal logic circuitry.
When operating with motor loads, active or passive free-wheeling configuration is available via SPI to select
the speed at which the inductive current can decay over the full-bridge circuit. The default setting is passive
free-wheeling.
Note:
Table 6
Active free-wheeling is effectively applied if the selected duty cycle corresponds to turn-on times of
the HS and the LS, which are longer than the sum of the cross conduction times tDHL + tDLH.
PWM capability and frequency selection per half-bridge output
Control Register:
PWM Frequency 80Hz
HBx_MODEn (n=0,1) (Control Register:
PWM_CH_FREQ_CTRL)
PWM Frequency 100Hz
(Control Register:
PWM_CH_FREQ_CTRL)
PWM Frequency 200Hz
(Control Register:
PWM_CH_FREQ_CTRL)
PWM Channel 1
PWM_CH1_FREQ_n (n=0,1) PWM_CH1_FREQ_n (n=0,1) PWM_CH1_FREQ_n (n=0,1)
Bit ‘01B’
Bit ‘10B’
Bit ‘11B’
PWM Channel 2
PWM_CH2_FREQ_n (n=0,1) PWM_CH2_FREQ_n (n=0,1) PWM_CH2_FREQ_n (n=0,1)
Bit ‘01B’
Bit ‘10B’
Bit ‘11B’
PWM Channel 3
PWM_CH3_FREQ_n (n=0,1) PWM_CH3_FREQ_n (n=0,1) PWM_CH3_FREQ_n (n=0,1)
Bit ‘01B’
Bit ‘10B’
Bit ‘11B’
Datasheet
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TLE94106ES
Half-Bridge Outputs
6.1.1.1
Inductive Load
An illustration is shown in Figure 5 with OUT1 and OUT2 driving a DC brush motor. With this configuration,
HS1 is permanently driven while LS2 is driven in PWM operation. HS2 serves to actively free-wheel (FW) the
motor current load, reducing the power dissipation of the device.
VS
HBn
HS2
active FW
HS1 ON
OUT 1
t
FW
OUT 1
M1
OUT 2
LS1
FW
FW
FW
OUT 2
CW
CW
CW
CW
t
LS2 PWM
CW = motor clockwise
FW = Free-wheeling
Figure 5
PWM operation on OUT 2
Assuming HBx Mode = 00 and both HSx and LSx are considered off (tri-state). The suggested SPI control
commands for proper PWM operation are:
Option 1: The considered output is not put in parallel with another one
•
Configure the frequency to 00 (PWM is stopped and off) for selected PWM channel
•
Configure active or passive free-wheeling of the inductive decay current in FW_CTRL register
•
Assign an appropriate PWM channel for selected half-bridge output in HB_MODE_CTRL register
•
Configure the duty cycle of the selected half-bridge output in PWM_DC_CTRL register
•
Select the PWM frequency in PWM_CH_FREQ_CTRL register to begin the PWM period
•
Activate the channel to be driven in PWM operation: HSn or LSn in the HB_ACT_CTRL register
Option 2: Outputs controlled by different control registers are put paralleled. This sequence ensures
that corresponding HS or LS are activated simultaneously
•
Configure the frequency 00 (PWM is stopped and off) for selected PWM channel
•
Configure active or passive free-wheeling of the inductive decay current in FW_CTRL register
•
Assign an appropriate PWM channel for selected half-bridge output in HB_MODE_CTRL register
•
Configure the duty cycle of the selected half-bridge output in PWM_DC_CTRL register
•
Activate the channel to be driven in PWM operation: HSn or LSn in the HB_ACT_CTRL register
•
Select the PWM frequency in PWM_CH_FREQ_CTRL register to begin the PWM period
Careful attention should be paid to the free-wheeling configuration of the half-bridge required to be driven in
PWM operation. For example, in the event a high-side channel is activated and assigned a PWM channel, and
active free-wheeling is selected, but a frequency mode of ‘00’ (PWM is stopped and off) is configured in the
Datasheet
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TLE94106ES
Half-Bridge Outputs
PWM_CH_FREQ_CTRL register, then the respective high-side channel will be configured low and the adjacent
low-side channel within the half-bridge will be enabled. This is a result of enabling active free-wheeling.
Datasheet
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TLE94106ES
Half-Bridge Outputs
6.1.1.2
LED mode (optional)
Outputs, OUT1 and OUT2, are designed to optionally drive low current loads such as LEDs. The high-side
channels, HS1 and HS2 are equipped with a lower open load threshold detection current and shorter filter
time, specifically for low current loads such as LEDs. See OL_SEL_HS1 and OL_SEL_HS2 bits in FW_OL_CTRL
register. Setting HS1 or HS2 in LED mode increases the RDSON and decreases the open load detection threshold.
An illustration is shown in Figure 6 with OUT1 driving an LED. With this configuration, HS1 is driven in PWM
operation while LS1 is deactivated.
VS
HS1 PWM
OUT 1
Figure 6
PWM operation on OUT 1
Assuming HBx Mode = 00 and both HSx and LSx are considered off (tri-state). The suggested SPI control
commands are:
•
Configure frequency 00 (PWM is stopped and off) for selected channel to ensure PWM is off.
•
Assign an appropriate PWM channel for selected HS1 or HS2 output in HB_MODE_CTRL register
•
Configure duty cycle of selected HS1 or HS2 output in PWM_DC_CTRL register
•
Activate channel to be driven in PWM operation: HS1 or HS2 in the HB_ACT_CTRL register
•
Select low current open load detection threshold for HS1 or HS2 in FW_OL_CTRL register
•
Select PWM frequency in PWM_CH_FREQ_CTRL register to begin the PWM period.
Datasheet
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TLE94106ES
Half-Bridge Outputs
6.2
Protection & Diagnosis
The TLE94106ES is equipped with an SPI interface to control and diagnose the state of the half-bridge drivers.
This device has embedded protective functions which are designed to prevent IC destruction under fault
conditions described in the following sections. Fault conditions are treated as “outside” normal operating
range. Protection functions are not designed for continuous repetitive operation.
The following table provides a summary of fault conditions, protection mechanisms and recovery states
embedded in the TLE94106ES device.
Table 7
Summary of diagnosis and monitoring of outputs
Fault
condition
Error Flag Error bit: Status Register
(EF)
behaviour
Overcurrent
Latch
Error output
1. Load Error bit, LE (bit 6) in
shutdown
SYS_DIAG 1: Global Status 1
and latched
Register
2. Localized error for each HS and
LS channel of half-bridge,
HBn_HS_OC and HBn_LS_OC bits
in SYS_DIAG_2, SYS_DIAG_3 status
registers.
High-Z
Open load
Latch
None
1. Load Error bit, LE (bit 6) in
SYS_DIAG 1: Global Status 1
Register
2. Localized error for each HS and
LS channel of half-bridge,
HBn_HS_OL and HBn_LS_OL bits in
SYS_DIAG_5, SYS_DIAG_6 status
registers.
No
An open load
state
detection does not
change change the state of
the output.
EF to be cleared.
Temperature Latch
pre-warning
Global error bit 1, TPW in
SYS_DIAG_1: Global Status 1
register
None
No
Not applicable
state
change
Temperature Latch
shutdown
Global error bit 2, TSD in
SYS_DIAG_1: Global Status 1
register
All outputs
shutdown
and latched.
High-Z
Datasheet
29
Output
Protection
mechanism
Output Output and error
error
flag (EF) recovery
state
Half-bridge control
bits remain set
despite error,
however the
impacted MOSFET
is shutdown. Clear
EF to reactivate the
impacted MOSFET.
Half-bridge control
bits remain set
despite error,
however the
output stage is
shutdown. Clear EF
to reactivate
output stage.
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TLE94106ES
Half-Bridge Outputs
Table 7
Fault
condition
Summary of diagnosis and monitoring of outputs (cont’d)
Error Flag Error bit: Status Register
(EF)
behaviour
Output
Protection
mechanism
Output Output and error
flag (EF) recovery
error
state
Power supply Latch
failure due to
undervoltage
Global error bit 5, VS_UV in
SYS_DIAG_1: Global Status 1
register
High-Z
All outputs
shutdown
and
automatically
recovers.
Half-bridge control
bits remain set
despite error,
however the
output stage is
shutdown. They
will automatically
be reactivated
once the power
supply recovers. EF
to be cleared.
Power supply Latch
failure due to
overvoltage
Global error bit 4, VS_OV in
SYS_DIAG_1: Global Status 1
register
High-Z
All outputs
shutdown
and
automatically
recover.
Half-bridge control
bits remain set
despite error,
however the
output stage is
shutdown. They
will automatically
be reactivated
once the power
supply recovers. EF
to be cleared.
Datasheet
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TLE94106ES
Half-Bridge Outputs
6.2.1
Short Circuit of Output to Supply or Ground
The high-side switches are protected against short to ground whereas the low-side switches are protected
against short to supply.
The high-side and low-side power switches will enter into an over-current condition if the current within the
switch exceeds the overcurrent shutdown detection threshold, ISD. Upon detection of the ISD threshold, an
overcurrent shutdown filter, tdSD is begun. As the current rises beyond the threshold ISD, it will be limited by the
current limit threshold, ILIM. Upon expiry of the overcurrent shutdown filter time, the affected power switch is
latched off and the corresponding error bit, HBn_HS_OC or HBn_LS_OC is set and latched. See Figure 7 and
Figure 8 for more detail. A global load error bit, LE, contained in the global status register, SYS_DIAG_1, is also
set for ease of error scanning by the application software. The power switch remains deactivated as long as
the error bit is set.
To resume normal functionality of the power switch (in the event the overcurrent condition disappears or to
verify if the failure still exists) the microcontroller shall clear the error bit in the respective status register to
reactivate the desired power switch.
VS
| IHS |
I ILIM_HS I
ON
I ILIM_HS - ISD_HS I
I ISD_HS I
OUTn
Short to GND
tdSD_ HS
t
Short condition on High-Side Switch
Figure 7
High-Side Switch - Short Circuit and Overcurrent Protection
VS
ILS
VS
ILIM_ LS
Short to Supply
OUTn
ILIM_ LS - ISD_LS
ISD_LS
ON
tdSD_LS
t
Short condition on Low-Side Switch
Figure 8
Datasheet
Low-Side Switch - Short Circuit and Overcurrent Protection
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Half-Bridge Outputs
Table 8
Control and Status register bit state in the event of an overcurrent condition for an
activated power switch
BEFORE
OVERCURRENT
DURING
OVERCURRENT
AFTER
OVERCURRENT
Bit State
Bit State
Bit State
REGISTER
TYPE
REGISTER NAME Bit
Control
HB_ACT_CTRL_n HBn_HS_EN
HBn_LS_EN
1
1
1 (corresponding
MOSFET
deactivated)
Status
SYS_DIAG_1:
Global Status 1
LE
0
0
1
Status
SYS_DIAG_x
where x=2,3
HBn_HS_OC
HBn_LS_OC
0
0
1
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TLE94106ES
Half-Bridge Outputs
6.2.2
Cross-Current
In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously
“ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to
create a dead-time between switching off of one power transistor and switching on of the adjacent power
transistor within the half-bridge. The dead times, tDHL and tDLH, as shown in Figure 9 case 3 and Figure 10 case
3, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross
conduction event.
CSN
t
Case 1: Delay Time High Side Driver OFF
Previous State Æ New State
HS ON
LS OFF
Æ HS OFF
VOUT_HSx [V]
VS
80%
tdOFFH 1)
Æ LS OFF
GND 1)
Case 2: Delay Time Low Side Driver ON
20%
t
Delay time HS OFF
VOUT_LSx [V]
Previous State Æ New State
HS OFF Æ HS OFF
VS
80%
tdONL2)
LS OFF
Æ LS ON
20%
GND
2)
t
Delay time LS ON without dead time ; HS previously OFF
Case 3: Delay Time Low Side Driver ON with tDHL dead time
Previous State Æ New State
HS ON Æ HS OFF
LS OFF
VOUT_LSx [V]
VS
80%
Low-Side
ON
delay time
Æ LS ON
20%
GND
3)
Figure 9
Datasheet
tdONL + tDHL
3)
t
Delay time LS ON with dead time ; HS previously ON
Half bridge outputs switching times - high-side to low-side transition
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TLE94106ES
Half-Bridge Outputs
CSN
t
Case 1: Delay Time High Side Driver OFF
Previous State Æ New State
HS OFF Æ HS OFF
VOUT_LSx [V]
VS
80%
tdOFFL1)
Æ LS OFF
LS ON
GND
20%
1)
t
Delay time LS OFF
Case 2: Delay Time High Side Driver ON
VOUT_HSx [V]
Previous State Æ New State
HS OFF Æ HS ON
LS OFF
VS
80%
tdONH2)
Æ LS OFF
20%
GND
2)
t
Delay time HS ON without dead time ; LS previously OFF
Case 3: Delay Time High Side Driver ON with tDLH dead time
Previous State Æ New State
HS OFF Æ HS ON
LS ON
VOUT _HSx [V]
VS
80%
High-Side
ON
delay time
Æ LS OFF
tdONH + tDLH3)
20%
GND
3)
Figure 10
Datasheet
t
HS ON delay time with dead time ; LS previously ON
Half bridge outputs switching times- low-side to high-side transition
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Half-Bridge Outputs
6.2.3
Temperature Monitoring
Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the
measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach
the warning temperature, the temperature pre-warning bit, TPW is set. This bit is latched and can only be
cleared via SPI. The outputs stages however remain activated.
If one or more temperature sensors reach the shut-down temperature threshold, all outputs are latched off.
The TSD bit in SYS_DIAG_1: Global Status 1 is set. All outputs remain deactivated until the TSD bit is cleared.
See Figure 11.
To resume normal functionality of the power switch (in the event the overtemperature condition disappears,
or to verify if the failure still exists) the microcontroller shall clear the TSD error bit in the status register to
reactivate the respective power switch.
Tj
TjSD
TjW
t
VOUTx
Output is switched off if
TjSD is reached, can be
reactivated if TSD bit is
cleared
ON
High Z
no error
t
TPW error bit
High
TPW is latched, can
be cleared via SPI
Low
t
no error
TSD error bit
High
TSD is latched, can be
cleared via SPI
Low
t
no error
Figure 11
Datasheet
Overtemperature Behavior
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TLE94106ES
Half-Bridge Outputs
Table 9
Control and Status register bit state in the event of an overtemperature condition for an
activated power switch
Tj < TjW
Tj > TjW
Tj > TjSD
Tj < TjSD - TjHYS
REGISTER
TYPE
REGISTER NAME
Bit
Bit State
Bit State
Bit State
Bit State
Control
HB_ACT_CTRL_n
HBn_HS_EN
HBn_LS_EN
1
1
1
(all outputs
are latched
off)
‘1’ (outputs
are latched off
unless error is
cleared)
Status
SYS_DIAG_1: Global TPW
status 1
0
1
(latched)
1
(latched)
‘0’ if error is
cleared and
Tj < TjW , else ‘1’
Status
SYS_DIAG_1: Global TSD
status 1
0
0
1
(latched)
‘0’ if error is
cleared, else
‘1’
6.2.4
Overvoltage and undervoltage shutdown
The power supply rails VS and VDD are monitored for supply fluctuations. The VS supply is monitored for underand over-voltage conditions where as the VDD supply is monitored for under-voltage conditions.
6.2.4.1
VS Undervoltage
In the event the supply voltage VS drops below the switch off voltage VUV OFF, all output stages are switched off,
however, the logic information remains intact and uncorrupted. The VS under-voltage error bit, VS_UV,
located in SYS_DIAG_1: Global Status 1 status register, will be set and latched. If VS rises again and reaches the
switch on voltage VUV ON threshold, the power stages will automatically be activated. The VS_UV error bit
should be cleared to verify if the supply disruption is still present. See Figure 12.
6.2.4.2
VS Overvoltage
In the event the supply voltage VS rises above the switch off voltage VOV OFF, all output stages are switched off.
The VS over-voltage error bit, VS_OV, located in SYS_DIAG_1: Global Status 1 status register, will be set and
latched. If VS falls again and reaches the switch on voltage VOV ON threshold, the power stages will automatically
be activated. The VS_OV error bit should be cleared to verify if the overvoltage condition is still present. See
Figure 12.
6.2.4.3
VDD Undervoltage
In the event the VDD logic supply decreases below the undervoltage threshold, VDD POffR, the SPI interface shall
no longer be functional and the TLE94106ES will enter reset.
The digital block will be initialized and the output stages are switched off to High impedance. The
undervoltage reset is released once VDD voltage levels are above the undervoltage threshold, VDD POR.
The reset event is reported in SYS_DIAG1 by the NPOR bit (NPOR = 0) once the TLE94106ES is in normal mode
(EN = High ; VDD > VDD POR).
Datasheet
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TLE94106ES
Half-Bridge Outputs
VS
VOV HY
VOV OFF
VOV ON
VUV HY
VUV ON
VUV OFF
t
VOUTx
VOUTx
Output
reactivated
ON
ON
t
High Z
VS_UV error bit
SPI command :
Clear SYS _DIAG1
VS_OV error bit
SPI command
Clear SYS_DIAG1
High
Low
6.2.5
t
High Z
High
Figure 12
Output
reactivated
Low
t
t
Output behavior during under- and overvoltage VS condition
Open Load
Both high-side and low-side switches of the half-bridge power outputs are capable of detecting an open load
in their activated state. If a load current lower than the open load detection threshold, IOLD for at least tdOLD is
detected at the activated switch, the corresponding error bit, HBn_HS_OL or HBn_LS_OL is set and latched. A
global load error bit, LE, in the global status register, SYS_DIAG_1: Global Status 1, is also set for ease of error
scanning by the application software. The half-bridge output however, remains activated.
The microcontroller must clear the error bit in the respective status register to determine if the open load is
still present or disappeared.
High-side outputs, HS1 and HS2, are specifically designed to detect open load thresholds for LED loads. Both
HS1 and HS2 have a unique and lower open load current threshold and filter time which are configurable via
SPI in control register, FW_OL_CTRL.
During PWM operation, the open load detection is blanked and will not be visible in the status register for
power stages used in active free-wheeling
Datasheet
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TLE94106ES
Serial Peripheral Interface (SPI)
7
Serial Peripheral Interface (SPI)
The TLE94106ES has a 16-bit SPI interface for output control and diagnostics. This section describes the SPI
protocol, the control and status registers.
7.1
SPI Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input
SCLK provided by the microcontroller. SCLK must be Low during CSN falling edge (Clock Polarity = 0). The SPI
incorporates an in-frame response: the content of the addressed register is shifted out at SDO within the same
SPI frame (see Figure 19 and Figure 21).The transmission cycle begins when the chip is selected by the input
CSN (Chip Select Not), Low active. After the CSN input returns from Low to High, the word that has been read
is interpreted according to the content. The SDO output switches to tri-state status (High impedance) at this
point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input register with every
falling edge on SCLK. The state of SDO is shifted out of the output register at every rising edge on SCLK (Clock
Phase = 1). The SPI protocol of the TLE94106ES is compatible with independent slave configuration and with
daisy chain. Daisy chaining is applicable to SPI devices with the same protocol.
Writing, clearing and reading is done byte wise. The SPI configuration and status bits are not cleared
automatically by the device and therefore must be cleared by the microcontroller, e.g. if the TSD bit was set
due to over temperature (refer to the respective register description for detailed information).
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
SCLK
time
Actual data
LSB
SDI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
MSB
15
New data
0
+
1
+
time
SDI: will accept data on the falling edge of SCLK signal
New status
Actual status
SDO
GEF
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15
GEF 0
+
+
1
+
time
SDO will change state on the rising edge of SCLK signal
Figure 13
SPI Data Transfer Timing (note the reversed order of LSB and MSB as shown in this figure
compared to the register description)
SPI messages are only recognized if a minimum set time, tSET, is observed upon rising edge of the EN pin
(Figure 14).
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Serial Peripheral Interface (SPI)
EN
EN
tSET
SPI
SPI
A) SPI message ignored
Figure 14
B) SPI message accepted
Setup time from EN rising edge to first SPI communication
t lead
tlag
tCSNH
tpCLK
0.8V DD
CSN
0.2V DD
tSCLKH
t SCLKL
0.8V DD
SCLK
0.2V DD
tSDI_setup
tSDI_hold
0.8V DD
SDI
0.2V DD
tENSDO
tVASDO
t DISSDO
0.8V DD
SDO
0.2V DD
Figure 15
SPI Data Timing
7.1.1
Global Error Flag
A logic OR combination between Global Error Flag (GEF) and the signal present on SDI is reported on SDO
between a CSN falling edge and the first SCLK rising edge (Figure 13). GEF is set if a fault condition is detected
or if the device comes from a Power On Reset (POR).
Note:
The SDI pin of all devices in daisy chain or non daisy chain mode must be Low at the beginning of the
SPI frame (between the CSN falling edge and the first SCLK rising edge).
It is possible to check if the TLE94106ES has detected a fault by reading the GEF without SPI clock pulse
(Figure 16).
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Serial Peripheral Interface (SPI)
CSN
time
SCLK
0
time
SDI
0
time
SDO
High Impedance
Global Error Flag
High Impedance
time
Figure 16
SDO behaviour with 0-clock cycle
7.1.2
Global Status Register
The SDO shifts out during the first eight SCLK cycles the Global Status Register. This register provides an
overview of the device status. All failures conditions are reported in this byte:
•
SPI protocol error (SPI_ERR)
•
Load Error (LE bit): logical OR between Open Load (OL) and Overcurrent (OC) failures
•
VS Undervoltage (VS_UV bit)
•
VS Overvoltage (VS_OV bit)
•
Negated Power ON Reset (NPOR bit)
•
Temperature Shutdown (TSD bit)
•
Temperature Pre-Warning (TPW bit)
See Chapter 7.7.1 for details.
Note:
The Global Error Flag is a logic OR combination of every bit of the Global Status Register with the
exception of NPOR: GEF = (SPI_ERR) OR (LE) OR (VS_UV) OR (VS_OV) OR (NOT(NPOR)) OR (TSD) OR
(TPW).
The following table shows how failures are reported in the Global Status Register and by the Global Error Flag.
Table 10
Failure reported in the Global Status Register and Global Error Flag
Type of Error
Failure reported in the Global
Status Register
Global Error Flag
SPI protocol error
SPI_ERR = 1
1
Open load or Overcurrent
LE = 1
1
VS Undervoltage
VS_UV = 1
1
VS Overvoltage
VS_OV = 1
1
Power ON Reset
NPOR = 0
1
Thermal Shutdown
TSD = 1
1
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Serial Peripheral Interface (SPI)
Table 10
Failure reported in the Global Status Register and Global Error Flag
Type of Error
Failure reported in the Global
Status Register
Global Error Flag
Thermal Warning
TPW = 1
1
No Error and no Power ON Reset
SPI_ERR = 0
LE = 0
VS_UV = 0
VS_OV = 0
NPOR = 1
TSD = 0
TPW = 0
0
Note:
The default value (after Power ON Reset) of NPOR is 0, therefore the default value of GEF is 1.
7.1.3
SPI protocol error detection
The SPI incorporates an error flag in the Global Status Register (SPI_ERR, Bit7) to supervise and preserve the
data integrity. If an SPI protocol error is detected during a given frame, the SPI_ERR bit is set in the next SPI
communication.
The SPI_ERR bit is set in the following error conditions:
•
the number of SCLK clock pulses received when CSN is Low is not 0, or is not a multiple of 8 and at least 16
•
the microcontroller sends an SPI command to an unused address. In particular, SDI stuck to High is
reported in the SPI_ERR bit
•
the LSB of an address byte is not set to 1. In particular, SDI stuck to Low is reported in the SPI_ERR bit
•
the Last Address Bit Token (LABT, bit 1 of the address byte, see Chapter 7.2) in independent slave
configuration is not set to 1
•
the LABT bit of the last address byte in daisy chain configuration is not set to 1 (see Chapter 7.3)
•
a clock polarity error is detected (see Figure 17 Case 2 and Case 3): the incoming clock signal was High
during CSN rising or falling edges.
For a correct SPI communication:
•
SCLK must be Low for a minimum tBEF before CSN falling edge and tlead after CSN falling edge
•
SCLK must be Low for a minimum tlag before CSN rising edge and tBEH after CSN rising edge
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Serial Peripheral Interface (SPI)
Case 1: Correct SCLK signal
Correct incoming clock signal
Correct clock during CSN rising edge
CSN
t BEF
tlead
tlag t BEH
time
SCLK
time
Case 2: Erroneous incoming clock signal
CSN
time
SCLK is High with CSN falling edge
SCLK
time
Case 3: Erroneous clock signal during CSN rising edge
CSN
Clock is High with CSN rising edge
time
SCLK
time
Figure 17
Datasheet
Clock Polarity Error
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Serial Peripheral Interface (SPI)
7.2
SPI with independent slave configuration
In an independent slave configuration, the microcontroller controls the CSN of each slave individually
(Figure 18).
SCLK
CSN
SDI2
TLE941xy_3
SDO2 SDI3
SPI
SPI
SDO3
SCLK
SDO1
SPI
CSN
SDI1
TLE941xy_2
CSN
TLE941xy_1
SCLK
Microcontroller
MCSN1
MCSN2
MCSN3
MCLK
MO
MI
Figure 18
SPI with independent slave configuration
Each SPI communication starts with one address byte followed by one data byte (Figure 19).The LSB of the
data byte must be set to ‘1’.The address bytes specifies:
•
the type of operation: READ ONLY (OP bit =0) or READ/ WRITE (OP bit = 1) of the configuration bits, and
READ ONLY (OP bit =0)or READ & CLEAR (OP bit = 1) of the status bits.
•
The target register address (A[6:2])
The Last Address Byte Token bit (LABT, Bit1 of the address byte) must be set to 1, as no daisy chain
configuration is used.
While the microcontroller sends the address byte on SDI, SDO shifts out GEF and the Global Status Register.
A further data byte (Bit15...8) is allocated to either configure the half-bridges or retrieve status information of
the TLE94106ES.
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Serial Peripheral Interface (SPI)
Address Byte
LSB
SDI
Data Byte
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
LABT
=1
A2
A3
A4
A5
A6
OP
D0
D1
D2
D3
D4
D5
D6
D7
Register content of the selected address
Global Status Register
LSB
0
SD0
0
1
TPW
2
TSD
3
4
5
NPOR VS_OV VS_UV
Data Byte (Response )
MSB
6
7
8
9
10
11
12
13
14
15
LE
SPI_
ERR
D0
D1
D2
D3
D4
D5
D6
D7
Time
LSB is sent first in SPI message
Figure 19
SPI Operation Mode with independent slave configuration
The in-frame response characteristic enables the microcontroller to read the contents of the addressed
register within the SPI command. See Figure 19.
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TLE94106ES
Serial Peripheral Interface (SPI)
7.3
Daisy chain operation
The TLE94106ES supports daisy chain operation with devices with the same SPI protocol.This section
describes the daisy chain hardware configuration with three devices from the TLE941xy family (See
Figure 20).
The master output (noted MO) is connected to a slave SDI and the first slave SDO is connected to the next slave
SDI to form a chain. The SDO of the final slave in the chain will be connected to the master input (MI) to close
the loop of the SPI communication frame. In daisy chain configuration, a single chip select, CSN, and clock
signal, SCLK, connected in parallel to each slave device, are used by the microcontroller to control or access
the SPI devices.
In this configuration, the Master Output must send the address bytes and data bytes in the following order:
•
All address bytes must be sent first:
– Address Byte 1 (for TLE941xy_1) is sent first, followed by Address Byte 2 (for TLE941xy_2) etc,...
– The LABT bit of the last address byte must be 1, while the LABT bit of all the other address bytes must
be 0
•
The data bytes are sent all together once all address bytes have been transmitted: Data Byte 1 (for
TLE941xy_1) is sent first, followed by Data Byte 2 (for TLE941xy_2) etc,...
Note:
The signal on the SDI pin of the first IC in daisy chain (and in non-daisy chain mode), must be Low at
the beginning of the SPI frame (between CSN falling edge and the first SCLK rising edge). This is
because each Global Error Flag in daisy chain operation is implemented in OR logic.
The Master Input (MI), which is connected to the SDO of the last device in the daisy chain receives:
•
A logic OR combination of all Global Error Flags (GEF), at the beginning of the SPI frame, between CSN
falling edge and the first SCLK rising edge
•
The logic OR combination of the GEFs is followed by the Global Status Registers in reverse order. In other
words MI receives first the Global Status Register of the last device of the daisy chain
•
Once all Global Status Registers are received, MI receives the response bytes corresponding to the
respective address and data bytes in reverse order. For example, if the daisy chain consists of three devices
with SDO or TLE941xy_3 connected to MI, the master receives first the Response Byte 3 of TLE941xy_3
(corresponding to Address Byte 3 and Data Byte 3) followed by the Response Byte 2 of TLE941xy_2 and
finally the Response Byte 1 of TLE941xy_1.
An example of an SPI frame with three devices from the TLE941xy family is shown in Figure 21.
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Serial Peripheral Interface (SPI)
SCLK
SDO2 SDI3
SPI
SPI
CSN
SDO1 SDI2
SPI
TLE941xy_3
SDO3
SCLK
TLE941xy_2
CSN
SDI1
CSN
MO
TLE941xy_1
SCLK
Microcontroller
MCSN
MCLK
MI
Figure 20
SCLK
Example of daisy chain hardware configuration with devices from the TLE941xy family
0
8 CLOCK CYCLES
8 CLOCK CYLES
8 CLOCK CYCLES
8 CLOCK CYLES
8 CLOCK CYCLES
8 CLOCK CYLES
CSN
LABT=0
MO = SDI1
SDI2 = SDO1
SDI3 = SDO2
MI =SDO3
0
GEF1
OR
GEF1/2
LABT=0
LABT=1
ADDRESS BYTE 1
ADDRESS BYTE 2
ADDRESS BYTE 3
DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
GLOBAL STATUS 1
ADDRESS BYTE 2
ADDRESS BYTE 3
RESPONSE 1
DATA BYTE 2
DATA BYTE 3
GLOBAL STATUS 2 GLOBAL STATUS 1
ADDRESS BYTE 3
RESPONSE 2
RESPONSE 1
DATA BYTE 3
GLOBAL STATUS 2 GLOBAL STATUS 1
RESPONSE 3
RESPONSE 2
RESPONSE 1
OR
GLOBAL STATUS 3
GEF1/2/3
Time
Figure 21
SPI frame with three devices of the TLE941xy family
Like in the individual slave configuration, it is possible to check if one or several TLE941xy have detected a fault
condition by reading the logic OR combination of all the Global Error Flags when CSN goes Low without any
clock cycle (Figure 22).
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Serial Peripheral Interface (SPI)
SCLK
0
CSN
MO = SDI1
SDI2 = SDO1
0
HiZ
GEF1
GEF1
HiZ
SDI3 = SDO2
OR
GEF1/2
HiZ
OR
GEF1/2
HiZ
MI = SDO3
OR
GEF1/2/3
HiZ
OR
GEF1/2/3
HiZ
Time
Figure 22
Global Error Flag with zero SCLK clock cycle in daisy chain consisting only of TLE941xy
devices
Note:
Some SPI protocol errors such as the LSB of an address byte is wrongly equal to 0, may be reported
in the SPI_ERR bit of another device in the daisy chain (refer to Chapter 7.1.3 and Chapter 7.7 for
more details on SPI_ERR). In this case some devices might accept wrong data during the corrupted
SPI frame. Therefore if one of the devices in the daisy chain reports an SPI error, it is recommended
to verify the content of the registers of all devices.
7.4
Status register change during SPI communication
If a new failure occurs after the transfer of the data byte(s), i.e. between the end of the last address byte and
the CSN rising edge, this failure will be reported in the next SPI frame (see example in Figure 23).
SCLK
0
8 CLOCK CYCLES
8 CLOCK CYLES
8 CLOCK CYCLES
8 CLOCK CYLES
CSN
End of the
address byte
SDI
0
SDO
ADDRESS BYTE
New failure
detection
Read status byte
corresponding to the failure
DATA BYTE
ADDRESS BYTE
Failure is NOT notified in this SPI frame
GEF
GLOBAL STATUS
DATA BYTE
DATA BYTE
Failure notified in the new SPI frame
HiZ
GEF
GLOBAL STATUS
DATA BYTE
HiZ
Time
Figure 23
Datasheet
Status register change during transfer of data byte - Example in independent slave
configuration
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Serial Peripheral Interface (SPI)
No information is lost, even if a status register is changed during a SPI frame, in particular during a Read and
Clear command. For example:
•
the microcontroller sends a Read and Clear command to a status register
•
the TLE94106ES detects during the transfer the data byte(s) a new fault condition, which is normally
reported in the target status register
The incoming Clear command will be ignored, so that the microcontroller can read the new failure in the
subsequent SPI frames.
Data inconsistency between the Global Status Register (see Chapter 7.7) and the data byte (status register)
within the same SPI frame is possible if:
•
an open load or overcurrent error is detected during the transfer of the data byte
•
the target status register corresponds to the new detected failure
In this case the new failure:
•
is not reported in the Global Status Register of the current SPI frame but in the next one
•
is reported in the data byte of the current SPI frame
Refer to Figure 23.
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TLE94106ES
Serial Peripheral Interface (SPI)
SPI Frame 1
Overcurrent failure detected on HS of HB 1 SPI frame: Read SYS _DIAG2 (OC error of HB 1-4)
Address Byte
LSB
SDI
Data Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
LABT
=1
A2
=0
A3
=0
A4
=1
A5
=1
A6
=0
OP
=0
X
X
X
X
X
X
X
X
Overcurrent failure detected on HS of HB 1 during the
transfer of the address byte
0
0
Target status register : OC error of HB 1-4
Global Status Register
LSB
SDO
MSB
1
2
TPW
TSD
3
4
5
NPOR VS_OV VS_UV
Response Data Byte : SYS_DIAG2
MSB
6
7
8
9
10
11
12
13
14
15
LE
=0
SPI_
ERR
D0
=0
D1
=1
D2
=0
D3
=0
D4
=0
D5
=0
D6
=0
D7
=0
HB1_HS_OC reports the new
Overcurrent failure on the HS of HB 1
Load Error bit (Overcurrent or Open Load )
does not report the new Overcurrent failure
Inconsistency between Global Status Register
and target Status Register
Time
SPI frame 2 (new)
New SPI frame : e.g. Read SYS _DIAG2 (OC error of HB 1-4)
Address Byte
LSB
Data Byte
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
LABT
=1
A2
=0
A3
=0
A4
=1
A5
=1
A6
=0
OP
=0
X
X
X
X
X
X
X
X
Target status register : OC error of HB 1-4
Global Status Register
LSB
0
0
1
TPW
2
3
4
5
TSD NPOR VS_OV VS_UV
Response Data Byte : SYS_DIAG2
MSB
6
7
8
9
10
11
12
13
14
15
LE
=1
SPI_
ERR
D0
=0
D1
=1
D2
=0
D3
=0
D4
=0
D5
=0
D6
=0
D7
=0
Consistent information : Both Load Error bit and HB 1_HS_OC report
the Overcurrent failure detected during the previous SPI frame
Figure 24
Datasheet
Example of inconsistency between Global Error Flag and Status Register when a status bit is
changed during the transfer of an address byte
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Serial Peripheral Interface (SPI)
7.5
SPI Bit Mapping
The SPI Registers have been mapped as shown in Figure 25 and Figure 26 respectively.
The control registers are READ/ WRITE registers. To set the control register to READ, bit 7 of the address byte
(OP bit) must be programmed to ‘0’, otherwise ‘1’ for WRITE.
The status registers are READ/CLEAR registers. To CLEAR any Status Register, bit 7 of the address byte must be
set to ‘1’, otherwise ‘0’ for READ.
15
14
13
12
11
10
9
8
CONTROL
REGISTERS
8 Data Bits [D7…D0]
for Configuration & Status Information
STATUS
REGISTERS
0
HB_ACT_1_CTRL
read/write 0 0 0 0 0 LABT 1
HB_ACT_2_CTRL
read/write 1 0 0 0 0 LABT 1
HB_MODE_1_CTRL
read/write 1 1 0 0 0 LABT 1
HB_MODE_2_CTRL
read/write 0 0 1 0 0 LABT 1
PWM_CH_FREQ_CTRL
read/write 0 1 1 0 0 LABT 1
PWM1_DC_CTRL
read/write 1 1 1 0 0 LABT 1
PWM2_DC_CTRL
read/write 0 0 0 1 0 LABT 1
PWM3_DC_CTRL
read/write 1 0 0 1 0 LABT 1
FW_OL_CTRL
read/write 0 1 0 1 0 LABT 1
CONFIG_CTRL
read
1 1 0 0 1 LABT 1
SYS_DIAG_1 : Global status 1
read/clear 0 0 1 1 0 LABT 1
SYS_DIAG_2 : OP ERROR_1_STAT
read/clear 1 0 1 1 0 LABT 1
SYS_DIAG_3 : OP ERROR_2_STAT
read/clear 0 1 1 1 0 LABT 1
SYS_DIAG_5 : OP ERROR_4_STAT
read/clear 0 0 0 0 1 LABT 1
SYS_DIAG_6 : OP ERROR_5_STAT
read/clear 1 0 0 0 1 LABT 1
Figure 25
TLE94106ES SPI Register mapping
Note:
LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3.
Datasheet
7
6 5 4 3 2
1
8 Address Bits [A7…0]
Access
type
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51
CONTROL
REGISTERS
STATUS
REGISTERS
15
HB4_MODE1
reserved
HB_MODE_1_CTRL
HB_MODE_2_CTRL
reserved
HB4_HS_OL
reserved
SYS_DIAG_3 : OP ERROR_2_STAT
SYS_DIAG_5 : OP ERROR_4_STAT
SYS_DIAG_6 : OP ERROR_5_STAT
SPI_ERR
HB4_HS_OC
SYS_DIAG_2 : OP ERROR_1_STAT
SYS_DIAG_1 : Global status 1
reserved
CONFIG_CTRL
PWM3_DC_CTRL_7
PWM3_DC_CTRL
FW_HB6
PWM2_DC_CTRL_7
PWM2_DC_CTRL
FW_OL_CTRL
PWM1_DC_CTRL_7
PWM1_DC_CTRL
FM_CLK_MOD1
reserved
HB_ACT_2_CTRL
PWM_CH_FREQ_CTRL
HB4_HS_EN
D7
HB_ACT_1_CTRL
Register Name
14
reserved
HB4_LS_OL
reserved
HB4_LS_OC
LE
reserved
FW_HB5
PWM3_DC_CTRL_6
PWM2_DC_CTRL_6
PWM1_DC_CTRL_6
FM_CLK_MOD0
reserved
HB4_MODE0
reserved
HB4_LS_EN
D6
13
reserved
HB3_HS_OL
reserved
HB3_HS_OC
VS_UV
reserved
FW_HB4
PWM3_DC_CTRL_5
PWM2_DC_CTRL_5
PWM1_DC_CTRL_5
PWM_CH3_FREQ_1
reserved
HB3_MODE1
reserved
HB3_HS_EN
D5
12
Data Bits D7…D0
11
D3
HB2_HS_EN
reserved
FW_HB2
PWM3_DC_CTRL_3
PWM2_DC_CTRL_3
PWM1_DC_CTRL_3
PWM_CH2_FREQ_1
HB6_MODE1
HB2_MODE1
HB6_HS_EN
reserved
HB3_LS_OL
reserved
HB3_LS_OC
VS_OV
HB6_HS_OL
HB2_HS_OL
HB6_HS_OC
HB2_HS_OC
NPOR
ST AT US REGIST ERS
reserved
FW_HB3
PWM3_DC_CTRL_4
PWM2_DC_CTRL_4
PWM1_DC_CTRL_4
PWM_CH3_FREQ_0
reserved
HB3_MODE0
reserved
HB3_LS_EN
CONTROL REGISTERS
D4
10
HB6_LS_OL
HB2_LS_OL
HB6_LS_OC
HB2_LS_OC
TSD
DEV_ID2
FW_HB1
PWM3_DC_CTRL_2
PWM2_DC_CTRL_2
PWM1_DC_CTRL_2
PWM_CH2_FREQ_0
HB6_MODE0
HB2_MODE0
HB6_LS_EN
HB2_LS_EN
D2
9
HB5_HS_OL
HB1_HS_OL
HB5_HS_OC
HB1_HS_OC
TPW
DEV_ID1
OL_SEL_HS2
PWM3_DC_CTRL_1
PWM2_DC_CTRL_1
PWM1_DC_CTRL_1
PWM_CH1_FREQ_1
HB5_MODE1
HB1_MODE1
HB5_HS_EN
HB1_HS_EN
D1
8
HB5_LS_OL
HB1_LS_OL
HB5_LS_OC
HB1_LS_OC
0
DEV_ID0
OL_SEL_HS1
PWM3_DC_CTRL_0
PWM2_DC_CTRL_0
PWM1_DC_CTRL_0
PWM_CH1_FREQ_0
HB5_MODE0
HB1_MODE0
HB5_LS_EN
HB1_LS_EN
D0
read/clear
read/clear
read/clear
read/clear
read/clear
read
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
1
0
1 0 0 0 1 LABT 1
0 0 0 0 1 LABT 1
0 1 1 1 0 LABT 1
1 0 1 1 0 LABT 1
0 0 1 1 0 LABT 1
1 1 0 0 1 LABT 1
0 1 0 1 0 LABT 1
1 0 0 1 0 LABT 1
0 0 0 1 0 LABT 1
1 1 1 0 0 LABT 1
0 1 1 0 0 LABT 1
0 0 1 0 0 LABT 1
1 1 0 0 0 LABT 1
1 0 0 0 0 LABT 1
0 0 0 0 0 LABT 1
7
6 5 4 3 2
Address Bits A7…A0
Access type
TLE94106ES
Serial Peripheral Interface (SPI)
Figure 26
TLE94106ES Bit Mapping
Note:
LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3.
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TLE94106ES
Serial Peripheral Interface (SPI)
7.6
SPI Control Registers
The Control Registers have a READ/WRITE access (see Chapter 7.5):
•
The ‘POR’ value is defined by the register content after a POR or device Reset
– The default value of all control registers is 0000 0000B with the exception of CONFIG_CTRL
– The default value of the CONFIG_CTRL register is 0000 0011B
•
One 16-bit SPI command consists of two bytes (see Figure 25 and Figure 26), i.e.
– an address byte
– followed by a data byte
•
The control bits are not cleared or changed automatically by the device. This must be done by the
microcontroller via SPI programming.
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= READ ONLY).
•
Writing to a register is done byte wise by setting the SPI bit 7 to “1”.
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Serial Peripheral Interface (SPI)
7.6.1
Control register definition
HB_ACT_1_CTRL
Half-bridge output control 1 (Address Byte [OP] 000 00[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
HB4_HS_EN
HB4_LS_EN
HB3_HS_EN
HB3_LS_EN
HB2_HS_EN
HB2_LS_EN
HB1_HS_EN
HB1_LS_EN
rw
rw
rw
rw
rw
rw
rw
rw
Field
Type
Description
HB4_HS_EN D7
rw
Half-bridge output 4 high side switch enable
0B HS4 OFF/ High-Z (default value)
1B HS4 ON
HB4_LS_EN D6
rw
Half-bridge output 4 low side switch enable
0B LS4 OFF/ High-Z (default value)
1B LS4 ON
HB3_HS_EN D5
rw
Half-bridge output 3 high side switch enable
0B HS3 OFF/ High-Z (default value)
1B HS3 ON
HB3_LS_EN D4
rw
Half-bridge output 3 low side switch enable
0B LS3 OFF/ High-Z (default value)
1B LS3 ON
HB2_HS_EN D3
rw
Half-bridge output 2 high side switch enable
0B HS2 OFF/ High-Z (default value)
1B HS2 ON
HB2_LS_EN D2
rw
Half-bridge output 2 low side switch enable
0B LS2 OFF/ High-Z (default value)
1B LS2 ON
HB1_HS_EN D1
rw
Half-bridge output 1 high side switch enable
0B HS1 OFF/ High-Z (default value)
1B HS1 ON
HB1_LS_EN D0
rw
Half-bridge output 1 low side switch enable
0B LS1 OFF/ High-Z (default value)
1B LS1 ON
Note:
Datasheet
Bits
r
The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the
digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the
logic turns off this half-bridge.
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Serial Peripheral Interface (SPI)
HB_ACT_2_CTRL
Half-bridge output control 2 (Address Byte [OP]100 00[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
reserved
reserved
reserved
reserved
HB6_HS_EN
HB6_LS_EN
HB5_HS_EN
HB5_LS_EN
rw
rw
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
reserved
D7
rw
Reserved. Always reads as ‘0’
reserved
D6
rw
Reserved. Always reads as ‘0’
reserved
D5
rw
Reserved. Always reads as ‘0’
reserved
D4
rw
Reserved. Always reads as ‘0’
HB6_HS_EN D3
rw
Half-bridge output 6 high side switch enable
0B HS6 OFF/ High-Z (default value)
1B HS6 ON
HB6_LS_EN D2
rw
Half-bridge output 6 low side switch enable
0B LS6 OFF/ High-Z (default value)
1B LS6 ON
HB5_HS_EN D1
rw
Half-bridge output 5 high side switch enable
0B HS5 OFF/ High-Z (default value)
1B HS5 ON
HB5_LS_EN D0
rw
Half-bridge output 5 low side switch enable
0B LS5 OFF/ High-Z (default value)
1B LS5 ON
Note:
Datasheet
The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the
digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the
logic turns off this half-bridge.
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TLE94106ES
Serial Peripheral Interface (SPI)
HB_MODE_1_CTRL
Half-bridge output mode control 1 (Address Byte [OP]110 00[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
HB4_MODE1 HB4_MODE0 HB3_MODE1 HB3_MODE0 HB2_MODE1 HB2_MODE0 HB1_MODE1 HB1_MODE0
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
HB4_MODEn
(n = 0,1)
D7:D6
rw
Half-bridge output 4 mode select
00B No PWM (default value)
01B PWM control with PWM Channel 1
10B PWM control with PWM Channel 2
11B PWM control with PWM Channel 3
HB3_MODEn
(n = 0,1)
D5:D4
rw
Half-bridge output 3 mode select
00B No PWM (default value)
01B PWM control with PWM Channel 1
10B PWM control with PWM Channel 2
11B PWM control with PWM Channel 3
HB2_MODEn
(n = 0,1)
D3:D2
rw
Half-bridge output 2 mode select
00B No PWM (default value)
01B PWM control with PWM Channel 1
10B PWM control with PWM Channel 2
11B PWM control with PWM Channel 3
HB1_MODEn
(n = 0,1)
D1:D0
rw
Half-bridge output 1 mode select
00B No PWM (default value)
01B PWM control with PWM Channel 1
10B PWM control with PWM Channel 2
11B PWM control with PWM Channel 3
Note:
Datasheet
rw
rw
Refer to Chapter 6.1.1 for more information on PWM operation
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TLE94106ES
Serial Peripheral Interface (SPI)
HB_MODE_2_CTRL
Half-bridge output mode control 2 (Address Byte [OP]001 00[LABT]1B)
D7
D6
D5
D4
reserved
reserved
reserved
reserved
rw
rw
rw
rw
D3
D2
D1
HB6_MODE1 HB6_MODE0 HB5_MODE1 HB5_MODE0
rw
rw
r
Field
Bits
Type
Description
reserved
D7:D6
rw
Reserved. Always reads as ‘0’.
reserved
D5:D4
rw
Reserved. Always reads as ‘0’.
HB6_MODEn
(n = 0,1)
D3:D2
rw
Half-bridge output 6 mode select
00B No PWM (default value)
01B PWM control with PWM Channel 1
10B PWM control with PWM Channel 2
11B PWM control with PWM Channel 3
HB5_MODEn
(n = 0,1)
D1:D0
rw
Half-bridge output 5 mode select
00B No PWM (default value)
01B PWM control with PWM Channel 1
10B PWM control with PWM Channel 2
11B PWM control with PWM Channel 3
Note:
Datasheet
D0
rw
rw
Refer to Chapter 6.1.1 for more information on PWM operation
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TLE94106ES
Serial Peripheral Interface (SPI)
PWM_CH_FREQ_CTRL
PWM channel frequency select (Address Byte [OP]011 00[LABT]1B)
D7
D6
FM_CLK_
MOD1
FM_CLK_
MOD0
rw
rw
D5
D4
D3
D2
D1
D0
PWM_CH3_F PWM_CH3_F PWM_CH2_F PWM_CH2_F PWM_CH1_F PWM_CH1_F
REQ_1
REQ_0
REQ_1
REQ_0
REQ_1
REQ_0
rw
rw
rw
rw
r
rw
Field
Bits
Type
Description
FM_MOD_EN
D7:D6
rw
FM Modulation Enable1)
00B No modulation (default)
01B Modulation frequency 15.625kHz
10B Modulation frequency 31.25kHz
11B Modulation frequency 62.5kHz
PWM_CH3_FREQ_ D5:D4
n (n=0,1)
rw
PWM Channel 3 frequency select
00B PWM is stopped and off (default value)
01B PWM frequency 1 : 80Hz
10B PWM frequency 2 : 100Hz
11B PWM frequency 3 : 200Hz
PWM_CH2_FREQ_ D3:D2
n (n=0,1)
rw
PWM Channel 2 frequency select
00B PWM is stopped and off (default value)
01B PWM frequency 1 : 80Hz
10B PWM frequency 2 : 100Hz
11B PWM frequency 3 : 200Hz
PWM_CH1_FREQ_ D1:D0
n (n=0,1)
rw
PWM Channel 1 frequency select
00B PWM is stopped and off (default value)
01B PWM frequency 1 : 80Hz
10B PWM frequency 2 : 100Hz
11B PWM frequency 3 : 200Hz
rw
1) Not subject to production test, guaranteed by design. Frequency may deviate by ±10%
Note:
Datasheet
Refer to Chapter 6.1.1 for more information on PWM operation
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TLE94106ES
Serial Peripheral Interface (SPI)
PWM1_DC_CTRL
PWM channel 1 duty cycle configuration (Address Byte [OP]111 00[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
PWM1_DC_
CTRL_7
PWM1_DC_
CTRL_6
PWM1_DC_
CTRL_5
PWM1_DC_
CTRL_4
PWM1_DC_
CTRL_3
PWM1_DC_
CTRL_2
PWM1_DC_
CTRL_1
PWM1_DC_
CTRL_0
rw
rw
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
PWM1_DC_CTRLn
D7:D0
rw
PWM Channel 1 Duty Cycle configuration (bit7=MSB;
bit0)
0000 0000B 100% OFF (default value)
xxxx xxxx B parts of 255 ON
1111 1111B 100% ON
Note:
Refer to Chapter 6.1.1 for more information on PWM operation
PWM2_DC_CTRL
PWM channel 2 duty cycle configuration (Address [OP]000 10[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
PWM2_DC_
CTRL_7
PWM2_DC_
CTRL_6
PWM2_DC_
CTRL_5
PWM2_DC_
CTRL_4
PWM2_DC_
CTRL_3
PWM2_DC_
CTRL_2
PWM2_DC_
CTRL_1
PWM2_DC_
CTRL_0
rw
rw
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
PWM2_DC_CTRLn
D7:D0
rw
PWM Channel 2 Duty Cycle configuration (bit7=MSB;
bit0)
0000 0000B 100% OFF (default value)
xxxx xxxx B parts of 255 ON
1111 1111B 100% ON
Note:
Datasheet
Refer to Chapter 6.1.1 for more information on PWM operation
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TLE94106ES
Serial Peripheral Interface (SPI)
PWM3_DC_CTRL
PWM channel 3 duty cycle configuration (Address Byte [OP]100 10[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
PWM3_DC_
CTRL_7
PWM3_DC_
CTRL_6
PWM3_DC_
CTRL_5
PWM3_DC_
CTRL_4
PWM3_DC_
CTRL_3
PWM3_DC_
CTRL_2
PWM3_DC_
CTRL_1
PWM3_DC_
CTRL_0
rw
rw
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
PWM3_DC_CTRLn
D7:D0
rw
PWM Channel 3 Duty Cycle configuration (bit7=MSB;
bit0)
0000 0000B 100% OFF (default value)
xxxx xxxx B parts of 255 ON
1111 1111B 100% ON
Note:
Datasheet
Refer to Chapter 6.1.1 for more information on PWM operation
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TLE94106ES
Serial Peripheral Interface (SPI)
FW_OL_CTRL
Free-wheeling configuration and Open load detection setting of HS1 and HS2 (Address Byte [OP]010
10[LABT]1B)
D7
D6
D5
D4
D3
D2
FW_HB6
FW_HB5
FW_HB4
FW_HB3
FW_HB2
FW_HB1
rw
rw
rw
rw
rw
rw
D1
D0
OL_SEL_HS2 OL_SEL_HS1
r
rw
rw
Field
Bits
Type
Description
FW_HB6
D7
rw
HB6 free-wheeling configuration
0B Passive free-wheeling (default value)
1B Active free-wheeling
FW_HB5
D6
rw
HB5 free-wheeling configuration
0B Passive free-wheeling (default value)
1B Active free-wheeling
FW_HB4
D5
rw
HB4 free-wheeling configuration
0B Passive free-wheeling (default value)
1B Active free-wheeling
FW_HB3
D4
rw
HB3 free-wheeling configuration
0B Passive free-wheeling (default value)
1B Active free-wheeling
FW_HB2
D3
rw
HB2 free-wheeling configuration
0B Passive free-wheeling (default value)
1B Active free-wheeling
FW_HB1
D2
rw
HB1 free-wheeling configuration
0B Passive free-wheeling (default value)
1B Active free-wheeling
OL_SEL_HS2
D1
rw
HS2 open load detection current and filter time select
0B High-current mode (default value)
1B LED Mode (Low current mode)
OL_SEL_HS1
D0
rw
HS1 open load detection current and filter time select
0B High current mode (default value)
1B LED Mode (Low current mode)
Note:
Datasheet
Refer to Chapter 6.1.1 for more information on PWM operation
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TLE94106ES
Serial Peripheral Interface (SPI)
CONFIG_CTRL
Device Configuration control (Address Byte [OP]110 01[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
reserved
reserved
reserved
reserved
reserved
DEV_ID2
DEV_ID1
DEV_ID0
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
reserved
D7:D3
r
Always reads as ‘0’
DEV_IDn
D2:D0
r
Device/ derivative identifier
Note:
000B
001B
010B
011B
100B
101B
110B
111B
Datasheet
r
These bits can be used to verify the silicon
content of the device
TLE94112EL chip
TLE94110EL chip
TLE94108EL chip
TLE94106EL/ES chip
TLE94104EP chip
TLE94103EP chip
reserved
reserved
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Serial Peripheral Interface (SPI)
7.7
SPI Status Registers
The Control Registers have a READ/CLEAR access (see also Chapter 7.5):
•
The ‘POR Value’ of the Status registers (content after a POR or device Reset) and is 0000 0000B.
•
One 16-bit SPI command consists of two bytes (see Figure 25 and Figure 26), i.e.
– an address byte
– followed by a data byte
•
Reading a register is done byte wise by setting the SPI bit 7 of the address byte to “0” (= Read Only).
•
Clearing a register is done byte wise by setting the SPI bit 7 of the address byte to “1”.
•
SPI status registers are not cleared automatically by the device. This must be done by the microcontroller
via SPI command.
Datasheet
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TLE94106ES
Serial Peripheral Interface (SPI)
7.7.1
Status register definition
SYS_DIAG1
Global status 1 (Address Byte [OP]001 10[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
SPI_ERR
LE
VS_UV
VS_OV
NPOR
TSD
TPW
reserved
rc
r
rc
rc
rc
rc
rc
r
r
Field
Bits
Type
Description
SPI_ERR
D7
rc
SPI error detection
0B No SPI protocol error is detected (default value).
1B An SPI protocol error is detected.
LE
D6
r
Load error detection (logic OR combination of Open Load and
Overcurrent)
0B No Open Load and no Overcurrent detected (default value)
1B Open Load or Overcurrent detected in at least one of the
power outputs. Error latched. Faulty output is latched off in
case of Overcurrent
VS_UV
D5
rc
VS Undervoltage error detection
0B No undervoltage on VS detected (default value)
1B Undervoltage on VS detected. Error latched and all outputs
disabled.
VS_OV
D4
rc
VS Overvoltage error detection
0B No overvoltage on VS detected (default value)
1B Overvoltage on VS detected. Error latched and all outputs
disabled.
NPOR
D3
rc
Not Power On Reset (NPOR) detection
0B POR on EN or VDD supply rail (default value)
1B No POR
TSD
D2
rc
Temperature shutdown error detection
0B Junction temperature below temperature shutdown
threshold (default value)
1B Junction temperature has reached temperature shutdown
threshold. Error latched and all outputs disabled.
TPW
D1
rc
Temperature pre-warning error detection
0B Junction temperature below temperature pre-warning
threshold (default value)
1B Junction temperature has reached temperature pre-warning
threshold.
reserved
D0
r
Bit reserved. Always reads ‘0’.
Note:
Datasheet
The LE bit in the Global Status register is read only. It reflects an OR combination of the respective
open load and overcurrent errors of the half-bridge channels. If all OC/ OL bits of the respective highside and low-side channels are cleared to ‘0’, the LE bit will be automatically updated to ‘0’.
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TLE94106ES
Serial Peripheral Interface (SPI)
SYS_DIAG_2 : OP_ERROR_1_STAT
Overcurrent error status of half-bridge outputs 1 - 4 (Address Byte [OP]101 10[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
HB4_HS_OC HB4_LS_OC HB3_HS_OC HB3_LS_OC HB2_HS_OC HB2_LS_OC HB1_HS_OC HB1_LS_OC
rc
Field
rc
rc
rc
rc
r
rc
rc
Type
Description
HB4_HS_OC D7
rc
High-side (HS) switch of half-bridge 4 overcurrent detection
0B No error on HS4 switch (default value)
1B Overcurrent detected on HS4 switch. Error latched and HS4
disabled.
HB4_LS_OC
D6
rc
Low-side (LS) switch of half-bridge 4 overcurrent detection
0B No error on LS4 switch (default value)
1B Overcurrent detected on LS4 switch. Error latched and LS4
disabled.
HB3_HS_OC D5
rc
High-side (HS) switch of half-bridge 3 overcurrent detection
0B No error on HS3 switch (default value)
1B Overcurrent detected on HS3 switch. Error latched and HS3
disabled.
HB3_LS_OC
D4
rc
Low-side (LS) switch of half-bridge 3 overcurrent detection
0B No error on LS3 switch (default value)
1B Overcurrent detected on LS3 switch. Error latched and LS3
disabled.
HB2_HS_OC D3
rc
High-side (HS) switch of half-bridge 2 overcurrent detection
0B No error on HS2 switch (default value)
1B Overcurrent detected on HS2 switch. Error latched and HS2
disabled.
HB2_LS_OC
D2
rc
Low-side (LS) switch of half-bridge 2 overcurrent detection
0B No error on LS2 switch (default value)
1B Overcurrent detected on LS2 switch. Error latched and LS2
disabled.
HB1_HS_OC D1
rc
High-side (HS) switch of half-bridge 1 overcurrent detection
0B No error on HS1 switch (default value)
1B Overcurrent detected on HS1 switch. Error latched and HS1
disabled.
HB1_LS_OC
rc
Low-side (LS) switch of half-bridge 1 overcurrent detection
0B No error on LS1 switch (default value)
1B Overcurrent detected on LS1 switch. Error latched and LS1
disabled.
Datasheet
Bits
rc
D0
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Serial Peripheral Interface (SPI)
SYS_DIAG_3 : OP_ERROR_2_STAT
Overcurrent error status of half-bridge outputs 5 - 8 (Address Byte [OP]011 10[LABT]1B)
D7
D6
D5
D4
reserved
reserved
reserved
reserved
rc
rc
rc
rc
D3
D2
D1
D0
HB6_HS_OC HB6_LS_OC HB5_HS_OC HB5_LS_OC
rc
rc
r
rc
rc
Field
Bits
Type
Description
reserved
D7
rc
Reserved. Always reads as ‘0’.
reserved
D6
rc
Reserved. Always reads as ‘0’.
reserved
D5
rc
Reserved. Always reads as ‘0’.
reserved
D4
rc
Reserved. Always reads as ‘0’.
HB6_HS_OC D3
rc
High-side (HS) switch of half-bridge 6 overcurrent detection
0B No error on HS6 switch (default value)
1B Overcurrent detected on HS6 switch. Error latched and HS6
disabled.
HB6_LS_OC
D2
rc
Low-side (LS) switch of half-bridge 6 overcurrent detection
0B No error on LS6 switch (default value)
1B Overcurrent detected on LS6 switch. Error latched and LS6
disabled.
HB5_HS_OC D1
rc
High-side (HS) switch of half-bridge 5 overcurrent detection
0B No error on HS5 switch (default value)
1B Overcurrent detected on HS5 switch. Error latched and HS5
disabled.
HB5_LS_OC
rc
Low-side (LS) switch of half-bridge 5 overcurrent detection
0B No error on LS5 switch (default value)
1B Overcurrent detected on LS5 switch. Error latched and LS5
disabled.
Datasheet
D0
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Serial Peripheral Interface (SPI)
SYS_DIAG_5 : OP_ERROR_4_STAT
Open load error status of half-bridge outputs 1 - 4 (Address Byte [OP]000 01[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
HB4_HS_OL
HB4_LS_OL
HB3_HS_OL
HB3_LS_OL
HB2_HS_OL
HB2_LS_OL
HB1_HS_OL
HB1_LS_OL
rc
rc
rc
rc
rc
rc
rc
rc
Field
Type
Description
HB4_HS_OL D7
rc
High-side (HS) switch of half-bridge 4 open load detection
0B No error on HS4 switch (default value)
1B Open load detected on HS4 switch. Error latched.
HB4_LS_OL D6
rc
Low-side (LS) switch of half-bridge 4 open load detection
0B No error on LS4 switch (default value)
1B Open load detected on LS4 switch. Error latched.
HB3_HS_OL D5
rc
High-side (HS) switch of half-bridge 3 open load detection
0B No error on HS3 switch (default value)
1B Open load detected on HS3 switch. Error latched.
HB3_LS_OL D4
rc
Low-side (LS) switch of half-bridge 3 open load detection
0B No error on LS3 switch (default value)
1B Open load detected on LS3 switch. Error latched.
HB2_HS_OL D3
rc
High-side (HS) switch of half-bridge 2 open load detection
0B No error on HS2 switch (default value)
1B Open load detected on HS2 switch. Error latched.
HB2_LS_OL D2
rc
Low-side (LS) switch of half-bridge 2 open load detection
0B No error on LS2 switch (default value)
1B Open load detected on LS2 switch. Error latched.
HB1_HS_OL D1
rc
High-side (HS) switch of half-bridge 1 open load detection
0B No error on HS1 switch (default value)
1B Open load detected on HS1 switch. Error latched.
HB1_LS_OL D0
rc
Low-side (LS) switch of half-bridge 1 open load detection
0B No error on LS1 switch (default value)
1B Open load detected on LS1 switch. Error latched.
Datasheet
Bits
r
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TLE94106ES
Serial Peripheral Interface (SPI)
SYS_DIAG_6 : OP_ERROR_5_STAT
Open load error status of half-bridge outputs 5 - 8 (Address Byte [OP]100 01[LABT]1B)
D7
D6
D5
D4
D3
D2
D1
D0
reserved
reserved
reserved
reserved
HB6_HS_OL
HB6_LS_OL
HB5_HS_OL
HB5_LS_OL
rc
rc
rc
rc
rc
rc
rc
rc
r
Field
Bits
Type
Description
reserved
D7
rc
Reserved. Always reads as ‘0’.
reserved
D6
rc
Reserved. Always reads as ‘0’.
reserved
D5
rc
Reserved. Always reads as ‘0’.
reserved
D4
rc
Reserved. Always reads as ‘0’.
HB6_HS_OL D3
rc
High-side (HS) switch of half-bridge 6 open load detection
0B No error on HS6 switch (default value)
1B Open load detected on HS6 switch. Error latched.
HB6_LS_OL D2
rc
Low-side (LS) switch of half-bridge 6 open load detection
0B No error on LS6 switch (default value)
1B Open load detected on LS6 switch. Error latched.
HB5_HS_OL D1
rc
High-side (HS) switch of half-bridge 5 open load detection
0B No error on HS5 switch (default value)
1B Open load detected on HS5 switch. Error latched.
HB5_LS_OL D0
rc
Low-side (LS) switch of half-bridge 5 open load detection
0B No error on LS5 switch (default value)
1B Open load detected on LS5 switch. Error latched.
Datasheet
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TLE94106ES
Application Information
8
Application Information
Note:
The following simplified application examples are given as a hint for the implementation of the
device only and shall not be regarded as a description or warranty of a certain functionality,
condition or quality of the device. The function of the described circuits must be verified in the real
application.
8.1
Application Diagram
VS
VBAT
VBAT
100nF
3 motors in
non-cascaded
configuration
VBAT
10µF
S1
VS V CC1
WK
100nF
100nF
VDD
VDD
VS1 VS2
5 motors in
cascaded
configuration
OUT 1
WK
10kΩ
1kΩ
µC
TLE9263
TLE94106ES
22nF,
50V
EN
M1
M1
OUT 2
SDO
M2
SDI
10µF
SDO
/CS
VCC2
VCCHSCAN
CAN-H
CSN
INT
60Ω
47nF
VDD
10kΩ
Series resistors are
recommended if VS1/2 of the
TLE94106ES is protected by
an active reverse polarity
protection
M4
OUT 5
60Ω
CAN-L
M3
RO
GND
M3
OUT 4
SCLK
SPLIT
CANL
M2
SDI
SCLK
CANH
OUT 3
GND GND
GND
M5
OUT 6
Landing pads for ceramic
capacitors at OUTx
Figure 27
Datasheet
Application example for DC-motor loads
68
1.0
2018-01-08
TLE94106ES
Application Information
VS
VBAT
VBAT
100nF
VBAT
10µF
S1
VS
WK
VCC1
100nF
100nF
VDD
VDD
VS1 VS2
OUT 1
WK
10kΩ
1kΩ
µC
TLE9263
TLE94106ES
22nF,
50V
EN
M1
OUT 2
SDO
x-adjustment
y-adjustment
M2
Right side
mirror
SDI
10µF
SDO
/CS
VCC2
VCCHSCAN
SDI
SCLK
CANH
OUT 4
CAN-H
CSN
INT
60Ω
47nF
OUT 3
VDD
M3
SCLK
SPLIT
Left side
mirror
OUT 5
10kΩ
60Ω
CANL
Series resistors are
recommended if VS1/2 of the
TLE94106ES is protected by
an active reverse polarity
protection
M4
CAN-L
x-adjustment
RO
y-adjustment
OUT 6
GND
GND GND
GND
Landing pads for ceramic
capacitors at OUTx
Figure 28
Application example for side mirrors
Notes on the application example
1. Series resistors between the microcontroller and the signal pins of the TLE94106ES are recommended if an
active reverse polarity protection (MOSFET) is used to protect VS1 and VS2 pins. These resistors limit the
current between the microcontroller and the device during negative transients on VBAT (e.g. ISO/TR 7637
pulse 1)
2. Landing pads for ceramic capacitors at the outputs of the TLE94106ES as close as possible to the connectors
are recommended (the ceramic capacitors are not populated if unused). These ceramic capacitors can be
mounted if a higher performance in term of ESD capability is required.
3. The electrolytic capacitor at the VSx pins should be dimensioned in order to prevent the VS voltage from
exceeding the absolute maximum rating. PWM operation with a too low capacitance can lead to a VS voltage
overshoot, which results in a VS overvoltage detection.
4. Unused outputs are recommended to be left unconnected (open) in the application. If unused output pins are
routed to an external connector which leaves the PCB, then these outputs should have provision for a zero
ohm jumper (depopulated if unused) or ESD protection. In other words, unused pins should be treated like
used pins.
Datasheet
69
1.0
2018-01-08
TLE94106ES
Application Information
5. Place bypass ceramic capacitors as close as possible to the VSx pins, with shortest connections the GND pins
and GND layer, for best EMC performance
Datasheet
70
1.0
2018-01-08
TLE94106ES
Application Information
8.2
Thermal application information
Ta = 85°C, Ch1 to Ch6 are dissipating a total of 0.81W (0.135W each).
Zth-ja for TLE94106ES
100
90
JEDEC 1s0p with footprint
80
Zth-ja [K/W]
70
60
JEDEC 1s0p with 300 mm² cooling area
JEDEC 1s0p with 600 mm² cooling area
JEDEC 2s2p with thermal vias
50
40
30
20
10
0
0.0001
0.001
0.01
0.1
1
10
100
1000
10000
time [s]
Figure 29
ZthJA Curve for different PCB setups
Zth-jc for TLE94106ES
3.5
3
Zth-jc [K/W]
2.5
2
1.5
1
0.5
0
0.000001 0.00001 0.0001
0.001
0.01
0.1
1
10
100
1000
10000
time [s]
Figure 30
Datasheet
ZthJC Curve
71
1.0
2018-01-08
TLE94106ES
Application Information
8.3
EMC Enhancement
In the event the emissions of the device exceed the allowable limits, a modulation of the oscillator frequency
is incorporated to reduce eventual harmonics of the 8MHz base clock. The frequencies can be selected based
on the resolution bandwidth of the peak detector during EMC testing.
The selection is achieved by setting the FM_CLK_MODn bits in the PWM_CH_FREQ_CTRL register as follows:
00B: OFF
01B: FM CLK=15.625 kHZ
10B: FM CLK=31.25 kHz
11B: FM CLK=62.5 kHz
Datasheet
72
1.0
2018-01-08
TLE94106ES
Package Outlines
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Figure 31
@
PG-TSDSO-24 (Plastic/Plastic Green - Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e lead-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Datasheet
73
Dimensions in mm
1.0
2018-01-08
TLE94106ES
Revision History
10
Revision History
Revision Date
Changes
1.0
Fist release
Datasheet
2017-01-08
74
1.0
2018-01-08
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-01-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
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