TLE9842-2QX

TLE9842-2QX Microcontroller with LIN and Power Switches for Automotive Applications Data Sheet Rev. 1.0, 2016-05-06 Automotive Power TLE9842-2QX Table of Contents Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 3.1 3.2 Device Pinout and Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Generation (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Reset Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 19 21 22 22 23 24 25 6 6.1 6.2 6.2.1 6.3 6.3.1 6.3.2 6.3.2.1 6.3.2.2 6.3.3 System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Input Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Crystal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 27 29 29 29 29 29 31 7 7.1 7.2 7.2.1 System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of the Power Modules System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 33 8 8.1 8.2 8.2.1 ARM Cortex-M0 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 36 36 9 Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 10.1 10.2 10.2.1 Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11.1 11.1.1 NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12 12.1 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data Sheet 2 39 39 39 39 Rev. 1.0, 2016-05-06 TLE9842-2QX Table of Contents 12.2 12.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13 13.1 13.2 Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.1.1 14.3.2 14.3.2.1 14.3.3 14.3.3.1 GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE9842-2QX Port Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 49 50 51 52 52 52 55 55 57 57 15 15.1 15.1.1 15.1.2 15.2 15.2.1 15.2.2 General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 59 59 59 60 61 16 16.1 16.2 16.2.1 Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 62 62 17 17.1 17.2 17.2.1 Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 64 64 65 18 18.1 18.2 18.2.1 18.3 UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 66 66 67 67 19 19.1 19.2 19.2.1 LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 68 69 20 20.1 20.2 20.2.1 High-Speed Synchronous Serial Interface SSC1/SSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 70 70 71 21 21.1 21.2 Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Data Sheet 3 Rev. 1.0, 2016-05-06 TLE9842-2QX Table of Contents 21.2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22 22.1 22.2 22.2.1 Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 74 74 74 23 23.1 23.2 23.2.1 10-Bit Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 76 76 24 24.1 24.2 24.2.1 High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 77 77 25 25.1 25.2 25.2.1 25.2.2 High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 78 79 79 79 26 26.1 26.2 Low-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 27 27.1 27.2 27.3 27.4 27.5 27.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relay Window Lift Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection of N.C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection of P0.2 for SWD debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection of TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Immunity According to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28.1 28.1.1 28.1.2 28.1.3 28.1.4 28.1.5 28.2 28.2.1 28.2.2 28.2.3 28.2.4 28.2.5 28.2.5.1 28.2.6 28.3 28.3.1 28.3.2 28.4 28.4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PMU Input Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PMU I/O Supply Parameters VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PMU Core Supply Parameters VDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 VDDEXT Voltage Regulator 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Load Sharing of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Electrical Characteristics Oscillators and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 External Clock Parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Data Sheet 4 82 82 83 83 84 84 84 Rev. 1.0, 2016-05-06 TLE9842-2QX Table of Contents 28.5 28.5.1 28.5.2 28.5.3 28.5.4 28.6 28.6.1 28.7 28.7.1 28.8 28.8.1 28.8.2 28.8.2.1 28.9 28.9.1 28.9.2 28.10 28.10.1 28.11 28.11.1 28.12 28.12.1 Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters Port 0, Port 1, TMS, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Temperature Sensor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC1 Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 30 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Data Sheet 5 103 103 104 106 107 109 109 113 113 114 114 117 117 118 118 118 120 120 121 121 124 124 Rev. 1.0, 2016-05-06 Microcontroller with LIN and Power Switches for Automotive Applications 1 TLE9842-2QX Overview Summary of Features • • • • • • • • • • • • • • • • • • • • • • • • 32-bit ARM Cortex-M0 Core – up to 40 MHz clock frequency – one clock per machine cycle architecture – single cycle multiplier On-chip memory – 40 KB Flash (including EEPROM) VQFN-48-31 – 4 KB EEPROM (emulated in Flash) – 768 bytes 100 Time Programmable Memory (100TP) – 2 KB RAM – Boot ROM for startup firmware and Flash routines On-chip OSC 2 Low-Side Switches incl. PWM functionality, can be used e.g. as relay driver 2 High-Side Switches with cyclic sense option and PWM functionality, e.g. for supplying LEDs or switch panels (min. 150 mA) 5 High Voltage Monitor Input pins for wake-up and with cyclic sense with analog measurement option 10 General-purpose I/O Ports (GPIO) 6 Analog input Ports 10-Bit A/D Converter with 6 analog inputs + VBAT_SENSE + VS + 5 high voltage monitoring inputs 8-Bit A/D Converter with 7 inputs for voltage and temperature supervision Measurement unit with 12 channels together with the onboard 10-Bit A/D converter and data post processing 16-Bit timers - GPT12, Timer 2 and Timer 21 Capture/compare unit for PWM signal generation (CCU6) 2 full duplex serial interfaces (UART1, UART2), UART1 with LIN support 2 synchronous serial channels (SSC1, SSC2) On-chip debug support via 2-wire SWD LIN Bootstrap loader to program the Flash via LIN (LIN BSL) 1 LIN 2.2 transceiver Single power supply from 3.0 V to 28 V Low-dropout voltage regulators (LDO) 5 V voltage supply VDDEXT for external loads (e.g. Hall-sensor) Core logic supply at 1.5 V Programmable window watchdog (WDT1) with independent on-chip clock source Power saving modes: – Micro Controller Unit slow-down mode Type Package Marking TLE9842-2QX VQFN-48-31 TLE9842-2QX Data Sheet 6 Rev. 1.0, 2016-05-06 TLE9842-2QX Overview • • • • • • • • – Sleep Mode with cyclic sense option – Cyclic wake-up during Sleep Mode – Stop Mode with cyclic sense option Power-on and undervoltage/brownout reset generator Overtemperature protection Short circuit protection for all voltage regulators and actuators (High Side, Low Side) Loss of clock detection with fail safe mode for power switches Temperature Range TJ: -40 °C up to 150 °C Package VQFN-48-31 with LTI feature Green package (RoHS compliant) AEC Qualified Data Sheet 7 Rev. 1.0, 2016-05-06 TLE9842-2QX Overview 1.1 Abbreviations The following acronyms and terms are used within this document. List see in Table 1. Table 1 Acronyms Acronyms Name AHB ARM Advanced High-Performance Bus CCU6 Capture Compare Unit 6 CGU Clock Generation Unit CLKMU Clock Management Unit CMU Cyclic Management Unit DPP Data Post Processing ECC Error Correction Code EEPROM Electrically Erasable Programmable Read Only Memory GPIO General Purpose Input Output HV High Voltage ICU Interrupt Control Unit LDO Low DropOut voltage regulator LIN Local Interconnect Network LSB Least Significant Bit LTI Lead Tip Inspection LV Low Voltage MCU Microcontroller Unit MF Measurement Functions MPU Memory Protection Unit MRST Master Receive / Slave Transmit, corresponds to MISO in SPI MSB Most Significant Bit MTSR Master Transmit / Slave Receive, corresponds to MOSI in SPI MU Measurement Unit NMI Non Maskable Interrupt NVIC Nested Vector Interrupt Controller OSC Oscillator OTP One Time Programmable PBA Peripheral Bridge PC Program Counter PCU Power Control Unit PD Pull Down PGU Power supply Generation Unit PLL Phase Locked Loop PMU Power Management Unit PPB Private Peripheral Bus Data Sheet 8 Rev. 1.0, 2016-05-06 TLE9842-2QX Overview Table 1 Acronyms Acronyms Name PSW Program Status Word PU Pull Up PWM Pulse Width Modulation RAM Random Access Memory RCU Reset Control Unit rfu reserved for future use RMU Reset Management Unit ROM Read Only Memory SCU System Control Unit SOW Short Open Window (for WDT1) SPI Serial Peripheral Interface SSC Synchronous Serial Channel SWD ARM Serial Wire Debug TCCR Temperature Compensation Control Register TMS Test Mode Select TSD Thermal Shut Down UART Universal Asynchronous Receiver Transmitter VBG Voltage reference Band Gap VCO Voltage Controlled Oscillator WDT1 Watchdog timer in SCU-PM (System Control Unit - Power Modules) WMU Wake-up Management Unit 100TP 100 Times Programmable Data Sheet 9 Rev. 1.0, 2016-05-06 TLE9842-2QX Block Diagram 2 Block Diagram TMS P0.0 TEST / DEBUG INTERFACE ARM CORTEX-M0 FLASH systembus SRAM slave ROM slave slave Multilayer AHB Matrix slave slave PBA0 P2.x (ANx) VBAT_SENSE ADC10B DPP1 LS1 UART1 CCU6 GPIO UART2 LS1 GNDLS LS2 PBA1 GPT12 LS2 SSC1 LIN SSC2 MU: P0.x P1.x P2.x LIN GNDLIN ADC8B HS1 HS1 HS2 HS2 T2 DPP2 T21 PMU – Power Management Unit VS RESET VDDEXT VDDP VDDC 1- 5 MON MON 1...5 PLL SCU_DM WDT1 SCU_PM Figure 1 Data Sheet Block Diagram, TLE9842-2QX 10 Rev. 1.0, 2016-05-06 TLE9842-2QX Device Pinout and Pin Configuration Device Pinout and Pin Configuration 3.1 Device Pinout 36 35 34 33 32 31 30 29 28 27 26 25 P2.3 P2.7 P2.6 P2.2 P2.4 / XTAL1 P2.5 / XTAL2 GNDP N.C. N.C. N.C. P1.4 P0.5 3 E E 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 P0.4 P0.3 P0.2 RESET P0.0 / SWD _CLK GNDP TMS / SWD _IO P0.1 P1.2 P1.1 P1.0 GNDLS LIN 1 GNDLIN 2 HS1 3 HS2 4 MON1 5 MON2 6 MON3 7 MON4 8 MON5 9 N.C. 10 LS1 11 LS2 12 E E P2.1 N.C. P2.0 N.C. N.C. VDDC GNDA VDDP VDDEXT N.C. VS VBAT _SENSE Figure 2 Data Sheet Device Pinout, TLE9842-2QX 11 Rev. 1.0, 2016-05-06 TLE9842-2QX Device Pinout and Pin Configuration 3.2 Pin Configuration After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings: • • • • Pull-up enabled only (PU) Pull-down enabled only (PD) Input with both pull-up and pull-down disabled (I) Output with output stage deactivated = high impedance state (Hi-Z) The functions and default states of the TLE9842-2QX external pins are provided in the following table. Type: indicates the pin type. • • • • I/O: Input or output I: Input only O: Output only P: Power supply Not all alternate functions listed, see Chapter 14. Table 2 Symbol Pin Definitions and Functions Pin Number Type Reset State P0 Function Port 0 Port 0 is an 6-Bit bidirectional general purpose I/O port. Alternate functions can be assigned and are listed in the Port description. Main function is listed below. P0.0 20 I/O I/PU SWD_CLK GPIO Serial Wire Debug Clock General Purpose IO Alternate function mapping see Table 8 P0.1 17 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 8 P0.2 22 I/O I/PD GPIO General Purpose IO Alternate function mapping see Table 8 P0.3 23 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 8 P0.4 24 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 8 P0.5 25 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 8 P1 Port 1 Port 1 is an 4-Bit bidirectional general purpose I/O port. Alternate functions can be assigned and are listed in the Port description. Main function is listed below. P1.0 14 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 P1.1 15 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 P1.2 16 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 P1.4 26 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 Data Sheet 12 Rev. 1.0, 2016-05-06 TLE9842-2QX Device Pinout and Pin Configuration Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset State P2 Function Port 2 Port 2 is an 8-Bit general purpose input-only port. Alternate functions can be assigned and are listed in the Port description. Main function is listed below. P2.0 39 I I AN0 ADC1 analog input channel 12 Alternate function mapping see Table 10 P2.1 37 I I AN1 ADC1 analog input channel 7 Alternate function mapping see Table 10 P2.2 33 I I AN2 ADC1 analog input channel 8 Alternate function mapping see Table 10 P2.3 36 I I AN3 ADC1 analog input channel 9 Alternate function mapping see Table 10 P2.4 32 I I P2.5 31 XTAL11) Alternate function mapping see Table 10 External oscillator input Alternate function mapping see Table 10 External oscillator output I O I Hi-Z XTAL21) P2.6 34 I I AN6 ADC1 analog input channel 10 Alternate function mapping see Table 10 P2.7 35 I I AN7 ADC1 analog input channel 11 Alternate function mapping see Table 10 VS 47 P – Battery supply input VDDP 44 P – I/O port supply (5.0 V). Do not connect external loads. For buffer and bypass capacitors. VDDC 42 P – Core supply (1.5 V during Active Mode, 0.9 V during Stop Mode). Do not connect external loads. For buffer/bypass capacitor. VDDEXT 45 P – External voltage supply output (5.0 V, 20 mA) GNDLS 13 P – Low-side ground LS1, LS2 GNDP 19, 30 P – Core supply ground GNDA 43 P – Analog supply ground GNDLIN 2 P – LIN ground MON1 5 I I High Voltage Monitor Input 1 MON2 6 I I High Voltage Monitor Input 2 MON3 7 I I High Voltage Monitor Input 3 MON4 8 I I High Voltage Monitor Input 4 MON5 9 I I High Voltage Monitor Input 5 Power Supply Monitor Inputs High-Side Switch / Low-Side Switch Outputs LS1 Data Sheet 11 O Hi-Z Low-Side switch output 1 13 Rev. 1.0, 2016-05-06 TLE9842-2QX Device Pinout and Pin Configuration Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset State Function LS2 12 O Hi-Z Low-Side Switch output 2 HS1 3 O Hi-Z High-Side Switch output 1 HS2 4 O Hi-Z High-Side Switch output 2 1 I/O PU LIN bus interface input/output TMS 18 I I/PD TMS SWD_IO RESET 21 I/O I/O/PU Reset input/output, not available during Sleep Mode VBAT_SENSE 48 I I Battery supply voltage sense input N.C. 10, 27, 28, 29, 38, 40, 41, 46 – – Not connected, can be connected to GND EP – – – Exposed Pad, connect to GND LIN Interface LIN Others test mode select input Serial Wire Debug input/output 1) configurable by user Data Sheet 14 Rev. 1.0, 2016-05-06 TLE9842-2QX Modes of Operation 4 Modes of Operation This highly integrated circuit contains analog and digital functional blocks. For system and interface control an embedded 32-Bit Cortex-M0 microcontroller is included. For internal and external power supply purposes, on-chip low drop-out regulators are existent. An internal oscillator (no external components necessary) provides a cost effective and suitable clock in particular for LIN slave nodes. As communication interface, a LIN transceiver and several High Voltage Monitor Inputs with adjustable threshold and filters are available. Furthermore two HighSides Switches (e.g. for driving LEDs or powering of switches), two low-side switches (e.g. for relays) and several general purpose input/outputs (GPIO) with pulse-width modulation (PWM) capabilities are available. The Micro Controller Unit supervision and system protection including reset feature is controlled by a programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. All relevant modules offer power saving modes in order to support terminal 30 connected automotive applications. A wake-up from the power saving mode is possible via a LIN bus message, via the monitoring inputs or repetitive with a programmable time period (cyclic wake-up). The integrated circuit is available in a package with 0.5 mm pitch and is designed to withstand the challenging conditions of automotive applications. The TLE9842-2QX has several operational modes mainly to support low power consumption requirements. The low power modes and state transitions are depicted in Figure 3 below. Power-up VS > 3V Reset WDT1 reset (error_wdt++) Transition by software Transition by external event VDDC stable & error_supp < 5 VDDC fail (error_supp++) Safety Fallback Transition by internal event Safety fallback error_supp = 5 Cyclic wake LIN wake or MON wake or GPIO wake Active Mode STOP command Stop Mode Cyclic wake LIN wake or MON wake SLEEP command Safety fallback error_wdt = 5 Sleep Mode Cyclic-sense Cyclic-sense PMU_System_Modes.vsd Figure 3 Data Sheet Power Control State Diagram 15 Rev. 1.0, 2016-05-06 TLE9842-2QX Modes of Operation Reset Mode The Reset Mode is a transition mode e.g. during power-up of the device after a power-on reset. In this mode the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable, the Active Mode is entered. In case the watchdog timer WDT1 fails for more than four times, a fail-safe transition to the Sleep Mode is done. Active Mode In Active Mode all modules are activated and the TLE9842-2QX is fully operational. Stop Mode The Stop Mode is one out of two major low power modes. The transition to the low power modes is done by setting the respective Bits in the mode control register. In Stop Mode the embedded microcontroller is still powered allowing faster wake-up reaction times, but not clocked. A wake-up from this mode is possible by LIN bus activity, the High Voltage Monitor Input pins or the respective 5V GPIOs. Sleep Mode The Sleep Mode is a major low-power mode. The transition to the low-power modes is done by setting the respective Bits in the Micro Controller Unit mode control register. The sleep time is configurable. In Sleep Mode the embedded microcontroller power supply is deactivated, allowing the lowest system power consumption, but the wake-up time is longer compared to the Stop Mode. In this mode a 64 bit wide buffer for data storage is available. A wake-up from this mode is possible by LIN bus activity or the High Voltage Monitor Input pins and cyclic wake. A wake-up from Sleep Mode behaves similar to a power-on reset. While changing into Sleep Mode, no incoming wake-requests are lost (i.e. no dead-time). It is possible to enter sleep-mode even with LIN dominant. Cyclic Wake-up Mode The cyclic wake-up mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the cyclic wake-up mode is done by first setting the respective Bits in the mode control register followed by the SLEEP or STOP command. Additional to the cyclic wake-up behavior (wake-up after a programmable time period), the wake-up sources of the normal Stop Mode and Sleep Mode are available. Cyclic Sense Mode The cyclic sense mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the cyclic sense mode is done by first setting the respective Bits in the mode control register followed by the STOP or SLEEP command. In cyclic sense mode the High-Side Switch can be switched on periodically for biasing some switches for example. The wake-up condition is configurable, when the sense result of defined monitor inputs at a window of interest changed compared to the previous wake-up period or reached a defined state respectively. In this case the Active Mode is entered immediately. The following table shows the possible power mode configurations of each major module or function respectively. Table 3 Power Mode Configurations Module/function Active Mode Sleep Mode Stop Mode Comment VPRE, VDDP, VDDC ON OFF ON – VDDEXT ON/OFF OFF cyclic ON/OFF – HSx ON/OFF cyclic ON/OFF cyclic ON/OFF cyclic sense LSx ON/OFF OFF OFF – LIN TRx ON/OFF wake-up only / OFF wake-up only/ OFF – Data Sheet 16 Rev. 1.0, 2016-05-06 TLE9842-2QX Modes of Operation Table 3 Power Mode Configurations (cont’d) Module/function Active Mode Sleep Mode Stop Mode Comment MONx (wake-up) n.a. disabled/static/ cyclic disabled/static/ cyclic cyclic: combined with HS=on MONx (measurement) ON/OFF OFF OFF available on all channels VS sense ON/OFF brownout detection brownout detection brownout detection brownout det. done in PCU VBAT_SENSE ON/OFF OFF OFF – GPIO 5V ON OFF ON – WDT1 ON OFF OFF – CYCLIC WAKE n.a. cyclic wake-up/ cyclic sense/OFF cyclic wake-up/ cyclic sense with HS; cyclic sense/OFF wake-up needs MC for enter Sleep Mode again Measurement ON1) OFF OFF – Micro Controller Unit ON/slowdown/STOP OFF OFF – CLOCK GEN (MC) ON OFF OFF – LP_CLK (fLP_CLK) ON OFF OFF WDT1 LP_CLK2 (fLP_CLK2) ON ON ON for cyclic wake-up 1) May not be switched off due to safety reasons Wake-up Source Prioritization All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are latched in order to provide all wake-up events to the application software. The software can clear the wake-up source flags. It is ensured, that no wake-up event is lost. As default wake-up sources, MON inputs and cyclic wake are activated after power-on reset, LIN is disabled as wake-up source by default. Wake-up Levels and Transitions The wake-up can be triggered by rising, falling or both signal edges for each monitor input individually. Data Sheet 17 Rev. 1.0, 2016-05-06 TLE9842-2QX Power Management Unit (PMU) 5 Power Management Unit (PMU) 5.1 Features • • • • • • System modes control (startup, sleep, stop and active) Power management (cyclic wake) Control of system voltage regulators with diagnosis (overload, short, overvoltage) Fail safe mode detection and operation in case of system errors (watchdog fail) Wake-up sources configuration and management (LIN, MON, GPIOs) System error logging 5.2 Introduction The purpose of the power management unit is to ensure the fail safe behavior of the system IC. Therefore the power management unit controls all system modes including the corresponding transitions. The power management unit is responsible for generating all needed voltage supplies for the embedded MCU (VDDC, VDDP) and the external supply (VDDEXT). Additionally, the PMU provides well defined sequences for the system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset behavior of all system functionalities especially the reset behavior of the embedded MCU. All these functions are controlled by finite state machines. The system master functionality of the PMU requires the generation of an independent logic supply and system clock. Therefore the PMU has a module internal logic supply and system clock which works independently of the MCU clock. Data Sheet 18 Rev. 1.0, 2016-05-06 TLE9842-2QX Power Management Unit (PMU) 5.2.1 Block Diagram The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules more detailed. VS Power Down Supply e.g. for WDT 1 Power Supply Generation Unit (PGU) I N T E R N A L LP_CLK Peripherals e.g. for cyclic wake LP_CLK2 PMU-PCU MONx LIN B U S LDO for External Supply VDDEXT VDDP VDDC VDDEXT PMU-SFR PMU-CMU PMU-WMU PMU-RMU PMU-Control Power Management Unit Power_ Management.vsd Figure 4 Power Management Unit Block Diagram Table 4 Description of PMU Submodules Mod. Name Modules Functions Power Down Supply Independent Supply Voltage Generation for PMU This supply is dedicated to the PMU to ensure an independent operation from generated power supplies (VDDP, VDDC). LP_CLK (= fLP_CLK) - Clock Source for all PMU submodules - Backup Clock Source for System - Clock Source for WDT1 This ultra low power oscillator generates the clock for the PMU. This clock is also used as backup clock for the system in case of PLL Clock failure and as independent clock source for WDT1. LP_CLK2 (= fLP_CLK2) Clock Source for PMU This ultra low power oscillator generates the clock for the PMU in Stop Mode and in the cyclic modes. Peripherals Peripheral Blocks of PMU These blocks include the analog peripherals to ensure a stable and fail safe PMU startup and operation (bandgap, bias). Data Sheet 19 Rev. 1.0, 2016-05-06 TLE9842-2QX Power Management Unit (PMU) Table 4 Description of PMU Submodules (cont’d) Mod. Name Modules Functions Power Supply Generation Unit (PGU) Voltage regulators for VDDP and VDDC This block includes the voltage regulators for the pad supply (VDDP) and the core supply (VDDC). VDDEXT Voltage regulator for VDDEXT to supply external modules (e.g. Sensors) This voltage regulator is a dedicated supply for external modules. PMU-SFR All PMU relevant Extended Special Function Registers This module contains all PMU relevant registers, which are needed to control and monitor the PMU. PMU-PCU Power Control Unit of the PMU This block is responsible for controlling all power related actions within the PGU Module.It also contains all regulator related diagnosis like under- and overvoltage detection, overcurrent and short circuit diagnoses. PMU-WMU Wake-up Management Unit of the PMU This block is responsible for controlling all Wake-up related actions within the PMU Module. PMU-CMU Cyclic Management Unit of the PMU This block is responsible for controlling all actions within cyclic mode. PMU-RMU Reset Management Unit of the PMU This block generates resets triggered by the PMU like undervoltage or short circuit reset, and passes all resets to the relevant modules and their register. A reset status register with every reset source is available. Data Sheet 20 Rev. 1.0, 2016-05-06 TLE9842-2QX Power Management Unit (PMU) 5.2.2 PMU Modes Overview The following state diagram shows the available modes of the device. VS > 4V and VS ramp up or VS < 3V and VS ramp down LIN-wake or MON-wake or cyclic -wake start-up VDDC =stable and error_supp 40V P_1.1.9 VIO,max -0.3 – VDDP V VIN < VDDPmax3) P_1.1.10 P_1.1.11 Voltages GPIOs Voltage on port pin P0.x, P1.x, P2.x, TMS and RESET +0.3 Currents Injection current in Sleep Mode on P0.x, P1.x, P2.x, TMS and RESET Ixx – – 5 mA maximum allowed injection current on single pin or sum of pins in Sleep Mode and unpowered device Injection current on HS IXLO – – 150 mA P_1.1.12 current flowing into HS pin (back supply in case of short to battery) Data Sheet 86 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 18 Absolute Maximum Ratings1) (cont’d) Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. ILS -300 – – mA current flowing out of P_1.1.13 LS pin, e.g. reverse polarity event (defined in LV124) or ISO Pulse event (defined in ISO 7637-2) Junction Temperature Tj -40 – 150 °C – P_1.1.14 Storage Temperature Tstg -55 – 150 °C – P_1.1.15 ESD Susceptibility HBM all pins VESD1 -2 – 2 kV JEDEC HBM4) P_1.1.16 ESD Susceptibility HBM pins LIN vs. LINGND VESD3 -6 – 6 kV JEDEC HBM4) P_1.1.17 ESD Susceptibility CDM VESD_CDM –500 – 500 V Charged device model, acc. JEDEC JESD22-C101 P_1.1.18 ESD Susceptibility CDM VESD_CDM pins 1, 12, 13, 24, 25, 36, 37, 48 (corner pins) –750 – 750 V Charged device model, acc. JEDEC JESD22-C101 P_1.1.19 Output current on LS Temperatures ESD Susceptibility 1) 2) 3) 4) Not subject to production test, specified by design. for -28V, external 3.9kΩ resistor is required to limit output current. One of these limits must be kept. Keeping V ESD susceptibility, “JEDEC HBM” according to ANSI/ESDA/JEDEC JS001 (1.5kΩ, 100pF). Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 28.1.2 Functional Range Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 87 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 19 Functional Range Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Supply voltage in Active Mode VS_AM 5.5 – 28 V – P_1.2.1 Extended Supply voltage in Active Mode - Range 1 VS_AM_exte 28 – 40 V Functional with parameter deviation1) P_1.2.12 Extended Supply voltage in Active Mode with reduced functionality (Microcontroller / Flash with full operation) - Range 2 VS_AM_exte 3.0 – 5.5 V Functional with parameter deviation2) P_1.2.2 Specified Supply voltage for LIN Transceiver - Active Mode VS_AM_LIN 5.5 – 18 V Parameter Specification P_1.2.3 Extended Supply voltage for LIN Transceiver - Active Mode VS_AM_LIN_ 4.8 – 28 V Functional with parameter deviation P_1.2.4 – 5.5 V Wakeup functionality ensured P_1.2.13 nd_1 nd_2 extend Extended Supply voltage for LIN & VS_SSM_LIN 3.6 Monitoring Input (MON) - Stop & Sleep _MON_extend Mode Min. Supply voltage in Stop Mode VS_Stopmin 3.0 – – V Min. Supply voltage in Sleep Mode VS_Sleepmin 3.0 – – V Supply Voltage transients slew rate Output current on any GPIO Output sum current for all GPIO pins dVS/dt IOH , IOL IGPIO,sum 4) sys Operating frequency f Junction Temperature Tj -5 – -10 – -50 – 5 10 50 P_1.2.5 P_1.2.6 V/µs 3) P_1.2.7 mA 3) P_1.2.8 mA 3) P_1.2.9 P_1.2.10 P_1.2.11 5 – 40 MHz 3) -40 – 150 °C – 1) This operation voltage range is only allowed for a short duration: tmax ≤ 400 ms. 2) Hall-Supply, ADC, SPI, UART, NVM, RAM, CPU fully functional and in spec down to 3V VS. Actuators (HS, LS) in VS range from 3V < VS < 5.5V functional but some parameters can be out of spec 3) Not subject to production test, specified by design. 4) Function not specified when limits are exceeded. 28.1.3 Data Sheet Current Consumption 88 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 20 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. – 19 22 mA fsys = 40 MHz Vs= 5.5V to 28V all digital modules enabled and functional, ADCs converting in sequencer mode, PLL running, no loads on GPIOs, VDDEXT off, LIN in recessive state (no communication), HSx & LSx enabled but off P_1.3.18 P_1.3.1 Current Consumption @VS pin Current Consumption in Active Mode IVs Current Consumption in Active Mode IVs_freduced – – 15 mA fsys = 10 MHz Vs= 13.5V all digital modules enabled and functional, ADCs converting in sequencer mode, PLL running, no loads on GPIOs, VDDEXT off, LIN in recessive state (no communication), HSx & LSx enabled but off1) Current consumption in Sleep Mode ISleep – – 15 µA System in Sleep Mode, P_1.3.2 microcontroller not powered, Wake capable via LIN and MON; GPIOs open (no loads) or connected to GND: TJ = -40°C to 25°C; Vs = 13.5V Current consumption in Sleep Mode (extended Temperature Range) ISleep(T_exte – – 25 µA System in Sleep Mode, P_1.3.3 microcontroller not powered, Wake capable via LIN and MON; GPIOs open (no loads) or connected to GND: TJ = 25°C to 85°C; Vs = 13.5V Current consumption in Sleep Mode (extended Voltage and Temperature Range) ISleep(V_T_e – – 30 µA System in Sleep Mode, P_1.3.4 microcontroller not powered, Wake capable via LIN and MON; GPIOs open (no loads) or connected to GND: TJ = -40°C to 85°C; Vs = 5.5V to 18V Data Sheet nd) xtend) 89 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 20 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number Max. Current consumption in Sleep Mode (extended Voltage and Temperature Range 2) ISleep(V_T_e – Current consumption in Sleep Mode with cyclic wake ICyclic Current consumption in Sleep Mode with cyclic wake (extended Temperature Range) ICyclic(T_exte – Current consumption in Stop Mode IStop – 65 115 µA P_1.3.19 System in Stop Mode, microcontroller not clocked, Wake capable via LIN and MON; GPIOs open (no loads) or connected to GND; TJ = 40°C to 85°C Current consumption in Stop Mode IStop_V_exte – 3.5 4.0 mA System in Stop Mode, P_1.3.21 microcontroller not clocked, Wake capable via LIN and MON; GPIOs open (no loads) or connected to GND; TJ = 40°C to 85°C; Vs = 3V Current consumption in Stop Mode with cyclic sense IStop_CS 70 125 µA System in Stop Mode (during stop P_1.3.20 period), microcontroller not clocked, Wake capable via LIN and MON; VDDEXT off; High Side off; GPIOs open (no loads) or connected to GND or VDDP; TJ = 40°C to 85°C; Vs = 5.5V to 28V – 40 µA System in Sleep Mode, P_1.3.7 microcontroller not powered, Wake capable via LIN and MON; GPIOs open (no loads) or connected to GND: TJ = -40°C to 85°C; Vs = 3V to 28V – 15 µA TJ = -40°C to 25°C; Vs = 13.5V xtend2) – P_1.3.5 during sleep period – 30 µA nd) TJ = 25°C to 85°C; Vs = 13.5V; P_1.3.6 during sleep period nd – 1) Not subject to production test, specified by design 28.1.4 Data Sheet Thermal Resistance 90 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 21 Thermal Resistance Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Junction to Case Rth(JC) – 6 – K/W 1) measured to Exposed Pad P_1.4.1 Junction to Ambient Rth(JA) – 33 – K/W 2) P_1.4.2 1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board . Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm). 28.1.5 Timing Characteristics The transition times between the system modes are specified here. Generally the timings are defined from the time when the corresponding Bits in register PMCON0 are set until the sequence is terminated. Table 22 System Timing1) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Wake-up over battery tstart – – 1 ms Battery ramp-up till MCU reset P_1.5.1 is released; Vs > 3V and RESET = ’1’ Sleep-Exit tsleep - exit – – 1 ms rising/falling edge of any P_1.5.2 wake-up signal (LIN, MON) till MCU software running Sleep-Entry tsleep - – 330 µs 2) – P_1.5.3 entry 1) Not subject to production test, specified by design. 2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached. Data Sheet 91 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.2 Power Management Unit (PMU) This chapter includes all electrical characteristics of the Power Management Unit 28.2.1 PMU Input Voltage VS Table 23 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number P_2.1.12 Min. Typ. Max. CVS1 0.1 – – µF 1) Required buffer capacitance for CVS2 stability (load jumps) 10 – – µF 2) Required decoupling capacitance ESR < 1Ω P_2.1.13 1) only min. value is tested. 2) Not subject to production test, specified by design. 28.2.2 PMU I/O Supply Parameters VDDP Table 24 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Parameter Specified Output Current Symbol IVDDP Values Min. Typ. Max. 0 – 50 Unit Note / Test Condition Number mA 2) P_2.1.1 CVDDP1 0.47 – – µF 3)4) Required buffer capacitance for CVDDP2 stability (load jumps) 0.47 – 1 µF 4)5) Required decoupling capacitance ESR < 1Ω P_2.1.2 P_2.1.3 Output Voltage including line and load regulation @ Active Mode VDDPOUT 4.9 5.0 5.1 V 6) Iload < 90mA;Vs > 5.5V P_2.1.4 Output Voltage including line and load regulation @ Stop Mode VDDPOUTS 4.5 5.0 5.25 V 6) Iload is only internal;Vs > 5.5V P_2.1.5 Output Drop Vs V DDPout – 50 +400 mV 7) IVDDP = 50mA; VS = 3V; P_2.1.6 Load Regulation VVDDPLOR -50 – 50 mV 2 ... 90mA; C = CVDDP1+CVDDP2 P_2.1.7 Line Regulation VVDDPLIR -50 – 50 mV Vs= 5.5 ... 28V P_2.1.8 Over Voltage Detection VDDPOV 5.14 – 5.4 V Vs > 5.5V; Overvoltage leads to SUPPLY_NMI P_2.1.9 Data Sheet TOP 92 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 24 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Under Voltage Reset VDDPUV 2.55 2.7 2.8 V – P_2.1.10 Over Current Diagnostic IVDDPOC 90 – 200 mA current including VDDC current consumption P_2.1.11 1) currents used in this table are positive but flowing out the pin VDDP 2) Specified output current for port supply and additional other external loads connected to VDDP, excluding on-chip current consumption. 3) only min. value is tested. 4) the total capacitance on VDDP must not exceed 2,2 µF 5) Not subject to production test, specified by design. 6) Load current includes internal supply. 7) Output drop for IVDDP plus internal supply Data Sheet 93 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.2.3 PMU Core Supply Parameters VDDC Table 25 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Required decoupling capacitance CVDDC1 0.1 – – µF 1) ESR < 1Ω P_2.2.1 Required buffer capacitance for stability (load jumps) CVDDC2 0.33 – 1 µF 2) – P_2.2.2 Output Voltage including line regulation @ Active Mode/Stop Mode VDDCOUT 1.44 1.5 1.56 V Iload < 40mA; with Load Regulation VDDCLOR -50 – 50 mV 2 ... 40mA; C = CVDDC1+CVDDC2 P_2.2.4 Line Regulation VDDCLIR -25 – 25 mV Vs= 5.5 ... 28V P_2.2.5 Over Voltage Detection VDDCOV 1.58 – 1.68 V Overvoltage leads to P_2.2.6 SUPPLY_NMI Under Voltage Reset VDDVUV 1.10 – 1.19 V – P_2.2.7 Over Current Diagnostic IVDDCOC 40 – 80 mA – P_2.2.8 P_2.2.3 setting of VDDC output voltage to 1.5V in Stop Mode 1) only min. value is tested. 2) Not subject to production test, specified by design. Data Sheet 94 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.2.4 VDDEXT Voltage Regulator 5.0V Table 26 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. 0 – 20 mA current flowing out of P_2.3.1 pin VDDEXT 330 – 1000 nF 2) P_2.3.3 P_2.3.4 VDDEXT Regulator Active Mode Specified Output Current IVDDEXT Required decoupling capacitance CVDDEXT1 Required buffer capacitance for stability (load jumps) CVDDEXT2 Output Voltage including line and VDDEXT load regulation Output Drop Vs-VDDEXT Load Regulation VDDEXTLOR Line Regulation VVDDEXTLIR ESR < 1 Ω P_2.3.2 100 – 1000 nF 3) 4.9 5.0 5.1 V Iload < 20mA;Vs ≥ 5.5V 50 +400 mV Iload < 20mA; 3V < Vs < 5.0V P_2.3.5 -80 – 20 mV 0.01 ... 20mA; C = CVDDEXT1+CVDDEXT2; Vs≥ 5.5V P_2.3.6 -50 – 50 mV Vs= 5.5 ... 28V P_2.3.7 Power Supply Ripple Rejection PSSRVDDEXT 50 – – dB 3) Under Voltage Shutdown VVDDEXTUV 1.9 2.2 V 4) 1.55 Over Current Limitation IVDDEXTOC VDDEXT output discharge resistance RVDDEXT_DIS 16 100 Vs= 13.5V; f=0 ... P_2.3.8 1KHz; Vr=2Vpp; 0 ... 20mA P_2.3.9 250 380 mA 3) 20 24 kΩ – P_2.3.11 – 5 mA – P_2.3.28 5.0 5.1 V Iload ≤ 5mA;Vs ≥ 5.5V P_2.3.29 50 +300 mV Iload ≤ 5mA; 3V < Vs ≤ 5V; C= CVDDEXT1+CVDDEXT2 P_2.3.30 – 250 mV 0 ... 5mA; C = CVDDEXT1+CVDDEXT2; Vs≥ 5.5V P_2.3.31 – 300 mV Iload ≤ 5mA; Vs= 5.5 ... 28V P_2.3.32 – – dB 3) – P_2.3.10 CHG VDDEXT Regulator Low Current Mode Specified Output Current IVDDEXT_LCM 0 Output Voltage including line and VDDEXT_LCM 4.6 load regulation - Load 1 1 Output Drop - Load 1 VsVDDEXT_LCM 1 Load Regulation - Load 1 VDDEXTLOR_ -250 LCM1 Line Regulation - Load 1 VVDDEXTLIR_ -300 LCM1 Power Supply Ripple Rejection PSSRVDDEXT 50 _LCM Data Sheet 95 Vs= 13.5V; f=0 ... P_2.3.33 1KHz; Vr=2Vpp; 0 ... 5mA Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 1) 2) 3) 4) currents used in this table are positive but flowing out the pin VDDEXT only min. value is tested. Not subject to production test, specified by design. When condition is met, the Bit VDDEXT_CTRL.VDDEXT_UV_IS will be set. Data Sheet 96 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.2.5 VPRE Voltage Regulator (PMU Subblock) Parameters The PMU VPRE Regulator acts as a supply of VDDP and VDDC voltage regulators. Table 27 Functional Range Parameter Symbol Specified Output Current IVPRE Values Min. Typ. Max. – – 90 Unit Note / Test Condition Number mA 1) P_2.4.1 1) Not subject to production test, specified by design. 28.2.5.1 Load Sharing of VPRE Regulator The figure below shows the load sharing concept of VPRE regulator. VS VPRE max. 90 mA max. 50 mA VDDP VDDP - 5V max. 90 mA C VDDP max. 0 mA GNDA (Pin 43) VDDC VDDC - 1.5V max. 40 mA C VDDC GNDA (Pin 43) Load Sharing VPRE Load_Sharing _VPRE.vsd Figure 36 Data Sheet Load Sharing of VPRE Regulator 97 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.2.6 Power Down Voltage Regulator (PMU Subblock) Parameters The PMU Power Down voltage regulator consists of two subblocks: • • Power Down Pre regulator: VDD5VPD Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers) Both regulators are used as purely internal supplies. The following table contains all relevant parameter: Table 28 Functional Range Parameter Symbol Values Min. Power-On Reset Threshold VDD1V5_PD_ 1.2 Typ. Max. – 1.5 Unit Note / Test Condition Number V 1) Iload = internal load P_2.5.1 connected to VDD1V5_PD RSTTH 1) Not subject to production test, specified by design Data Sheet 98 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.3 System Clocks 28.3.1 Electrical Characteristics Oscillators and PLL Table 29 Electrical Characteristics System Clocks VS = 5.5 V to 28 V,, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Unit Note / Test Condition Number Typ. Max. 17 20 23 MHz this clock is used at startup P_3.1.1 and can be used in case the PLL fails 70 100 130 kHz this clock is used for cyclic wake MHz within any 100 ms, e.g. after P_3.1.3 synchronization to a LIN frame (includes PLL accumulated jitter value).Assuption: Tj is varying < 30°C. PMU Oscillators (Power Management Unit) Frequency of LP_CLK fLP_CLK Frequency of LP_CLK2 fLP_CLK2 P_3.1.2 CGU Oscillator (Clock Generation Unit Microcontroller) Short term frequency deviation1) fTRIMST -0.4% – +0.4% Absolute accuracy fTRIMABSA -1.49% – +1.49% MHz Including temperature& lifetime P_3.1.4 tOSC – CGU-OSC Start-up time drift and supply variation – 10 µs 2) startup time OSC from Sleep Mode, power supply stable P_3.1.5 PLL (Clock Generation Unit Microcontroller) 2) fREF 0.8 1 1.25 MHz P_3.1.25 VCO frequency (tuning) fVCO range 75 – 160 MHz P_3.1.21 4 – 6 MHz see also specified limits for fVCO and fREF resulting in restrictions for possible N divider settings P_3.1.6 4 – 6 MHz see also specified limits for fVCO and fREF resulting in restrictions for possible N divider settings P_3.1.23 15 – 40 MHz see also specified limits for fVCO and fREF resulting in restrictions for possible N divider settings P_3.1.7 – 34 – MHz P_3.1.24 VCO reference frequency range Input frequency range fOSC XTAL1 input freq. range fOSCHP Output freq. range fPLL Free-running frequency fVCOfree Data Sheet 99 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 29 Electrical Characteristics System Clocks (cont’d) VS = 5.5 V to 28 V,, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Number Input clock high/low time thigh/low 10 – – ns Peak period jitter tjp -500 – 500 ps for K=2; this parameter value is only valid with the combination of an external quartz oscillator (e.g. 5 MHz) P_3.1.9 Accumulated jitter with external oscillator jacc_ext – – 5 ns for K=2; this parameter value is only valid with the combination of an external quartz oscillator (e.g. 5 MHz). P_3.1.10 Lock-in time tL – – 260 µs this parameter represents the duration from module power-on to assertion of lock signal P_3.1.11 P_3.1.8 1) The typical oscillator frequency is 40 MHz 2) Not subject to production test, specified by design. 28.3.2 External Clock Parameters XTAL1, XTAL2 Table 30 Functional Range VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Parameter Symbol Values Max. Unit Note / Test Condition -1.7 + VDDC – 1.7 V 2) P_3.2.1 0.3 x VDDC – – V 3) Peak-to-peak voltage P_3.2.2 0 V < VIN < VDDI P_3.2.3 Min. Input voltage range limits for signal on XTAL1 VIX1_SR Input voltage (amplitude) on VAX1_SR XTAL1 Typ. Number XTAL1 input current IIL – – ±20 µA Oscillator frequency fOSC 4 – 6 MHz Clock signal P_3.2.4 Oscillator frequency fOSC 4 – 6 MHz Crystal or Resonator P_3.2.5 High time t1_VCOBYP 6 – – ns 4)5) ns 4)5) – P_3.2.7 ns 4)5) – P_3.2.8 ns 4)5) – P_3.2.9 ns 5)6) – P_3.2.10 Low time Rise time Fall time High time Data Sheet t2_VCOBYP t3_VCOBYP t4_VCOBYP t1_PLLNM 6 – – 12 – 8 8 – 100 – 8 8 – P_3.2.6 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 30 Functional Range (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Parameter Low time Rise time Fall time Symbol t2_PLLNM t3_PLLNM t4_PLLNM Values Min. Typ. Max. Unit Note / Test Condition 12 – – ns 5)6) – P_3.2.11 ns 5)6) – P_3.2.12 ns 5)6) – P_3.2.13 – – 7 7 7 7 Number 1) Not subject to production test, specified by design. 2) Overload conditions must not occur on pin XTAL1. 3) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by VIX1. 4) this performance is only valid for Prescaler Mode (VCO Bypass mode). 5) tested with rectangular signal with VIN_Low = 0V to VIN_High = VDDC 6) this performance is only valid for PLL Normal Mode. Data Sheet 101 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.4 Flash Parameters This chapter includes the parameters for the 40 KByte embedded flash module. 28.4.1 Flash Characteristics Table 31 Flash Characteristics1) VS = 5.5 V to 28 V,, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Programming time per 128 Byte page tPR – Typ. Unit Note / Number Test Condition Max. 3 2) 3.5 ms 3V < VS < 28V P_4.1.1 2) 4.5 ms 3V < VS < 28V P_4.1.2 Erase time per sector/page tER – 4 Data retention time tRET 20 – – years 1,000 erase / P_4.1.3 program cycles Data retention time tRET 50 – – years 1,000 erase / P_4.1.4 program cycles Tj = 30°C3) Flash erase endurance for user sectors NER 30 – – kcycles Data retention time 5 years P_4.1.5 Flash erase endurance for security pages4) NSEC 10 – – cycles Data retention time 20 years P_4.1.6 Drain disturb limit NDD 32 – – kcycles 5) P_4.1.7 1) Not subject for production test, specified by design. 2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system clock cycles. The requirement is only relevant for extremely low system frequencies. 3) Derived by extrapolation of lifetime tests. 4) Temperature: 25 °C 5) This parameter limits the number of subsequent programming operations within a physical sector without a given page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM emulation firmware routines handle this limit automatically, for wordline erases in code sectors (without EEPROM emulation) it is recommended to execute a software based refresh, which may make use of the integrated random number generator NVMBRNG to statistically start a refresh. Data Sheet 102 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.5 Parallel Ports (GPIO) 28.5.1 Description of Keep and Force Current VDDP keeper current PU Device PUDSEL P1.x P0.x \PUDSEL keeper current PD Device VSS Pull- Up- Down.vsd Figure 37 Pull-Up/Down Device UGPIO Logical „1" 7.5 KOhm (equivalent) (1.5V / 200uA) *) VIH - VDDP undefined 2.33 KOhm (equivalent) (3.5V / 1.5mA) *) VIL - VDDP Logical „0" -I PLF I -IPLK Current_Diag.vsd *) value for port 0 and 1, as example Figure 38 Data Sheet Pull-Up Keep and Forced Current 103 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics UGPIO Logical „1" 2.33 KOhm (equivalent) (3.5V / 1.5mA) *) VIH undefined 7.5 KOhm (equivalent) (1.5V / 200uA) *) VIL Logical „0" IPLK I I PLF Current_Diag-Pull _down.vsd *) value for port 0 and 1, as example Figure 39 Pull-Down Keep and Force Current 28.5.2 DC Parameters Port 0, Port 1, TMS, Reset Table 32 DC Characteristics Port0, Port1 VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input low voltage VIL -0.3 – 0.3 x VDDP V 1) 4.5V ≤ VDDP ≤ 5.5V P_5.2.1 Input low voltage VIL_extend -0.3 0.42 x – 2) 2.6V ≤ VDDP < 4.5V P_5.2.14 Input high voltage VIH 0.7 x VDDP Input high voltage VIH_extend – V VDDP – VDDP + 0.3 V 1) 4.5V ≤ VDDP ≤ 5.5V P_5.2.2 0.52 x VDDP + 0.3 V 2) 2.6V ≤ VDDP < 4.5V P_5.2.15 – V 2) 4.5V ≤ VDDP ≤ 5.5V; Series resistance = 0 Ω P_5.2.3 – V 2) 2.6V ≤ VDDP < 4.5V; Series resistance = 0 Ω P_5.2.16 P_5.2.4 VDDP 0.11 x VDDP – Input Hysteresis HYS Input Hysteresis HYSextend – 0.09 x Output low voltage VOL – – 1.0 V 3) 4) Output low voltage VOL – – 0.4 V 3) 5) IOL ≤ IOLnom P_5.2.5 Output high voltage VOH VDDP - 1.0 – – V 3) 4) IOH ≥ IOHmax P_5.2.6 V 3) 5) IOH ≥ IOHnom P_5.2.7 µA 6) Output high voltage Input leakage current VOH IOZ2 VDDP - 0.4 -5 VDDP – – – +5 IOL ≤ IOLmax TJ ≤ 85°C, 0.45 V < VIN P_5.2.8 < VDDP Data Sheet 104 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 32 DC Characteristics Port0, Port1 (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input leakage current IOZ2 -15 – +15 µA TJ ≤ 150°C, 0.45 V < VIN < VDDP P_5.2.9 Pull level keep current7) IPLK – – ±200 µA 8) VPIN ≥ VIH (up) VPIN ≤ VIL (dn) P_5.2.10 Pull level force current7) IPLF ±1.5 – – mA 8) VPIN ≥ VIL (up) VPIN ≤ VIH (dn) P_5.2.11 Pin capacitance CIO – – 10 pF 2) P_5.2.12 – µs 9) P_5.2.13 Reset Pin Timing Reset Pin Input Filter Time Tfilt_RESET – 5 1) Tested at VDDP = 5V, specified for 2.55V < VDDP < 5.1V. 2) Not subject to production test, specified by design. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for pin groups must be respected. 4) Tested at 2.55V < VDDP < 5.1V, IOL = 4mA, IOH = -4mA, specified for 2.7V < VDDP < 5.1V. 5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→GND, VOH→VDDP). Tested at 2.55V < VDDP < 5.1V, IOL = 1mA, IOH = -1mA. 6) The given values are worst-case values. In production test, this leakage current is only tested at 125°C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 × e(1.5 + 0.028×TJ) [μA]. For example, at a temperature of 95°C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 × DV) [μA] This voltage derating formula is an approximation which applies for maximum temperature. 7) Negative current is representing pullup; positive current is representing pulldown 8) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down. These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. 9) This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Table 33 Current Limits for Port Output Drivers1) Port Output Driver Mode Maximum Output Current Data Sheet - VDDP ≥ 4.5V 2.55V < VDDP < 4.5V 5 mA 1.6 mA 1.0 mA < 4.5V Strong Driver Output Current (IOLnom , 3 mA 105 Number IOHnom) (IOLmax , - IOHmax) VDDP ≥ 4.5V 2.55V < VDDP P_5.2.20 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 33 Current Limits for Port Output Drivers1) (cont’d) Port Output Driver Mode Maximum Output Current Output Current (IOLnom , - Number (IOLmax , - IOHmax) VDDP ≥ 4.5V 2.55V < VDDP VDDP ≥ 4.5V 2.55V < VDDP < 4.5V Medium Driver 3 mA 1.8 mA 1.0 mA 0.8 mA P_5.2.21 Weak Driver 0.5 mA 0.3 mA 0.25 mA 0.15 mA P_5.2.22 < 4.5V IOHnom) 1) Not subject to production test, specified by design. 28.5.3 DC Parameters Port 2 These parameters apply to the IO voltage range, 2.55 V ≤ VDDP ≤ 5.5 V. Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Table 34 DC Characteristics Port 2 VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Number Min. Typ. Max. -0.3 – 0.3 x VDDP V 1) 4.5V ≤ VDDP ≤ 5.5V P_5.3.1 0.42 x – 2) 2.6V ≤ VDDP < 4.5V P_5.3.8 Input low voltage VIL_P2 Input low voltage VIL_P2_exte -0.3 nd Input high voltage VIH_P2 Input high voltage VIH_P2_ext – 0.7 x VDDP end HYSP2 Input Hysteresis HYSP2_ext – end Input leakage current IOZ1_P2 Input leakage current (extended temperature range) IOZ1_P2_T_ -1 Pull level keep current4) IPLK_P2 -400 V VDDP – VDDP + 0.3 V 1) 4.5V ≤ VDDP ≤ 5.5V P_5.3.2 0.52 x VDDP + 0.3 V 2) 2.6V ≤ VDDP < 4.5V P_5.3.9 – V 2) 4.5V ≤ VDDP ≤ 5.5V; Series resistance = 0 Ω P_5.3.3 – V 2) 2.6V ≤ VDDP < 4.5V; Series resistance = 0 Ω P_5.3.10 – +400 nA 4.5V ≤ VDDP ≤ 5.5V TJ ≤ 85°C, 0 V < VIN < VDDP P_5.3.4 – +1 uA 2.6V ≤ VDDP < 4.5V TJ ≤ 150°C, 0 V < VIN < VDDP P_5.3.11 – ±30 µA 3) VDDP 0.11 x VDDP – Input Hysteresis Data Sheet Unit Note / Test Condition 0.09 x VDDP extend – 106 VPIN ≥ VIH (up) P_5.3.5 VPIN ≤ VIL (dn) Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 34 DC Characteristics Port 2 (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol 4) Pull level force current IPLF_P2 Values Min. Typ. Max. Unit Note / Test Condition ±750 – – µA 3) 10 pF 2) CIO_P2 – – Pin capacitance (digital inputs/outputs) 1) Tested at VDDP = 5V, specified for 4.9V < VDDP < 5.1V. Number VPIN ≤ VIL (up) P_5.3.6 VPIN ≥ VIH (dn) P_5.3.7 2) Not subject to production test, specified by design. 3) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down. 4) Negative current is representing pullup; positive current is representing pulldown 28.5.4 Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the TLE9842-2QX. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: Typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum parameter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage. Additional details are described where applicable. Table 35 Operating Condition Parameters VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Digital core supply voltage Symbol VDDC Values Min. Typ. Max. 1.35 – 1.6 Unit Note / Test Condition Number V Full active mode P_5.4.1 P_5.4.2 Digital supply voltage for IO pads VDDP 2.55 5.0 5.5 V 1) Digital ground voltage VSS 0 – 0 V Reference voltage P_5.4.3 Overload current IOV - 5.0 – 5.0 mA Per IO pin2)3) P_5.4.4 Overload current IOV - 2.0 – 5.0 mA Per analog input pin2)3) P_5.4.5 Overload positive current coupling factor for analog inputs4) KOVA – 1.0 x 10-6 1.0 x 10-4 – IOV > 03) P_5.4.6 Overload negative current coupling factor for analog inputs KOVA – 2.5 x 10-4 1.5 x 10-3 – IOV < 03) P_5.4.7 Overload positive current coupling factor for digital I/O pins KOVD – 1.0 x 10-4 5.0 x 10-3 – IOV > 03) P_5.4.8 Overload negative current coupling factor for digital I/O pins KOVD – 1.0 x 10-2 3.0 x 10-2 – IOV < 03) P_5.4.9 Absolute sum of overload currents Σ|IOV| – – 80 mA 3) P_5.4.10 Data Sheet 107 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 1)Performance of pad drivers, A/D Converter, and Flash module depends on VDDP. If the external supply voltage VDDP becomes lower than the specified operating range, a power reset must be generated. Otherwise, the core supply voltage VDDI may rise above its specified operating range due to parasitic effects. This power reset can be generated by the on-chip SWD. If the SWD is disabled the power reset must be generated by activating the PORST input 2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin (IOV < 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation under overload conditions depends on the application. Overload conditions must not occur on pin XTAL1 (powered by VDDIM). 3) Not subject to production test, specified by design. 4) An overload current (IOV) through a pin injects an error current (IINJ) into the adjacent pins. This error current adds to that pin’s leakage current (IOZ). The value of the error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is reversed from the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ| + (|IOV| x KOV). The additional error current may distort the input voltage on analog inputs. Data Sheet 108 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.6 LIN Transceiver 28.6.1 Electrical Characteristics Table 36 Electrical Characteristics LIN Transceiver Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number Max. Bus Receiver Interface Receiver threshold voltage, Vth_dom recessive to dominant edge Receiver dominant state VBUSdom -27 Receiver threshold voltage, Vth_rec dominant to recessive edge Receiver recessive state 0.4 ×VS 0.45 ×VS 0.53 x VS V VBUSrec 0.47 x VS SAE J2602 P_6.1.1 0.4 ×VS V LIN Spec 2.2 (Par. 17) P_6.1.2 0.55 ×VS 0.6 ×VS V SAE J2602 P_6.1.3 – 0.6 ×VS – 1.15 ×VS V 1) LIN Spec 2.2 (Par. 18) P_6.1.4 LIN Spec 2.2 (Par. 19) P_6.1.5 Receiver center voltage VBUS_CN 0.475 × VS T 0.5 ×VS 0.525 × VS V 2) Receiver hysteresis VHYS 0.07 × VS 0.12 ×VS 0.175 × VS V 3) LIN Spec 2.2 (Par. 20) P_6.1.6 Wake-up threshold voltage VBUS,wk 0.4 ×VS 0.5 ×VS 0.6 ×VS V – P_6.1.7 30 150 µs P_6.1.8 including analog and digital filter time. Digital filter time can be adjusted by PMU.CNF_WAKE_FIL TER Dominant time for bus wake- tWK,bus up – Bus Transmitter Interface Bus recessive output voltage VBUS,ro 0.8 ×VS – VS V VTxD = high Level P_6.1.9 Bus short circuit current IBUS,sc 40 100 150 mA Current Limitation for driver dominant state driver on VBUS = 18 V; LIN Spec 2.2 (Par. 12) P_6.1.10 Leakage current IBUS_NO_ -1000 -450 0 µA VS = 0 V; VBUS = -12 V; P_6.1.11 LIN Spec 2.2 (Par. 15) GND Leakage current IBUS_NO_ – 10 20 µA IBUS_PAS -1 Leakage current IBUS_PAS – – – mA VS = 18 V; VBUS = 0 V; LIN Spec 2.2 (Par. 13) P_6.1.13 – 20 µA VS = 8 V; VBUS = 18 V; P_6.1.14 _dom LIN Spec 2.2 (Par. 14) _rec Data Sheet P_6.1.12 LIN Spec 2.2 (Par. 16) BAT Leakage current VS = 0 V; VBUS = 18 V; 109 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 36 Electrical Characteristics LIN Transceiver (cont’d) Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Bus pull-up resistance Symbol RBUS Values Unit Note / Test Condition Number Min. Typ. Max. 20 30 47 kΩ Normal mode LIN Spec P_6.1.15 2.2 (Par. 26), also present in Sleep mode AC Characteristics - Transceiver Normal Slope Mode td(L),R 0.1 1 6 µs LIN Spec 2.2 (Param. 31) P_6.1.16 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 1 6 µs LIN Spec 2.2 (Param. 31) P_6.1.17 -2 – 2 µs tsym,R = td(L),R - td(H),R; P_6.1.18 Propagation delay bus dominant to RxD LOW Receiver delay symmetry tsym,R LIN Spec 2.2 (Par. 32) 4) Duty cycle D1 Normal Slope Mode (for worst case at 20 kbit/s) tduty1 0.396 – – P_6.1.19 duty cycle 1 THRec(max) = 0.744 ×VS; THDom(max) = 0.581 ×VS; tbit = 50 µs; D1 = tbus_rec(min) / 2 x tbit; LIN Spec 2.2 (Par. 27) Duty cycle D2 Normal Slope Mode (for worst case at 20 kbit/s) tduty2 – – 0.581 4) P_6.1.20 duty cycle 2 THRec(min) = 0.422 ×VS; THDom(min) = 0.284 ×VS; tbit = 50 µs; D2 = tbus_rec(max) / 2 x tbit; LIN Spec 2.2 (Par. 28) AC Characteristics - Transceiver Low Slope Mode td(L),R 0.1 1 6 µs LIN Spec 2.2 (Param. 31) P_6.1.21 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 1 6 µs LIN Spec 2.2 (Param. 31) P_6.1.22 -2 – 2 µs tsym,R = td(L),R - td(H),R; LIN Spec 2.2 (Par. 32) P_6.1.23 Propagation delay bus dominant to RxD LOW Receiver delay symmetry Data Sheet tsym,R 110 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 36 Electrical Characteristics LIN Transceiver (cont’d) Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number 4) Duty cycle D3 (for worst case at 10,4 kbit/s) tduty1 0.417 – – P_6.1.24 duty cycle 3 THRec(max) = 0.778 ×VS; THDom(max) = 0.616 ×VS; tbit = 96 µs; D3 = tbus_rec(min) / 2 x tbit; LIN Spec 2.2 (Par. 29) Duty cycle D4 (for worst case at 10,4 kbit/s) tduty2 – – 0.590 4) duty cycle 4 P_6.1.25 THRec(min) = 0.389 ×VS; THDom(min) = 0.251 ×VS; tbit = 96 µs; D4 = tbus_rec(max) / 2 x tbit; LIN Spec 2.2 (Par. 30) AC Characteristics - Transceiver Fast Slope Mode td(L),R 0.1 1 6 µs – P_6.1.26 td(H),R Propagation delay bus recessive to RxD HIGH 0.1 1 6 µs – P_6.1.27 µs tsym,R = td(L),R - td(H),R; P_6.1.42 Propagation delay bus dominant to RxD LOW Receiver delay symmetryextended supply voltage range tsym,R -2.0 – 2.0 Duty cycle D5 (used for 62,5 kbit/s) tduty1 0.395 – – duty cycle 5 P_6.1.29 THRec(max) = 0.744 ×VS; THDom(max) = 0.581 ×VS; tbit = 16µs; D5 = tbus_rec(min) / 2 x tbit; Duty cycle D6 (used for 62,5 kbit/s) tduty2 – – 0.581 4) td(L),R 0.1 0.5 6 µs – P_6.1.31 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 0.5 6 µs – P_6.1.32 -1.0 – 2.0 µs tsym,R = td(L),R - td(^H),R; P_6.1.44 4) P_6.1.30 duty cycle 6 THRec(min)= 0.422 ×VS; THDom(min)= 0.284 ×VS; tbit = 16 µs; D6 = tbus_rec(max) / 2 x tbit; AC Characteristics - Flash Mode Propagation delay bus dominant to RxD LOW Receiver delay symmetry Data Sheet tsym,R 111 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 36 Electrical Characteristics LIN Transceiver (cont’d) Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Duty cycle D7 tduty1 (for worst case at 115 kbit/s) for +1 µs Receiver delay symmetry (used for 250 kbit/s programming) 0.395 – – duty cycle D7 P_6.1.34 THRec(max) = 0.744 ×VS; THDom(max) = 0.581 ×VS; tbit = 8.7 µs; D7 = tbus_rec(min) / 2 x tbit; tduty2 Duty cycle D8 (for worst case at 115 kbit/s) for +1 µs Receiver delay symmetry (used for 250 kbit/s programming) – – 0.578 5) 5) P_6.1.35 duty cycle D8 THRec(min) = 0.422 ×VS; THDom(min) = 0.284 ×VS; tbit = 8.7 µs; D8 = tbus_rec(max) / 2 x tbit; LIN input capacity CLIN_IN – 15 30 pF 6) P_6.1.36 TxD dominant time out ttimeout 6 12 20 ms VTxD = 0 V P_6.1.37 180 200 °C 6) P_6.1.38 K 6) P_6.1.39 Thermal Shutdown (Junction Temperature) Thermal shutdown temp. Thermal shutdown hyst. 1) 2) 3) 4) TjSD ∆T 160 – 10 – Maximum limit specified by design. VBUS_CNT = (Vth_dom +Vth rec)/2 VHYS = VBUSrec - VBUSdom Bus load concerning LIN Spec 2.2: Load 1 = 1 nF / 1 kΩ = CBUS / RBUS Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS Load 3 = 10 nF / 500 Ω = CBUS / RBUS 5) Bus load Load 1 = 1 nF / 500 Ω = CBUS / RBUS 6) Not subject to production test, specified by design. Data Sheet 112 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.7 High-Speed Synchronous Serial Interface 28.7.1 SSC Timing The table below provides the SSC timing in the TLE9842-2QX. Table 37 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Max. Note / Number Test Condition – 2) VDDP > 2.7 V P_7.1.1 – ns 2) VDDP > 2.7 V P_7.1.2 ns 2) VDDP > 2.7 V P_7.1.3 MRST hold from SCLK t3 15 – – ns 1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period. 2) VDDP > 2.7 V P_7.1.4 1) t0 SCLK clock period t1 MTSR delay from SCLK 10 t2 MRST setup to SCLK 2 * TSSC – – 10 – – 2) Not subject to production test, specified by design. t0 SCLK1) t1 t1 MTSR1) t2 t3 Data valid MRST1) t1 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_Tmg1 Figure 40 Data Sheet SSC Master Mode Timing 113 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.8 Measurement Unit 28.8.1 Electrical Characteristics Table 38 Supply Voltage Signal Conditioning VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number Max. ADC1 - Battery / Supply Voltage Measurement VBAT_SENSE / VS Input to output voltage attenuation: VBAT_SENSE / VS ATTVBAT_SENSE – , ATTVS 0.047 – P_8.1.10 VBAT_SENSE, Nominal operating input voltage range VBAT_SENSE / range, VS, range 0 – 25.7 7 V 2) Accuracy of VBAT_SENSE / VS after calibration - with IIR filter -200 – 200 mV Vs= 5.5V to 18V, Tj = -40..125°C, fADCI = fsys_max VS ∆VBAT_SENSE_II R, VS_IIR Max. value corresponds P_8.1.11 to typ. ADC full scale input; P_8.1.12 ADC1_FILTCOEFF0_11. CHx = 11’b. Accuracy of VBAT_SENSE / VS after calibration ∆VBAT_SENSE, -300 – 300 mV VS Vs= 5.5V to 18V, Tj = -40..125°C, fADCI = fsys_max. P_8.1.36 ADC1 - Monitoring Input Voltage Measurement VMONx Input to output voltage attenuation: VMONx ATTVMONx – 0.039 – Nominal operating input voltage range VMONx VMONx,range 0 – 31.0 5 V 2) Accuracy of VMONx sense after calibration - with IIR filter ∆VMONx_IIR -241 – 241 mV Vs= 5.5V to 18V, Tj = -40..125°C, fADCI = fsys_max P_8.1.13 Max. value corresponds P_8.1.14 to typ. ADC full scale input; P_8.1.33 ADC1_FILTCOEFF0_11. CHx = 11’b. Accuracy of VMONx sense ∆VMONx_ROR_IIR -170 after calibration - Reduced Operating Range - with IIR filter – 170 mV 2) Vs= 5.5V to 18V, Tj = -40..125°C, VMONx,range= 0V to 12V, fADCI = fsys_max, P_8.1.20 ADC1_FILTCOEFF0_11. CHx = 11’b. Data Sheet 114 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 38 Supply Voltage Signal Conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Accuracy of VMONx sense after calibration Symbol ∆VMONx Values Unit Note / Test Condition Min. Typ. Max. -361 – 361 mV Number 2) Vs= 5.5V to 18V, Tj = -40..125°C, fADCI = fsys_max. P_8.1.37 – P_8.1.15 ADC1 - Port 2.x Voltage Measurement V2.x Input to output voltage attenuation: VPort2.x ATT2.x – 0.219 – Nominal operating input voltage range VPort2.x VPort2.x,range 0 – 5.53 Accuracy of VPort2.x sense after calibration - with IIR filter ∆VPort2.x_IIR -43 V 2) mV Vs= 5.5V to 18V, Tj = -40..125°C, fADCI = fsys_max 1) – 43 Max. value corresponds P_8.1.16 to typ. ADC full scale input; P_8.1.34 ADC1_FILTCOEFF0_11. CHx = 11’b. Accuracy of VPort2.x sense after calibration ∆VPort2.x -67 – 67 mV Vs= 5.5V to 18V, Tj = -40..125°C, fADCI = fsys_max. P_8.1.38 ADC2 - Supply Voltage Measurement VS Input to output voltage attenuation: VS ATTVS_ADC2 – 0.039 – Nominal operating input voltage range VS VS,ADC2 3 – 31.0 5 V 2) Accuracy of VS after calibration ∆VS,ADC2 -270 – 270 mV Vs= 5.5V to 18V, Tj = -40..125°C P_8.1.3 – P_8.1.17 P_8.1.1 Max. value corresponds P_8.1.2 to typ. ADC full scale input; 3V < VS < 28V ADC2 - VDDEXT Voltage Measurement VDDEXT Input to output voltage attenuation: VDDEXT ATTVDDEXT – 0.203 – Nominal operating input voltage range VDDEXT VDDEXT,range 0 – 5.96 V 2) Max. value corresponds P_8.1.18 to typ. ADC full scale input; ADC2 - Pad Supply Voltage Measurement VVDDP Input-to-output voltage attenuation: VDDP ATTVDDP – 0.203 – Nominal operating input voltage range VDDP VDDP,range 0 – 5.96 Data Sheet 115 – V P_8.1.4 2) Max. value corresponds P_8.1.5 to typ. ADC full scale input; Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 38 Supply Voltage Signal Conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Number ADC2 - Reference Voltage Measurement VBG Input-to-output voltage attenuation: VBG ATTVBG – 0.75 – – Nominal operating input voltage range VBG VBG,range 0.8 – VDD V C0.1V 2) Value of ADC2-VBG measurement after calibration VBG_PMU 0.90 1.0 1.1 – P_8.1.39 P_8.1.8 V P_8.1.6 Max. value corresponds P_8.1.7 to typ. ADC full scale input; ADC2 - Core supply Voltage Measurement VDDC Input-to-output voltage attenuation: VDDC ATTVDDC – 0.75 – – Nominal operating input voltage range VDDC VDDC,range 0.6 – VDD V C+ 0.1V 2) Max. value corresponds P_8.1.9 to typ. ADC full scale input; 1) This typical theoretical full scale is not reached as the internal ESD Clamping Structure limits the voltage to max. 5.2V. 2) Not subject to production test, specified by design. Data Sheet 116 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.8.2 Central Temperature Sensor Module 28.8.2.1 Electrical Characteristics Table 39 Electrical Characteristics Temperature Sensor Module VS = 5.5 V to 28 V, , Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number T0=0°C (273 K) P_8.2.1 Min. Typ. Max. a – 0.628 – V Temperature sensitivity b 2) b – 2.31 – mV/K Output voltage VTEMP at T0=0°C (273 K)2) P_8.2.2 Accuracy_1 Acc_1 -10 – 10 °C 1) -40°C < Tj < 85°C P_8.2.3 Accuracy_2 Acc_2 -15 – 15 °C 125°C < Tj < 175°C P_8.2.4 °C 2) P_8.2.5 Accuracy_3 Acc_3 -5 – 5 85°C < Tj < 125°C 1) Accuracy with reference to on-chip temperature calibration measurement. 2) Not subject to production test, specified by design. Data Sheet 117 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.9 ADC1 (10-Bit) 28.9.1 ADC1 Reference Voltage Table 40 DC Specifications VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Note / Test Condition Number Min. Typ. Max. 1.211 +1% V P_9.1.10 +1% V P_9.1.11 Reference Voltage VBG -1% Temperature Drift ∆VBG -1% 28.9.2 Unit Electrical Characteristics ADC1 (10-Bit) These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 41 A/D Converter Characteristics VS = 5.5 V to 28 V, , Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Analog clock frequency fADCI 5 – 40 MHz 1) DNL error EADNL – – ±2 LSB 2) INL error EAINL – – ±3 LSB – P_9.2.1 – P_9.2.8 P_9.2.9 4) P_9.2.10 4) P_9.2.11 Gain error EAGAIN – – ± 1.2 % of calibrated; FSR Gain Error is 3) calibrated by implemented calibration unit Offset error EAOFF – – ± 2.5 LSB Total unadjusted error EATUE – – ± 10 LSB already calibrated Data Sheet 118 Number calibrated; Offset Error is calibrated by implemented calibration unit P_9.2.33 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 41 A/D Converter Characteristics (cont’d) VS = 5.5 V to 28 V, , Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Input referred noise Symbol VNoise_LSB Values Min. Typ. Max. – – 1.5 Unit Note / Test Condition Number LSB rms P_9.2.34 4) Tj = 25°C; this value is determined out of 4 consecutive measurements which are averaged. Cross-coupling Attenuation between LV Channels EACCOUP – ±1 ±2 LSB 4) Input capacitance of a HV analog input CAINT_HVI – – 200 fF 4) P_9.2.13 Input capacitance of a LV analog input CAINT_LVI – – 200 fF 4) P_9.2.19 1) 2) 3) 4) – P_9.2.12 The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting. this parameter is measured with disabled hardware calibration this Gain error is calibrated by IFX end of line Not subject to production test Data Sheet 119 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.10 High-Voltage Monitoring Input 28.10.1 Electrical Characteristics Table 42 Electrical Characteristics Monitoring Input VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number V without external serial P_10.1.1 resistor Rs (with Rs:DV = IPD/PU * Rs); 0.06*Vs 0.10*Vs V P_10.1.2 in all modes; without external serial resistor Rs (with Rs:dV = IPD/PU * Rs); 5.5 V < VS < 18 V Threshold hysteresisextended supply voltage range VMONth,hys 0.02*Vs 0.06*Vs 0.12*Vs V P_10.1.7 in all modes; without external serial resistor Rs (with Rs:dV = IPD/PU * Rs); 18 V < VS < 28 V Pull-up current IPU, MON -20 -10 -5 µA 0.6*Vs; P_10.1.3 Pull-down current IPD, MON 5 10 20 µA 0.4*Vs; P_10.1.4 Input leakage current ILK,MON -2 – 2 µA 0 V < VMON_IN < 28 V P_10.1.5 tFT,MON - 20 - µs 1) P_10.1.6 Min. Typ. Max. 0.4*Vs 0.5*Vs 0.6*Vs MON Input Pin characteristics Wake-up/monitoring threshold voltage VMONth Threshold hysteresis VMONth,hys 0.015* Vs _VS_extende d Timing Wake-up filter time 1) With pull-up, pull down current disabled. Data Sheet 120 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.11 High Side Switches 28.11.1 Electrical Characteristics Table 43 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number PWM frequency of HS with Slew Rate Control fPWM_W_SR 0 – 10 kHz 1) Frequency must be configured in the PWM Generator P_11.1.1 PWM frequency of HS without Slew Rate Control fPWM_W/O_SR 0 – 252) kHz 1) Frequency must be configured in the PWM Generator P_11.1.2 ON-State Resistance RON 2 10 18 Ω 5.5 V < VS < 28V, Ids=100mA, Tj = 25 °C P_11.1.3 Output leakage Current Ileakage – – 2 µA Output OFF 0 V < VXLO < VS; Tj ≤ 150 °C P_11.1.4 1 – 10 V/µs 20% to 80% of VS VS = 9 to 18V RL =300Ω1) P_11.1.5 -10 – -1 V/µs 80% to 20% of VS VS = 9 to 18V RL =300Ω1) P_11.1.6 18.0 – 55.0 V/µs 20% to 80% of VS VS = 9 to 18V RL =300Ω1) P_11.1.7 P_11.1.8 Output HS Output Slew Rate (rising) with SRraise_SR1 slow Slew Rate setting (Slew Rate 1) Output Slew Rate (falling) with slow Slew Rate setting (Slew Rate 1) SRfall_SR1 Output Slew Rate (rising) with SRraise_SR2 fast Slew Rate setting (Slew Rate 2) Output Slew Rate (falling) with fast Slew Rate setting (Slew Rate 2) SRfall_SR2 -43.4 – -12.5 V/µs 80% to 20% of VS VS = 9 to 18V RL =300Ω1) Turn ON Delay time (Slew Rate 1) tIN-HS_SR1 – – 4.5 µs ON = 1 to 20% of VS RL =300Ω P_11.1.9 Turn ON time (Slew Rate 1) tON_SR1 1 – 15 µs VS = 9 to 18V P_11.1.10 HS_ON=1 to 80% of VS RL =300Ω Tj =25°C Turn OFF time (Slew Rate 1) tOFF_SR1 1 – 15 µs VS = 9 to 18V P_11.1.11 HS_ON= 0 to 20% of VS RL =300Ω; Tj =25°C Data Sheet 121 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 43 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number Turn ON Delay time (Slew Rate 2) tIN-HS_SR2 – – 1 µs ON = 1 to 20% of VS RL =300Ω P_11.1.55 Turn ON time (Slew Rate 2) tON_SR2 – – 3 µs VS = 9 to 18V P_11.1.56 HS_ON=1 to 80% of VS RL =300Ω Tj =25°C Turn OFF time (Slew Rate 2) tOFF_SR2 – – 3 µs VS = 9 to 18V P_11.1.57 VS = 13.5V P_11.1.12 HS_ON= 0 to 20% of VS RL =300Ω; Tj =25°C Over-current detection Overcurrent threshold 0 Iocth0 26 42 60 mA HSx_OC_SEL =00 Overcurrent threshold 0 hysteresis Iocth0,hyst – 14 – mA 1) Overcurrent threshold 1 Iocth1 51 60 80 mA VS = 13.5V HSx_OC_SEL =00 P_11.1.13 P_11.1.14 HSx_OC_SEL =01 Overcurrent threshold 1 hysteresis Iocth1,hyst – 17 – mA 1) Overcurrent threshold 2 Iocth2 101 123 150 mA VS = 13.5V HSx_OC_SEL =01 P_11.1.15 P_11.1.16 HSx_OC_SEL =10 Overcurrent threshold 2 hysteresis Iocth2,hyst – 25 – mA 1) Overcurrent threshold 3 Iocth3 151 176 210 mA VS = 13.5V HSx_OC_SEL =11 P_11.1.19 VS = 13.5V, P_11.1.20 HSx_OC_SEL =10 P_11.1.17 P_11.1.18 HSx_OC_SEL =11 Overcurrent threshold 3 hysteresis Iocth3,hyst – 30 – mA 1) Over-current shutdown response time tocft 8 – 80 µs 1) RL =100Ω, HS_ON to OC_SD (including switchon time) ON-state open load detection Open load threshold IOLONth 0.46 1.32 2.2 mA – P_11.1.21 Hysteresis IOLONhys 35 155 300 µA – P_11.1.22 IHS max 40 – – mA Sleep Mode / Stop Mode P_11.1.23 – – 40 Ω Ids = 40mA, P_11.1.24 Cyclic sense mode Current capability sleep_pd ON-State Resistance Data Sheet RON,static 122 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics Table 43 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Output Slew Rate (rising) SRrise_cyc 1 – – V/µs 20% to 80% of VS VS = 9 to 18V RL =300Ω P_11.1.25 Output Slew Rate (falling) SRfal_cycl – – -1 V/µs 80% to 20% of VS VS = 9 to 18V RL =300Ω P_11.1.26 – – 2 µs ON =1 to 20% of VS RL=300Ω P_11.1.27 – – 15 µs VS = 9 to 18V P_11.1.28 Delay Time CYCLIC_ON-HS tIN_cyc Turn-ON time tON_cyc ON=1 to 80% RL =300Ω Turn-OFF time tOFF_cyc – – 15 µs VS = 9 to 18V P_11.1.29 ON=0 to 20% of VS RL =300Ω; Tj=25°C 1) Not subject to production test, specified by design. 2) this is an additional requirement which refers to a 47Ohm series resistor to charge an external power mos gate. Data Sheet 123 Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 28.12 Low Side Switches 28.12.1 Electrical Characteristics Table 44 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 1) PWM Frequency of LS fPWM – – 25 kHz Overcurrent Limitation ILSTyp 270 300 330 mA ON-State Resistance RON 1 4 10 Ω Ids =100mA; P_12.1.3 Leakage Current Ileakage – – 2 µA 0 V < VLS < VS; Tj < 85°C P_12.1.5 Turn ON Delay time, slow mode tdOn-LS – – 50 µs 2) P_12.1.6 Turn ON Delay time, PWM mode tdOn,f-LS RL =270Ω Number P_12.1.1 P_12.1.2 LS_ON=1 to 0.9*Vs VS=13.5V, RL =270Ω – – 0.5 µs LS_ON=1 to 0.9*Vs P_12.1.7 VS=13.5V, RL =270Ω Turn ON fall time, PWM mode tONF,PWM – 1 1.25 µs VLS 0.9*Vs to 0.1*Vs VS=13.5V, RL =270Ω P_12.1.8 Turn ON fall time, slow mode tONF,Slow – 100 150 µs 2) VLS 0.9*Vs to 0.1*Vs VS=13.5V, RL =270Ω P_12.1.9 – – 50 µs 2) P_12.1.10 Turn OFF Delay time, slow mode tdOff-LS tdOff,f-LS LS_ON=0 to 0.1*Vs VS=13.5V, RL =270Ω – – 2 µs LS_ON=0 to 0.1*Vs VS=13.5V, RL =270Ω P_12.1.11 Turn OFF Rise time, PWM mode tOFFR,PWM – 1 1.25 µs VLS 0.1*Vs to 0.9*Vs; VS=13.5V, RL =270Ω P_12.1.12 100 150 µs 2) VLS 0.1*Vs to 0.9*Vs; VS=13.5V, RL =270Ω P_12.1.13 Turn OFF Delay time, PWM mode Turn OFF Rise time, slow mode tOFFR,Slow – Minimum Duty Cycle Pulse Width tonMIN variation 1.5 2 3.5 µs ton(dig) = 2µs1) P_12.1.14 Typical (systematic) Pulse Width d tonTYP increase LS_ON to VLS – 1.25 – µs ton(dig) = 2µs1) P_12.1.15 Zener Clamp Voltage VAZ – 50 – V values are valid at Tj = 25°C P_12.1.16 Clamping Energy (repetitive) Eclamp – – 2 mJ 1)3) 1.000.000 cycles, @ Imax = 90mA P_12.1.17 Clamping Energy Eclamp – – 14 mJ 1)3) 10 cycles, Tstart = 25°C, @ Imax = 230mA P_12.1.18 Clamping Energy (single), hot Eclamp – – 7 mJ 1)3) P_12.1.19 Data Sheet 124 10 cycles, Tstart = 85°C, @ Imax = 230mA Rev. 1.0, 2016-05-06 TLE9842-2QX Electrical Characteristics 1) Not subject to production test, specified by design. 2) Static ON mode (no PWM) 3) valid for one low-side, not for both at the same time Data Sheet 125 Rev. 1.0, 2016-05-06 TLE9842-2QX Package Outlines Package Outlines 0.9 MAX. (0.65) 0. 13 ± +0.03 1) 0.4 x 45° Index Marking C 0.15 ±0.05 0.1 ±0.05 48 13 (0 (0.2) 0.05 MAX. 2) 37 1 12 1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Figure 41 36 25 24 SEATING PLANE 7 ±0.1 6.8 48x 0.08 0.5 0.5 ±0.07 0.1±0.03 B 26 0. 6.8 11 x 0.5 = 5.5 (6) A (5.2) 7 ±0.1 0. 05 29 .3 0.23 ±0.05 5) (5.2) Index Marking 48x 0.1 M A B C (6) PG-VQFN-48-29, -31-PO V05 Package outline VQFN-48-31 (with LTI) Notes 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 2. Dimensions in mm. Data Sheet 126 Rev. 1.0, 2016-05-06 TLE9842-2QX Revision History 30 Revision History Revision History Page or Item Subjects (major changes since previous revision) Rev. 1.0, 2016-05-06 Initial revision Data Sheet 127 Rev. 1.0, 2016-05-06 Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™. Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2016-05-06 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 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