TLE9879QTW40XUMA1

TLE9879QTW40 Microcontroller with LIN and BLDC MOSFET Driver for Automotive Applicati ons BF-step Extended operating temperatur e range (grade 0) Features • 32-bit Arm®* Cortex®-M3 core • 128 KB flash • 6 KB RAM • On-chip OSC and PLL for clock generation • MOSFET driver including charge pump • 1 LIN 2.2 transceiver • High-speed operational amplifier for motor current sensing via shunt • Single power supply from 5.5 V to 27 V • Temperature range Tj = -40°C to +175°C Potential applications • Wiper • Aux. pumps • Fans • Window lift • Sunroof • Tailgate Product validation Qualified for automotive applications. Product validation according to AEC-Q100/101. Description Type Package TLE9879QTW40 TQFP-48-10 Marking * Arm and Cortex are registered trademarks of Arm Limited, UK Datasheet www.infineon.com 1 Rev. 1.0 2020-07-23 TLE9879QTW40 Table of contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 3.1 3.2 Device pinout and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.3.3 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMU modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power supply generation unit (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage regulator 5.0 V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage regulator 1.5 V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External voltage regulator 5.0 V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 19 21 22 22 23 24 6 6.1 6.2 6.2.1 6.3 6.3.1 6.3.2 6.3.2.1 6.3.2.2 System control unit – digital modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-precision clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-precision oscillator circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External input clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External crystal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 26 28 28 28 29 29 7 7.1 7.2 7.2.1 System control unit – power modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 8 8.1 8.2 8.2.1 Arm® Cortex®-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 33 9 9.1 9.2 9.2.1 9.3 9.3.1 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 35 35 36 36 10 Address space organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 11.1 11.2 Memory control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Datasheet 2 Rev. 1.0 2020-07-23 TLE9879QTW40 11.2.1 11.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 NVM module (flash memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12 12.1 12.2 12.2.1 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.1 13.2 Watchdog timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.1.1 14.3.2 14.3.2.1 14.3.3 14.3.3.1 GPIO ports and peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 and port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE9879QTW40 port module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 45 47 48 48 48 50 50 52 52 15 15.1 15.1.1 15.1.2 15.2 15.2.1 15.2.2 General-purpose timer units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features of block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features of block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 54 54 54 55 56 57 16 16.1 16.2 16.2.1 Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer2 and Timer21 mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 58 58 58 17 17.1 17.2 17.3 17.3.1 Timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer3 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 60 60 60 18 18.1 18.2 18.2.1 Capture/compare unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 63 64 19 19.1 19.2 19.2.1 UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 65 65 Datasheet 3 41 41 41 41 Rev. 1.0 2020-07-23 TLE9879QTW40 19.3 UART modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20 20.1 20.2 20.2.1 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 67 68 21 21.1 21.2 21.2.1 High-speed synchronous serial interface (SSC1/SSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 69 70 70 22 Measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1.1 BEMF comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 72 73 23 23.1 23.2 23.2.1 23.2.2 Core measurement module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Core measurement module mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 74 74 74 75 24 24.1 24.2 24.2.1 10-bit analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 76 76 77 25 25.1 25.2 25.2.1 High-voltage monitor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 78 78 78 26 26.1 26.2 26.2.1 26.2.2 Bridge driver (incl. charge pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 80 80 27 27.1 27.2 27.2.1 Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 81 81 82 28 28.1 28.2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 BLDC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ESD immunity according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 29 29.1 29.1.1 29.1.2 29.1.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datasheet 4 86 86 86 89 90 Rev. 1.0 2020-07-23 TLE9879QTW40 29.1.4 29.1.5 29.2 29.2.1 29.2.2 29.2.3 29.2.4 29.2.4.1 29.2.5 29.3 29.3.1 29.3.2 29.4 29.4.1 29.5 29.5.1 29.5.2 29.5.3 29.6 29.6.1 29.7 29.7.1 29.8 29.8.1 29.8.2 29.8.3 29.8.3.1 29.8.3.2 29.9 29.9.1 29.9.2 29.10 29.11 29.11.1 29.12 29.12.1 29.13 29.13.1 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PMU I/O supply (VDDP) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PMU core supply (VDDC) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 VDDEXT voltage regulator (5.0 V) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 VPRE voltage regulator (PMU subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Load-sharing scenario for the VPRE regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Power-down voltage regulator (PMU subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 System clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Parameters of oscillators and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 External clock parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Flash parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Parallel ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Description of the keep and force currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DC parameters of port 0, port 1, TMS, and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DC parameters of port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 High-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SSC timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 System voltage measurement parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Central temperature sensor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ADC2 VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC2 reference voltage VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC1 reference voltage - VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Electrical characteristics of VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Electrical characteristics of the ADC1 (10-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 High-voltage monitoring input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 MOSFET driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 30 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Datasheet 5 Rev. 1.0 2020-07-23 TLE9879QTW40 Overview 1 Overview Summary of Features • 32-bit Arm® Cortex®-M3 core – Up to 40 MHz clock frequency – One clock per machine cycle architecture • On-chip memory – 128 KB flash including – 4 KB EEPROM (emulated in flash) – 512 byte 100-time programmable memory (100TP) – 6 KB RAM – Boot ROM for startup firmware and flash routines • On-chip OSC and PLL for clock generation – PLL loss-of-lock detection • MOSFET driver including charge pump • 10 general-purpose I/O Ports (GPIO) • 5 analog inputs, 10-bit A/D Converter (ADC1) • 16-bit timers - GPT12, Timer2, Timer21, and Timer3 • Capture/compare unit for PWM signal generation (CCU6) • 2 full-duplex serial interfaces (UART) with LIN support (for UART1 only) • 2 synchronous serial channels (SSC) • On-chip debug support via 2-wire SWD • 1 LIN 2.2 transceiver • 1 high-voltage monitoring input • Single power supply from 5.5 V to 27 V • Extended power supply voltage range from 3 V to 28 V • Low-dropout voltage regulators (LDO) • High-speed operational amplifier for motor current sensing via shunt • 5 V voltage supply for external loads (e.g., Hall sensor) • Core logic supply at 1.5 V • Programmable window watchdog (WDT1) with independent on-chip clock source • Power-saving modes – MCU slow-down mode – Sleep mode – Stop mode – Cyclic wake-up sleep mode • Power-on and undervoltage/brownout reset generator • Overtemperature protection • Short-circuit protection • Loss of clock detection with fail-safe mode entry for low system power consumption • Temperature range Tj = -40°C to +175°C Datasheet 6 Rev. 1.0 2020-07-23 TLE9879QTW40 Overview • Package TQFP-48 • Green package (RoHS compliant) • AEC-qualified Datasheet 7 Rev. 1.0 2020-07-23 TLE9879QTW40 Overview 1.1 Abbreviations The following acronyms and terms are used within this document. List see in Table 1. Table 1 Acronyms Acronyms Name AHB Advanced High-performance Bus APB Advanced Peripheral Bus CCU6 Capture compare unit 6 CGU Clock generation unit CMU Cyclic management unit CP Charge pump for MOSFET driver CSA Current-sense amplifier DPP Data post-processing ECC Error correction code EEPROM Electrically erasable programmable read only memory EIM Exceptional interrupt measurement FSM Finite state machine GPIO General-purpose input/output H-Bridge Half-bridge ICU Interrupt control unit IEN Interrupt enable IIR Infinite impulse response LDM Load instruction LDO Low-dropout voltage regulator LIN Local interconnect network LSB Least significant bit LTI Lead tip inspection MCU Microcontroller unit MF Measurement functions MSB Most significant bit MPU Memory protection unit MRST Master receive, slave transmit MTSR Master transmit, slave receive MU Measurement unit NMI Non-maskable interrupt NVIC Nested vector interrupt controller NVM Non-volatile memory OTP One-time programmable OSC Oscillator PBA Peripheral bridge Datasheet 8 Rev. 1.0 2020-07-23 TLE9879QTW40 Overview Table 1 Acronyms (cont’d) Acronyms Name PCU Power control unit PD Pull-down PGU Power supply generation unit PLL Phase-locked loop PPB Private Peripheral Bus PU Pull-up PWM Pulse-width modulation RAM Random-access memory RCU Reset control unit RMU Reset management unit ROM Read-only memory SCU-DM System control unit – digital modules SCU-PM System control unit – power modules SFR Special function register SOW Short open window (for WDT) SPI Serial Peripheral Interface SSC Synchronous serial channel STM Store instruction SWD Arm® Serial Wire Debug TCCR Temperature compensation control register TMS Test mode select TSD Thermal shut-down UART Universal asynchronous receiver-transmitter VBG Voltage reference bandgap VCO Voltage-controlled oscillator VPRE Preregulator WDT Watchdog timer in SCU-DM WDT1 Watchdog timer in SCU-PM WMU Wake-up management unit 100TP 100-time programmable Datasheet 9 Rev. 1.0 2020-07-23 TLE9879QTW40 Block diagram 2 Block diagram TMS P0.0 TEST / DEBUG INTERFACE Arm® Cortex®-M3 µDMA CONTROLLER system bus FLASH slave SRAM slave ROM slave slave Multilayer AHB matrix slave VAREF GND_REF P2.0, P2.2, P2.3, P2.4, P2.5 (AN0, AN2, AN3, AN4, AN5) MU-VAREF Figure 1 Datasheet PBA1 SCU_DM ADC 1 DPP1 GPT12 UART1 UART2 SSC1 SSC2 MOSFET driver CCU6 T2 T21 SCU_DM WDT SCU_PM WDT1/ CLKWDT CP µDMA controller PLL XTAL1 XTAL2 GPIO P0.1 – P0.4 P1.0 – P1.4 LIN OP AMP VCP VSD CP2H CP2L CP1H CP1L PBA0 OP AMP VDH GH3 SH3 GL3 GH2 SH2 GL2 GH1 SH1 GL1 SL slave LIN GND_LIN MU MF / ADC2 DPP2 OP AMP OP1 OP2 PMU – power control system functions VS RESET VDDEXT VDDP VDDC MON MON T3 Block diagram 10 Rev. 1.0 2020-07-23 TLE9879QTW40 25 P0. 2 27 P1.4 28 GND 29 P2. 0/XTAL1 30 P2. 2/XTAL2 31 P2.5 32 P2.4 33 GND_REF Device pinout 34 VAREF 3.1 35 P2.3 Device pinout and pin configuration 36 OP2 3 26 P1. 3 Device pinout and pin configuration OP1 37 24 P0.3 EP VDDC 38 23 P0.1 EP GND 39 22 RESET VDDP 40 21 P0.0 VDDEXT 41 20 TMS 19 GND GND_LIN 42 TLE 987x LIN 43 18 P0.4 VDH 44 17 P1.2 VS 45 16 P1.1 SH3 46 15 P1.0 VSD 47 14 MON 13 GL1 Note: Figure 2 Datasheet GL2 12 GL3 11 SL 10 GH1 9 SH1 8 GH2 7 SH2 6 GH3 5 CP2L 4 VCP 2 CP2H 3 CP1L 1 CP1H 48 = Low voltage pins Device pinout 11 Rev. 1.0 2020-07-23 TLE9879QTW40 Device pinout and pin configuration 3.2 Pin configuration After a reset, all pins are configured as input (except supply and LIN pins) with one of the following settings: • Pull-up device enabled only (PU) • Pull-down device enabled only (PD) • Input with both pull-up and pull-down devices disabled (I) • Output with output stage deactivated = high-impedance state (Hi-Z) The functions and default states of the TLE9879QTW40 external pins are provided in the following table. Type: indicates the pin type. • I/O: Input or output • I: Input only • O: Output only • P: Power supply Not all alternate functions are listed. Table 2 Symbol Pin definitions and functions Pin number Type Reset Function state1) P0 Port 0 Port 0 is a 5-bit bidirectional general-purpose I/O port. Alternate functions can be assigned and are listed in the port description. The main functions are listed below. P0.0 21 I/O I/PU SWD Serial wire debug clock P0.1 23 I/O I/PU GPIO General-purpose I/O Alternate function mapping see Table 8. P0.2 25 I/O I/PD GPIO General-purpose I/O Alternate function mapping see Table 8. Note: For a functional SWD connection, this GPIO must be tied to zero. P0.3 24 I/O I/PU GPIO General-purpose I/O Alternate function mapping see Table 8. P0.4 18 I/O I/PD GPIO General-purpose I/O Alternate function mapping see Table 8. P1 Port 1 Port 1 is a 5-bit bidirectional general-purpose I/O port. Alternate functions can be assigned and are listed in the port description. The main functions are listed below. P1.0 15 I/O I GPIO General-purpose I/O Alternate function mapping see Table 8. P1.1 16 I/O I GPIO General-purpose I/O Alternate function mapping see Table 9. P1.2 17 I/O I GPIO General-purpose I/O Alternate function mapping see Table 9. Datasheet 12 Rev. 1.0 2020-07-23 TLE9879QTW40 Device pinout and pin configuration Table 2 Pin definitions and functions (cont’d) Symbol Pin number Type Reset Function state1) P1.3 26 I/O I GPIO General-purpose I/O, used for inrush transistor Alternate function mapping see Table 9. P1.4 27 I/O I GPIO General-purpose I/O Alternate function mapping see Table 9. P2 Port 2 Port 2 is a 5-bit general-purpose input-only port. Alternate functions can be assigned and are listed in the port description. The main functions are listed below. P2.0/XTAL1 29 I/I I AN0 ADC analog input 0 Alternate function mapping see Table 10. P2.2/XTAL2 30 I/O I AN2 ADC analog input 2 Alternate function mapping see Table 10. P2.3 35 I I AN3 ADC analog input 3 Alternate function mapping see Table 10. P2.4 32 I I AN4 ADC analog input 4 Alternate function mapping see Table 10. P2.5 31 I I AN5 ADC analog input 5 Alternate function mapping see Table 10. 45 P – Battery supply input Power supply VS VDDP 40 P – 2) VDDC 38 P – 3) Core supply (1.5 V in Active mode). Do not connect external loads, but connect an external buffer capacitor. VDDEXT 41 P – External voltage supply output (5.0 V, 20 mA) GND 19 P – GND digital GND 28 P – GND digital GND 39 P – GND analog 14 I – High voltage monitor input LIN 43 I/O – LIN bus interface input/output GND_LIN 42 P – LIN ground CP1H 48 P – Charge pump capacity 1 high, connect external C CP1L 1 P – Charge pump capacity 1 low, connect external C CP2H 3 P – Charge pump capacity 2 high, connect external C CP2L 4 P – Charge pump capacity 2 low, connect external C VCP 2 P – Charge pump capacity I/O port supply (5.0 V). Connect external buffer capacitor. Monitor input MON LIN interface Charge pump Datasheet 13 Rev. 1.0 2020-07-23 TLE9879QTW40 Device pinout and pin configuration Table 2 Pin definitions and functions (cont’d) Symbol Pin number Type Reset Function state1) VSD 47 P – Battery supply input for charge pump VDH 44 P – Voltage drain high-side MOSFET driver SH3 46 P – Source high-side FET 3 SH2 6 P – Source high-side FET 2 GH2 7 P – Gate high-side FET 2 SH1 8 P – Source high-side FET 1 GH1 9 P – Gate high-side FET 1 SL 10 P – Source low-side FET GL2 12 P – Gate low-side FET 2 GL1 13 P – Gate low-side FET 1 GH3 5 P – Gate high-side FET 3 GL3 11 P – Gate low-side FET 3 GND_REF 33 P – GND for VAREF VAREF 34 I/O – 5V ADC1 reference voltage, optional buffer or input OP1 37 I – Negative operational amplifier input OP2 36 I – Positive operational amplifier input TMS 20 I I/O I/PD TMS SWD RESET 22 I/O – Reset input, not available during sleep mode EP – – – Exposed pad, connect to GND MOSFET driver Others Test mode select input Serial Wire Debug input/output 1) Only valid for digital IO. 2) Also named VDD5V. 3) Also named VDD1V5. Datasheet 14 Rev. 1.0 2020-07-23 TLE9879QTW40 Modes of operation 4 Modes of operation The TLE9879QTW40 highly integrated circuit contains analog and digital functional blocks. An embedded 32bit microcontroller is available for system and interface control. On-chip, low-dropout regulators are provided for internal and external power supply. An internal oscillator provides a cost-effective clock that is particularly well suited for LIN communications. A LIN transceiver is available as a communication interface. Driver stages for a motor bridge or BLDC motor bridge with external MOSFET are integrated, featuring PWM capability, protection features, and a charge pump for operation at low supply voltage. A 10-bit SAR ADC is implemented for high-precision sensor measurement. An 8-bit ADC is used for diagnostic measurements. The Micro controller unit supervision and system protection (including a reset feature) is complemented by a programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. All relevant modules offer power saving modes in order to support automotive applications connected to terminal 30. A wake-up from power-save mode is possible via a LIN bus message, via the monitoring input, or using a programmable time period (cyclic wake-up). The TLE9879QTW40 has several operation modes mainly to support low power consumption requirements. Reset mode The Reset mode is a transition mode used, e.g., during power-up of the device after a power-on reset, or after wake-up from Sleep mode. In this mode, the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable, the device enters Active mode. If the watchdog timer WDT1 fails more than four times, the device performs a fail-safe transition to Sleep mode. Active mode In Active mode, all modules are activated and the TLE9879QTW40 is fully operational. Stop mode Stop mode is one of two major low-power modes. The transition to the low-power modes is performed by setting the corresponding bits in the mode control register. In Stop mode, the embedded microcontroller is still powered, allowing for shorter wake-up response times. Wake-up from this mode is possible through LIN bus activity, by using the high-voltage monitoring pin, or through the corresponding 5 V GPIOs. Stop mode with cyclic wake-up The Cyclic Wake-Up mode is a special operating mode of the Stop mode. The transition to the Cyclic Wake-Up mode is performed by first setting the corresponding bits in the mode control register, followed by the Stop Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Stop mode. Sleep mode The Sleep mode is a low-power mode. The transition to the low-power mode is performed by setting the corresponding bits in the MCU mode control register or in case of failure (see below). In Sleep mode the embedded microcontroller power supply is deactivated, allowing for the lowest system power consumption. A wake-up from this mode is possible by LIN bus activity, the High Voltage Monitor Input pin, or through cyclic wake-up. Sleep mode in case of failure Sleep mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case, MON is enabled as the wake source and cyclic wake-up is activated with 1 s of dead time. Datasheet 15 Rev. 1.0 2020-07-23 TLE9879QTW40 Modes of operation Sleep Mode with cyclic wake-up The Cyclic Wake-Up mode is a special operating mode of the Sleep mode. The transition to Cyclic Wake-Up mode is performed by first setting the corresponding bits in the mode control register followed by the Sleep Mode and Stop Mode commands. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Sleep mode. When using Sleep mode with cyclic wake-up, the voltage regulator is switched off and started again with the wake. A limited number of registers is buffered during sleep, and can be used by software, e.g., for counting sleep/wake cycles. MCU Slow Down mode In MCU Slow Down mode the MCU frequency is reduced to save power during operation. LIN communication is still possible. LS MOSFET can be activated. Wake-up source prioritization All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless, all wake-up sources are latched in order to provide all wake-up events to the application software. The software can clear the wakeup source flags. This is to ensure that no wake-up event is lost. As the default wake-up source, the MON input is activated after power-on reset only. Additionally, the device is in Cyclic Wake-Up mode with the configurable dead time setting. The following table shows the possible power mode configurations including the Stop mode. Table 3 Power mode configurations Module/function Active mode Stop mode Sleep mode Comment VDDEXT ON/OFF ON (no dynamic load)/OFF OFF – Bridge Driver ON/OFF OFF OFF LIN TRx ON/OFF Wake-up only/OFF Wake-up only/OFF VS sense ON/OFF Brownout detection Brownout detection POR on VS Brownout detection performed in PCU GPIO 5V (wake-up) n.a. Disabled/static OFF – GPIO 5V (active) ON ON OFF – WDT1 ON OFF OFF – CYCLIC WAKE n.a. Cyclic wake-up/ cyclic sense/OFF Cyclic wake-up/OFF – Measurement ON1) OFF OFF – OFF – 2) – MCU ON/slow-down/STOP STOP CLOCK GEN (MC) ON OFF OFF – LP_CLK (18 MHz) ON OFF OFF WDT1 LP_CLK2 (100 kHz) ON/OFF ON/OFF ON/OFF For cyclic wake-up 1) May not be switched off due to safety reasons. 2) MC PLL clock disabled, MC supply reduced to VDDCOUT_Stop_Red. Datasheet 16 Rev. 1.0 2020-07-23 TLE9879QTW40 Modes of operation Wake-up levels and transitions The wake-up can be triggered by rising, falling, or both signal edges for the monitor input, GPIOs, by LIN, or by cyclic wake-up. Datasheet 17 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) 5 Power management unit (PMU) 5.1 Features • System mode control (startup, sleep, stop and active) • Power management (cyclic wake-up) • Control of system voltage regulators with diagnosis (overload, short, overvoltage) • Fail-safe mode detection and operation in case of system errors (watchdog fail) • Wake-up sources configuration and management (LIN, MON, GPIOs) • System error logging 5.2 Introduction The power management unit is responsible for generating all required voltage supplies for the embedded MCU (VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure failsafe behavior of the system IC by controlling all system modes, including the corresponding transitions. Additionally, the PMU provides well-defined sequences for the system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset behavior of all system functions, especially the reset behavior of the embedded MCU. All these functions are controlled by a state machine. The system master function of the PMU uses an independent logic supply and system clock. For this reason, the PMU has an "Internal logic supply and system clock" module which works independently of the MCU clock. Datasheet 18 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) 5.2.1 Block diagram The following figure shows the structure of the power management unit. Table 4 describes the submodules in more detail. VS Power-down supply e.g. for WDT1 Power supply generation unit (PGU) I N T E R N A L LP_CLK Peripherals e.g. for cyclic wake and sense LP_CLK2 B U S PMU-PCU MON LIN P0.0...P0.4 P1.0...P1.4 LDO for external supply VDDEXT VDDP VDDC VDDEXT PMU-SFR PMU-CMU PMU-WMU PMU-RMU PMU control Power management unit Figure 3 Power management unit block diagram Table 4 Description of PMU submodules Module name Modules Functions Power-down supply Independent supply voltage generation for PMU. This supply is dedicated to the PMU to ensure an operation independently of generated power supplies (VDDP, VDDC). LP_CLK (18 MHz) • Clock source for all PMU submodules. • Backup clock source for the system. • Clock source for WDT1. This ultra-low-power oscillator generates the clock for the PMU. This clock is also used as the backup clock for the system in case of PLL clock failures and as an independent clock source for WDT1. LP_CLK2 (100 kHz) Clock source for PMU. This ultra-low-power oscillator generates the clock for the PMU in Stop mode and in the cyclic modes. Peripherals Peripheral blocks of PMU. These blocks include the analog peripherals to ensure a stable and fail-safe PMU startup and operation (bandgap, bias). Datasheet 19 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) Table 4 Description of PMU submodules (cont’d) Module name Modules Functions Power supply Voltage regulators for VDDP and generation VDDC. unit (PGU) This block includes the voltage regulators for the pad supply (VDDP) and the core supply (VDDC). VDDEXT Voltage regulator for VDDEXT to supply external modules (e.g., sensors). This voltage regulator is a dedicated supply for external modules and can also be used for cyclic sense operations (e.g., with hall sensor). PMU-SFR All extended special function registers This module contains all registers needed to control that are relevant to the PMU. and monitor the PMU. PMU-PCU Power control unit of the PMU. This block is responsible for controlling all powerrelated actions within the PGU module. It also contains all regulator-related diagnostics such as undervoltage and overvoltage detection as well as overcurrent and short-circuit diagnostics. PMU-WMU Wake-up management unit of the PMU. This block is responsible for controlling all actions related to wake-up within the PMU module. PMU-CMU Cyclic management unit of the PMU. This block is responsible for controlling all actions in cyclic mode. PMU-RMU Reset management unit of the PMU. This block generates resets triggered by the PMU, such as undervoltage or short-circuit reset, and passes all resets to the relevant modules and their registers. Datasheet 20 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) 5.2.2 PMU modes overview The following state diagram shows the available modes of the device. VS > 4 V and VS ramp-up or VS < 3 V and VS ramp-down LIN-wake or MON-wake or cyclic-wake start-up VDDC = stable and error_supp < 5 VDDC / VDDP = fail (short-circuit)  error_supp ++ error_supp=5 sleep active Sleep command (from MCU) or WDT1_SEQ_FAIL = 1 ( error_wdt = 5) or VDDC / VDDP = overload or system overtemperature LIN-wake or MON-wake or GPIO-wake or cyclic_wake or PMU_PIN = 1 or SUP_TMOUT = 1 PMU_PIN = 1 or PMU_SOFT = 1 or (PMU_Ext_WDT = 1 and WDT1_SEQ_FAIL = 0  error_wdt ++) Stop command (from MCU) stop cyclic-sense Figure 4 Power management unit system modes Datasheet 21 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) 5.3 Power supply generation unit (PGU) 5.3.1 Voltage regulator 5.0 V (VDDP) This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and other 5 V analog functions (e.g. LIN transceiver). Features • 5 V low-drop voltage regulator • Overcurrent monitoring and shutdown with MCU signaling (interrupt) • Overvoltage monitoring with MCU signaling (interrupt) • Undervoltage monitoring with MCU signaling (interrupt) • Undervoltage monitoring with reset (undervoltage reset, VDDPUV) • Preregulator for the VDDC regulator • GPIO supply • Pull-down current source at the output for Sleep mode only (typ. 5 mA) The output capacitor CVDDP is mandatory to ensure proper regulator functionality. VDDP regulator VS VPRE A VDDP CVDDP V GND (pin 39) I 5 V LDO PMU_5V_OVERVOLT PMU_5V_OVERLOAD LDO supervision Figure 5 Datasheet Module block diagram of the VDDP voltage regulator 22 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) 5.3.2 Voltage regulator 1.5 V (VDDC) This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core, the digital peripherals, and other internal analog 1.5 V functions (e.g., ADC2) of the chip. To further reduce the current consumption of the MCU during Stop mode the output voltage can be lowered to VDDCOUT_Stop_Red. Features • 1.5 V low-drop voltage regulator • Overcurrent monitoring and shutdown with MCU signaling (interrupt) • Overvoltage monitoring with MCU signaling (interrupt) • Undervoltage monitoring with MCU signaling (interrupt) • Undervoltage monitoring with reset • Pull-down current source at the output for Sleep mode only (typ. 100 μA) The output capacitor CVDDC is mandatory to ensure a proper regulator functionality. VDDC regulator VDDP (5 V) VDDC (1.5 V) A V CVDDP CVDDC GND (pin 39) I 1.5 V LDO PMU_1V5_OVERVOLT PMU_1V5_OVERLOAD LDO supervision Figure 6 Datasheet Module block diagram of the VDDC voltage regulator 23 Rev. 1.0 2020-07-23 TLE9879QTW40 Power management unit (PMU) 5.3.3 External voltage regulator 5.0 V (VDDEXT) This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used, e.g., to supply an external sensor, LEDs, or potentiometers. Features • Switchable +5 V, low-drop voltage regulator • Switch-on overcurrent blanking time in order to drive small capacitive loads • Overcurrent monitoring and shutdown with MCU signaling (interrupt) • Overvoltage monitoring with MCU signaling (interrupt) • Undervoltage monitoring with MCU signaling (interrupt) • Pull-down current source at the output for Sleep mode only (typ. 100 μA) • Cyclic sense option together with GPIOs The output capacitor CVDDEXT is mandatory to ensure a proper regulator functionality. VDDEXT regulator VS A VPRE VDDEXT CVDDEXT V GND (pin 39) I 5 V LDO Figure 7 Datasheet VDDEXT_CTRL.OVERLOAD VDDEXT_CTRL.OVERVOLT VDDEXT_CTRL.SHORT LDO supervision Module block diagram of the external voltage regulator 24 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – digital modules (SCU-DM) 6 System control unit – digital modules (SCU-DM) 6.1 Features • Flexible clock configuration features • Reset management of all system resets • System modes control for all power modes (Active mode, Stop mode, Sleep mode) • Enabling interrupts for many system peripherals • General-purpose input/output control • Debug mode control of system peripherals 6.2 Introduction The system control unit (SCU) supports all central control tasks in the TLE9879QTW40. The SCU is made up of the following submodules: • Clock system and control • Reset control • Power management • Interrupt management • General port control • Flexible peripheral management • Module suspension control • Watchdog timer • Error detection and correction in data memory • Miscellaneous control Datasheet 25 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – digital modules (SCU-DM) 6.2.1 Block diagram "On" signals to digital peripherals; status signals from digital peripherals AHB PMCU WDT CGU XTAL1 XTAL2 I N T E R N A L fOSC OSC_HP PLL LP_CLK fSYS fPCLK fMI_CLK fTFILT_CLK PMU_1V5DidPOR PMU_PIN PMU_ExtWDT PMU_IntWDT PMU_SOFT PMU_Wake RESET_TYPE_3 RESET_TYPE_4 P0_POCONy.PDMx P1_POCONy.PDMx fPLL CG fSYS NMI ICU INTISR B U S Misc. control MODPISELx RCU Port control System control unit – digital modules Figure 8 System control unit – digital modules block diagram AHB (Advanced High-Performance Bus) PMCU (power module control unit) WDT (watchdog timer in SCU-DM) • fSYS: System clock Datasheet 26 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – digital modules (SCU-DM) CGU (clock generation unit) • fSYS: System clock • fPCLK: Peripheral clock • fMI_CLK: Measurement interface clock • fTFILT_CLK: Analog module filter clock • LP_CLK Clock source for all PMU submodules and WDT1 ICU (interrupt control unit) • NMI (non-maskable interrupt) • INTISR External interrupt signals RCU (reset control unit) • PMU_1V5DidPOR Undervoltage reset of power-down supply • PMU_PIN Reset generated by reset pin • PMU_ExtWDT WDT1 reset • PMU_IntWDT WDT (SCU) reset • PMU_SOFT Software reset • PMU_Wake Sleep mode/Stop mode exit with reset • RESET_TYPE_3 Peripheral reset (contains all resets) • RESET_TYPE_4 Peripheral reset (without SOFT and WDT reset) Port control • P0_POCONy.PDMx Driver strength control • P1_POCONy.PDMx Driver strength control Miscellaneous control • MODPISELx mode selection registers for UART (source section) and timer (trigger or count selection) Datasheet 27 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – digital modules (SCU-DM) 6.3 Clock generation unit The clock generation unit (CGU) enables a flexible clock generation for the TLE9879QTW40. During user program execution, the frequency can be modified to optimize the performance/power consumption ratio, allowing power consumption to be adapted to the actual application state. The CGU in the TLE9879QTW40 consists of one oscillator circuit (OSC_HP), a phase-locked loop (PLL) module with an internal oscillator (OSC_PLL), and a clock control unit (CCU). The CGU can convert a low-frequency input/external clock signal to a high-frequency internal clock. The system clock fSYS is generated from one of the following selectable clocks: • PLL clock output fPLL • Direct clock from oscillator OSC_HP fOSC • Low-precision clock fLP_CLK (hardware-enabled for startup after reset and during power-down wake-up sequence) CGU PLL_CON OSC_CON HPOSCCON CMCON1 XTAL1 PLL OSC_HP SYSCON0 f PLL XTAL2 0 f OSC_int f LP_CLK LP_CLK LP_CLK f LP_CLK PMU Figure 9 1 fSYS 2 3 Clock generation unit block diagram The following sections describe the different parts of the CGU. 6.3.1 Low-precision clock The clock source LP_CLK is a low-precision RC oscillator (LP-OSC) with a nominal frequency of 18 MHz that is enabled by hardware as an independent clock source for the TLE9879QTW40 startup after reset and during the power-down wake-up sequence. fLP_CLK is not user-configurable. 6.3.2 High-precision oscillator circuit (OSC_HP) The high-precision oscillator circuit, designed to work with either an external crystal oscillator or an external stable clock source, consists of an inverting amplifier with XTAL1 as the input and XTAL2 as the output. Datasheet 28 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – digital modules (SCU-DM) 6.3.2.1 External input clock mode When supplying the clock signal directly, not using an external crystal and bypassing the oscillator, the input frequency needs to be equal or greater than 4 MHz if the PLL VCO part is used. When using an external clock signal, it must be connected to XTAL1. XTAL2 is left open (unconnected). 6.3.2.2 External crystal mode When using an external crystal, its frequency can be within the range of 4 MHz to 25 MHz. An external oscillator load circuitry must be used, connected to the XTAL1 and XTAL2 pins. It normally consists of two load capacitances C1 and C2. A series damping resistor could be required for some crystals. The exact values and the corresponding operating ranges depend on the crystal and have to be determined and optimized in cooperation with the crystal vendor using the negative-resistance method. The following load cap values can be used as starting points for the evaluation: Table 5 External CAP capacitors Fundamental mode crystal frequency (approx., MHz) Load caps C1, C2 (pF) 4 33 8 18 12 12 16 10 20 10 25 8 Datasheet 29 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – power modules (SCU-PM) 7 System control unit – power modules (SCU-PM) 7.1 Features • Clock watchdog unit (CWU): Supervises all clocks with NMI signaling relevant to power modules. • Interrupt control unit (ICU): All interrupt flags and status flags with system relevance. • Power control unit (PCU): Takes over control when device enters and exits Sleep and Stop mode. • External watchdog (WDT1): Independent system watchdog for monitoring system activity. 7.2 Introduction 7.2.1 Block diagram The system control unit of the power modules consists of the submodules in the figure shown below: "On" signals to analog peripherals; status signals from analog peripherals AHB I N T E R N A L PCU WDT1 fSYS MI_CLK LP_CLK PREWARN_SUP_NMI B U S CWU TFILT_CLK ICU PREWARN_SUP_INT INT System control unit – power modules Figure 10 Block diagram of system control unit – power modules AHB (Advanced High-performance Bus) CWU (clock watchdog unit) • fsys: System frequency • MI_CLK: Measurement interface clock (analog clock), derived from fsys using division factors 1/2/3/4 • TFILT_CLK: Clock used for digital filters, derived from fsys using configurable division factors Datasheet 30 Rev. 1.0 2020-07-23 TLE9879QTW40 System control unit – power modules (SCU-PM) WDT1 (system watchdog) • LP_CLK Clock source for all PMU submodules and WDT1 ICU (interrupt control unit) • PREWARN_SUP_NMI Supply prewarning NMI request • PREWARN_SUP_INT Supply prewarning interrupt • Grouping of peripheral interrupts for external interupt nodes: – Grouping single peripheral interrupts for interrupt node INT (measurement unit (MU)) – Grouping single peripheral interrupts for interrupt node INT (ADC1-VAREF) – Grouping single peripheral interrupts for interrupt node INT (UART1-LIN transceiver) – Grouping single peripheral interrupts for interrupt node INT (bridge driver) Datasheet 31 Rev. 1.0 2020-07-23 TLE9879QTW40 Arm® Cortex®-M3 core 8 Arm® Cortex®-M3 core 8.1 Features The key features of the Arm® Cortex®-M3 implemented are listed below. Processor core: a low-gate-count core, with low-latency interrupt processing • A subset of the Thumb®-2 instruction set • Banked stack pointer (SP) only • 32-bit hardware divide instructions, SDIV and UDIV (Thumb-2 instructions) • Handler and thread modes • Thumb and debug states • Interruptible-continued instructions LDM/STM, push/pop for low interrupt latency • Automatic processor state saving and restoration for low-latency interrupt service routine (ISR) entry and exit • Arm® architecture v7-M Style BE8/LE support • Arm®v6 unaligned accesses Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing • Interrupts, configurable from 1 to 16 • Bits of priority (4) • Dynamic reprioritization of interrupts • Priority grouping. This enables selection of preemptive interrupt levels and non-preemptive interrupt levels. • Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without the overhead of state-saving and restoration between interrupts. • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. Bus interfaces • Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and system bus interface • Memory access alignment • Write buffer for buffering of write data Datasheet 32 Rev. 1.0 2020-07-23 TLE9879QTW40 Arm® Cortex®-M3 core 8.2 Introduction The Arm® Cortex®-M3 processor is a leading 32-bit processor and provides a high-performance and costoptimized platform for a broad range of applications including microcontrollers, automotive body systems and industrial control systems. Like the other Arm® Cortex® family processors, the Arm® Cortex®-M3 processor implements the Thumb®-2 instruction set architecture. With the optimized feature set the Arm® Cortex®-M3 delivers 32-bit performance in an application space that is usually associated with 8- and 16-bit microcontrollers. 8.2.1 Block diagram Figure 11 shows the functional blocks of the Arm® Cortex®-M3. Arm® Cortex ®-M3 processor Interrupt and power control Nested vectored interrupt controller (NVIC) Arm® Cortex®-M3 processor core Serial-wire (SW-DP) AHB access port (AHB-AP) ICode AHB-Lite instruction interface Serial-wire debug interface Figure 11 Datasheet Bus matrix DCode AHB-Lite data interface System bus ICode PBA0 PBA1 Arm® Cortex®-M3 block diagram 33 Rev. 1.0 2020-07-23 TLE9879QTW40 DMA controller 9 DMA controller Figure 12 shows the top level block diagram of the TLE9879QTW40. The bus matrix allows the μDMA to access the PBA0, PBA1, and RAM. 9.1 Features The principal features of the DMA Controller are: • It is compatible with AHB-Lite for DMA transfers. • It is compatible with APB for register programming. • It has a single AHB-Lite master for transferring data using a 32-bit address bus and a 32-bit data bus. • It supports 13 DMA channels. • Each DMA channel has dedicated handshake signals. • Each DMA channel has a programmable priority level. • Each priority level arbitrates using a fixed priority that is determined by the DMA channel number. The DMA also supports multiple transfer types: - Memory-to-memory - Memory-to-peripheral - Peripheral-to-memory • It supports multiple DMA cycle types. • It supports multiple DMA transfer data widths. • Each DMA channel can access a primary and an alternate channel control data structure. • All the channel control data is stored in system memory (RAM) in little-endian format. • It performs all DMA transfers using the single AHB-Lite burst type. The destination data width is equal to the source data width. • The number of transfers in a single DMA cycle can be programmed from 1 to 1024. • The transfer address increment can be greater than the data width. Datasheet 34 Rev. 1.0 2020-07-23 TLE9879QTW40 DMA controller 9.2 Introduction Please also refer to Chapter 9.3, Functional description. 9.2.1 Block diagram SSC1 ADC1 Timer3 DMA requests DMA requests DMA requests DMA controller Bus matrix PBA1 M AHB-Lite S M AHB-Lite S AHB2APB APB interface interrupts PBA0 M AHB-Lite S SCU_DM RAM M AHB-Lite S Arm® core interrupts M AHB-Lite M M Figure 12 Datasheet S S AHB-Lite S DMA controller top level block diagram 35 Rev. 1.0 2020-07-23 TLE9879QTW40 DMA controller 9.3 Functional description 9.3.1 DMA mode overview The DMA controller implements the following 13 hardware DMA requests: • ADC1 complete sequence 1 done: DMA transfer is requested on completion of the ADC1 channel conversion sequence. • ADC1 exceptional sequence 2 (ESM) done: DMA transfer is requested on completion of the ADC1 conversion sequence triggered by an exceptional measurement request. • SSC1/2 transmit byte: DMA transfer is requested upon the completion of data transmission via SSC1/2. • SSC1/2: receive byte: DMA transfer is requested upon the completion of data reception via SSC1/2. • ADC1 channel 0 conversion done: DMA transfer is requested on completion of the ADC1 channel 0 conversion. • ADC1 channel 1 conversion done: DMA transfer is requested on completion of the ADC1 channel 1 conversion. • ADC1 channel 2 conversion done: DMA transfer is requested on completion of the ADC1 channel 2 conversion. • ADC1 channel 3 conversion done: DMA transfer is requested on completion of the ADC1 channel 3 conversion. • ADC1 channel 4 conversion done: DMA transfer is requested on completion of the ADC1 channel 4 conversion. • ADC1 channel 5 conversion done: DMA transfer is requested on completion of the ADC1 channel 5 conversion. • ADC1 channel 6 conversion done: DMA transfer is requested on completion of the ADC1 channel 6 conversion. • ADC1 channel 7 conversion done: DMA transfer is requested on completion of the ADC1 channel 7 conversion. • Timer3 ccu6_int: DMA transfer is requested following a timer trigger. Datasheet 36 Rev. 1.0 2020-07-23 TLE9879QTW40 Address space organization 10 Address space organization The TLE9879QTW40 manipulates operands in the following memory spaces: • 128 KB (incl. 4 KByte emulated EEPROM) of flash memory in code space • 32 KB Boot ROM memory in code space (used for boot code and IP storage) • 6 KB RAM memory in code space and data space (RAM can be read/written as program memory or external data memory) • Special function registers (SFRs) in peripheral space The figure below shows the detailed address alignment of the TLE9879QTW40: 00000000H Reserved (boot ROM) 00008000H 10FFFFFFH Flash, 128 KB 1101FFFFH 17FFFFFFH 11000000H Reserved 11020000H SRAM, 6 KB 18000000H 180017FFH Reserved 18001800H 3FFFFFFFH PBA0 40000000H 47FFFFFFH PBA1 48000000H 5FFFFFFFH Reserved 60000000H DFFFFFFFH Private Peripheral Bus E0000000H E00FFFFFH Reserved FFFFFFFFH Figure 13 Datasheet TLE9879QTW40 memory map 37 Rev. 1.0 2020-07-23 TLE9879QTW40 Memory control unit 11 Memory control unit 11.1 Features • Handles all system memory types and their interaction with the CPU • Memory protection functions for all system memory types (D-flash, P-flash, RAM) • Address management with access violation detection including reporting • Linear address range for all memory types (no paging) 11.2 Introduction 11.2.1 Block diagram The memory control unit is divided into the following submodules: • NVM memory module (embedded flash memory) • RAM memory module • BootROM memory module • Memory protection unit (MPU) module • Peripheral bridge PBA0 Datasheet 38 Rev. 1.0 2020-07-23 TLE9879QTW40 Memory control unit NVM RAM S0 S1 BROM PBA0 S2 S3 ROM code/ data RAM code/ data NVM code/ data Memory protection unit Sx: Bus slave Mx: Bus master M0 M1 M2 M3 Bus matrix Figure 14 Datasheet Block diagram of the memory control unit 39 Rev. 1.0 2020-07-23 TLE9879QTW40 Memory control unit 11.3 NVM module (flash memory) The flash memory provides embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. Features • In-system programming via LIN (flash mode) and SWD. • Error correction code (ECC) for detection of single-bit and double-bit errors and dynamic correction of single-bit errors. • Interrupts and signals double-bit errors by the NMI. • Program width of 128 byte (page). • Minimum erase width of 128 bytes (page). • Integrated hardware support for EEPROM emulation. • 8-byte read access. • Physical read access time: 75 ns. • Code-read access acceleration integrated; read buffer and automatic pre-fetch. • Page-program time: tPR . • Page-erase (128 bytes) and sector-erase (4 KB) time: tER. • Erased bit (cell) is read as ‘1’, for code flash and 100TP. • Erased bit (cell) is read as ‘0’ plus NMIMAP request, for data flash. Note: The user has to ensure that no flash operations which change the content of the flash get interrupted at any time. The clock for the NVM is supplied with the system frequency fsys. Integrated firmware routines for erasing NVM, EEPROM emulation, and other operations are provided. Datasheet 40 Rev. 1.0 2020-07-23 TLE9879QTW40 Interrupt system 12 Interrupt system 12.1 Features • Up to 16 interrupt nodes for on-chip peripherals • Up to 8 NMI nodes for critical system events • Maximum flexibility for all 16 interrupt nodes 12.2 Introduction Before enabling an interrupt, all corresponding interrupt status flags must be cleared. 12.2.1 Overview The TLE9879QTW40 supports 16 interrupt vectors with 16 priority levels. Fifteen of these interrupt vectors are assigned to the on-chip peripherals: GPT12, SSC, CCU6, DMA, bridge driver and A/D converter are each assigned to one dedicated interrupt vector; while UART1 and Timer2, as well as UART2, external interrupt 2 and Timer21 share interrupt vectors. Two vectors are dedicated for external interrupt 0 and 1. Table 6 Interrupt vector table Service request Node ID Description GPT12 0/1 GPT interrupt (T2-T6, CAPIN) MU-ADC2/T3 2 Measurement unit, VBG, Timer3, BEMF ADC1 3 ADC1 interrupt / VREF5V overload / VREF5V OV/UV CCU0 4 CCU6 node 0 interrupt CCU1 5 CCU6 node 1 interrupt CCU2 6 CCU6 node 2 interrupt CCU3 7 CCU6 node 3 interrupt SSC1 8 SSC1 interrupt (receive, transmit, error) SSC2 9 SSC2 interrupt (receive, transmit, error) UART1 10 UART1 (ASC-LIN) interrupt (receive, transmit), Timer2, linsync1, LIN UART2 11 UART2 interrupt (receive, transmit), Timer21, external interrupt (EINT2) EXINT0 12 External interrupt (EINT0), MON EXINT1 13 External interrupt (EINT1) BDRV/CP 14 Bridge driver / charge pump DMA 15 DMA controller Datasheet 41 Rev. 1.0 2020-07-23 TLE9879QTW40 Interrupt system Table 7 NMI interrupt table Service request Node Description Watchdog timer NMI NMI Watchdog timer overflow PLL NMI NMI PLL loss-of-lock NVM operation complete NMI NMI NVM operation complete Overtemperature NMI NMI System overtemperature Oscillator watchdog NMI NMI Oscillator watchdog / MI_CLK watchdog timer overflow NVM map error NMI NMI NVM map error ECC error NMI NMI RAM/NVM uncorrectable ECC error Supply prewarning NMI NMI Supply prewarning Datasheet 42 Rev. 1.0 2020-07-23 TLE9879QTW40 Watchdog timer (WDT1) 13 Watchdog timer (WDT1) 13.1 Features There are two watchdog timers in the system. The watchdog timer (WDT) within the system control unit – digital modules (see SCU_DM) and the Watchdog Timer (WDT1) located within the system control unit – power modules (see SCU_PM). The watchdog timer WDT1 is described in this section. In Active mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way to recover from software or hardware failures. The WDT1 is always enabled in Active mode. In Sleep mode, Stop Mode and SWD mode (Debug mode), the WDT1 is automatically disabled. Functional Features • Windowed watchdog timer with programmable timing in Active mode. • Long-open window (typ. 80 ms) after power-up, reset, wake-up. • Short-open window (typ. 30 ms) to facilitate flash programming. • Disabled during debugging. • Safety shutdown to Sleep mode after 5 missed WDT1 services. Datasheet 43 Rev. 1.0 2020-07-23 TLE9879QTW40 Watchdog timer (WDT1) 13.2 Introduction The behavior of the watchdog timer in Active mode is illustrated in Figure 15. Reset Always Long Open Window Trigger and count_SOW = 0 Normal "windowed" operation Trigger and count_SOW = 0 Figure 15 Datasheet Trigger and count_SOW = 0 Short open window and SOW Trigger SOW and count_SOW++ Watchdog timer behavior 44 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O 14 GPIO ports and peripheral I/O The TLE9879QTW40 has 15 port pins organized into three parallel ports: Port 0 (P0), port 1 (P1) and port 2 (P2). Each port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. P0 and P1 are bidirectional and can be used as general-purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. For ports configured as an output, the open drain mode can be selected. On port 2 (P2), analog inputs are shared with general-purpose inputs. 14.1 Features Features of bidirectional ports (P0, P1) • Configurable pin direction • Configurable pull-up/pull-down devices • Configurable open-drain mode • Configurable drive strength • Transfer of data through digital inputs and outputs (general-purpose I/O) • Alternate input/output for on-chip peripherals Features of the analog port (P2) • Configurable pull-up/pull-down devices • Transfer of data through digital inputs • Alternate inputs for on-chip peripherals 14.2 Introduction 14.2.1 Port 0 and port 1 Figure 16 shows the block diagram of a TLE9879QTW40 bidirectional port pin. Each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register, each individual pin can be configured as an input or an output. The user can also configure each pin as an open-drain pin with or without an internal pull-up/pull-down. Each bidirectional port pin can be configured for input or output operation. Switching between input and output mode is accomplished through the register Px_DIR (x = 0 or 1), which enables or disables the output and input drivers. A port pin can only be configured as either input or output at any one time. In input mode (default after reset), the output driver is switched off (high-impedance). The voltage level present at the port pin is translated into a logical 0 or 1 via a Schmitt trigger device and can be read via the register Px_DATA. In output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin. In the output driver, each port line can be switched to open-drain mode or normal mode (push-pull mode) via the register Px_OD. The output multiplexer in front of the output driver enables the port output function to be used for different purposes. If the pin is used for general-purpose output, the multiplexer is switched by software to the data register Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin. If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be switched via the multiplexer to the output driver circuitry. Selection of the alternate output function is defined Datasheet 45 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O in registers Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used in an alternate function, its direction must be set accordingly in the register Px_DIR. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register Px_PUDSEL selects whether a pull-up or pull-down device is activated, while register Px_PUDEN enables or disables the pull device. PUDSEL Pull-up / pull-down select register Pull-up / pull-down control logic PUDEN Pull-up / pull-down enable register TCCR Temperature compensation control register I N T E R N A L B U S Px_POCONy Port output driver control registers OD Open-drain control register DIR Direction register ALTSEL0 Alternate select register 0 ALTSEL1 Alternate select register 1 Pull device AltDataOut 3 11 AltDataOut 2 10 Output driver 01 AltDataOut 1 Out Px_DATA Data register In 00 Input driver AltDataIn Schmitt trigger Figure 16 Datasheet Pad General structure of a bidirectional port (P0, P1) 46 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O 14.2.2 Port 2 Figure 17 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated, while register P2_PUDEN enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt trigger device for direct feed-through to the ADC input channels. I N T E R N A L PUDSEL Pull-up / pull-down select register Pull-up / pull-down control logic PUDEN Pull-up / pull-down enable register DIR Direction register Pull device B U S DATA Data register Input driver In Schmitt trigger Pad AltDataIn AnalogIn Figure 17 Datasheet General structure of input port (P2) 47 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O 14.3 TLE9879QTW40 port module 14.3.1 Port 0 14.3.1.1 Port 0 functions Table 8 Port 0 input/output functions Port pin Input/output Select Connected signals From/to module P0.0 Input GPI P0_DATA.P0 – INP1 SWCLK / TCK_0 SW INP2 T12HR_0 CCU6 INP3 T4INA GPT12T4 INP4 T2_0 Timer2 INP5 – – INP6 EXINT2_3 SCU GPO P0_DATA.P0 – ALT1 T3OUT GPT12T3 ALT2 EXF21_0 Timer 21 ALT3 RXDO_2 UART2 GPI P0_DATA.P1 – INP1 T13HR_0 CCU6 INP2 TxD1 LIN_TxD INP3 CAPINA GPT12CAP INP4 T21_0 Timer21 INP5 T4INC GPT12T4 INP6 MRST_1_2 SSC1 INP7 EXINT0_2 SCU GPO P0_DATA.P1 – ALT1 TxD1 UART1 / LIN_TxD ALT2 – – ALT3 T6OUT GPT12T6 Output P0.1 Input Output Datasheet 48 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O Table 8 Port 0 input/output functions (cont’d) Port pin Input/output Select Connected signals From/to module P0.2 Input GPI P0_DATA.P2 – INP1 CCPOS2_1 CCU6 INP2 T2EUDA GPT12T2 INP3 MTSR_1 SSC1 INP4 T21EX_0 Timer21 INP5 T6INA GPT12T6 GPO P0_DATA.P2 – ALT1 COUT60_0 CCU6 ALT2 MTSR_1 SSC1 ALT3 EXF2_0 Timer2 GPI P0_DATA.P3 – INP1 SCK_1 SSC1 INP2 CAPINB GPT12 INP3 T5INA GPT12T5 INP4 T4EUDA GPT12T4 INP5 CCPOS0_1 CCU6 GPO P0_DATA.P3 – ALT1 SCK_1 SSC1 ALT2 EXF21_2 Timer21 ALT3 T6OUT GPT12T6 GPI P0_DATA.P4 – INP1 MRST_1_0 SSC1 INP2 CC60_0 CCU6 INP3 T21_2 Timer21 INP4 EXINT2_2 SCU INP5 T3EUDA GPT12T3 INP6 CCPOS1_1 CCU6 GPO P0_DATA.P4 – ALT1 MRST_1_0 SSC1 ALT2 CC60_0 CCU6 ALT3 CLKOUT_0 SCU Output P0.3 Input Output P0.4 Input Output Datasheet 49 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O 14.3.2 Port 1 14.3.2.1 Port 1 functions Table 9 Port 1 input/output functions Port pin Input/output Select Connected signals From/to module P1.0 Input GPI P1_DATA.P0 – INP1 T3INC GPT12T3 INP2 T4EUDB GPT12T4 INP3 CC61_0 CCU6 INP4 SCK_2 SSC2 INP5 EXINT1_2 SCU GPO P1_DATA.P0 – ALT1 SCK_2 SSC2 ALT2 CC61_0 CCU6 ALT3 EXF21_3 Timer21 GPI P1_DATA.P1 – INP1 – – INP2 T6EUDA GPT12T6 INP3 – – INP4 MTSR_2 SSC2 INP5 T21_1 Timer21 INP6 EXINT1_0 SCU GPO P1_DATA.P1 – ALT1 MTSR_2 SSC2 ALT2 COUT61_0 CCU6 ALT3 TXD2_0 UART2 GPI P1_DATA.P2 – INP1 T2INA GPT12T2 INP2 T2EX_1 Timer2 INP3 T21EX_3 Timer21 INP4 MRST_2_0 SSC2 INP5 RXD2_0 UART2 INP6 CCPOS2_2 CCU6 INP7 EXINT0_1 SCU GPO P1_DATA.P2 – ALT1 MRST_2_0 SSC2 ALT2 COUT63_0 CCU6 ALT3 T3OUT GPT12T3 Output P1.1 Input Output P1.2 Input Output Datasheet 50 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O Table 9 Port 1 input/output functions (cont’d) Port pin Input/output Select Connected signals From/to module P1.3 Input GPI P1_DATA.P3 – INP1 T6INB GPT12T6 INP2 – – INP3 CC62_0 CCU6 INP4 T6EUDB GPT12T6 INP5 – – INP6 CCPOS0_2 CCU6 INP7 EXINT1_1 SCU GPO P1_DATA.P3 – ALT1 EXF21_1 Timer21 ALT2 CC62_0 CCU6 ALT3 TXD2_1 UART2 GPI P1_DATA.P4 – INP1 EXINT2_1 SCU INP2 T21EX_1 Timer21 INP3 T5EUDA GPT12T5 INP4 RxD1 UART1 INP5 T2INB GPT12T2 INP6 CCPOS1_2 CCU6 INP7 MRST_1_3 SSC1 GPO P1_DATA.P4 – ALT1 CLKOUT_1 SCU ALT2 COUT62_0 CCU6 ALT3 RxD1 UART1 / LIN_RxD Output P1.4 Input Output Datasheet 51 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O 14.3.3 Port 2 14.3.3.1 Port 2 functions Table 10 Port 2 input functions Port pin Input/output Select Connected signals From/to module P2.0 Input GPI P2_DATA.P0 – INP1 CCPOS0_3 CCU6 INP2 - – INP3 T12HR_2 CCU6 INP4 EXINT0_0 SCU INP5 CC61_2 CCU6 ANALOG AN0 ADC1 XTAL (in) XTAL GPI P2_DATA.P2 – INP1 CCPOS2_3 CCU6 INP2 T13HR_2 CCU6 INP3 – – INP4 CC62_2 CCU6 ANALOG AN2 ADC1 OUT XTAL (out) XTAL GPI P2_DATA.P3 – INP1 CCPOS1_0 CCU6 INP2 CTRAP#_1 CCU6 INP3 T21EX_2 Timer21 INP4 CC60_1 CCU6 INP5 EXINT0_3 SCU ANALOG AN3 ADC1 GPI P2_DATA.P4 – INP1 CTRAP#_0 CCU6 INP2 T2EUDB GPT12T2 INP3 MRST_1_1 SSC1 INP4 EXINT1_3 SCU ANALOG AN4 ADC1 P2.2 P2.3 P2.4 Datasheet Input Input Input 52 Rev. 1.0 2020-07-23 TLE9879QTW40 GPIO ports and peripheral I/O Table 10 Port 2 input functions (cont’d) Port pin Input/output Select Connected signals From/to module P2.5 Input GPI P2_DATA.P5 – INP1 RXD2_1 UART2 INP2 T3EUDB GPT12T3 INP3 MRST_2_1 SSC2 INP4 T2_1 Timer 2 ANALOG AN5 ADC1 Datasheet 53 Rev. 1.0 2020-07-23 TLE9879QTW40 General-purpose timer units (GPT12) 15 General-purpose timer units (GPT12) 15.1 Features 15.1.1 Features of block GPT1 The following list summarizes the supported features: • fGPT is derived from PCLK • fGPT/4 maximum resolution • 3 independent timers/counters • Timers/counters can be concatenated • 4 Operating modes: – Timer mode – Gated Timer mode – Counter mode – Incremental Interface mode • Reload and capture functionality • Shared interrupt: node 0 15.1.2 Features of block GPT2 The following list summarizes the supported features: • fGPT is derived from PCLK • fGPT/2 maximum resolution • 2 independent timers/counters • Timers/counters can be concatenated • 3 Operating modes: – Timer mode – Gated Timer mode – Counter mode • Extended capture/reload functions via 16-bit capture/reload register CAPREL • Shared interrupt: node 1 Datasheet 54 Rev. 1.0 2020-07-23 TLE9879QTW40 General-purpose timer units (GPT12) 15.2 Introduction The general-purpose timer unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse-width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as Gated Timer or Counter mode, or may be concatenated with another timer of the same block. Each block has alternate input/output functions and specific interrupts associated with it. Input signals can be selected from several sources through the PISEL register. The GPT module is clocked with clock fGPT. fGPT is a clock derived from PCLK. Datasheet 55 Rev. 1.0 2020-07-23 TLE9879QTW40 General-purpose timer units (GPT12) 15.2.1 Block diagram of GPT1 The GPT1 block contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. T3CON.BPS1 fGPT 2n : 1 Basic clock U/D T2IN T2EUD T2 mode control Interrupt request (T2IRQ) Aux. timer T2 Capture Reload Toggle Latch T3IN T3 mode control U/D Core timer T3 T3EUD T3OTL T3OUT Interrupt request (T3IRQ) Capture Reload T4IN T4EUD T4 mode control U/D Figure 18 Datasheet Aux. timer T4 Interrupt request (T4IRQ) GPT1 block diagram (n = 2 … 5) 56 Rev. 1.0 2020-07-23 TLE9879QTW40 General-purpose timer units (GPT12) 15.2.2 Block diagram of GPT2 The GPT2 block contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is fGPT/2. An additional capture/reload register (CAPREL) supports capture and reload operation with extended functionality. T6CON.BPS2 2n : 1 fGPT Basic clock Toggle FF T5IN T2 mode control T5EUD U/D Interrupt request (T5IRQ) GPT2 timer T5 Clear Capture CAPIN T3IN/ T3EUD CAPREL mode control GPT2 CAPREL Interrupt request (CRIRQ) Reload Interrupt request (T6IRQ) Clear T6IN T6 mode control GPT2 timer T6 T6EUD Figure 19 Datasheet T6OTL T6OUT U/D T6OUF GPT2 block diagram (n = 1 … 4) 57 Rev. 1.0 2020-07-23 TLE9879QTW40 Timer2 and Timer21 16 Timer2 and Timer21 16.1 Features • 16-bit auto-reload mode – Selectable up- or down-counting • One-channel 16-bit capture mode 16.2 Introduction The timer modules are general-purpose 16-bit timers. Timer 2 and Timer 21 can function as timers or counters in each of their modes. As timers, they count with an input clock of fPCLK/12 (if the prescaler is disabled). As a counter, Timer2 counts 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for counting is fPCLK/24 (if the prescaler is disabled). 16.2.1 Timer2 and Timer21 mode overview Table 11 Timer2 and Timer21 modes Mode Description Auto-reload Up/down-count-disabled Datasheet • Counting up only. • Counting starts from the 16-bit reload value, overflow at FFFFH. • The reload event can be configured to be triggered only by the overflow condition or by a negative or positive edge at the input pin T2EX as well. • Programmable reload value in register RC2. • Interrupt is generated with reload events. 58 Rev. 1.0 2020-07-23 TLE9879QTW40 Timer2 and Timer21 Table 11 Timer2 and Timer21 modes (cont’d) Mode Description Auto-reload Up/down-count-enabled • Counting up or down, direction determined by level at input pin T2EX. • No interrupt is generated. • Counting up – Counting starts from the 16-bit reload value, overflow at FFFFH. – Reload event triggered by overflow condition. – Programmable reload value in register RC2. • Counting down – Counting starts from FFFFH, underflow at value defined in register RC2. – Reload event triggered by underflow condition. – Reload value fixed at FFFFH. Channel capture Datasheet • Counting up only. • Counting starts from 0000H, overflow at FFFFH. • Reload event triggered by overflow condition. • Reload value fixed at 0000H. • Capture event triggered by falling/rising edge at pin T2EX. • Captured timer value stored in register RC2. • Reload or capture events generate interrupts. 59 Rev. 1.0 2020-07-23 TLE9879QTW40 Timer3 17 Timer3 17.1 Features • 16-bit incremental timer/counter (counting up) • Counting frequency up to fsys • Selectable clock prescaler • Six operating modes • Interrupt on overflow • Interrupt on compare 17.2 Introduction The possible applications for this timer include measuring the time interval between events, counting events, and generating a signal at regular intervals. Timer3 can function as a timer or a counter. When functioning as a timer, Timer3 is incremented in periods based on the MI_CLK or LP_CLK clocks. When functioning as a counter, Timer3 is incremented in response to a 1-to-0 transition (falling edge) at its configured input. Timer3 can be configured in four different operating modes for a variety of applications (see Table 12). The different operating modes allow the timer to be used for tasks such as: • Simple measurements of the times between two events. • Triggering the measuring unit upon PWM/CCU6 unit • Measurement of the 100 kHz LP_CLK2 17.3 Functional description Six modes of operation are provided to enable using this timer for various tasks. In every mode, the clocking source can be selected from MI_CLK and LP_CLK. In addition, a prescaler provides the capability to divide the selected clock source by 2, 4, or 8. The timer counts upwards, starting with the value in the timer count registers, up to the maximum count value, which depends on the selected mode of operation. Timer 3 provides two individual interrupts on counter overflow, one for the low-byte and one for the high-byte counter register. 17.3.1 Timer3 modes overview The following table provides an overview of the timer modes together with the reasonable configuration options in Table 12. Table 12 Timer3 modes Mode Submode Operation 0 No 13-bit timer submode The timer essentially operates an 8-bit counter with a divide-by-32 prescaler. 1 a Datasheet 16-bit timer The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter. 60 Rev. 1.0 2020-07-23 TLE9879QTW40 Timer3 Table 12 Timer3 modes (cont’d) Mode Submode Operation 1 b 2 No 8-bit timer with auto-reload submode The timer register TL3 is reloaded with a user-defined 8-bit value in TH3 on overflow. 3 a Timer3 operating as two 8-bit timers The timer registers TL3 and TH3, operate as two separate 8-bit counters. 3 b Timer3 operating as two 8-bit timers for clock measurement The timer registers, TL3 and TH3, operate as two separate 8-bit counters. In this mode, the LP_CLK2 low power clock can be measured. TL3 acts as an edge counter for the clock edges and TH3 measures the interval between the edges. Datasheet 16-bit timer triggered by an event The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter, which is triggered by an event to enable a single-shot measurement on a preset channel with the measurement unit. 61 Rev. 1.0 2020-07-23 TLE9879QTW40 Capture/compare unit 6 (CCU6) 18 Capture/compare unit 6 (CCU6) 18.1 Feature set overview This section gives an overview over the different building blocks and their main features. Timer 12 block features • Three capture/compare channels. Each channel can be used either as capture or as compare channel. • Supports three-phase PWM (six outputs with separate signals for high-side and low-side switches). • 16-bit resolution, maximum count frequency = peripheral clock. • Dead-time control for each channel to avoid short-circuits in the power stage. • Concurrent update of the T12 registers. • Center-aligned and edge-aligned PWM can be generated. • Single-shot mode is supported. • Start can be controlled by external events. • External events can be counted. • Multiple interrupt request sources. • Hysteresis-like control mode. Timer 13 block features • One independent compare channel with one output. • 16-bit resolution, maximum count frequency = peripheral clock. • Concurrent update of T13 registers. • Can be synchronized to T12. • Interrupt generation at period-match and compare-match. • Single-shot mode is supported. • Start can be controlled by external events. • Capability of counting external events. Additional specific functions • Block commutation for brushless DC-drives implemented. • Position detection via hall-sensor pattern. • Noise filter for position input signals supported. • Automatic rotational speed measurement and commutation control for block commutation. • Integrated error handling. • Fast emergency stop without CPU load via external signal (CTRAP). • Control modes for multi-channel AC drives. • Output levels can be selected and adapted to the power stage. Datasheet 62 Rev. 1.0 2020-07-23 TLE9879QTW40 Capture/compare unit 6 (CCU6) 18.2 Introduction The CCU6 unit is made up of the T12 timer block with three capture/compare channels and the T13 timer block with one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or they can jointly generate control signal patterns to drive DC motors or inverters. A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation of interrupt request signals provide efficient software control. Note: The capture/compare module itself is referred to as CCU6 (capture/compare unit 6). A capture/compare channel inside this module is referred to as CC6x. The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined (e.g., a channel works in compare mode, whereas another channel works in capture mode). The timer T13 can work only in compare mode. The multi-channel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for modulating signals. Datasheet 63 Rev. 1.0 2020-07-23 TLE9879QTW40 Capture/compare unit 6 (CCU6) 18.2.1 Block diagram CCU6 Module Kernel CC60 T12SUSP T13SUSP T12 1 CC61 1 CC62 1 Deadtime control Multichannel control Trap control 3 SR[3:0] 2 2 2 Trap Input Hall input Output select Compare Compare Capture 1 3 1 CTRAP CCPOS2 CCPOS1 CCPOS0 COUT63 CC62 COUT62 COUT61 CC60 COUT60 T13HR Input/output control T12HR Interrupt control Compare CC63 Compare T13 CC61 fCC6 Clock control Output select Start Debug suspend Compare Port control P0.x Figure 20 Datasheet P1.x P2.x CCU6 block diagram 64 Rev. 1.0 2020-07-23 TLE9879QTW40 UART1/UART2 19 UART1/UART2 The description in this chapter applies to both UART1 and UART2. 19.1 • Features Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first. – Fixed or variable baud rate. • Receive-buffered. • Multiprocessor communication. • Interrupt are generated when data transmission or receptions are complete. • Baud-rate generator with fractional divider for generating a wide range of baud rates. • Hardware logic for break and synch byte detection. 19.2 Introduction The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time when the reception of the second byte is complete, one of the bytes will be lost. The serial port receive and transmit registers are both accessed through the special function register (SFR) SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. 19.2.1 Block diagram UART disreq from SCU_DM RI TXD TI RXD TXD SCU_DM Interrupt control URIOS SCU_DM UART module fUART2 Clock control P0.x f Baud rate generator BR P1.x P2.x RXDO_2 AHB interface Datasheet RXD_1 Port control Address decoder Figure 21 RXD_0 SCU_DM UART GPIOs UART block diagram 65 Rev. 1.0 2020-07-23 TLE9879QTW40 UART1/UART2 19.3 UART modes The UART can be used in four different modes. In mode 0, it operates as an 8-bit shift register. In mode 1, it operates as an 8-bit serial port. In modes 2 and 3, it operates as a 9-bit serial port. The only difference between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. The different modes are selected by setting bits SM0 and SM1 to the appropriate values, as shown in Table 13. Table 13 UART modes SM0 SM1 Operating mode Baud rate 0 0 Mode 0: 8-bit shift register fPCLK/2 0 1 Mode 1: 8-bit shift UART Variable 1 0 Mode 2: 9-bit shift UART fPCLK/64 1 1 Mode 3: 9-bit shift UART Variable UART1 is connected to the integrated LIN transceiver, and to GPIO for test purposes. UART2 is connected to GPIO only. Datasheet 66 Rev. 1.0 2020-07-23 TLE9879QTW40 LIN transceiver 20 LIN transceiver 20.1 Features General functional features • Compliant with the LIN2.2 standard, backward-compatible with LIN1.3, LIN2.0, and LIN 2.1 • Compliant with SAE J2602 (slew rate, receiver hysteresis) Special features • Measurement of the LIN master baudrate via Timer2 • LIN can be used as input/output with SFR bits • TxD timeout feature (optional, on by default) Operation mode features • LIN Sleep mode (LSLM) • LIN Receive-Only mode (LROM) • LIN Normal mode (LNM) • High voltage input/output mode (LHVIO) Supported baud rates • Mode for transmission with up to 10.4 kilobaud • Mode for transmission with up to 20 kilobaud • Mode for transmission with up to 40 kilobaud • Mode for transmission with up to 115.2 kilobaud Slope mode features • Normal Slope mode (20 kbit/s) • Low Slope mode (10.4 kbit/s) • Flash mode (115.2 kbit/s) Wake-up features • LIN bus wake-up 20.2 Introduction The LIN module is a transceiver for the Local Interconnect Network (LIN), compliant with the LIN2.2 standard and backward-compatible with LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller and the physical network. The LIN bus is a single-wire, bidirectional bus typically used for in-vehicle networks, using baud rates between 2.4 kilobaud and 20 kilobaud. Additionally, baud rates up to 115.2 kilobaud are implemented. The LIN module offers several different operation modes, including a LIN Sleep mode and the LIN Normal mode. The integrated slope control allows using several data transmission rates with optimized EMC performance. For data transfer at the end of line, a Flash mode up to 115.2 kilobaud is implemented. In Datasheet 67 Rev. 1.0 2020-07-23 TLE9879QTW40 LIN transceiver specific conditions, this Flash mode supports data rates of up to 250 kbit/s. (In production environments, in point-to-point communications with reduced wire lengths and limited supply voltages.). 20.2.1 Block diagram VS LIN transceiver RBUS LIN.CTRL_STS LIN CTRL Driver, current limiter, and TSD TxD_1 from UART LIN-FSM STATUS Transmitter CTRL STATUS GND_LIN Filter RxD_1 to UART and TIMER2, pin T2EX (T2EXCON=0, T2EXIS=0) Receiver Filter LIN_Wake Sleep comparator GND_LIN Figure 22 Datasheet LIN transceiver block diagram 68 Rev. 1.0 2020-07-23 TLE9879QTW40 High-speed synchronous serial interface (SSC1/SSC2) 21 High-speed synchronous serial interface (SSC1/SSC2) 21.1 Features • Master and Slave mode operation – Full-duplex or half-duplex operation • Transmit- and receive-buffered • Flexible data format – Programmable number of data bits: 2 to 16 bits – Programmable shift direction: least significant bit (LSB) or most significant bit (MSB) shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock • Variable baud rate • Compatible with Serial Peripheral Interface (SPI) • Interrupt generation – On a “transmitter empty” condition – On a “receiver full” condition – On an error condition (receive, phase, baud rate, or transmission error) Datasheet 69 Rev. 1.0 2020-07-23 TLE9879QTW40 High-speed synchronous serial interface (SSC1/SSC2) 21.2 Introduction The high-speed synchronous serial interface (SSC) supports both full-duplex and half-duplex serial synchronous communication. The serial clock signal can be generated by the SSC internally (Master mode), using its own 16-bit baud rate generator, or can be received from an external master (Slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices as well as devices using other synchronous serial interfaces. Data is transmitted or received on the TXD and RXD lines, which are normally connected to the MTSR (Master Transmit, Slave Receive) and MRST (Master Receive, Slave Transmit) pins. The clock signal is output via the MS_CLK (Master Serial Shift Clock) line or input via the SS_CLK (Slave Serial Shift Clock) line. Both lines are normally connected to the SCLK pin. Transmission and reception of data are double-buffered. 21.2.1 Block diagram Figure 23 shows all functionally relevant interfaces associated with the SSC kernel. MRSTA TIR MTSRA SSC module AHB interface Datasheet MRST P0.x Port control fhw_clk P1.x P2.x SCLKA SCLKB SCLK Ma st er Address decoder Figure 23 MTSRB Slave Clock control MTSR RIR Slave SCU_DM interrupt control MRSTB Ma st er EIR Module Product interface SSC interface diagram 70 Rev. 1.0 2020-07-23 TLE9879QTW40 Measurement unit 22 Measurement unit 22.1 Features • 1 x 8-bit ADC with 10 inputs. Attenuators allow measuring high-voltage input signals. • Supply voltage attenuators for attenuating VS, VDDP and VDDC. • VBG monitoring of the 8-bit ADC to guarantee functional safety requirements. • Bridge driver diagnosis measurement (VDH, VCP). • Temperature sensor for monitoring the chip temperature and PMU regulator temperature. • BEMF comparators for triggering commutation in BLDC applications. • Supplement block with reference voltage generation, bias current generation, voltage buffer for NVM reference voltage, voltage buffer for analog module reference voltage, and a test interface. 22.2 Introduction The measurement unit is a functional unit that comprises the following submodules: Table 14 Measurement functions and associated modules Module name Module Functions Central function unit Bandgap reference circuit The bandgap reference submodule provides two reference voltages: 1. A trimmable reference voltage for the 8-bit ADC. A local dedicated bandgap circuit ensures that the reference voltage does not drop, e.g., because of crosstalk or ground voltage shift. 2. The reference voltage for the NVM module. 8-bit ADC (ADC2) 8-bit ADC module with 10 multiplexed inputs and including high-voltage input attenuators • 5 high-voltage inputs supporting the full supply range (2.5 V...30.7 V(FS)) • 2 medium-voltage inputs (0..5 V/7 V FS). • 3 low-voltage inputs (0..1.2 V/1.6 V FS) (See the following figure for the allocation of the inputs). 10-bit ADC (ADC1) 10-bit ADC module with 8 multiplexed inputs Five (5 V) analog inputs from port 2.x. VDH input voltage attenuator VDH input voltage attenuator Scales down (VDH) to the input voltage range of ADC1.CH6. Temperature sensor Temperature sensor with two multiplexed sensing elements: Generates an output voltage that is a linear function of the local chip (junction) temperature. Datasheet • Sensor located on the PMU • Sensor located on the central chip 71 Rev. 1.0 2020-07-23 TLE9879QTW40 Measurement unit Table 14 Measurement functions and associated modules (cont’d) Module name Module Functions BEMF comparators Back electromotive force comparators Comparators are used to detect the back electromotive force (zero-crossing event), which can be used as a commutation trigger for BLDC applications. Core measurement module Digital signal processing and ADC2 1. Generates the control signal for the 8-bit ADC2 and the synchronous clock for the switched control unit capacitor circuits. 2. Performs digital signal processing functions and provides status outputs for interrupt generation. 22.2.1 Block diagram VS GND_REF VAREF P2.0 CH0 VARE F OP1 GND_SENSE CH1 CSA OP2 CH2 P2.2 CH3 P2.3 CH4 P2.4 CH5 VREF MUX P2.5 A VDH rfu 10 / Channel sequencer SFR ADC 1 CH6 ATTVDH_1 ATTVDH_2 ATTVDH_3 D CH7 10 Bit ADC + DPP1 Programmable range setting rfu CH0 ATTVS_1 ATTVS_2 CH1 ATTVSD CH2 VCP ATTVCP CH3 MON ATTMON CH4 VSD VBG MUX VDDP VAREF PMU-VBG VDDC Temperature sensor ATTVDD P CH5 ATTVARE F CH6 ATTVBG CH7 ATTVDD C CH8 A D 8 / Calibra tion a nd filter unit with upper and lower threshold detection and interrupt SFR ADC 2 CH9 8 Bit ADC + DPP2 Measurement unit Figure 24 Datasheet Measurement unit, overview (with opamp) 72 Rev. 1.0 2020-07-23 TLE9879QTW40 Measurement unit 22.2.1.1 BEMF comparator block diagram V phase U W V U VS/2 SH3 R SH2 R BEMF comparator Blank filter Spike filter R SH1 BEMF IN BEMF OUT R t Measurement unit, BEMF comparators Figure 25 Datasheet BEMF comparator (applies to each of the three comparators) 73 Rev. 1.0 2020-07-23 TLE9879QTW40 Core measurement module (incl. ADC2) 23 Core measurement module (incl. ADC2) 23.1 Features • 10 individually programmable channels, split into two groups of user-configurable and non-configurable channels, respectively. • Individually programmable channel prioritization scheme for the measurement unit. • Two independent filter stages with programmable low-pass and time filter characteristics for each channel. • Two channel configurations: – Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis. – Two individually programmable trigger thresholds with limit hysteresis settings. • Individually programmable interrupts and statuses for all channel thresholds. 23.2 Introduction The basic function of this block is the digital postprocessing of several digitized analog measurement signals by filtering, level comparison, and interrupt generation. The measurement postprocessing block consists of ten identical channel units attached to the outputs of the 10-channel 8-bit ADC (ADC2). It processes ten channels, where the channel sequence and prioritization is programmable within a wide range. 23.2.1 Block diagram 4 / Core measurement module MUX_SEL Channel controller (sequencer) SQ0 – SQ9 FILT_OUTx.OUT_CHx TSENS_SEL CNTUP + 1 / MMODE THy_z_LOWER. CHx - CNTLOW THy_z_UPPER. CHx HYSUP CH8 + 8 / HYSLOW VDDC Temperature sensor y= a + (1+b)*x 10 / FILTENLOW CH7 D FILTENUP PMU-VBG A 8 / Calibration unit: FILTENLOW CH6 EN CH5 MUX_CTRL VDDP VAREF First-order IIR 8-bit ADC VREF MUX MUX_CTRL CH4 EN MON COEFF_IIR CH3 COEFF_B CH2 VCP MUX_CTRL CH1 VSD EN CH0 CTRL_STS rfu VS COEFF A SOC EOC ADC2 - SFR +/- ADC2_CHx_UPPER_STS +/- ADC2_CHx_LOWER_STS 1 / Digital signal processing CH9 TSENSE Figure 26 Datasheet Module block diagram 74 Rev. 1.0 2020-07-23 TLE9879QTW40 Core measurement module (incl. ADC2) 23.2.2 Core measurement module mode overview The basic function of this unit is the digital signal processing of several digitized analog measurement signals by filtering, level comparison, and interrupt generation. The core measurement module processes ten channels in a quasi-parallel process. As shown in the figure above, the ADC2 postprocessing unit consists of a channel controller (sequencer), a 10channel demultiplexer, and the signal-processing block, which filters and compares the sampled ADC2 values for each channel individually. The channel control block controls the multiplexer sequencing on the analog side, before the ADC2, and in the digital domain, behind the ADC2. The channel sequence can be controlled in a flexible way, which allows a certain degree of channel prioritization. This capability can be used, e.g., to give supply voltage channels a higher priority than the other channel measurements. In addition, the core measurement module offers two different postprocessing measurement modes for over- and undervoltage detection and for two-level threshold detection. The channel controller (sequencer) runs in one of the following modes: • Normal Sequencer: Channels are selected according to the 10 sequence registers which contain individual enablers for each of the 10 channels. • Exceptional Interrupt Measurement: Following a hardware event, a high-priority channel is inserted into the current sequence. The current actual measurement is not destroyed. • Exceptional Sequence Measurement: Following a hardware event, a complete sequence is inserted after the current measurement is finished. The current sequence is interrupted by the exception sequence. Datasheet 75 Rev. 1.0 2020-07-23 TLE9879QTW40 10-bit analog-to-digital converter (ADC1) 24 10-bit analog-to-digital converter (ADC1) 24.1 Features The principal features of the ADC1 are: • Up to 8 analog input channels (channel 7 reserved for future use). • Flexible results handling – 8-bit and 10-bit resolution. • Flexible source selection due to sequencer: – Insert one exceptional sequence (ESM). – Insert one interrupt measurement into the current sequence (EIM), single or up to 128 times. – Software mode. • Conversion sample time (separate for each channel) adjustable to adapt to sensors and reference. • Standard external reference (VAREF) to support ratiometric measurements and different signal scales. • DMA support, transfer ADC conversion results via DMA into RAM. • Support of suspended and power-saving modes. • Result data protection for slow CPU access (Wait-for-Read mode). • Programmable clock divider. • Integrated sample and hold circuitry. 24.2 Introduction The TLE9879QTW40 includes a high-performance 10-bit analog-to-digital converter (ADC1) with eight multiplexed analog input channels. The ADC1 uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC1 are available at AN0 and AN2 to AN5. Datasheet 76 Rev. 1.0 2020-07-23 TLE9879QTW40 10-bit analog-to-digital converter (ADC1) 24.2.1 Block diagram 3 / 3 / MUX_SEL EoC - SoC Channel controller (sequencer) Settings ADC1 - SFR 10 P2.0 CH0 10 CH1 P2.2 P2.3 P2.4 CH4 P2.5 CH5 VDH rfu OP1 OP2 Figure 27 ADC1 CH2 CH3 10 MUX A 10 10 D / MUX 10 10 10 CH6 10 CH7 10 / ADC1_OUT_CH0 / ADC1_OUT_CH1 / ADC1_OUT_CH2 / ADC1_OUT_CH3 / ADC1_OUT_CH4 / ADC1_OUT_CH5 / ADC1_OUT_CH6 / ADC1_OUT_CH7 / ADC1_RES_OUT_EIM OPA ADC1 top-level block diagram As shown in the figure above, the ADC1 postprocessing block consists of a channel controller (Sequencer) and an 8-channel demultiplexer. The channel control block controls the multiplexer sequencing on the analog side, before the ADC1, and in the digital domain, behind the ADC1. The channel sequence can be controlled in a flexible way, which allows a certain degree of channel prioritization. This capability can be used, e.g., to give supply voltage channels a higher priority than the other channel measurements. Datasheet 77 Rev. 1.0 2020-07-23 TLE9879QTW40 High-voltage monitor input 25 High-voltage monitor input 25.1 Features • High-voltage input with VMONth threshold voltage • Integrated selectable pull-up and pull-down current sources • Wake capability for power-saving modes • Level change sensitivity configurable for transitions from low to high, high to low, or both directions 25.2 Introduction This module is dedicated to monitor external voltage levels above or below a specified threshold or it can be used to detect a wake-up event at the high-voltage MON pin in low-power mode. The input level can be monitored if the module is enabled (PMU_MON_CNF). To use the Wake function when the IC is in a low-power mode, the monitoring pin is switched to Sleep mode via the SFR bit EN. 25.2.1 Block diagram VS MON + Filter - to internal circuitry MON Logic SFR Figure 28 Datasheet High-voltage monitor input block diagram 78 Rev. 1.0 2020-07-23 TLE9879QTW40 Bridge driver (incl. charge pump) 26 Bridge driver (incl. charge pump) 26.1 Features The MOSFET driver is intended to drive external normal-level NFET transistors in bridge configurations. The driver provides many diagnostic functions for detecting faults. Functional features • External power NFET transistor driver stage with driver capability of Qtot_max. • Adjustable cross-conduction protection. • Supply voltage (VSD) monitoring incl. adjustable over- and undervoltage shutdown with configurable interrupt signalling. • VSD operating range: VSD_AM. • VDS comparators for short-circuit-detection in both on- and off-states. • Open-load detection in the off-state. • Flexible PWM frequency range. Rates above 25 kHz require power dissipation and duty-cycle resolution analysis. 26.2 Introduction The MOSFET driver stage can be used for controlling external power NFET transistors (normal level). The module output is controlled by the SFR or the System PWM Machine (CCU6). Datasheet 79 Rev. 1.0 2020-07-23 TLE9879QTW40 Bridge driver (incl. charge pump) 26.2.1 Block diagram VDH VCP PWM unit CCU6 (not part of the module) Predriver BDRV.TRIM_DRVx. LSDRV_DS_TFILT_SEL BDRV.TRIM_DRVx. LS_HS_BT_TFILT_SEL Spike filter Blank filter BDRV.CTRL3. DSMONVTH + VDS - High-side driver 1) 1 GHx 0 VREF RGG ND BDRV.CTRL1.HSx_PW M SFR SHx 1 IPDDiag 0 BDRV.CTRL1.LSx_PW M Spike filter Blank filter Low-side driver 1) + VDS GLx - BDRV.TRIM_DRVx. LSDRV_DS_TFILT_SEL 1) BDRV.TRIM_DRVx. LS_HS_BT_TFILT_SEL BDRV.CTRL3. DSMONVTH RGG ND VREF SL The VGSx limiter and fast discharge functions are implemented in this block. Figure 29 26.2.2 Bridge driver module block diagram (incl. system connections) General The bridge driver can be controlled in two different ways: • In Normal mode, the output stage is fully controllable through the SFR registers CTRLx (x = 1,2,3). Protection functions such as overcurrent and open-load detection are available. • The PWM mode can be enabled by setting the corresponding bit in CTRL1 and CTRL2. The PWM must be configured in the System PWM Module (CCU6). All protection functions are available in PWM mode as well. Protection functions • Overcurrent detection and shutdown feature for external MOSFET based on drain-source measurements. • Programmable minimum cross-current protection time. • Open-load detection feature in the off-state for external MOSFET. Datasheet 80 Rev. 1.0 2020-07-23 TLE9879QTW40 Current sense amplifier 27 Current sense amplifier 27.1 Features Main features • Programmable gain settings: G • Differential input voltage: VIX • Wide common-mode input range: VCM • Low setting time: TSET 27.2 Introduction The current sense amplifier in the following figure can be used to measure near-ground differential voltages via the 10-bit ADC. Its gain is digitally programmable through internal control registers. Linear calibration has to be applied to achieve high gain accuracy, e.g., end-of-line calibration using the shunt resistor. The following figure shows how the current sense amplifier can be used as a low-side current sense amplifier where the motor current is converted to a voltage by means of a shunt resistor RSH. A differential amplifier input is used to eliminate measurement errors caused by a voltage drop across the stray resistance RStray and differences between the external and internal grounds. If the voltage at one or both inputs is outside the operating range, the input circuit is overloaded and requires a certain specified recovery time. In general, an external low-pass filter should suppress of EMI. Datasheet 81 Rev. 1.0 2020-07-23 TLE9879QTW40 Current sense amplifier 27.2.1 Block diagram VDH VAREF or VREF5V VZERO MOSFET bridge CSAÆ CTRL.VZERO Low-pass filter ROPAFILT RSH OP2 Rin_OP2 Input offset G = 10/20/40/60 + COPAFILT ROPAFILT OP1 G - Rin_OP1 + Vzero + (VOP2 -VOP1)*G 10-bit ADC CSA_CTRL RStray AHB CSA GND Figure 30 Datasheet Current sense amplifier block diagram 82 Rev. 1.0 2020-07-23 TLE9879QTW40 Application information 28 Application information 28.1 BLDC driver The following figure shows the TLE9879QTW40 in an electric drive application setup controlling a BLDC motor. Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition, or quality of the device. Rev. polarity protection LPF ILT VBAT CPF ILT1 CPF ILT1 CVDDP2 EMC filter CVD DP1 DVS VS CVS 2 CVDDC1 VDDP VDDC CVS1 RMON IGN CMON MON CVDDC2 CP1H CP1L CP2H CP2L VCP CCPS1 CCPS2 RVS D VSD CVS D LIN LIN CLIN CVDH GND_LIN GND_REF D RGA TE G GH1 VAREF CVA REF CVC P RVDH VDH TH1 RGS 1) CGS SH1 CPH 1 D S G CEM CP1 RVDDPU TLE4946-2K Hall CADC CVDD_EX T2 CVDD_EX T1 GH2 D S G RGA TE GH3 SH3 P1.4 TH3 RGS CGS S D P0.2 RADC CADC TLE987x G GL1 TL1 RGS RGA TE CGS M D S G GL2 Temperature sensor TL2 P2.2 RGS CGS D S RGA TE G GL3 TL3 P1.2 RGS SL OP2 OP1 ROP AFI LT RGA TE RShunt P2.0 P2.3 P2.4 RESET TMS P0.0 RTM S 1) Input protection circuit Input protection circuit Input protection circuit P0.1 P0.4 P2.5 P1.3 GND BLDC system RGA TE ROP AFI LT P1.1 Debug connector CGS S COP AFI LT P1.0 CPH 3 U V W CEM CP3 RVDDPU RGA TE TLE4946-2K Hall CPH 2 CGS CEM CP2 RVDDPU RADC TH2 RGS SH2 P0.3 RADC TLE4946-2K Hall CADC VDDEXT RGA TE GND Note: Not connected to board GND. Figure 31 Note: Datasheet Simplified sample application diagram This is a very simplified example of an application circuit and bill of materials. The function must be verified in the actual application. 83 Rev. 1.0 2020-07-23 TLE9879QTW40 Application information Table 15 External components (BOM) Symbol Function Component CVS1 Blocking capacitor at VS pin ≥ 100 nF ceramic, ESR < 1 Ω CVS2 Blocking capacitor at VS pin > 2.2 µF Elco1) CVDDP Blocking capacitor at VDDP pin See P_2.1.2 and P_2.1.20 CVDD_EXT Blocking capacitor at VDDEXT pin See P_2.3.22 and P_2.3.20 CVDDC Blocking capacitor at VDDC pin See P_2.2.1 and P_2.2.17 CVAREF Blocking capacitor at VAREF pin See P_9.1.1 CLIN Standard C for LIN slave 220 pF CVSD Filter C for charge pump end driver 1 µF CCPS1 Charge pump capacitor 220 nF CCP2S Charge pump capacitor 220 nF CVCP Charge pump capacitor 470 nF CMON Filter C for ISO pulses 10 nF CVDH Capacitor 3.3 nF CPH1 Capacitor 220 µF CPH2 Capacitor 220 µF CPH3 Capacitor 220 µF COPAFILT Capacitor 1 nF CEMCP1 Capacitor 1 nF CEMCP2 Capacitor 1 nF CEMCP3 Capacitor 1 nF CPFILT1, CPFILT2 Capacitor RMON Resistor at MON pin RVSD 2Ω Limitation of reverse current due to transient (-2 V, 8 ms). Max. ratings of the VSD pin has to be met, alternatively the resistor shall be replaced by a diode RVDH Resistor 1 kΩ RGATE Resistor 2Ω ROPAFILT Resistor 12 Ω RSH1 Resistor Optional RSH2 Resistor Optional RSH3 Resistor Optional 3.9 kΩ – LPFILT DVS Reverse-polarity protection diode – 1) The capacitor must be dimensioned so as to ensure that operations which modify the content of the flash are never interrupted (e.g., in case of power loss). Datasheet 84 Rev. 1.0 2020-07-23 TLE9879QTW40 Application information 28.2 ESD immunity according to IEC61000-4-2 Note: Tests for ESD immunity according to IEC61000-4-2 “gun test” (150 pF, 330 Ω) have been performed. The results and test conditions will be available in a test report. Table 16 ESD “gun test” Performed test ESD at pin LIN, versus GND1) 1) ESD at pin LIN, versus GND Result Unit Remarks >6 kV Positive pulse < -6 kV Negative pulse 1) ESD test “ESD GUN” is specified with external components; see application diagram: CMON = 100 nF, RMON = 1 kΩ, CLIN = 220 pF, CVS = > 20 µF ELCO + 100 nF ESR < 1 Ω, CVSD = 1 µF, RVSD = 2 Ω. Datasheet 85 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29 Electrical characteristics This chapter includes all relevant electrical characteristics of the product TLE9879QTW40. 29.1 General characteristics 29.1.1 Absolute maximum ratings Table 17 Absolute maximum ratings1) Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Number Voltages – supply pins Supply voltage VS VS -0.3 – 40 V Load dump P_1.1.1 Supply voltage VSD VSD -0.3 – 48 V – P_1.1.2 Supply voltage VSD VSD_max_extend -2.8 – 48 V Series resistor RVSD = 2.2 Ω, t = 8 ms 2) P_1.1.32 Voltage range VDDP VDDP -0.3 – 5.5 V – P_1.1.3 Voltage range VDDP VDDP_max_extend -0.3 – 7 V P_1.1.41 In case of voltage transients on VS with ∆VS/∆t ≥ 1 V/µs; duration: t ≤ 150 µs; CVDDP ≤ 570 nF Voltage range VDDEXT VDDEXT -0.3 – 5.5 V – Voltage range VDDEXT VDDEXT_max_extend -0.3 – 7 V P_1.1.42 In case of voltage transients on VS with ∆VS/∆t ≥ 1 V/µs; duration: t ≤ 150 µs; CVDDEXT ≤ 570 nF Voltage range VDDC VDDC -0.3 – 1.6 V – P_1.1.5 Input voltage at LIN VLIN -28 – 40 V – P_1.1.7 Input voltage at MON VMON_maxrate -28 – 40 V 3) P_1.1.8 V 4) P_1.1.38 P_1.1.9 P_1.1.4 Voltages – high-voltage pins Input voltage at VDH VVDH_maxrate -2.8 – 40 Voltage range at GHx VGH -8.0 – 48 V 5) Voltage range at GHx vs. SHx VGHvsSH -0.3 – 14 V – P_1.1.44 Voltage range at SHx VSH -8.0 – 48 V – P_1.1.11 Voltage range at SLx VSL -8.0 – 48 V – P_1.1.48 P_1.1.13 P_1.1.45 Voltage range at GLx VGL -8.0 – 48 V 6) Voltage range at GLx vs. SL VGLvsSL -0.3 – 14 V – Datasheet 86 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 17 Absolute maximum ratings1) (cont’d) Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Min. Typ. Unit Note or Test Condition Max. VCPx -0.3 – 48 V 7) Vin -0.3 – VDDP + 0.3 V 9) IVCP -15 – – mA – P_1.1.35 Injection current on any port pin IGPIONM -5 – 5 mA 10) P_1.1.34 Sum of all injected currents in Normal mode IGPIOAM_sum -50 – 50 mA 10) P_1.1.30 Sum of all injected currents in IGPIOPD_sum Power-down mode (Stop mode) -5000 – 50 µA 10) P_1.1.36 Sum of all injected currents in Sleep mode IGPIOSleep_sum -5 – 5 mA 10) P_1.1.37 Input voltage VAREF VAREF -0.3 – VDDP + 0.3 V – P_1.1.17 Input voltage OP1, OP2 VOAI -7 – 7 V – P_1.1.23 Junction temperature Tj -40 – 175 °C – P_1.1.18 Storage temperature Tstg -55 – 150 °C – P_1.1.19 ESD susceptibility all pins VESD1 -2 – 2 kV HBM 11) P_1.1.20 ESD susceptibility pins MON, VS, VSD vs.GND VESD2 -4 – 4 kV HBM 12) P_1.1.21 ESD susceptibility pins LIN vs. GND_LIN VESD3 -6 – 6 kV HBM 11) P_1.1.22 ESD susceptibility CDM all pins vs. GND VESD_CDM1 -500 – 500 V 13) P_1.1.28 ESD susceptibility CDM pins 1, 12, 13, 24, 25, 36, 37, 48 (corner pins) vs. GND VESD_CDM2 -750 – 750 V 13) P_1.1.43 Voltage range at charge pump pins CP1H, CP1L, CP2H, CP2L, VCP Symbol Values Number P_1.1.15 Voltages – GPIOs Voltage on any port pin8) VIN < VDDPmax P_1.1.16 Current at VCP pin Max. current at VCP pin Injection current at GPIOs Other voltages Temperatures ESD susceptibility 1) Not subject to production test, specified by design. Datasheet 87 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 2) 3) 4) 5) Conditions and minimum values are derived from application conditions for reverse polarity events. The minimum voltage of -28 V applies only with an external 3.9 kΩ series resistor. The minimum voltage of -2.8 V applies only with an external 1 kΩ series resistor. To achieve the maximum ratings on this pin, the following relationships with parameter P_1.1.44 have to be observed: VGH < VSH + VGHvsSH_min and VSH < VGH + 0.3 V. 6) To achieve the maximum ratings on this pin, the following relationships with parameter P_1.1.45 have to be observed: VGL < VSL + VGLvsSL_min and VSL < VGL + 0.3 V. 7) These limits can be kept if the maximum current drawn out of the pin does not exceed the limit of 200 µA. 8) See the XTAL parameter specification, when GPIOs (Port pins P2.0 and P2.2) are used as XTAL. 9) Includes TMS and RESET. 10) P_1.1.16 must not been exceeded in the injection current. 11) ESD susceptibility based on the HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF). 12) MON with external circuitry of a series resistor with 3.9 kΩ and 10 nF (at connector); VS with an external ceramic capacitor with 100 nF; VSD with an external capacitor with 470 nF; VDH with external circuitry of a series resistor with 1 kΩ and 3.3 nF (at pin). 13) ESD susceptibility based on the HBM according to ANSI/ESDA/JEDEC JESD22-C101F. Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect the reliability of the device. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered to be outside the normal operating range. Protection functions are not designed for continuous repetitive operation. Datasheet 88 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.1.2 Functional range Table 18 Functional range Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Supply voltage in Active mode Symbol VS_AM Values Number Min. Typ. Max. Unit Note or Test Condition 5.5 V – P_1.2.1 1)2) – 28 Extended supply voltage in Active mode VS_AM_extend 28 – 40 V Extended supply P_1.2.16 range leads to parameter deviation. Supply voltage in Active mode for MOSFET driver supply VSD_AM 5.4 – 28 V – Extended supply voltage in Active mode for MOSFET driver supply VSD_AM_extend 28 – 32 V 1)2)5) Specified supply voltage for LIN transceiver VS_AM_LIN 5.5 – 18 V Parameter specification. Extended supply voltage for LIN transceiver VS_AM_LIN 4.8 – 28 V 3) Supply voltage in Active mode with VS_AMmin reduced functionality (retaining full operation for microcontroller and flash) 3.0 – 5.5 V 4) P_1.2.3 Supply voltage in Sleep mode 3.0 – 28 V – P_1.2.4 P_1.2.5 VS_Sleep P_1.2.18 Extended supply P_1.2.17 range leads to parameter deviation. P_1.2.2 Extended supply P_1.2.14 range leads to parameter deviation. Supply voltage transients slew rate ∆VS/∆t -1 – 1 V/µs 5) Output sum current for all GPIO pins IGPIO,sum -50 – 50 mA 5) P_1.2.7 6) P_1.2.15 Operating frequency fsys 5 – 40 MHz Junction temperature range 1 Tj_extend_1 -40 – 150 °C – P_1.2.22 Junction temperature range 2 Tj_extend_2 -40 – 165 °C 5) Incl. flash read/write/erase P_1.2.23 Junction temperature range 3 Tj_extend_3 165 – 175 °C 5) P_1.2.24 Incl. flash read 1) This operation voltage range is only allowed for a short duration: tmax ≤ 400 ms (continuous operation at this voltage is not allowed), fsys = 24 MHz, IVDDP = 10 mA, IVDDEXT = 5 mA. In addition, the power dissipation caused by the charge pump and the MOSFET driver has to be considered. Charge pump and MOSFET driver operation above the specified voltage range is not allowed. 2) Parameter deviations mean that the electrical parameters of the device may present values outside the range specified within the minimum and maximum values. 3) Parameter deviations mean that the electrical parameters of the device may present values outside the range specified within the minimum and maximum values. 4) Functionality is reduced (for example, cranking pulse); parameter deviations are possible: The electrical parameters of the device may present values outside the range specified within the minimum and maximum values. 5) Not subject to production test, specified by design. 6) Function not specified when limits are exceeded. Datasheet 89 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.1.3 Current consumption Table 19 Electrical characteristics VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption at VS pin Current consumption in IVs Active mode at VS pin – 30 35 mA fsys = 20 MHz P_1.3.1 No loads on pins, LIN in recessive state1) Current consumption in IVSD Active mode at VSD pin – – 40 mA 20 kHz PWM on bridge driver Current consumption in ISDM_3P Slow-down mode – – 35 mA P_1.3.19 fsys = 5 MHz; LIN communication running; charge pump on (reverse polarity FET on), external low-side FET static on (Motor Break mode); VDDEXT on; all other modules set to power down; VS = 13.5 V Current consumption in ISleep Sleep mode – 30 35 µA System in Sleep mode, microcontroller not powered, wake-capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: -40°C ≤ Tj ≤ 85°C; VS = 5.5 V to 18 V 2) P_1.3.3 Current consumption in ISleep_extend_1 – Sleep mode, extended temperature 1 90 200 µA System in Sleep mode, microcontroller not powered, wake-capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: -40°C ≤ Tj ≤ 150°C; VS = 5.5 V to 18 V 2) P_1.3.15 Current consumption in ISleep_extend_2 – Sleep mode, extended temperature 2 300 500 µA System in Sleep mode, microcontroller not powered, wake-capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: 150°C ≤ Tj ≤ 175°C; VS = 5.5 V to 18 V 2) P_1.3.16 Datasheet 90 P_1.3.8 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 19 Electrical characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption in ISleep Sleep mode – – 33 µA System in Sleep mode, microcontroller not powered, wake-capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: -40°C ≤ Tj ≤ 40°C; VS = 5.5 V to 18 V 2) P_1.3.9 Current consumption in ICyclic Sleep mode with cyclic wake – – 110 µA -40°C ≤ Tj ≤ 85°C; VS = 5.5 V to 18 V; tCyclic_ON = 4 ms; tCyclic_OFF = 2048 ms 2) P_1.3.4 Current consumption in ICyclic_extend Sleep mode with cyclic wake, extended temperature range – – 600 µA -40°C ≤ Tj ≤ 175°C; VS = 5.5 V to 18 V; tCyclic_ON = 4 ms; tCyclic_OFF = 2048 ms 2) P_1.3.18 Current consumption in IStop Stop mode – 110 160 µA System in Stop mode, microcontroller not clocked, wake-capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND; -40°C ≤ Tj ≤ 85°C; VS = 5.5 V to 18 V P_1.3.10 Current consumption in IStop_extend Stop mode, extended temperature range 1 – 600 1800 µA System in Stop mode, microcontroller not clocked, wake-capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND; -40°C ≤ Tj ≤ 150°C; VS = 5.5 V to 18 V P_1.3.20 1) Current on VS, ADC1/2 active, timer running, LIN active (recessive). 2) Incl. leakage currents from VDH, VSD and MON. Note: Datasheet Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified under the conditions noted in the related electrical characteristics table. 91 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.1.4 Table 20 Thermal resistance Thermal resistance Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Junction to soldering point RthJSP – 6 – K/W 1) Measured to exposed pad P_1.4.1 Junction to ambient RthJA – 33 – K/W 1)2) P_1.4.2 K/W 1)2) P_1.4.3 ΨJTOP 2s2p – Junction to top 8 – 1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 with natural convection on an FR4 2s2p board. Board: 76.2 × 114.3 × 1.5 mm3 with two inner copper layers (35 µm strong), with thermal dissipation via array under the exposed pad contacting the first inner copper layer and 300 mm2 of cooling area on the bottom layer (70 µm). 29.1.5 Timing characteristics The transition times between the system modes are specified here. Generally, the timings are defined from the time when the corresponding bits in register PMCON0 are set until the sequence is terminated. Table 21 System timing1) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Wake-up time when running on battery tstart – – 3 ms Battery ramp-up time until the start of code execution P_1.5.6 Wake-up time when running on battery tstartSW – – 1.5 ms Battery ramp-up time until the MCU reset is released; VS > 3 V and RESET = 1 P_1.5.1 Time to exit sleep tsleep - exit – – 1.5 ms Rising/falling edge of any wake-up signal (LIN, MON) until the MCU reset is released P_1.5.2 Time to enter sleep tsleep - – 330 µs 2) P_1.5.3 – entry 1) Not subject to production test, specified by design. 2) Wake events during sleep entry are stored and lead to wake-up after Sleep mode is reached. Datasheet 92 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.2 Power management unit (PMU) This chapter includes all electrical characteristics of the power management unit. 29.2.1 PMU I/O supply (VDDP) parameters This chapter describes electrical parameters which are observable on the SoC level. The pad-supply VDDP and the transition times between the system modes are specified in the following table. Table 22 Electrical characteristics VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Specified output current IVDDP 0 – 50 mA 1) P_2.1.1 Specified output current IVDDP 0 – 30 mA 1)2) P_2.1.22 Required decoupling capacitance CVDDP1 0.47 – 2.2 µF 3)4)5) Required buffer capacitance for stability (load jumps) CVDDP2 1 – 2.2 µF 3)4)6) P_2.1.20 Output voltage including line and VDDPOUT load regulation in Active mode 4.9 5.0 5.1 V 7) Iload < 90 mA; VS > 5.5 V P_2.1.3 Output voltage including line and VDDPOUT load regulation in Active mode 4.9 5.0 5.1 V 2)7) P_2.1.23 Output voltage including line and VDDPOUTSTOP load regulation in Stop mode 4.5 5.0 5.5 V 7) Iload is only internal; P_2.1.21 VS > 5.5 V; -40°C ≤ Tj ≤ -150°C Output voltage including line and VDDPOUTSTOP_HT 3.5 load regulation in Stop mode, extended temperature range 5.0 5.8 V 7) Iload is only internal; P_2.1.29 VS > 5.5 V; 150°C < Tj ≤ 175°C ESR < 1 Ω Iload < 70 mA; VS > 5.5 V P_2.1.2 Output drop in Active mode VSVDDPout – 50 400 mV IVDDP = 30 mA8); 3.5 V < VS < 5.0 V P_2.1.4 Load regulation in Active mode VVDDPLOR -50 – 50 mV 2 mA … 90 mA; C = 570 nF; -40°C < Tj ≤ 150°C P_2.1.5 Load regulation in Active mode, extended temperature range VVDDPLOR_HT -70 – 70 mV 2 mA … 90 mA; C = 570 nF; 150°C < Tj ≤ 175°C P_2.1.30 Line regulation in Active mode VVDDPLIR -50 – 50 mV VS = 5.5 V … 28 V P_2.1.6 Overvoltage detection VDDPOV 5.14 – 5.4 V VS > 5.5 V; P_2.1.7 Overvoltage leads to SUPPLY_NMI – 735 – µs 3)9) P_2.1.24 V 3) P_2.1.25 P_2.1.26 P_2.1.8 Overvoltage detection filter time tFILT_VDDPOV Voltage OK detection threshold 10) VDDPOK – 3 – Voltage stable detection range ∆VDDPSTB -220 – 220 mV 3) Undervoltage reset VDDPUV 2.5 2.7 V – Datasheet 2.6 93 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 22 Electrical characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Unit Note or Test Condition Min. Typ. Max. Number Overcurrent diagnostic IVDDPOC 91 Overcurrent diagnostic filter time tFILT_VDDPOC Overcurrent diagnostic shutdown time Values – – 27 tFILT_VDDPOC_SD – 100 220 – – mA – P_2.1.9 µs 3)9) P_2.1.27 µs 3)9)11) P_2.1.28 1) Specified output current for port supply and additional other external loads, already excluding VDDC current. 2) This use case applies when the output current on VDDEXT does not exceed 40 mA. 3) Not subject to production test, specified by design. 4) Ceramic capacitor. 5) Ranges of P_2.1.2 and P_2.1.20 can be added to one ceramic capacitor with ESR < 1 Ω. 6) Ranges of P_2.1.2 and P_2.1.20 can be added to one ceramic capacitor with ESR < 1 Ω. 7) Load current includes internal supply. 8) Output drop for IVDDP without internal supply current. 9) This filter time is derived from the time base tLP_CLK = 1 / fLP_CLK. 10) The absolute voltage value is the sum of parameters VDDP + ∆VDDPSTB. 11) When tFILT_VDDCOC_SD is passed and the overcurrent condition is still present, the device will enter Sleep mode. Datasheet 94 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.2.2 PMU core supply (VDDC) parameters This chapter describes electrical parameters which are observable on the SoC level. The core-supply VDDC and the transition times between the system modes are specified in the following table. Table 23 Electrical characteristics VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Required decoupling capacitance CVDDC1 Values Min. Unit Note or Test Condition Typ. Max. 0.1 – 1 Number µF 1)2)3) P_2.2.17 ESR < 1 Ω P_2.2.1 Required buffer capacitance for stability (load jumps) CVDDC2 0.33 – 1 µF 2)4) Output voltage including line regulation in Active mode VDDCOUT 1.44 1.5 1.56 V Iload < 40 mA P_2.2.2 Reduced output voltage including line regulation in Stop mode VDDCOUT_ 0.95 1.1 1.3 V With internal VDDC load only: Iload_internal < 1.5 mA P_2.2.23 Stop_Red Load regulation in Active mode VDDCLOR -50 – 50 mV 2 mA … 40 mA; C = 430 nF P_2.2.3 Line regulation in Active mode VDDCLIR -25 – 25 mV VDDP = 2.5 V … 5.5 V P_2.2.4 Overvoltage detection VDDCOV 1.59 1.62 1.68 V Overvoltage leads to P_2.2.5 SUPPLY_NMI – 735 µs 1)5) P_2.2.18 mV 1) P_2.2.19 mV 1) P_2.2.20 – P_2.2.6 mA – P_2.2.7 P_2.2.21 P_2.2.22 Overvoltage detection filter time tFILT_VDDCOV 6) Voltage OK detection range ∆VDDCOK 7) -280 – – 280 Voltage stable detection range ∆VDDCSTB -110 Undervoltage reset VDDVUV 1.136 1.20 1.264 V Overcurrent diagnostic IVDDCOC 45 – – 110 100 Overcurrent diagnostic filter time tFILT_VDDCOC – 27 – µs 1)5) Overcurrent diagnostic shutdown time – 290 – µs 1)5)8) 1) 2) 3) 4) 5) 6) 7) 8) tFILT_VDDCOC_SD Not subject to production test, specified by design. Ceramic capacitor. Ranges of P_2.2.1 and P_2.2.17 can be added to one ceramic capacitor with ESR < 1 Ω. Ranges of P_2.2.1 and P_2.2.17 can be added to one ceramic capacitor with ESR < 1 Ω. This filter time is derived from the time base tLP_CLK = 1 / fLP_CLK. This absolute voltage value is the sum of parameters VDDC + ∆VDDCSTB. This absolute voltage value is the sum of parameters VDDC + ∆VDDCOK. When tFILT_VDDCOC_SD is passed and the overcurrent condition is still present the device will enter Sleep mode. Datasheet 95 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.2.3 Table 24 VDDEXT voltage regulator (5.0 V) parameters Electrical characteristics VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number mA – P_2.3.1 P_2.3.21 Min. Typ. Max. Specified output current IVDDEXT 0 – 20 Specified output current IVDDEXT 0 – 40 mA 1) Required decoupling capacitance CVDDEXT1 0.1 – 2.2 µF 2)5)3) Required buffer capacitance for stability (load jumps) CVDDEXT2 1 – 2.2 µF 2)5)4) P_2.3.20 Output voltage including line and VDDEXT load regulation 4.9 5.0 5.1 V 5) Iload < 20 mA; VS > 5.5 V P_2.3.3 Output voltage including line and VDDEXT load regulation 4.8 5.0 5.2 V Iload < 40 mA; VS > 5.5 V P_2.3.23 ESR < 1 Ω P_2.3.22 Output drop in Active mode VS-VDDEXT 50 300 mV 5) Iload < 20 mA; 3 V < VS < 5.0 V P_2.3.4 Output drop in Active mode VS-VDDEXT – 400 mV Iload < 40 mA; 3 V < VS < 5.0 V P_2.3.14 Load regulation in Active mode VDDEXTLOR -50 – 50 mV 2 mA … 40 mA; C = 200 nF P_2.3.5 Line regulation in Active mode VVDDEXTLIR -50 – 50 mV VS = 5.5 V … 28 V P_2.3.6 – dB 5) VS = 13.5 V; f = 0 kHz … 1 kHz; Vr = 2 Vpp P_2.3.7 5.4 V VS > 5.5 V P_2.3.8 µs 5)6) P_2.3.24 – V 5) P_2.3.25 220 mV 5) P_2.3.26 P_2.3.9 Power supply ripple rejection in Active mode PSSRVDDEXT 50 Overvoltage detection VVDDEXTOV 5.18 – Overvoltage detection filter time tFILT_VDDEXTOV – – 735 Voltage OK detection threshold VVDDEXTOK – Voltage stable detection range7) ∆VVDDEXTSTB -220 – 3 – Undervoltage trigger VVDDEXTUV 2.6 2.8 3.0 V 8) Overcurrent diagnostic IVDDEXTOC 50 – 160 mA – P_2.3.10 – 27 – µs 5)6) P_2.3.27 µs 5)6) P_2.3.28 Overcurrent diagnostic filter time tFILT_VDDEXTOC Overcurrent diagnostic shutdown time 1) 2) 3) 4) 5) 6) 7) 8) tFILT_VDDEXTOC_SD – 100 – This use case requires the reduced utilization of VDDP output current by 20 mA, see P_2.1.22. Ceramic capacitor. Ranges of P_2.3.22 and P_2.3.20 can be added to one ceramic capacitor with ESR < 1 Ω. Ranges of P_2.3.22 and P_2.3.20 can be added to one ceramic capacitor with ESR < 1 Ω. Not subject to production test, specified by design. This filter time is derived from the time base tLP_CLK = 1 / fLP_CLK. The absolute voltage value is the sum of parameters VDDEXT + ∆VDDEXTSTB. When the undervoltage condition is met, the VDDEXT_CTRL.bit.SHORT bit is set. Datasheet 96 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.2.4 VPRE voltage regulator (PMU subblock) parameters The PMU VPRE regulator acts as a supply for the VDDP and VDDEXT voltage regulators. Table 25 Functional range Parameter Symbol Specified output current IVPRE Values Min. Typ. Max. Unit Note or Test Condition – – 110 mA Number 1) P_2.4.1 1) Not subject to production test, specified by design. 29.2.4.1 Load-sharing scenario for the VPRE regulator The figure below shows the load-sharing scenario for VPRE regulator. VS VPRE VDDEXT VDDEXT 5V VDDP 5V CVDDEXT VDDP CVDDP GND (pin 39) GND (pin 39) VDDC 1.5 V VDDC CVDDC GND (pin 39) Figure 32 Datasheet Load-sharing scenario for the VPRE regulator 97 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.2.5 Power-down voltage regulator (PMU subblock) parameters The PMU power-down voltage regulator consists of two subblocks: • Power-down preregulator: VDD5VPD • Power-down core regulator: VDD1V5_PD (Supply used for the GPUDATAxy registers) Both regulators are used as purely internal supplies. The following table contains all relevant parameters. Table 26 Functional range Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition – 1.5 V Number VDD1V5_PD Power-on reset threshold VDD1V5_PD_RSTTH 1.2 1) P_2.5.1 1) Not subject to production test, specified by design. Datasheet 98 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.3 System clocks 29.3.1 Parameters of oscillators and PLLs Table 27 Electrical characteristics of the system clocks VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Unit Note or Test Condition Number P_3.1.1 Typ. Max. 14 18 22 MHz This clock is used during startup and can be used when the PLL fails. 70 100 130 kHz This clock is used for cyclic P_3.1.2 wakes. 2)3) PMU oscillators (power management unit) Frequency of LP_CLK fLP_CLK Frequency of LP_CLK2 fLP_CLK2 CGU oscillator (clock generation unit microcontroller) Short-term frequency deviation1) fTRIMST -0.4 – 0.4 % Within any 10 ms, e.g., after synchronization to a LIN frame. (The PLL settings must not change in these 10 ms.) Absolute accuracy fTRIMABSA -1.5 – 1.5 % Including temperature and P_3.1.4 lifetime deviation; -40°C ≤ Tj ≤ 150°C Absolute accuracy, fTRIMABSA_HT -2.0 extended temperature range – 2.0 % Including temperature and P_3.1.18 lifetime deviation; 150°C ≤ Tj ≤ 175°C – 10 µs 3) CGU-OSC start-up time tOSC – P_3.1.3 Start-up time OSC from P_3.1.5 Sleep mode, power supply stable PLL (Clock generation unit microcontroller) 3) VCO frequency range mode 0 fVCO-0 48 – 112 MHz VCOSEL = ”0” P_3.1.6 VCO frequency range mode 1 fVCO-1 96 – 160 MHz VCOSEL = ”1” P_3.1.7 Input frequency range fOSC 4 – 16 MHz – P_3.1.8 XTAL1 input frequency fOSC range 4 – 16 MHz – P_3.1.9 Output frequency range fPLL 0.04687 – 80 MHz – P_3.1.10 Free-running frequency mode 0 fVCOfree_0 – 38 MHz VCOSEL = ”0” P_3.1.11 Datasheet – 99 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 27 Electrical characteristics of the system clocks (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Free-running frequency mode 1 fVCOfree_1 – – 76 MHz VCOSEL = ”1” P_3.1.12 Input clock high/low time thigh/low 10 – – ns – P_3.1.13 Peak period jitter tjp -500 – 500 ps 4) for K = 1 P_3.1.14 for K = 1 P_3.1.15 Accumulated jitter jacc – – 5 ns 4) Lock-in time tL – – 200 µs – 1) 2) 3) 4) P_3.1.16 The typical oscillator frequency is 5 MHz. VDDC = 1.5 V, Tj = 25°C. Not subject to production test, specified by design. This parameter is valid for PLL operation with an external clock source and thus reflects the real PLL performance. 29.3.2 Table 28 External clock parameters XTAL1, XTAL2 Functional range VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified).1) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Input voltage range limits VIX1_SR for signal on XTAL1 -1.7 + VDDC – 1.7 V 2) P_3.2.1 Input voltage (amplitude) VAX1_SR on XTAL1 0.3 × VDDC – – V 3) Peak-to-peak voltage P_3.2.2 XTAL1 input current IIL – – ±20 µA 0 V < VIN < VDDI P_3.2.3 Oscillator frequency fOSC 4 – 24 MHz Clock signal P_3.2.4 Oscillator frequency fOSC 4 – 16 MHz Crystal or resonator P_3.2.5 High time t1 6 – – ns – P_3.2.6 Low time t2 6 – – ns – P_3.2.7 Rise time t3 – 8 8 ns – P_3.2.8 Fall time t4 – 8 8 ns – P_3.2.9 1) This parameter table is not subject to production test, specified by design. 2) Overload conditions must not occur on pin XTAL1. 3) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by VIX1. Datasheet 100 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.4 Flash memory This chapter includes the parameters for the 128 kByte embedded flash module. 29.4.1 Table 29 Flash parameters Flash characteristics1) VS = 3.0 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Programming time per 128 byte page tPR – 32) 3.5 ms 3) 3 V ≤ VS ≤ 28 V P_4.1.1 Erase time per sector or page tER – 42) 4.5 ms 3) 3 V ≤ VS ≤ 28 V P_4.1.2 Data retention time tRET 20 – – year 1,000 erase/program P_4.1.3 cycles Data retention time tRET 50 – – year 1,000 erase/program P_4.1.9 cycles Tj = 30°C 4) Flash erase endurance for pages in user sectors NER 30 – – kilocycles Data retention time 5 years Flash erase endurance for security pages NSEC 10 – – cycles Data retention time P_4.1.5 20 years Drain disturb limit NDD 32 – – kilocycles 6) Junction temperature range 1 Tj_extend_1 -40 – 150 °C P_4.1.4 5) P_4.1.6 P_4.1.10 1) Junction temperature range 2 Tj_extend_2 -40 – 165 °C Incl. flash erase/write/read P_4.1.11 Junction temperature range 3 Tj_extend_3 165 – 175 °C 1) P_4.1.12 Incl. flash read 1) Not subject to production test, specified by design. 2) Programming and erase times depend on the internal flash clock source. The control state machine needs a few system clock cycles. The requirement is only relevant for extremely low system frequencies. 3) While the flash memory is being programmed or erased, flash read operation is not possible to be performed. 4) Determined by extrapolating of lifetime tests. 5) Tj = 25°C. 6) This parameter limits the number of subsequent programming operations within a physical sector without a given page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles, this limit will not be violated. For data sectors, the integrated EEPROM emulation firmware routines handle this limit automatically. For wordline erases in code sectors (without EEPROM emulation), it is recommended to execute a software-based refresh, which use of the integrated NVMBRNG random number generator to statistically start a refresh. Datasheet 101 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.5 Parallel ports (GPIO) 29.5.1 Description of the keep and force currents VDDP keeper current PU device PUDSEL P1.x P0.x \PUDSEL keeper current PD device VSS Figure 33 Pull-up/down device UGPIO Logical 1 7.5 kΩ (equivalent) (1.5 V / 200 μA) VIH - VDDP Undefined 2.33 kΩ (equivalent) (3.5 V / 1.5 mA) VIL - VDDP Logical 0 -IPLF Figure 34 I -IPLK Pull-up keep and force currents UGPIO Logical 1 2.33 kΩ (equivalent) (3.5 V / 1.5 mA) VIH Undefined 7.5 kΩ (equivalent) (1.5 V / 200 μA) VIL Logical 0 IPLK Figure 35 Datasheet IPLF I Pull-down keep and force currents 102 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.5.2 DC parameters of port 0, port 1, TMS, and reset Note: Operating conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the maximum allowed current that can be taken out of VDDP. Current limits for port output drivers1) Table 30 Port output driver mode Maximum output current (IOLmax, - IOHmax) Maximum output current (IOLnom, - IOHnom) Number VDDP ≥ 4.5 V 2.6 V < VDDP < 4.5 V VDDP ≥ 4.5 V 2.6 V < VDDP < 4.5 V 2) Strong driver 3) Medium driver 3) Weak driver 5 mA 3 mA 1.6 mA 1.0 mA P_5.1.15 3 mA 1.8 mA 1.0 mA 0.8 mA P_5.1.1 0.5 mA 0.3 mA 0.25 mA 0.15 mA P_5.1.2 1) Not subject to production test, specified by design. 2) Not available for port pins P0.4, P1.0, P1.1, and P1.2. 3) All P0.x and P1.x pins. Table 31 DC characteristics of port0 and port1 VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Input hysteresis HYSP0_P1 Input hysteresis HYSP0_P1_exend – Input low voltage VIL Input low voltage VIL_extend Max. Unit Note or Test Condition – V 1) 0.09 × VDDP – V 1) 0.3 × VDDP V 2) 4.5 V ≤ VDDP ≤ 5.5 V P_5.1.3 V 1) 2.6 V ≤ VDDP ≤ 4.5 V P_5.1.17 4.5 V ≤ VDDP ≤ 5.5 V P_5.1.4 2.6 V ≤ VDDP ≤ 4.5 V P_5.1.18 Typ. 0.11 × VDDP – -0.3 -0.3 – 0.42 × VDDP – Number Series resistance P_5.1.5 = 0 Ω; 4.5 V ≤ VDDP ≤ 5.5 V Series resistance P_5.1.16 = 0 Ω; 2.6 V ≤ VDDP ≤ 4.5 V Input high voltage VIH 0.7 × VDDP – VDDP + 0.3 V 2) Input high voltage VIH_extend – 0.52 × VDDP VDDP + 0.3 V 1) – V 3)4) IOL ≤ IOLmax P_5.1.6 IOL ≤ IOLnom P_5.1.7 Output low voltage VOL – 1.0 Output low voltage VOL – – 0.4 V 3)5) Output high voltage VOH VDDP - 1.0 – – V 3)4) IOH ≥ IOHmax P_5.1.8 VDDP - 0.4 – – V 3)5) IOH ≥ IOHnom P_5.1.9 Input leakage current IOZ_extend1 -500 – 500 nA -40°C ≤ Tj ≤ 25°C, 0.45 V < VIN < VDDP P_5.1.20 Input leakage current IOZ1 -5 – 5 µA 6) 25°C < TJ ≤ 85°C, 0.45 V < VIN < VDDP P_5.1.10 Input leakage current IOZ_extend2 -15 – 15 µA 85°C < TJ ≤ 150°C, 0.45 V < VIN < VDDP P_5.1.21 Output high voltage Datasheet VOH 103 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 31 DC characteristics of port0 and port1 (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Input leakage current IOZ_extend3 -20 – 20 µA 85°C < TJ ≤ 175°C, 0.45 V < VIN < VDDP P_5.1.11 Pull level keep current IPLK -200 – 200 µA 7) VPIN ≥ VIH (up) VPIN ≤ VIL (down) P_5.1.12 Pull level force current IPLF -1.5 – 1.5 mA 7) VPIN ≤ VIL (up) VPIN ≥ VIH (down) P_5.1.13 Pin capacitance CIO – – 10 pF 1) P_5.1.14 tfilt_RESET – 5 – µs 1) P_5.1.19 Reset pin timing Reset pin input filter time 1) Not subject to production test, specified by design. 2) Tested at VDDP = 5 V, specified for 4.5 V < VDDP < 5.5 V. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for pin groups must be respected. 4) Tested at 4.9 V < VDDP < 5.1 V, IOL = 4 mA, IOH = -4 mA, specified for 4.5 V < VDDP < 5.5 V. 5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→GND, VOH→VDDP). Tested at 4.9 V < VDDP < 5.1 V, IOL = 1 mA, IOH = -1 mA. 6) The given values are worst-case values. In production tests, this leakage current is only tested at 150°C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 × e(1.5 + 0.028×Tj) [µA]. For example, at a temperature of 95°C, the resulting leakage current is 3.2 µA. Leakage derating depending on the voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 × DV) [µA] This voltage derating formula is an approximation which applies for the maximum temperature. 7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VIL for a pull-up; VPIN ≥ VIH for a pull-down. These values apply to the fixed pull devices in dedicated pins and to the user-selectable pull devices in generalpurpose IO pins. Datasheet 104 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.5.3 DC parameters of port 2 These parameters apply to the IO voltage range 4.5 V ≤ VDDP ≤ 5.5 V. Note: Table 32 Operating conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. DC characteristics of port 2 VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Input low voltage Symbol VIL Values Min. Typ. Max. -0.3 – 0.3 × VDDP V 4.5 V ≤ VDDP ≤ 5.5 V P_5.2.1 V 2) 2.6 V ≤ VDDP ≤ 4.5 V P_5.2.10 VDDP + 0.3 V 1) 4.5 V ≤ VDDP ≤ 5.5 V P_5.2.2 0.52 × VDDP VDDP + 0.3 V 2) 2.6 V ≤ VDDP ≤ 4.5 V P_5.2.11 VIL_extend -0.3 0.42 × VDDP – Input high voltage VIH 0.7 × VDDP – VIH_extend – Number 1) Input low voltage Input high voltage Unit Note or Test Condition – V 2) Series resistance = 0 Ω; 4.5 V ≤ VDDP ≤ 5.5 V P_5.2.3 0.09 × VDDP – V 2) Series resistance = 0 Ω; 2.6 V ≤ VDDP < 4.5 V P_5.2.12 – 400 nA 3) P_5.2.4 Input leakage current, IOZ2_HT_P2_0 -2500 extended temperature range for port pin P2.0 – 2500 nA 3) Input leakage current, IOZ2_HT_P2_x -1500 extended temperature range for all other P2.x – 1500 nA 3) Pull-level keep current IPLK -30 – 30 µA 4) Pull-level keep current, IPLK_HT_P2 extended temperature range -27 – 27 µA 4) 150°C < Tj ≤ 175°C, P_5.2.15 VPIN ≥ VIH (up) VPIN ≤ VIL (down) Pull-level force current IPLF -750 – 750 µA 4) VPIN ≤ VIL (up) VPIN ≥ VIH (down) P_5.2.6 Pin capacitance (digital CIO inputs/outputs) – – 10 pF 2) P_5.2.7 0.11 × VDDP – Input hysteresis HYSP2 Input hysteresis HYSP2_extend – Input leakage current IOZ2 -400 TJ ≤ 85°C, 0 V < VIN < VDDP 85°C < Tj ≤ 175°C, P_5.2.14 0 V < VIN < VDDP 85°C < Tj ≤ 175°C, P_5.2.13 0 V < VIN < VDDP -40°C < Tj ≤ 150°C, P_5.2.5 VPIN ≥ VIH (up) VPIN ≤ VIL (down) 1) Tested at VDDP = 5 V, specified for 4.5 V < VDDP < 5.5 V. 2) Not subject to production test, specified by design. 3) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Datasheet 105 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 4) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VIL for a pull-up; VPIN ≥ VIH for a pull-down. Datasheet 106 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.6 LIN transceiver 29.6.1 Electrical characteristics Table 33 Electrical characteristics of the LIN transceiver Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. 0.4 × VS 0.45 × VS 0.53 × VS V SAE J2602 P_6.1.1 – Bus receiver interface Receiver threshold voltage, recessive to dominant edge Vth_dom Receiver dominant state VBUSdom -27 Receiver threshold voltage, dominant to recessive edge Receiver recessive state 0.4 × VS V LIN spec 2.2 (par. 17) P_6.1.2 Vth_rec 0.47 × VS 0.55 × VS 0.6 × VS V SAE J2602 P_6.1.3 VBUSrec 0.6 × VS 1.15 × VS V 1) LIN spec 2.2 (par. 18) P_6.1.4 0.525 × VS V 2) LIN spec 2.2 (par. 19) P_6.1.5 LIN spec 2.2 (par. 20) P_6.1.6 – Receiver center voltage VBUS_CNT 0.475 × VS 0.5 × VS Receiver hysteresis VHYS 0.07 × VS 0.12 × VS 0.175 × VS V 3) Wake-up threshold voltage VBUS,wk 0.4 × VS 0.5 × VS 0.6 × VS V – Dominant time for bus wake-up (internal analog filter delay) tWK,bus 3 – 15 µs P_6.1.8 The overall dominant time for bus wake-up is the sum of tWK,bus and the adjustable digital filter time. The digital filter time can be adjusted by setting the PMU.CNF_WAKE_FILTE R.CNF_LIN_FT register Bus recessive output voltage VBUS,ro 0.8 × VS – VS V VTxD = high level Bus dominant output voltage VBUS,do – – 0.22 × VS V P_6.1.7 Bus transmitter interface Datasheet 107 P_6.1.9 Driver dominant voltage P_6.1.78 RL = 500 Ω Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 33 Electrical characteristics of the LIN transceiver (cont’d) Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Bus short circuit current Symbol IBUS,sc Bus short circuit filter time tBUS,sc Values Unit Note or Test Condition Number Min. Typ. Max. 40 100 150 mA Current limitation for driver-dominant state driver on VBUS = 18 V; LIN spec 2.2 (par. 12) – 5 – µs 6) The overall bus short P_6.1.71 circuit filter time is the sum of tBUS,sc and the digital filter time. The digital filter time is 4 µs (typ.) -450 1000 µA VS = 12 V; 0 V < VBUS < 18 V; LIN spec 2.2 (par. 15) P_6.1.11 10 20 µA VS = 0 V; VBUS = 18 V; LIN spec 2.2 (par. 16) P_6.1.12 – – mA VS = 18 V; VBUS = 0 V; LIN spec 2.2 (par. 13) P_6.1.13 – 20 µA VS = 8 V; VBUS = 18 V; LIN spec 2.2 (par. 14) P_6.1.14 30 47 kΩ Normal mode, LIN spec 2.2 (par. 26) P_6.1.15 IBUS_NO_ -1000 Leakage current (loss of ground) GND Leakage current IBUS_NO_ – BAT Leakage current IBUS_PAS_ -1 dom Leakage current IBUS_PAS_ – rec Bus pull-up resistance RBUS 20 P_6.1.10 AC characteristics - transceiver Normal Slope mode Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs LIN spec 2.2 (par. 31) P_6.1.16 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs LIN spec 2.2 (par. 31) P_6.1.17 Receiver delay symmetry -2 – 2 µs tsym,R = td(L),R - td(H),R; LIN spec 2.2 (par. 32) P_6.1.18 0.396 – – tsym,R Duty cycle D1 tduty1 Normal Slope mode (for worst case at 20 kbit/s) Datasheet 108 4) P_6.1.19 Duty cycle D1 THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 5.5 V … 18 V; tbit = 50 µs; D1 = tbus_rec(min) / 2 tbit; LIN spec 2.2 (par. 27) Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 33 Electrical characteristics of the LIN transceiver (cont’d) Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol tduty2 Duty cycle D2 Normal Slope mode (for worst case at 20 kbit/s) Values Unit Note or Test Condition Number Min. Typ. Max. – – 0.581 4) P_6.1.20 Duty cycle D2 THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 5.5 V … 18 V; tbit = 50 µs; D2 = tbus_rec(max) / 2 tbit; LIN spec 2.2 (par. 28) AC characteristics - transceiver Low Slope mode Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs LIN spec 2.2 (par. 31) P_6.1.21 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs LIN spec 2.2 (par. 31) P_6.1.22 Receiver delay symmetry tsym,R -2 – 2 µs tsym,R = td(L),R - td(H),R; LIN spec 2.2 (par. 32) P_6.1.23 Duty cycle D3 (for worst case at 10.4 kbit/s) tduty1 0.417 – – P_6.1.24 Duty cycle D3 THRec(max) = 0.778 × VS; THDom(max) = 0.616 × VS; VS = 5.5 V … 18 V; tbit = 96 µs; D3 = tbus_rec(min) / 2 tbit; LIN spec 2.2 (par. 29) Duty cycle D4 (for worst case at 10.4 kbit/s) tduty2 – – 0.590 4) 4) P_6.1.25 Duty cycle D4 THRec(min) = 0.389 × VS; THDom(min) = 0.251 × VS; VS = 5.5 V … 18 V; tbit = 96 µs; D4 = tbus_rec(max) / 2 tbit; LIN spec 2.2 (par. 30) AC characteristics - transceiver Fast Slope mode Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs – P_6.1.26 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs – P_6.1.27 Receiver delay symmetry -1.5 – 1.5 µs tsym,R = td(L),R - td(H),R; -40°C ≤ Tj ≤ 150°C P_6.1.28 Receiver delay symmetry- tsym,R_HT -2.0 Extended temperature range – 2.0 µs tsym,R = td(L),R - td(H),R; 150°C < Tj ≤ 175°C P_6.1.74 Datasheet tsym,R 109 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 33 Electrical characteristics of the LIN transceiver (cont’d) Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs – P_6.1.31 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs – P_6.1.32 Receiver delay symmetry tsym,R -1.0 – 1.5 µs tsym,R = td(L),R - td(H),R P_6.1.33 Duty cycle D7 (for worst case at 115 kbit/s) for +1 µs receiver delay symmetry tduty1 0.399 – – Duty cycle D7 P_6.1.34 THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 13.5 V; tbit = 8.7 µs; D7 = tbus_rec(min) / 2 tbit Duty cycle D8 (for worst case at 115 kbit/s) for +1 µs receiver delay symmetry tduty2 – – 0.578 5) LIN input capacity CLIN_IN – 15 30 pF 6) P_6.1.69 TxD dominant time out ttimeout 6 12 20 ms VTxD = 0 V P_6.1.36 AC characteristics - Flash mode 5) Duty cycle D8 P_6.1.35 THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 13.5 V; tbit = 8.7 µs; D8 = tbus_rec(max) / 2 tbit Thermal shutdown (junction temperature) Thermal shutdown temperature TjSD 190 200 215 °C 6) P_6.1.65 Thermal shutdown hysteresis ∆T – 10 – K 6) P_6.1.66 1) 2) 3) 4) Maximum limit specified by design. VBUS_CNT = (Vth_dom +Vth rec)/2. VHYS = VBUSrec - VBUSdom. Bus load concerning LIN spec 2.2: Load 1 = 1 nF / 1 kΩ = CBUS / RBUS Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS Load 3 = 10 nF / 500 Ω = CBUS / RBUS 5) Bus load Load 1 = 1 nF / 500 Ω = CBUS / RBUS. 6) Not subject to production test, specified by design. Datasheet 110 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.7 High-speed synchronous serial interface 29.7.1 SSC timing parameters The table below provides the SSC timing in the TLE9879QTW40. Table 34 SSC master mode timing (operating conditions apply; CL = 50 pF) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. SCLK clock period 1) t0 Typ. 2 × TSSC – Unit Max. Note or Number Test Condition – 2) VDDP > 2.7 V P_7.1.1 VDDP > 2.7 V P_7.1.2 MTSR delay from SCLK t1 10 – – ns 2) MRST setup to SCLK t2 10 – – ns 2) VDDP > 2.7 V P_7.1.3 ns 2) VDDP > 2.7 V P_7.1.4 MRST hold from SCLK t3 15 – – 1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period. 2) Not subject to production test, specified by design. t0 SCLK 1) t1 t1 MTSR 1) t2 t3 Data valid MRST 1) t1 1) This timing is based on the following setup: CON.PH = CON.PO = 0. Figure 36 Datasheet SSC master mode timing 111 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.8 Measurement unit 29.8.1 System voltage measurement parameters Table 35 Supply voltage signal conditioning VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Measurement output voltage range at VAREF5 VA5 0 – 5 V – P_8.1.15 Measurement output voltage range at VAREF1V2 VA1V2 0 – 1.23 V – P_8.1.16 SFR setting 1 P_8.1.41 Battery/supply voltage measurement Input-to-output voltage attenuation: VS ATTVS_1 – 0.055 – Nominal operating input voltage range VS VS,range1 3 – 22 V 1) SFR setting 1; max. value corresponds to typ. ADC full scale input; 3 V < VS < 28 V P_8.1.1 Accuracy of VS after calibration VS,range1 -312 – 312 mV SFR setting 1, VS = 5.5 V to 18 V P_8.1.70 Input-to-output voltage attenuation: VS ATTVS_2 – 0.039 – SFR setting 2 P_8.1.42 Nominal operating input voltage range VS VS,range2 3 – 31 V 1) SFR setting 2; max. value corresponds to typ. ADC full scale input 3 V < VS < 28 V P_8.1.40 Accuracy of VS after calibration VS,range2 -440 – 440 mV SFR setting 2, VS = 5.5 V to 18 V P_8.1.44 – P_8.1.21 Drivers supply voltage measurement VSD Input-to-output voltage attenuation: VSD ATTVSD – 0.039 – Nominal operating input voltage range VSD VSD,range 2.5 – 31 V 1) P_8.1.2 Accuracy of VSD sense after calibration ∆VSD -440 – 440 mV VS = 5.5 V to 18 V P_8.1.47 – – – P_8.1.56 Charge pump voltage measurement VCP Input-to-output voltage attenuation: VCP Datasheet ATTVCP 0.023 112 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 35 Supply voltage signal conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Nominal operating input voltage range VCP Symbol VCP,range Accuracy of VCP sense after ∆VCP calibration Values Unit Note or Test Condition Number Min. Typ. Max. 2.5 – 52 V 1) P_8.1.7 747 mV VS = 5.5 V to 18 V P_8.1.62 – P_8.1.49 -747 – Monitoring input voltage measurement VMON Input-to-output voltage attenuation: VMON ATTVMON – 0.039 – Nominal operating input voltage range VMON VMON,range 2.5 – 31 V 1) P_8.1.8 Accuracy of VMON sense after calibration ∆VMON -440 – 440 mV VS = 5.5 V to 18 V P_8.1.68 Pad supply voltage measurement VVDDP Input-to-output voltage attenuation: VDDP ATTVDDP – 0.164 – – P_8.1.33 Nominal operating input voltage range VDDP VDDP,range 0 – 7.50 V 1) P_8.1.50 Accuracy of VDDP sense after calibration ∆VDDP_SENSE -105 – 105 2) mV VS = 5.5 V to 18 V P_8.1.5 10-bit ADC reference voltage measurement VAREF Input-to-output voltage attenuation: VAREF ATTVAREF – 0.219 – – P_8.1.22 Nominal operating input voltage range VAREF VAREF,range 0 – 5.62 V 1) P_8.1.51 Accuracy of VAREF sense after calibration ∆VAREF -79 – 79 VS = 5.5 V to 18 V P_8.1.48 mV 8-bit ADC reference voltage measurement VBG Input-to-output voltage attenuation: VBG ATTVBG – 0.75 – – P_8.1.57 Nominal operating input voltage range VBG VBG,range 0.8 – 1.64 V 1) P_8.1.52 Value of ADC2-VBG measurement after calibration VBG_PMU 1.01 1.07 1.18 V -40°C ≤ Tj ≤ 150°C P_8.1.73 Value of ADC2-VBG measurement after calibration, extended temperature range VBG_PMU_HT 1.01 1.07 1.44 V 150°C < Tj ≤ 175°C P_8.1.75 Datasheet 113 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 35 Supply voltage signal conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Core supply voltage measurement VDDC Input-to-output voltage attenuation: VDDC ATTVDDC – 0.75 – – P_8.1.34 Nominal operating input voltage range VDDC VDDC,range 0.8 – 1.64 V 1) P_8.1.53 Accuracy of VDDC sense after calibration ∆VDDC_SENSE -22 – 22 VS = 5.5 V to 18 V P_8.1.6 mV VDH input voltage measurement VVDH10BITADC VDH input-to-output voltage attenuation ATTVDH_1 – 0.166 – SFR setting 1 P_8.1.64 VDH input-to-output voltage attenuation ATTVDH_2 – 0.224 – SFR setting 2 P_8.1.65 VDH input-to-output voltage attenuation ATTVDH_3 – 0.226 – 1) SFR setting 2 -40°C ≤ Tj ≤ 85°C P_8.1.81 Nominal operating input voltage range VVDH, attenuation range 1 VVDH,range1 – – 30 V SFR setting 1 P_8.1.66 Nominal operating input voltage range VVDH, attenuation range 2 VVDH,range2 – – 20 V SFR setting 2 P_8.1.67 VVDH 10-bit ADC, range 1 ∆VVDHADC10B -300 – 300 mV VVDH = 5.5 V to 17.5 V, -40°C ≤ Tj ≤ 150°C P_8.1.39 Accuracy of VVDH 10-bit ADC, ATTVDH_1, extended temperature range ∆VVDHADC10B -800 – 800 mV VVDH = 5.5 V to 17.5 V, -40°C ≤ Tj ≤ 175°C P_8.1.77 Accuracy of VVDH 10-bit ADC, ATTVDH_3 ∆VVDHADC10B -200 – 200 mV 1) VVDH = 5.5 V to 17.5 V, -40°C ≤ Tj ≤ 85°C ATTVDH_3 P_8.1.80 Accuracy of VVDH 10-bit ADC, ATTVDH_2 ∆VVDHADC10B -400 – 400 mV VVDH = 5.5 V to 17.5 V, -40°C ≤ Tj ≤ 150°C P_8.1.71 Accuracy of VVDH 10-bit ADC, ATTVDH_2, extended temperature range ∆VVDHADC10B -1.5 – 1.5 V VVDH = 5.5 V to 17.5 V, -40°C ≤ Tj ≤ 175°C P_8.1.78 200 390 470 kΩ PD_N = 1 (on-state) P_8.1.3 10-bit ADC measurement, Rin_VDH,measure input resistance for VDH Datasheet 114 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 35 Supply voltage signal conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Unit Note or Test Condition Number Max. Measurement input leakage current for VVDH Ileak_VDH, measure -0.05 – 2.0 µA PD_N = 0 (off-state), -40°C ≤ Tj ≤ 150°C P_8.1.10 Measurement input leakage current for VVDH, extended temperature range Ileak_VDH, -0.05 – 4.0 µA PD_N = 0 (off-state), 150°C ≤ Tj ≤ 175°C P_8.1.79 measure_HT 1) Not subject to production test, specified by design. 2) Accuracy is valid for a calibrated device. Datasheet 115 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.8.2 Table 36 Central temperature sensor parameters Electrical characteristics of the temperature sensor module VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. a – 0.666 – V 1) Temperature sensitivity b b – 2.31 – mV/K 1) °C 1)2) -40°C ≤ Tj ≤ 85°C P_8.2.5 °C 1)2) 125°C < Tj ≤ 175°C P_8.2.6 °C 1)2) 85°C < Tj ≤ 125°C P_8.2.7 Output voltage VTEMP at T0 = 273 K (0°C) Accuracy_1 Accuracy_2 Accuracy_3 Acc_1 Acc_2 Acc_3 -10 -10 -5 – – – 10 10 5 T0 = 273 K (0°C) P_8.2.2 P_8.2.4 1) Not subject to production test, specified by design. 2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1. Datasheet 116 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.8.3 ADC2 VBG 29.8.3.1 ADC2 reference voltage VBG Table 37 DC specifications VS = 3.0 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Reference voltage VBG Values Min. Typ. Max. Unit Note or Test Condition 1.199 1.211 1.223 V 1) Number P_8.3.1 1) Not subject to production test, specified by design. 29.8.3.2 ADC2 specifications Table 38 DC specifications VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Resolution RES – 8 – bit Full P_8.3.18 Guaranteed offset error EAOFF_8Bit -2.0 ±0.3 2.0 LSB Not calibrated P_8.3.19 Gain error EAGain_8Bit -2.0 ±0.5 2.0 %FSR Not calibrated P_8.3.20 Differential non-linearity EADNL_8Bit (DNL) -0.8 ±0 0.8 LSB Full; -40°C ≤ Tj ≤ 150°C P_8.3.21 Differential non-linearity EADNL_8Bit_HT -1.2 (DNL), extended temperature range ±0 1.2 LSB Full; 150°C < Tj ≤ 175°C P_8.3.28 -1.2 ±0 1.2 LSB Full; -40°C ≤ Tj ≤ 150°C P_8.3.22 ±0 1.50 LSB Full; 150°C < Tj ≤ 175°C P_8.3.29 Integral non-linearity (INL) EAINL_8Bit Integral non-linearity (INL), extended temperature range EAINL_8Bit_HT -1.50 Datasheet 117 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.9 ADC1 reference voltage - VAREF 29.9.1 Electrical characteristics of VAREF Table 39 Electrical characteristics of VAREF VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Required buffer capacitance CVAREF 0.1 – 1 µF ESR < 1 Ω P_9.1.1 Reference output voltage VAREF 4.95 5 5.05 V P_9.1.2 DC supply voltage rejection DCPSRVAREF 30 – – dB VS > 5.5 V 1) 1) P_9.1.3 Supply voltage ripple rejection ACPSRVAREF 26 – – dB VS = 13.5 V; f = 0 kHz … 1 kHz; Vr = 2 Vpp P_9.1.4 Turn-on time tso – – 200 µs 1) P_9.1.5 Input resistance at VAREF pin RIN,VAREF – 100 – kΩ 1) Cext = 100 nF PD_N to 99.9% of final value Input impedance in P_9.1.20 case of VAREF is applied from external input 1) Not subject to production test, specified by design. Datasheet 118 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.9.2 Electrical characteristics of the ADC1 (10-bit) These parameters describe the conditions for optimum ADC performance. Note: Table 40 Operating conditions apply. A/D converter characteristics VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Number Test Condition Min. Typ. Max. Analog reference supply VAREF VAGND + 1.0 – VDDPA + 0.05 V 1) P_9.2.1 Analog reference ground VAGND VSS - 0.05 – 1.5 V – P_9.2.2 Analog input voltage range VAIN VAGND – VAREF V 2) P_9.2.3 5 – 24 MHz 3) P_9.2.4 P_9.2.5 Analog clock frequency fADCI Conversion time for 10-bit result tC10 (13 + STC) (13 + STC) (13 + STC) – × tADCI × tADCI × tADCI + 2 × tSYS + 2 × tSYS + 2 × tSYS 1)4) Conversion time for 8-bit result tC8 (11 + STC) (11 + STC) (11 + STC) – × tADCI × tADCI × tADCI + 2 × tSYS + 2 × tSYS + 2 × tSYS 1) P_9.2.6 Wake-up time from analog power-down, Fast mode tWAF – – 4 µs 1) P_9.2.7 Wake-up time from analog power-down, Slow mode tWAS – – 15 µs 1)5) P_9.2.8 Total unadjusted error (8 bit) TUE8B -2 ±1 2 counts 6)7) Total unadjusted error (10 bit) TUE10B -12 ±6 12 counts 8)9) DNL error EADNL -3 ±0.8 3 counts – P_9.2.10 INL error EAINL_int_V -5 ±0.8 5 counts Reference is internal VAREF P_9.2.11 ±0.4 10 counts Reference is internal VAREF P_9.2.12 ±0.5 2 counts – P_9.2.13 AREF Gain error EAGAIN_int_ -10 VAREF Offset error EAOFF -2 Reference is P_9.2.9 internal VAREF Reference is P_9.2.22 internal VAREF Total capacitance of an analog input CAINT – – 10 pF 1)5)10) Switched capacitance of an analog input CAINS – – 4 pF 1)5)10) Datasheet 119 P_9.2.14 P_9.2.15 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 40 A/D converter characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Number Test Condition Resistance of the analog input path RAIN – – 2 kΩ 1)5)10) P_9.2.16 Total capacitance of the reference input CAREFT – – 15 pF 1)5)10) P_9.2.17 Switched capacitance of the reference input CAREFS – – 7 pF 1)5)10) P_9.2.18 – – 2 kΩ 1)5)10) P_9.2.19 Resistance of RAREF the reference input path 1) Not subject to production test, specified by design. 2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion results in these cases will be 0000H or 03FFH, respectively. 3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting. 4) This parameter includes the sample time (and the additional sample time specified by STC), the time to determine the digital results and the time to load the result register with the conversion result. 5) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 µs. 6) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 7) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 8) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 9) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 10) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply voltage), typical values can be used for the calculation. At room temperature and nominal supply voltage, the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kΩ. 29.10 Datasheet Reserved 120 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.11 High-voltage monitoring input 29.11.1 Electrical characteristics Table 41 Electrical characteristics of the monitoring input Tj = -40°C to +175°C; VS = 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Unit Note or Test Condition Number Max. MON input pin characteristics Wake-up/monitoring threshold voltage VMONth Threshold hysteresis VMONth,hys 0.015 × 0.05 × VS VS 0.1 × VS V In all modes; without P_11.1.12 external serial resistor Rs (with Rs:dV = IPD/PU × Rs); VS = 5.5 V to 18 V Threshold hysteresis VMONth,hys 0.02 × VS 0.06 × VS 0.12 × VS V In all modes; without P_11.1.2 external serial resistor Rs (with Rs:dV = IPD/PU × Rs); VS = 18 V to 28 V Pull-up current IPU, MON -20 -10 -1 µA 0.6 × VS P_11.1.3 Pull-down current IPD, MON 3 10 20 µA 0.4 × VS P_11.1.4 Input leakage current ILK,MON -2.5 – 2.5 µA 1) P_11.1.5 tFT,MON – 500 – ns 2) 0.4 × VS 0.5 × VS 0.675 × V VS Without external serial resistor Rs (with Rs:DV = IPD/PU × Rs) 0 V < VMON_IN < 28 V P_11.1.1 Timing Wake-up filter time (internal analog filter delay) The overall filter time P_11.1.6 for MON wake-up is the sum of tFT,MON and the adjustable digital filter time. The digital filter time can be adjusted by setting the PMU.CNF_WAKE_FILTER .CNF_MON_FT register 1) Input leakage is valid for the disabled state. 2) With pull-up, pull-down current disabled. Datasheet 121 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.12 MOSFET driver 29.12.1 Electrical characteristics Table 42 Electrical characteristics of the MOSFET driver VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number MOSFET driver output Maximum total charge driver capability Qtot_max – – 100 nC 1) Maximum total charge driver capability (threephase PWM) Qtot_max,20kHz – – 150 nC 1) Due to charge pump P_12.1.120 current capability, six MOSFETs and additional external capacitors with a total charge of maximal 150 nC can be driven simultaneously at a PWM frequency of 20 kHz. VSD,min ≥ 6.5 V for VGS,min ≥ 7 V Source current - charge current (low gate voltage) high-side driver ISoumax_HS 230 345 450 mA VSD ≥ 8 V, CLoad = 10 nF, ISou = CLoad × slew rate (= 20% to 50% of VGHx1), ICHARGE = IDISCHG = 31(max) Sink current - discharge current - high-side driver ISinkmax_HS 230 330 450 mA VSD ≥ 8 V, CLoad = 10 nF, P_12.1.79 ISink = CLoad × slew rate (from 80% to 50% of VGHx1), ICHARGE = IDISCHG = 31(max) Source current - charge current (low gate voltage) low-side driver ISoumax_LS 200 295 375 mA VSD ≥ 8 V, CLoad = 10 nF, ISou = CLoad × slew rate (= 20% to 50% of VGLx1), ICHARGE = IDISCHG = 31(max) Sink current - discharge current - low-side driver ISinkmax_LS 200 314 375 mA VSD ≥ 8 V, CLoad = 10 nF, P_12.1.81 ISink = CLoad × slew rate (from 80% to 50% of VGLx1), ICHARGE = IDISCHG = 31(max) Datasheet 122 P_12.1.20 Due to charge pump current capability, six MOSFETs and additional external capacitors with a total charge of maximal 100 nC can be driven simultaneously at a PWM frequency of 25 kHz P_12.1.78 P_12.1.80 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 42 Electrical characteristics of the MOSFET driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number High-level output voltage Gxx vs. Sxx VGxx1 10 – 14 V VSD ≥ 8 V, CLoad = 10 nF, ICP = 2.5 mA2) P_12.1.3 High-level output voltage GHx vs. SHx VGxx2 8 – 14 V VSD = 6.4 V1), CLoad = 10 nF, ICP = 2.5 mA2) P_12.1.4 High-level output voltage GHx vs. SHx VGxx3 7 – 14 V VSD = 5.4 V, CLoad = 10 nF, ICP = 2.5 mA2) P_12.1.5 High-level output voltage GLx vs. GND VGxx6 8 – 14 V VSD = 6.4 V1), CLoad = 10 nF, ICP = 2.5 mA2) P_12.1.6 High-level output voltage GLx vs. GND VGxx7 7 – 14 V VSD = 5.4 V, CLoad = 10 nF, ICP = 2.5 mA2) P_12.1.7 Rise time trise3_3nf – 200 – ns 1) CLoad = 3.3 nF, P_12.1.8 VSD ≥ 8 V, 25% to 75% of VGxx1, ICHARGE = IDISCHG = 31(max) Fall time tfall3_3nf – 200 – ns 1) CLoad = 3.3 nF, P_12.1.9 VSD ≥ 8 V, 75% to 25% of VGxx1, ICHARGE = IDISCHG = 31(max) Rise time trisemax 100 250 450 ns CLoad = 10 nF, P_12.1.57 VSD ≥ 8 V, 25% to 75% of VGxx1, ICHARGE = IDISCHG = 31(max) Fall time tfallmax 100 250 450 ns CLoad = 10 nF, P_12.1.58 VSD ≥ 8 V, 75% to 25% of VGxx1, ICHARGE = IDISCHG = 31(max) Rise time trisemin 1.25 2.5 5 µs 1) CLoad = 10 nF, VSD ≥ 8 V, 25% to 75% of VGxx1, ICHARGE = IDISCHG = 3(min) P_12.1.14 Fall time tfallmin 1.25 2.5 5 µs 1) P_12.1.15 Datasheet 123 CLoad = 10 nF, VSD ≥ 8 V, 75% to 25% of VGxx1, ICHARGE = IDISCHG = 3(min) Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 42 Electrical characteristics of the MOSFET driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. tr_f(diff)LSx Absolute difference between rise and fall for all LSx – – 100 ns CLoad = 10 nF, P_12.1.35 VSD ≥ 8 V, 25% to 75% of VGxx1, ICHARGE = IDISCHG = 31(max) Absolute difference tr_f(diff)HSx between rise and fall for all HSx – – 100 ns CLoad = 10 nF, P_12.1.36 VSD ≥ 8 V, 25% to 75% of VGxx1, ICHARGE = IDISCHG = 31(max) Resistor between GHx/GLx and GND RGGND 30 40 50 kΩ 1) Resistor between SHx and GND RSHGN 30 40 50 kΩ 1)3) Low-RDSON mode (boosted discharge mode) RONCCP – 9 12 Ω VVSD = 13.5 V, VVCP = VVSD + 14.0 V; ICHARGE = IDISCHG = 31(max); 50 mA forced into Gx, Sx grounded -40°C ≤ Tj ≤ 150°C P_12.1.50 Low-RDSON mode RONCCP_HT (boosted discharge mode), extended temperature range – 9 14.5 Ω VVSD = 13.5 V, VVCP = VVSD + 14.0 V; ICHARGE = IDISCHG = 31(max); 50 mA forced into Gx, Sx grounded 150°C < Tj ≤ 175°C P_12.1.84 Resistance between VDH and VSD IBSH – 4 – kΩ 1) P_12.1.24 Input propagation time (LS on) tP(ILN)min – 1.5 3 µs 1) CLoad = 10 nF, ICharge = 3(min), 25% of VGxx1 P_12.1.37 Input propagation time (LS off) tP(ILF)min – 1.5 3 µs 1) P_12.1.38 Datasheet 124 P_12.1.11 P_12.1.10 This resistance is the resistance between GHx and GND connected through a diode to SHx. As a consequence, the voltage at SHx can rise up to 0.6 V typ. before it is discharged through the resistor CLoad = 10 nF, IDischarge = 3(min), 75% of VGxx1 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 42 Electrical characteristics of the MOSFET driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. tP(IHN)min – 1.5 3 µs 1) CLoad = 10 nF, ICharge = 3(min), 25% of VGxx1 P_12.1.39 Input propagation time (HS tP(IHF)min off) – 1.5 3 µs 1) CLoad = 10 nF, IDischarge = 3(min), 75% of VGxx1 P_12.1.40 Input propagation time (LS tP(ILN)max on) – 200 350 ns CLoad = 10 nF, ICharge = 31(max), 25% of VGxx1 P_12.1.26 Input propagation time (LS tP(ILF)max off) – 200 300 ns CLoad = 10 nF, IDischarge = 31(max), 75% of VGxx1 P_12.1.27 Input propagation time (HS tP(IHN)max on) – 200 350 ns CLoad = 10 nF, ICharge = 31(max), 25% of VGxx1 P_12.1.28 Input propagation time (HS tP(IHF)max off) – 200 300 ns CLoad = 10 nF, IDischarge = 31(max), 75% of VGxx1 P_12.1.29 Absolute input propagation tPon(diff)LSx time difference between propagation times for all LSx (LSx on) – – 100 ns CLoad = 10 nF, ICharge = 31(max), 25% of VGxx1 P_12.1.30 Absolute input propagation tPoff(diff)LSx time difference between propagation times for all LSx (LSx off) – – 100 ns CLoad = 10 nF, IDischarge = 31(max), 75% of VGxx1 P_12.1.41 Absolute input propagation tPon(diff)HSx time difference between propagation times for all HSx (HSx on) – – 100 ns CLoad = 10 nF, ICharge = 31(max), 25% of VGxx1 P_12.1.42 Absolute input propagation tPoff(diff)HSx time difference between propagation times for all HSx (HSx off) – – 100 ns CLoad = 10 nF, IDischarge = 31(max), 75% of VGxx1 P_12.1.43 Input propagation time (HS on) Datasheet 125 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 42 Electrical characteristics of the MOSFET driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. – – – 0.07 0.35 0.55 0.65 0.90 1.00 1.20 1.40 0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 0.40 0.650 0.90 1.25 1.45 1.80 2.10 2.40 Number Drain source monitoring Drain source monitoring threshold VDSMONVTH V DRV_CTRL3.DSMONVTH xxx 000 001 010 011 100 101 110 111 µA IDISCHG = 1; VSHx = 5.0 V P_12.1.47 Open load diagnostic currents Pull-up diagnostic current IPUDiag -220 -370 -520 Pull-down diagnostic current IPDDiag 650 900 1100 µA IDISCHG = 1; VSHx = 5.0 V P_12.1.48 Output voltage VCP vs. VSD VCPmin1 8.5 – – V VVSD = 5.4 V, ICP = 5 mA, CCP1, CCP2 = 220 nF, bridge driver enabled -40°C ≤ Tj ≤ 150°C P_12.1.53 Output voltage VCP vs. VSD, extended temperature range VCPmin1_HT 8.4 – – V VVSD = 5.4 V, ICP = 5 mA, CCP1, CCP2 = 220 nF, bridge driver enabled 150°C < Tj ≤ 175°C P_12.1.85 Regulated output voltage VCP vs. VSD VCP 12 14 16 V 8 V ≤ VVSD ≤ 28 V, ICP = 10 mA, CCP1, CCP2 = 220 nF, fCP = 250 kHz P_12.1.49 Turn-on time tON_VCP 10 24 40 us 8 V ≤ VVSD ≤ 28 V, (25%) of VCP1)4), CCP1, CCP2 = 220 nF, fCP = 250 kHz P_12.1.59 Rise time trise_VCP 20 60 88 us 8 V ≤ VVSD ≤ 28 V, (25% to 75%) of VCP1)5), CCP1, CCP2 = 220 nF, fCP = 250 kHz P_12.1.60 Charge pump 1) Not subject to production test, specified by design. 2) The condition ICP = 2.5 mA emulates a BLDC driver with 6 MOSFETs switching at 20 kHz with a CLoad = 3.3 nF. Test condition: IGx = -100 µA, ICHARGE = IDISCHARGE = 31 (max), IDISCHARGEDIV2_N = 1 and ICHARGEDIV2_N = 1. Datasheet 126 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 3) This resistance is connected through a diode between SHx and GHx to ground. 4) This time applies when the DRV_CP_CTRL_STS.bit.CP_EN bit is set. 5) This time applies when the DRV_CP_CLK_CTRL.bit.CPCLK_EN bit is set. Datasheet 127 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics 29.13 Operational amplifier 29.13.1 Electrical characteristics Table 43 Electrical characteristics of the operational amplifier VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Min. Differential gain (uncalibrated) Typ. Unit Max. Gain settings GAIN: P_13.1.6 00 01 10 11 G 9.5 19 38 57 10 20 40 60 Note or Test Condition Number 10.5 21 42 63 Differential input operating VIX voltage range OP2 - OP1 -1.5 / G – 1.5 / G V G is the gain specified below Operating: common mode VCM input voltage range (referred to GND: OP2 GND or OP1 - GND -2.0 – 2.0 V Input common mode has P_13.1.2 to be checked in evaluation if it fits the required range Max. input voltage range (referred to GND: OP_2 GND or OP1 - GND VIX_max -7.0 – 7.0 V Max. rating of operational amplifier inputs when no measurement is performed Single-ended output voltage range (linear range) VOUT VZERO - 1.5 – VZERO + 1.5 V 1)2) Offset output voltage P_13.1.4 2 V ±1.5 V Linearity error EPWM -15 – 15 mV P_13.1.5 Maximum deviation from best-fit straight line divided by the maximum value of the differential output voltage range (0.5 V - 3.5 V); this parameter is determined with G = 10 Linearity error EPWM_% -1.0 – 1.0 % P_13.1.24 Maximum deviation from best fit straight line divided by the maximum value of the differential output voltage range (0.5 V - 3.5 V); this parameter is determined with G = 10 Datasheet 128 P_13.1.1 P_13.1.3 Rev. 1.0 2020-07-23 TLE9879QTW40 Electrical characteristics Table 43 Electrical characteristics of the operational amplifier (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Gain drift Values Unit Note or Test Condition Number Min. Typ. Max. -1 – 1 % Gain drift after calibration with G = 10 P_13.1.7 Adjusted output offset voltage VOOS -40 10 40 mV VAIP= VAIN = 0 V and G = 40, -40°C < Tj ≤ 150°C P_13.1.17 Adjusted output offset voltage, extended temperature range VOOS_HT -50 10 50 mV VAIP= VAIN = 0 V and G = 40, 150°C < Tj ≤ 175°C P_13.1.28 58 80 – dB CMRR (in dB) = -20*log P_13.1.8 (differential mode gain / common mode gain) VCMI = -2 V … 2 V, VAIP - VAIN= 0 V, -40°C ≤ Tj ≤ 150°C DC input voltage common DC57 mode rejection ratio, CMRR_ extended temperature HT range 80 – dB P_13.1.27 CMRR (in dB) = -20*log (differential mode gain / common mode gain) VCMI = -2 V … 2 V, VAIP - VAIN= 0 V, 150°C ≤ Tj ≤ 175°C Settling time to 98% TSET – 800 1400 ns 2) Derived from 80% 20% rise fall times for ±2 V overload condition (3 Tau value of settling time constant) P_13.1.9 Current sense amplifier input resistance at OP1, OP2 Rin_OP1_ 1 1.25 1.5 kΩ 2) P_13.1.25 DC input voltage common DCmode rejection ratio CMRR OP2 1) Typical VZERO = 0,4 × VAREF. 2) Not subject to production test, specified by design. Datasheet 129 Rev. 1.0 2020-07-23 TLE9879QTW40 Package information C Seating Plane 11 x 0.5 = 5.5 0.22 ±0.05 0.08 C 48x Coplanarity 12° 0.2 MIN. -0.035 0°...7° 12° H 0.125 +0.075 0.5 1.2 MAX. Package information 0.1±0.05 STAND OFF 1±0.05 30 0.6 ±0.15 (1) 0.08 M A-B D C 48x 9 7 0.2 A-B D 48x 1) 5 0.2 A-B D H 4x 4 2) D Exposed Diepad 5 9 7 1) 48 4 2) B A 48 1 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Exposed pad for soldering purpose Figure 37 PG-TQFP-48-8-PO V01 Package outline TQFP-48-10 1) Green product (RoHS-compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations, the device is available as a green product. Green products are RoHS-compliant (i.e., Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages 1) Dimensions in mm Datasheet 130 Rev. 1.0 2020-07-23 TLE9879QTW40 Revision history 31 Revision history Revision Date Rev. 1.0 Datasheet Changes 2020-07-23 Datasheet initial release. 131 Rev. 1.0 2020-07-23 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2020-07-23 Published by Infineon Technologies AG 81726 Munich, Germany © 2020 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Z8F61925599 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). 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